Voltage-delay converter

Abstract

The present disclosure describes a voltage-delay converter comprising: a first reset transistor (402P) having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal (CLKRST), and a second terminal coupled to a top plate of a first integrating capacitor (404P); and a second reset transistor (402M) having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal (CLKRST), and a second terminal coupled to a top plate of a second integrating capacitor (404M). A first input transistor (412P) and a second input transistor (412M) receive a first input voltage (INP) and a second input voltage (INM), and are coupled between the top plates of the first integrating capacitor and the second integrating capacitor and a first current source (410), respectively. A discharge current source (406) is coupled to the base plates of the first and second integrating capacitors. A pulse generator (330) has first and second inputs coupled to the top plates of the first and second integrating capacitors, respectively.

Description

Technical Field

[0001] The present disclosure relates to data conversion circuitry and, more particularly, to delay domain analog-to-digital converters. Background Art

[0002] Advances in wireless communication technology have enabled widespread deployment and new applications for such communications in recent years. Wireless communications are now common in short-range communications (e.g., "personal area networks"), in wireless premises networks (e.g., home or office "WiFi" networks), and in long-range communications (e.g., cellular networks). Performance requirements across these network types can range from low data rate and latency tolerant applications to high data rate, real-time applications at gigahertz frequencies.

[0003] In any of these wireless communication applications, the conversion of analog signal levels to digital data and vice versa is an important function performed at each network node or device. The performance requirements for high data rate communication devices, especially in mobile devices and battery-powered devices (such as user equipment capable of "5G" cellular communications), are reflected in the performance requirements of data conversion circuitry in those devices. In these applications (especially for mobile devices), data converters may need to provide high performance (e.g., low error rate) conversion at high data rates, over wide input bandwidths but at low power consumption levels. The power constraints on data converters are particularly severe in multiple-input multiple-output (MIMO) network devices, which typically include integrated transceivers with up to eight or sixteen transmitters and receivers (e.g., 8T8R, 16T16R).

[0004] ADCs operating in the "delay domain" have been proposed for high performance applications. An exemplary delay domain ADC includes a voltage-to-delay (V2D) converter that converts an input voltage level into a delay between two pulses. A time-to-digital converter (TDC) encodes the delay interval output from the V2D converter into a digital output word.

[0005] Figure 1AA prior art dynamic differential amplifier 100 is shown that receives a differential input voltage at input terminals INP, INM and presents a differential output voltage at output terminals INTP, INTM. In one branch of the dynamic amplifier 100, an integrating capacitor 106P has a top plate coupled to the output terminal INTP and a bottom plate at a common potential (e.g., circuit ground). An N-channel metal oxide semiconductor (NMOS) transistor 104P has a drain coupled to the top plate of the integrating capacitor 106P and a gate that receives a clock signal CLK_V2V. The source of the NMOS transistor 104P is coupled to the drain of the NMOS input transistor 102P at the node VP, and is also coupled to the drain of a p-channel MOS (PMOS) transistor 105P. The PMOS transistor 105P has a drain coupled to a power supply voltage V dd The NMOS input transistor 102P has a gate coupled to the input terminal INP and a source coupled to the tail node T. The second branch of the dynamic amplifier 100 is similarly constructed, wherein the integrating capacitor 106M has a top plate coupled to the output terminal INTM and a bottom plate at the circuit ground. The NMOS transistor 104M has a drain coupled to the top plate of the integrating capacitor 106M, a gate receiving the clock signal CLK_V2V, and a source coupled to the drain of the NMOS input transistor 102M and the drain of the PMOS transistor 105M at the node VM. The PMOS transistor 105M has a gate coupled to the power supply voltage V dd The NMOS input transistor 102M has a gate coupled to the input terminal INM and a source coupled to the tail node T.

[0006] Tail node T is coupled to the drain of NMOS transistor 109. NMOS transistor 109 has a gate receiving signal CLK_BIAS and a source coupled to the drain of NMOS transistor 110. NMOS transistor 110 has a drain coupled to the source of NMOS transistor 109, a gate receiving signal NBIAS_V2V, and a source at circuit ground.

[0007] The dynamic amplifier 100 is configured to initially precharge the integrating capacitors 106P, 106M to a selected voltage (e.g., the supply voltage V dd The differential input voltage at the input terminals INP, INM differentially turns on the input transistors 102P, 102M, thereby discharging the integrating capacitors 102P, 102M toward ground at a relative rate corresponding to the input differential voltage to produce a differential voltage at the output terminals INTP, INTM. Summary of the invention

[0008] According to an example, a voltage-delay converter includes: a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor; and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. A first input transistor and a second input transistor have gates coupled to receive a first input voltage and a second input voltage, first terminals coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively, and second terminals coupled to a first current source. A discharge current source is coupled to the bottom plates of the first integrating capacitor and the second integrating capacitor. A pulse generator has a first input and a second input coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively.

[0009] According to another example, an analog-to-digital conversion method includes: charging a first plate of each of a first integrating capacitor and a second integrating capacitor to a first voltage; applying a differential voltage across gate terminals of a first transistor and a second transistor coupled between the first plates of the first integrating capacitor and the second integrating capacitor, respectively; discharging a second plate of each of the first integrating capacitor and the second integrating capacitor; generating a first pulse and a second pulse having a relative delay corresponding to the voltages at the first plates of the first integrating capacitor and the second integrating capacitor; and generating a digital output word corresponding to the relative delay of the first pulse and the second pulse.

[0010] According to another example, an analog-to-digital converter includes a voltage-delay converter and a delay-to-digital converter. The voltage-delay converter includes: a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor; and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. A first input transistor and a second input transistor have gates coupled to receive a first input voltage and a second input voltage, first terminals coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively, and second terminals coupled to a first current source. A discharge current source is coupled to the bottom plates of the first integrating capacitor and the second integrating capacitor. A pulse generator has a first input and a second input coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively. The delay-to-digital converter has a first input and a second input coupled to the first output and the second output of the pulse generator, respectively, and has a digital output, and is configured to generate a digital output word corresponding to a relative delay between pulses at the first output and the second output of the pulse generator.

[0011] Exemplary technical advantages achieved by one or more of these examples include providing a delay domain analog-to-digital converter with improved noise performance, reduced sensitivity to input transistor mismatch, and improved current source margin to maintain transistor saturation. Improved linearity in conversion can be provided by calibration of the gain characteristic of the current discharge stage to eliminate nonlinearity in the input stage, thereby providing good linearity over variations in process, voltage, and temperature.

[0012] Other technical advantages achieved by the disclosed examples will become apparent to those of ordinary skill in the art after referring to the following description and its drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is an electrical diagram in schematic form of a prior art dynamic amplifier.

[0014] Figure 1B It is shown Figure 1A Timing diagram of the operation of the dynamic amplifier.

[0015] Figure 1C yes Figure 1A A graph of gain versus input voltage for an example of a dynamic amplifier.

[0016] Figure 2 is an electrical diagram in block form of an exemplary analog-to-digital converter (ADC).

[0017] Figure 3is an electrical diagram in block form of an exemplary voltage-to-delay (V2D) converter.

[0018] Figure 4A yes Figure 3 An electrical diagram in schematic form of an exemplary dynamic amplifier, constant current discharge circuit, and pulse generator of a V2D converter.

[0019] Figure 4B It is shown Figure 4A A timing diagram of the operation of an example of a dynamic amplifier and constant current discharge circuit.

[0020] Figure 4C yes Figure 4A A graph of gain versus input voltage for an example of a constant current discharge circuit.

[0021] Figure 4D yes Figure 4A A graph of gain linearity versus input voltage of an example of a V2D converter.

[0022] Figure 5 is an electrical diagram in schematic form of another exemplary constant current discharge circuit.

[0023] Figure 6 is used for Figure 3 An electrical diagram in schematic form of an exemplary calibration logic of a V2D converter.

[0024] Figure 7 is an electrical diagram in schematic form of another exemplary constant current discharge circuit.

[0025] Figure 8 is used for Figure 3 An electrical diagram in schematic form of a portion of an exemplary pulse generator of a V2D converter.

[0026] Fig. 9 is a flow chart illustrating an exemplary method of converting an input voltage into a delay domain signal.

[0027] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0028] Figure 2 A high-level architecture of an exemplary delay domain analog-to-digital converter (ADC) 200 is shown. ADC 200 includes a voltage-to-delay (V2D) converter 210 and a time-to-digital converter (TDC) 220.

[0029] The V2D converter 210 has a receiving input voltage V in Input voltage V inThe voltage may be a single-ended or differential voltage from which the ADC 200 generates a digital output word D out For example, the input voltage V in V may be a sample acquired from a received communication signal by a sample and hold circuit operating at a selected sampling rate. In this example, the V2D converter 210 generates a signal corresponding to the input voltage V in For example, the delay domain signal ΔT may be transmitted by the V2D converter 210 with a delay domain signal having a magnitude similar to the input voltage V in A pair of pulses with amplitudes corresponding to the relative delay ΔT is output in the form of one or more conductor pairs.

[0030] TDC 220 has an input that receives the delayed domain signal ΔT from V2D converter 210 on one or more conductor pairs. TDC 220 includes a signal processor arranged to generate a digital output word D at an output. out For example, TDC 220 may have a series or parallel output, so that for an input voltage V in Each converted sample of out . Digital output word D out May be output synchronously with an associated system clock for communication to downstream processing circuitry (not shown) as appropriate for the particular application.

[0031] Examples of TDC converter architectures suitable for use as the TDC 220 in this example are described in U.S. Patent Nos. 10,673,453; 10,778,243; 11,316,525; 11,387,840; and 11,316,526; U.S. Patent Application Publication Nos. US2022 / 0247420; US2022 / 0247421; and US2022 / 0224349; and pending U.S. Patent Application No. 18 / 174,187 filed on February 24, 2023, each of which is commonly assigned with the present application and is each incorporated herein by reference in its entirety.

[0032] The linearity of the ADC's output amplitude as a function of the input amplitude is an important factor in the accuracy and performance of the ADC converter. The variation in the input voltage step width associated with each output codeword value is called differential nonlinearity (DNL) error. Excessive DNL error can result in missing output code values ​​within the full-scale range of the ADC. Integral nonlinearity (INL) error represents the deviation of the ADC transfer function from a straight line over the full-scale range.

[0033] When implementing a delay domain ADC, the use of a dynamic differential amplifier in the V2D converter stage is attractive because the dynamic amplifier operation helps to generate the delayed pulse from the differential input voltage. In addition, the gain from the dynamic amplifier effectively relaxes the noise specification of the delay domain ADC. However, for example Figure 1A Some dynamic amplifiers, such as the prior art dynamic amplifier 100, exhibit significant nonlinearity.

[0034] At this point, Figure 1B Show Figure 1A 1 is an exemplary operating cycle of a prior art dynamic amplifier 100. This operating cycle includes a reset phase, in which the integrating capacitors 106P and 106M are precharged to a selected voltage, such as close to the supply voltage V dd In this reset phase, transistors 105P, 105M, and 108 are turned on by gate signal CLK_BIAS being at a low level, and transistors 104P, 104M, and 109 are turned off by gate signals CLK_BIAS and CLK_V2V being at a low level. As a result, nodes VP, VM, and T are at or near the power supply voltage V dd , and the top plates of capacitors 106P and 106M are charged to the power supply voltage V dd This reset phase causes the output nodes INTP and INTM to be charged to the supply voltage V dd At or near the level, such as Figure 1B As shown in .

[0035] After pre-charging of the integrating capacitors 106P and 106M in the reset phase, the differential voltage at the input terminals INP, INM is sensed in the amplification phase of the operating cycle. This amplification phase is initiated by the signal CLK_BIAS making a low-to-high transition, turning on the NMOS transistor 109 and turning off the PMOS transistors 105P, 105M and 108. Transistors 104P, 104M are turned on during the amplification phase, allowing the differential gate voltage applied at the inputs INP, INM, respectively, in this amplification phase to determine the relative rate at which the integrating capacitors 106P, 106M are discharged through the input transistors 102P, 102M. NMOS transistor 110 acts as a current source, controlling the sum of the discharge currents according to the gate voltage NBIAS_V2V. In Figure 1B In the example of , a negative differential voltage (e.g., a voltage at input INP that is differentially lower than a voltage at input INM) causes integrating capacitor 106M to discharge faster through input transistor 102M relative to integrating capacitor 106P. As integrating capacitors 106P, 106M discharge in this amplification phase, the voltage at output node INTP remains differentially higher than the voltage at output node INTM.

[0036] In the hold phase following the amplification phase, transistors 104P, 104M are turned off by a high-to-low transition of signal CLK_V2V. Thus, output nodes INTP, INTM are isolated from their corresponding input transistors 102P, 102M, thereby preventing the discharge of integrating capacitors 106P, 106M. The differential output voltage across output nodes INTP, INTM at the end of the amplification phase is thereby maintained for a certain interval, thereby allowing downstream circuitry to respond, for example, by generating a pair of pulses with a relative delay corresponding to the differential voltage at output nodes INTP, INTM. The dynamic amplifier 100 may then be reset for the next operating cycle.

[0037] A first order expression for the gain G of the dynamic amplifier 100 may be expressed as:

[0038]

[0039] where g m is the input transistor transconductance, T int is the discharge time constant of the integrating capacitor, and C is the capacitance of the integrating capacitor. As is apparent from this equation (1), the gain G is proportional to the input voltage V in , and thus, good linearity is possible as long as the transistors in the dynamic amplifier 100 are in saturation. Also, linearity in the operation of a dynamic amplifier is often limited by the transistor drain-to-source voltage (V ds ) tolerance, especially at low supply voltages (e.g., 1.0V nominal V dd )Down.

[0040] For example, if Figure 1A As shown in FIG. 1 , the dynamic amplifier 100 includes four MOS transistors (eg, transistors 104P, 102P, 109, 110) with source / drain paths connected in series at a supply voltage V dd If the power supply voltage V dd is about 1.0V, so a very small drain-to-source voltage (V ds ) tolerance to maintain all of these devices in saturation, especially at a specifiable differential input voltage V in In addition, Figure 1B It is shown that when the integrating capacitors 106P, 106M discharge during amplification, the common mode voltage at the output terminals INTP, INTM drops, which tends to bring one or more of the transistors in the series coupled path out of saturation.

[0041] Thus, the dynamic amplifier 100 may exhibit nonlinearity in its gain as a function of the input differential voltage. For example, it has been observed that the gain of the dynamic amplifier 100 exhibits a quadratic characteristic over the input voltage range, where the square term (e.g., V in 2 The term ) has a negative coefficient. Figure 1C An exemplary normalized graph showing this gain characteristic of the dynamic amplifier 100 is shown, where the gain decreases as the differential input voltage increases, exhibiting a "compression" nonlinearity.

[0042] Figure 3 An exemplary V2D converter 210 is shown in the ADC 200. In this example, the V2D converter 210 includes a dynamic amplifier input stage 310, a constant current discharge stage 320, a pulse generator 330, and calibration logic 340.

[0043] In this example, the dynamic amplifier input stage 310 is a differential dynamic amplifier, where the differential input terminals INP, INM receive a differential input voltage V in The dynamic amplifier input stage 310 performs the input voltage V in The constant current discharge stage 320 is coupled to the intermediate output nodes INTP, INTM as an input of the pulse generator 330. The pulse generator 330 generates logic level pulses at the output terminals OUTP, OUTM based on the voltages at the intermediate output nodes INTP, INTM, respectively. The relative delay of the logic level pulses at the output terminals OUTP, OUTM from the pulse generator 330 reflects the differential input voltage V at the input of the dynamic amplifier input stage 310. in , thereby realizing the voltage-delay (V2D) conversion to the delay domain signal ΔT.

[0044] The calibration logic 340 in this example of the V2D converter 210 has inputs coupled to the output terminals OUTP, OUTM, and one or more outputs CAL coupled to the constant current discharge stage 320. Optionally, the calibration logic 340 may also have inputs coupled to the input terminals INP, INM. The calibration logic 340 comprises analog or digital logic arranged to generate a calibration word at its output CAL in response to a comparison of the pulses at the output terminals OUTP, OUTM with a known input value (e.g., as transmitted from the input terminals INP, INM).

[0045] Figure 4AThe configuration of an exemplary dynamic amplifier input stage 310, an exemplary constant current discharge stage 320, and an exemplary pulse generator 330 implemented into the V2D converter 210 is shown. The V2D converter 210 also includes a clock circuit system 440 and is under the timing control of the clock circuit system. The dynamic amplifier input stage 310 includes NMOS transistors 408P, 408M, 409, 410, 412P, and 412M. The constant current discharge stage 320 includes PMOS transistors 402M, 402P, 402B, NMOS transistors 405, 406, an integrating capacitor 404P, 404M, a boost capacitor 420P, 420M, and a boost driver 425. The pulse generator 330 includes inverters 432P, 432M, 434P, 434M, 436P, 436M.

[0046] NMOS transistor 408P in dynamic amplifier input stage 310 has a drain coupled to intermediate output node INTP and a gate receiving clock signal CLK_V2V from clock circuitry 440. A source of NMOS transistor 408P is coupled to a drain of NMOS input transistor 412P having a gate coupled to input terminal INP and a source coupled to the drain of NMOS transistor 409 at node T. Similarly, NMOS transistor 408M has a drain coupled to intermediate output node INTM and a gate receiving clock signal CLK_V2V from clock circuitry 440. A source of NMOS transistor 408M is coupled to a drain of NMOS input transistor 412M having a gate coupled to input terminal INM and a source coupled to the drain of NMOS transistor 409 at node T. NMOS transistor 409 has a gate that receives a clock signal CLK_BIAS from clock circuitry 440, and a source coupled to a drain of NMOS transistor 410. NMOS transistor 410 has a source coupled to a common potential (e.g., circuit ground) and a gate that receives a reference voltage NBIAS_V2V. Reference voltage NBIAS_V2V may be a regulated voltage, such as generated by a voltage regulator circuitry. Voltage NBIAS_V2V controls the total current conducted by the two input transistor branches (e.g., the sum of the currents conducted by input transistors 412P and 412M) so that NMOS transistor 410 acts as a current source.

[0047] The integrating capacitor 404P in the constant current discharge stage 320 has a top plate coupled to the intermediate output node INTP. The integrating capacitor 404M has a top plate coupled to the intermediate output node INTM. The PMOS reset transistor 402P has a drain coupled to the intermediate output node INTP and coupled to the power supply voltage V ddThe PMOS reset transistor 402M similarly has a drain coupled to the intermediate output node INTM and a drain coupled to the power supply voltage V dd 404M each has a bottom plate coupled to the drain of NMOS transistor 405 at node BP. NMOS transistor 405 has a gate receiving a clock signal CLK_V2D from clock circuitry 440, and a source coupled to the drain of NMOS transistor 406. NMOS transistor 406 has a source coupled to circuit ground and a gate receiving a reference voltage NBIAS_V2D. Voltage NBIAS_V2D may be a regulated voltage generated by a voltage regulator circuitry included in V2D converter 210 or elsewhere in the same integrated circuit. PMOS reset transistor 402B has a drain coupled to node BP at the bottom plates of integrating capacitors 404P, 404M, and coupled to a supply voltage V dd The PMOS reset transistors 402B, 402P, 402M each have a gate receiving a reset clock signal CLK_RST from the clock circuit system 440.

[0048] Boost capacitor 420P has a top plate coupled to intermediate output node INTP, and boost capacitor 420M has a top plate coupled to intermediate output node INTM. Bottom plates of boost capacitors 420P, 420M are coupled to the output of boost driver 425, which has an input that receives a boosted clock signal CLK_BOOST from clock circuitry 440. Figure 4A The boost capacitors 420P, 420M are shown as a single example. However, each of the boost capacitors 420P, 420M may be implemented as multiple capacitors in parallel, as described below.

[0049] The clock circuit system 440 may be disposed within the ADC 200 or elsewhere in the same integrated circuit with the ADC 200. The clock circuit system 440 includes appropriate clock generator circuits for generating clock signals CLK_V2V, CLK_RST, CLK_BOOST, CLK_V2D, and CLK_BOOST at appropriate times in a conversion cycle. In an example, the clock circuit system 440 generates these clock signals in response to a sampling clock ADC_CLK operating at a desired conversion rate.

[0050] In this example, the pulse generator 330 includes a pair of inverter chains. In one inverter chain, the inverter 432P has an input coupled to the intermediate output node INTP, wherein the inverters 434P and 436P are coupled in series at the output of the inverter 432P. The output of the inverter 436P is coupled to the output terminal OUTP. Similarly, the inverter 432M has an input coupled to the intermediate output node INTM. The inverters 434M and 436M are coupled in series at the output of the inverter 432M. The inverter 436M has an output that drives the output terminal OUTM.

[0051] Figure 4B Show Figure 4A 2D converter 210. In this example, each conversion cycle can be considered to include a reset phase, a V2V phase, and a V2D phase. In the reset phase, the power supply voltage V dd The integrating capacitors 404P, 404M and the boost capacitors 420P, 420M are charged. In the V2V phase, in response to the differential voltage at the input terminals INP, INM, the dynamic amplifier input stage 310 generates a differential voltage at the intermediate output nodes INTP, INTM. In the V2D phase, the constant current discharge stage 320 forwards the differential voltage at the intermediate output nodes INTP, INTM to the pulse generator 330, and the pulse generator 330 generates pulses at the output terminals OUTP, OUTM with a relative delay corresponding to the differential voltage at the input terminals INTP, INTM.

[0052] Figure 4B The conversion cycle shown in FIG. 1 starts at time t0, where the clock circuit system 440 drives each of the clock signals CLK_RST, CLK_V2V, and CLK_V2D to a low logic level, thereby enabling the reset phase. In this reset phase, the reset transistors 402P, 402M, 402B are turned on by the low level of the clock signal CLK_RST, and the transistors 408P, 408M in the dynamic amplifier input stage 310 and the transistor 405 in the constant current discharge stage 320 are turned off. The reset transistors 402P, 402M, 402B in the on stage push the integration capacitors 404P, 404M and the boost capacitors 420P, 420M toward the power supply voltage V dd (e.g., in this example, at about 1.0V). This pre-charge voltage is present at Figure 4B At both intermediate output nodes INTP and INTM shown in .

[0053] After the integrating capacitors 404P, 404M and the boost capacitors 420P, 420M are charged in the reset phase, the clock circuitry 440 Figure 4B The time t1 shown in FIG. 1 drives the clock signal CLK_RST to a high logic level. The high logic level of the clock signal CLK_RST turns off the reset transistors 402P, 402M, 402B and turns on the transistors 408P, 408M in the dynamic amplifier input stage 310. At this time, the clock signal CLK_V2D remains at a low level, thereby keeping the transistor 405 turned off in the constant current discharge stage 320. In this V2V stage, the differential voltage at the input terminals INP, INM (e.g., which can be obtained by a sample and hold circuit) generates a differential voltage at the intermediate output nodes INTP, INTM. Figure 4B In the example of , a negative differential input voltage (the voltage of the input terminal INTP is lower than the voltage of the input terminal INTM) turns on the input transistor 412M more difficultly than the input transistor 412P. As a result, the intermediate output node INTM discharges faster than the intermediate output node INTP in the V2V stage, as shown in FIG. Figure 4B The total discharge current through the input transistors 412P, 412M is controlled by the transistor 410 used as a current source in the dynamic amplifier input stage 310.

[0054] As from Figure 4B It is apparent from FIG. 3 that during the V2V phase, both intermediate output nodes INTP, INTM are discharged through the dynamic amplifier input stage 310. Therefore, during the V2V phase, the common mode voltage V CM_INT (e.g., the midpoint voltage) also decreases. According to this example, during the V2V phase, the clock circuit system 440 ramps the signal CLK_BOOST from a low level. The voltage ramp of the signal CLK_BOOST causes the boost driver 425 to drive the bottom plates of the boost capacitors 420P, 420M, thereby slowing down the rate at which the intermediate output nodes INTP, INTM discharge during the V2V phase. As a result, the common-mode voltage V at the intermediate output nodes INTP, INTM decreases. CM_INT is held high, thereby helping to keep the transistors of the dynamic amplifier input stage 310 in saturation. At the end of the approximately V2V phase, the signal CLK_BOOST reaches a selected voltage (eg, approximately 250 mV) and is held at this voltage by the clock circuitry 440 .

[0055] exist Figure 4BIn the example of , the clock circuit system 440 starts the V2D phase of the conversion cycle at time t2 by driving the clock signal CLK_V2D to a high level and driving the clock signal CLK_V2V to a low level. The low logic level of the clock signal CLK_V2V turns off the transistors 408P, 408M in the dynamic amplifier input stage 310, which decouples the input transistors 412P, 412M from the intermediate output nodes INTP, INTM, respectively. The high logic level of the clock signal CLK_V2D in the V2D phase turns on the transistor 405 of the constant current discharge stage 320. In response, the bottom plate of the integrating capacitors 404P, 404M at the node BP is discharged toward the circuit ground through the transistors 405, 406. The total discharge current is controlled by the transistor 406 used as a current source. In this example, the bottom plate of the integrating capacitors 404P, 404M is discharged with a constant current to help isolate the remainder of the current source transistor 406 from the voltage at the top plate of the integrating capacitor. This effect has been observed to significantly reduce the effects of noise in the constant current discharge stage. This effect also reduces the flicker noise exhibited by dynamic amplifiers, where the integrating capacitor is discharged from the top plate, as in Figure 1A in the example.

[0056] During the V2V phase of this conversion cycle, the voltage at the intermediate output nodes INTP, INTM continues to drop, as shown in FIG. Figure 4B In this example, the intermediate output node INTM falls to the input threshold of the inverter 432M in the pulse generator 330 at about time t3 in the V2D phase. In response to the intermediate output node INTM falling to this level, the chain of inverters 432M, 434M, 436M in the pulse generator 330 produces a low-to-high transition at the output terminal INTM. At some later time, shown as Figure 4B At time t4 in, the intermediate output node INTP drops to the input threshold of the inverter 432P in the pulse generator 330. This produces a low-to-high transition at the output terminal INTP as produced by the inverters 432P, 434P, 436P of the pulse generator 330. The relative delay ΔT between the low-to-high transitions of the output terminals OUTP, OUTM indicates the magnitude of the differential input voltage applied to the input terminals INP, INM. For example, a larger input differential voltage produces a longer relative delay at the output terminals OUTP, OUTM. The polarity of the differential voltage at the input terminals INP, INM determines which of the pulses at the output terminals OUTP, OUTM leads the other.

[0057] The clock circuit system 440 drives the clock signals CLK_V2D and CLK_RST to a low level. Figure 4BThe V2D phase of the conversion cycle ends at about time t5. The intermediate output nodes INTP and INTM are again precharged to the power supply voltage V dd , so that the pulse generator 330 drives both output terminals OUTP, OUTM to a high logic level during this reset phase of the next conversion cycle.

[0058] As mentioned above about Figure 1C Described, for example Figure 1A The dynamic amplifier shown in exhibits compression nonlinearity in its gain characteristic, where the gain of the amplifier decreases as the differential input voltage increases, generally according to a quadratic characteristic. Figure 4A In the example of the V2D converter 210 of FIG. 1 , the dynamic amplifier input stage 310 may exhibit similar nonlinear characteristics. However, in this example, Figure 4A The constant current discharge stage 320 of the construction shown in exhibits a "spreading" nonlinearity in its gain characteristic, also generally in accordance with a quadratic characteristic. Figure 4C An example of a quadratic expansion gain characteristic for an example of a constant current discharge stage 320 is shown. Figure 4C As is apparent from FIG. 3 , the gain increases as the differential input voltage increases. The combination of the dynamic amplifier input stage 310 and the constant current discharge stage 320 provides two opposing nonlinear characteristics that can effectively cancel each other. Thus, the resulting V2D converter 210 exhibits excellent gain linearity over its full-scale input voltage range.

[0059] In general, as the differential input voltage V in The gain of the dynamic amplifier input stage 310 is a function of v2v The expression for follows a quadratic relation:

[0060]

[0061] Among them G v2v is the nominal gain of the input stage 310, and A1 and A2 are positive coefficients. In one example, coefficient A1 is several orders of magnitude smaller than coefficient A2. The negative sign of the square term in this equation (2) indicates compression nonlinearity, where Gain v2v With the differential input value V in The gain of the constant current discharge stage 320 is v2d With respect to the differential input voltage V in Similar expressions for follow from the quadratic relation:

[0062]

[0063] Among them G v2dis the nominal gain of the constant current discharge stage 320, and B1 and B2 are positive coefficients. In one example, coefficient B1 is several orders of magnitude smaller than coefficient B2. The positive sign of the square term in this equation (3) indicates expansion nonlinearity, where Gain v2d With the differential input value V in According to this example, the constant current discharge stage 320 is implemented so that the value of its square term coefficient B2 in equation (3) is close to the value of the square term coefficient A2 in equation (2).

[0064] Analysis of the delay at one of the intermediate output nodes INTP, INTM (eg, the intermediate output node INTP used in the following discussion) during the V2D phase of the conversion cycle provides the following expression for the square term coefficient B2 in equation (3):

[0065]

[0066] in:

[0067]

[0068] Among them C 404 and C 420 are the capacitances of the integrating capacitor 404P and the boosting capacitor 420P (or the integrating capacitor 404M and the boosting capacitor 420M), respectively. In this equation (5), I is the regulated current conducted by the current source transistor 406, and R is the source resistance of the transistor 406 (e.g., the on-resistance R on ), V th is the input threshold voltage of the first inverters 432P and 432M in the pulse generator 330, and V CM_INT = is the common mode output voltage at the intermediate output nodes INTP and INTM. Therefore, the common mode voltage at the intermediate output nodes INTP and INTM can be controlled by controlling the capacitance ratio of the integral capacitors 404P and 404M and the boost capacitors 420P and 420M, by controlling the resistance R of the current source transistor 406, by controlling the threshold voltage at the inverters 432P and 432M, or by controlling the common mode voltage at the intermediate output nodes INTP and INTM. Figure 4A The constant current discharge stage 320 controls the expanded nonlinear gain characteristic of equation (3).

[0069] Figure 5 The common mode voltage V arranged to control the intermediate output nodes INTP, INTM is shown. CM_INT More specifically, the constant current discharge stage 520 controls the common mode voltage V by controlling the amount of boost capacitor enabled in the V2D phase of the conversion cycle. CM_INTThe constant current discharge stage 520 includes reset transistors 402M, 402P, 402B, integrating transistors 404P, 404M, and NMOS transistors 405 and 406, as shown in FIG. Figure 4A in the example.

[0070] like Figure 5 As shown in , the constant current discharge stage 520 includes a plurality of boost capacitors 520 coupled to each of the intermediate output nodes INTP, INTM. In this example, the three boost capacitors 520PA, 520PB, 520PC each have a top plate coupled to the intermediate output node INTP. Similarly, the three boost capacitors 520MA, 520MB, 520MC each have a top plate coupled to the intermediate output node INTM. Boost driver 525A has an output coupled to the bottom plates of boost capacitors 520PA and 520MA. Boost driver 525B has an output coupled to the bottom plates of boost capacitors 520PB and 520MB. Boost driver 525C has an output coupled to the bottom plates of boost capacitors 520PC and 520MC. The capacitances of boost capacitors 520PA, 520PB, 520PC and boost capacitors 520MA, 520MB, 520MC may be binary weighted, equivalently weighted, or have some other weighted relationship. In this example, Figure 5 In FIG. 3 , three boost capacitors 520PA, 520PB, 520PC and three boost capacitors 520MA, 520MB, 520MC are shown. In other examples, more or fewer boost capacitors may be provided instead, depending on the adjustment of the common mode voltage V CM_INT The desired resolution.

[0071] In this example, boost drivers 525A, 525B, 525C each have an input driven by the output of decoder and timing logic 530. Decoder and timing logic 530 has an input that receives a calibration word CAL and an input from clock circuitry 440 ( Figure 4A ) receives a clock input of a clock signal CLK_BOOST.

[0072] In operation, in response to the clock signal CLK_BOOST at an appropriate time within a conversion cycle (eg, starting in the V2V stage and entering the V2D stage, such as Figure 4B), the decoder and timing logic 530 drives one or more of the boost drivers 525A, 525B, 525C. The selection of which boost drivers 525A, 525B, 525C are driven by the decoder and timing logic 530 is determined by the value of the calibration word CAL received by the decoder and timing logic 530. Driving more boost capacitors at the intermediate output nodes INTP, INTM (e.g., driving more of the boost drivers 525A, 525B, 525C or driving those associated with more boost capacitors) enhances the effect of the boost capacitors and thus mitigates the common mode voltage V CM_INT The less boost capacitor at the driving intermediate output nodes INTP, INTM will allow the common-mode voltage V CM_INT Discharge faster.

[0073] Figure 6 An example of calibration logic 340 is shown. Calibration logic 340 includes a duty cycle measurement circuit 602, an analog-to-digital converter (ADC) 604, and a linear correction circuit 606. Duty cycle measurement circuit 602 has inputs coupled to output terminals OUTP, OUTM and corresponding outputs DCP, DCM coupled to inputs of ADC 604. Duty cycle measurement circuit 602 includes analog and digital circuitry arranged to measure the duty cycle of pulses at output terminals OUTP, OUTM as pulse generator 330 generates those pulses in response to samples of the differential input voltage at input terminals INP, INM, as described above. In this example, the outputs DCP, DCM from duty cycle measurement circuit 602 transmit analog levels indicative of the measured duty cycle. ADC 604 includes multiple channels to convert each of the analog levels into digital values ​​at its input. As Figure 6 As shown in FIG. 6 , ADC 604 may optionally include additional channels to convert the differential input voltage V in The current samples (eg, input samples corresponding to pulses at output terminals OUTP, OUTM received by calibration logic 340) are converted into digital values. The digital values ​​obtained by ADC 604 are forwarded to the input of linearity correction circuit 606.

[0074] Linearity correction circuit 606 includes digital logic configured or programmed to analyze the linearity of V2D converter 210 as the differential input voltage V in The decoder and timing logic 530 selectively drives the boost drivers 525A, 525B, 525C to adjust the boost impact at the intermediate output nodes INTP, INTM, and thus controls the common mode voltage at these nodes to compensate for the detected nonlinearity. Figure 6For example, the differential input voltage V in The linearity correction circuit 606 may be forwarded (directly or indirectly) to the calibration logic 340, which may periodically perform the operation of the linearity correction circuit 606 during normal operation of the V2D converter 210. Alternatively or in addition, the calibration logic 340 may be enabled to perform a calibration routine during a power-on reset routine or otherwise. Further, in an alternative scenario where the calibration logic 340 is enabled during a separate calibration routine, the linearity correction circuit 606 may analyze the nonlinearity of the V2D converter 210 based on a preset sequence of differential input voltages within an input range. In this case, the input voltage V in It does not have to be applied to ADC 604.

[0075] In which the common-mode voltage V is adjusted by controlling the boost capacitor CM_INT In the example of , an improved linearity of the V2D converter 210 can be obtained. In one embodiment evaluated by means of simulation, the quadratic gain characteristic of the dynamic amplifier input stage 310 is evaluated as:

[0076]

[0077] As is apparent from this equation (6a), this gain characteristic is dominated by negative square terms and is therefore compressive. Figure 4D Curve 450 in FIG. 4 shows one side of this compression gain characteristic (eg, for input voltage V in Similarly, according to Figure 5 and Figure 6 Example of calibrating the common mode voltage V CM_INT Afterwards, the quadratic gain characteristic of the instantiation of the constant current discharge stage 320 is evaluated as:

[0078]

[0079] Curve 452 shows that when the input voltage V in Thus, due to the close correspondence in the values ​​of the squared terms of opposite sign in equations (6a) and (6b), the expansion gain characteristic of the constant current discharge stage 320 closely compensates for the compression gain characteristic of the dynamic amplifier input stage 310. The combination of the two stages in the V2D converter 210 according to this example can provide good gain linearity with respect to the input voltage, such as Figure 4D Quantitatively, the nonlinearity of the dynamic amplifier input stage 310 shown by curve 450 is 50.2 dBc. On the other hand, the nonlinearity of the constant current discharge stage 320 shown by curve 452 is about 51 dBc, but in the opposite direction. In this example, the combination of the two stages in the V2D converter 210 shown by curve 455 is about 72 dBc, providing an improvement of about 20 dBc with proper calibration.

[0080] As described above, according to Figure 5 The V2D converter 210 of the example controls the common mode voltage V by controlling the boost capacitor applied at the intermediate output nodes INTP and INTM. CM_INT This control can calibrate the nonlinear compensation applied by the constant current discharge stage 320 to improve the linearity of the V2D stage 210. As described above, other parameters can be calibrated to control the square term coefficient of the quadratic gain characteristic of equation (3) for the constant current discharge stage 320. Figure 7 A constant current discharge stage 730 is shown that illustrates an example of such a calibration according to an alternative parameter. This alternative parameter is the source resistance R associated with the current source transistor 406.

[0081] Figure 7 The example of the constant current discharge stage 230 shown in includes a set of switches 710 associated with a set of resistors 715. At circuit ground, each switch 710 is coupled in series with its associated resistor 715 between the drain of the current source transistor 406 and its source. Figure 7 Three series connected networks of switches 710 and resistors 715 are shown coupled in parallel to each other. However, more or fewer networks of switches and resistors may be implemented. The resistors 715 may have different resistances, such as binary weighted, or may have the same resistance value.

[0082] The decoder and timing logic 730 has an input for receiving the calibration word CAL and a clock input for receiving the clock signal CLK_BOOST, as previously described. The decoder and timing logic 730 has an output coupled to an input of the boost driver 725, which has an output coupled to the bottom plate of the boost capacitors 420P, 420M. In addition, the decoder and timing logic 730 also has an output coupled to a control input of each switch 710.

[0083] In operation, the decoder and timing logic 730 receives a calibration word CAL, for example, from the calibration logic 340. In response to the value of the calibration word CAL, the decoder and timing logic 730 issues control signals to each switch 710. These control signals operate a corresponding each of the switches 710 to connect its associated resistor 715 in parallel with the source / drain path of the current source transistor 406 or to disconnect the associated resistor from the parallel connection of the source / drain path. The total source resistance R of the current source implemented by the transistor 406 is determined by the on-resistance R of the transistor 406 itself in parallel with one or more of the resistors 715 associated with the closed switch 710. on As described above with respect to equations (3) to (5), by using Figure 7The source resistance R is adjusted to control the square term coefficient B2 in the quadratic expression of the gain of the constant current discharge stage 320 and the input voltage.

[0084] In this example, if Figure 7 , the decoder and timing logic 730 can be used to drive the boost driver 725 in response to the clock signal CLK_BOOST. In this example, only a single instance of the boost capacitors 420P, 420M need be implemented by calibration of the source resistance R by the switch 710 and the resistor 715. The driving of the bottom plate of the boost capacitors 420P, 420M by the boost driver 725 slows down the common mode voltage V CM_INT discharge, thereby helping to maintain the circuit transistors in saturation.

[0085] Figure 8 An example of a portion 330P of a pulse generator 330 coupled between an input at an intermediate output node INTP and an output at an output terminal OUTP is shown. In this example, the pulse generator 330 as a whole also includes a similarly constructed portion 330M having an input at an intermediate output node INTM and an output at an output terminal OUTM.

[0086] like Figure 8 , the pulse generator portion 330P includes inverters 432P, 434P, 436P. Inverter 432P includes a PMOS transistor 840 and an NMOS transistor 842. Inverter 434P includes a PMOS transistor 850 and an NMOS transistor 852. Inverter 536P includes a PMOS transistor 860 and an NMOS transistor 862. In this example, the pulse generator portion 330P includes a set of switches 820 associated with a set of capacitors 825. At node B, each switch 820 and its associated capacitor 825 are coupled in series between the intermediate output node INTP and the output of inverter 434P. Figure 8 Three series connected switch 820 and capacitor 825 networks are shown coupled in parallel to each other. However, fewer or more switch and capacitor networks may be implemented. The capacitors 825 may have different capacitances, such as binary weighted, or may have the same capacitance as each other. The switches 820 each have a control input coupled to a corresponding output of the decoder and timing logic 830 so as to be independently controlled.

[0087] PMOS transistor 840 in inverter 432P has a voltage coupled to a power supply voltage V ddThe source of the inverter 434P is coupled to the drain of the NMOS transistor 842 at the output node A, and the gate is coupled to the gate of the NMOS transistor 842 at the intermediate output node INTP. The drain of the NMOS transistor 842 is at the circuit ground. The PMOS transistor 850 in the inverter 434P has a power supply voltage V coupled to the power supply voltage V dd 436P, and a drain coupled to the drain of NMOS transistor 852 at output node B. The source of NMOS transistor 852 is at circuit ground. The gate of NMOS transistor 852 is coupled to the output of inverter 432P at node A, and the gate of PMOS transistor 850 receives clock signal CLK_PULSE_RESET from clock circuitry 440. PMOS transistor 860 in inverter 436P has a gate coupled to power supply voltage V dd The source of MOSFET 861 is coupled to the drain of NMOS transistor 862 at output terminal OUTP, and the gate of MOSFET 862 is coupled to the gate of NMOS transistor 862 at output node B from inverter 434P. The drain of NMOS transistor 862 is at circuit ground.

[0088] In operation, the pulse generator portion 330P is reset by the clock circuitry 440 driving the clock signal CLK_PULSE_RESET to a low logic level, such as during the V2V phase of a conversion cycle of the V2D converter 210 ( Figure 4B ). The low level of the clock signal CLK_PULSE_RESET turns on the PMOS transistor 850 of the inverter 434P and forces the output node B to be the power supply voltage V dd Inverter 436P drives output terminal OUTP to a low logic level. In the reset phase of the conversion cycle ( Figure 4B ), the intermediate output node INTP is precharged to the power supply voltage V dd , causing the output node A to be pulled to ground by the NMOS transistor 842.

[0089] When the intermediate output nodes INTP, INTM discharge in a conversion cycle, one of those nodes that discharges first to the input threshold voltage of the inverter 432P, 432M, as the case may be, causes the inverter to change state. However, the transition at the output of the inverter can be coupled back to its corresponding input. For example, referring to Figure 8 The low-to-high transition at the output node A of the inverter 432P can be coupled back to the inverter input at the intermediate output node INTP as a positive polarity noise pulse. It has been observed that this noise due to coupling at the pulse generator 330 can degrade the linearity of the V2D converter 210.

[0090] supply Figure 8The "kickback" capacitor 825 in the example of the embodiment is used to eliminate the effect of the noise caused by the switching of the inverter 432P. The decoder and timing logic 830 closes one or more of the switches 820 and couples the corresponding one or more of the capacitors 825 between the intermediate output node INTP and the output node B of the inverter 434P. Because the inverter 434P performs a transition opposite to the transition performed by the inverter 432P, in response to the transition from low to high at the output node A, a transition from high to low is presented at the output node B. By coupling one or more capacitors 825 between the intermediate output node INTP and the output node B, this transition from high to low at the output node B is coupled back to the intermediate output node INTP, thereby providing a noise pulse of opposite polarity caused by the transition of the inverter 432P. Therefore, the linearity of the V2D converter 210 is improved by this example.

[0091] The capacitive coupling of the kickback capacitor 825 may be calibrated, for example, by the calibration logic 340 generating a corresponding calibration word CAL2 to the decoder and timing logic 830, such as Figure 8 This calibration may be performed periodically during normal operation of the V2D converter 210 or alternatively (or additionally) during a calibration routine (eg, during a power-on reset).

[0092] Fig. 9 An exemplary method of converting an input voltage into a delay domain signal is shown, such as may be performed by an ADC 200 including a T2D converter 210. The following description of this exemplary method refers to the above description with respect to Figure 4A and specific components of ADC 200 and T2D converter 210 described below.

[0093] Fig. 9 An exemplary method shows that the input voltage V in The conversion of a sample of, for example, may be performed by ADC 200 in a manner that includes Figure 4B The operations mentioned are performed within a conversion cycle. For example, at a selected sampling or data rate corresponding to the incoming communication bit stream or data stream for additional samples Fig. 9 Continued operation of the exemplary method may continue by repeating the exemplary method in a loop.

[0094] Fig. 9 The conversion cycle operation begins at process block 900, where the top plates of the integrating capacitors 404P and 404M are charged to, for example, a supply voltage V dd At or near Figure 4A and 4B, process block 900 is performed by reset transistors 402P, 402M, 402B being turned on by clock signal CLK_RST from clock circuit system 440. During this process block 900, the top plates of integration capacitors 404P, 404M and also boost capacitors 420P, 420M are driven toward supply voltage V by reset transistors 402P, 402M, 402B. dd Charge.

[0095] In process block 902, a differential input voltage V is applied to input terminals INP and INM. in The clock circuit system 440 also turns off the reset transistors 402P, 402M, 402B and turns on the transistors 408P and 408M. This allows the input transistors 412P, 412M to be switched on according to the differential input voltage V at the input terminals INP, INM. in The top plates of the integrating capacitors 404P, 404M are differentially discharged toward circuit ground. The differential voltage at the intermediate output nodes INTP, INTM is presented as a result. Process block 902 corresponds to Figure 4B The V2V phase of the conversion cycle.

[0096] In process block 904, the constant current discharge stage 320 of the V2D converter 210 discharges the bottom plates of the integrating capacitors 404P, 404M toward circuit ground through the transistor 405 and the current source transistor 406. Process block 904 in this example is initiated by the clock signal CLK_V2D from the clock circuit system 440 turning on the transistor 405, thereby initiating the above process block 904 with respect to the circuit ground. Figure 4B In process block 904, the total discharge current from the bottom plates of the integrating capacitors 404P, 404M is controlled by the current source transistor 406 in response to the regulated voltage NBIAS_V2D applied to its gate. Controlling the conduction of the current source transistor 406 by the regulated voltage NBIAS_V2D maintains this total discharge current as a function of the differential input voltage V in The changes are roughly constant.

[0097] During operation of process block 904 in the V2D phase, a drive signal CLK_BOOST may also be applied at the input of the boost driver 425 to control the common mode voltage V at the intermediate output nodes INTP, INTM. CM_INT , as described above. Signal CLK_BOOST may be initiated by clock circuitry 440 during the V2V phase (eg, during process block 902), as described above with respect to Figure 4B described.

[0098] The constant current discharge from the bottom plates of the integrating capacitors 404P, 404M in process block 904 continues to discharge the voltage at the intermediate output nodes INTP, INTM toward the circuit ground while maintaining the differential voltage across these nodes. When the voltage at the intermediate output nodes INTP, INTM is discharged to the input threshold voltage of the inverters 432P, 432M, respectively, a corresponding pair of pulses (e.g., from low to high logic level transitions) is generated by the pulse generator 330 at the output terminals OUTP, OUTM, respectively, to perform process block 906. The relative delay ΔT between the leading edges of the pulses at the output terminals OUTP, OUTM corresponds to the polarity and magnitude of the differential input voltage applied at the input terminals INTP, INTM.

[0099] In process block 908, TDC converter 220 outputs D out A digital output word corresponding to the relative delay ΔT of the pulses at the output terminals OUTP, OUTM as generated in process block 906 is generated. The manner in which the delays in these pulses are converted into a digital output word depends on the specific construction and arrangement of the TDC converter 220. Examples of architectures that can be used in the TDC converter 220 are described in the U.S. patents and publications incorporated above.

[0100] As described above, the constant current discharge stage 320 may be calibrated to operate in process block 904 according to a gain characteristic having a nonlinear behavior that is opposite to and thus compensates for the nonlinearity of the gain characteristic of the dynamic amplifier input stage 310. In the example described above, this calibration involves adjusting the common mode voltage V including the intermediate output nodes INTP, INTM. CM_INT , the source resistance R of the constant current discharge current source, and other parameters. Adjustment of one or more of these parameters can adjust the square term coefficient in the quadratic gain characteristic of the constant current discharge stage 320 to match the characteristics of the dynamic amplifier input stage 310, but with opposite signs. This calibration can be performed at manufacturing time, at power-up or in other reset routines, or periodically during normal operation of the ADC 200. In any case, this calibration of the gain of the constant current discharge stage 320 is performed at Fig. 9 The exemplary method begins at process block 910 .

[0101] In process block 910, the pulses at the output terminals OUTP, OUTM are applied to the inputs of the calibration logic 340. In this example, process block 910 includes measuring the duty cycle of the pulses at the output terminals OUTP, OUTM by the measurement circuit 602 to produce analog values ​​at its outputs DCP, DCM. The ADC 604 converts these analog levels into digital values ​​and forwards those digital values ​​to the linearity correction circuit 606. And, in process block 910, the linearity correction circuit 606 responds to the input values ​​(e.g., the differential input voltage V as forwarded to the ADC 604) relative to the input values. in , or based on a stored reference value of a programmed calibration routine) to generate a calibration word CAL.

[0102] As mentioned above, Fig. 9 Calibration is performed by one or more of the various parameters shown in process blocks 912A, 912B, 912C. Figure 5 In the described example corresponding to process block 912A, the calibration word CAL is used to select one or more boost capacitors 520PA, 520PB and 520PC and one or more boost capacitors 520MA, 520MB, 520MC to be driven by the corresponding boost drivers 525A, 525B, 525C, and thus adjust the common mode voltage V CM_INT . In contrast to the above Figure 7 The depicted example corresponds to process block 912B in which the calibration word CAL is used to close one or more of the switches 710 to include a corresponding one or more of the resistors 715 into the effective source resistance R of the current source transistor 406 in the constant current discharge stage 720 .

[0103] Additionally, process block 912C may additionally be performed, for example, in response to the same or different calibration word CAL2 generated in process block 910. Process block 912C is performed to close one or more of switches 820 to include a corresponding one or more of capacitors 825 as a “kickback” capacitor at pulse generator 330, as described above in Figure 8 Described in the example of .

[0104] After performing one or more of the calibration process blocks 912A, 912B, 912C, operation of the V2D converter 210 may continue, for example, from operation of the constant current discharge stage 320 in process block 904 .

[0105] One or more exemplary technical advantages may be achieved according to the described examples. Using a boost capacitor at the constant current discharge stage helps maintain the input stage transistors in saturation and control the output common mode voltage. Improved noise performance, reduced sensitivity to input transistor mismatch, and improved current source margin may be achieved. Calibration of the constant current discharge block achieves improvement in the linearity of the T2D stage by providing a gain characteristic that eliminates nonlinearity in the input stage, providing good linearity in variations in process, voltage, and temperature.

[0106] One or more examples described in this specification are implemented into a delay domain analog-to-digital converter because it is considered that such an implementation is particularly advantageous in the described context. However, it is also considered that aspects of these examples can be beneficially applied to other applications operating in the delay domain. Therefore, it should be understood that the following description is provided by way of example only and is not intended to limit the true scope of the claimed invention.

[0107] As used herein, the terms "terminal", "node", "interconnection" and "pin" are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their terminals.

[0108] Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

[0109] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0110] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually only include semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party. Although in some exemplary embodiments certain elements are included in the integrated circuit and other elements are outside the integrated circuit, in other exemplary embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit may be included in the integrated circuit, and / or some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0111] The circuits described herein can be reconfigured to include replaced components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively. Components shown as switches may be implemented as single transistors controlled by gate voltages, parallel couplings and complementary gate voltages controlled, or complementary transistors controlled by other devices and circuits suitable for related manufacturing technologies.

[0112] Use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0113] Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

1. A voltage-delay converter circuit, comprising: a first reset transistor having a first terminal coupled to the power supply terminal and having a gate terminal coupled to receive a reset signal; a first integrating capacitor having a first terminal coupled to the second terminal of the first reset transistor and having a second terminal; a second reset transistor having a first terminal coupled to the power supply terminal and having a gate terminal coupled to receive the reset signal; a second integrating capacitor having a first terminal coupled to the second terminal of the second reset transistor and having a second terminal; a first current source having a first terminal coupled to a common potential; a first input transistor having a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the first integrating capacitor, and a gate terminal coupled to receive a first input voltage; a second input transistor having a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the second integrating capacitor, and a gate terminal coupled to receive a second input voltage; a discharge current source having a first terminal coupled to a second terminal of each of the first integrating capacitor and the second integrating capacitor, and a second terminal coupled to the common potential; as well as A pulse generator has a first input coupled to the first terminal of the first integrating capacitor, a second input coupled to the first terminal of the second integrating capacitor, and first and second outputs.

2. The voltage-delay converter circuit according to claim 1, further comprising: a first boost capacitor having a first terminal coupled to the first terminal of the first integrating capacitor and having a second terminal; a second boost capacitor having a first terminal coupled to the first terminal of the second integrating capacitor and having a second terminal; as well as A boost driver has an output coupled to the second terminal of each of the first boost capacitor and the second boost capacitor.

3. The voltage-delay converter circuit of claim 2, wherein the boost driver has an input coupled to receive a boost clock signal; And the voltage-delay converter circuit further comprises: Clock circuitry is provided for generating the boosted clock signal.

4. The voltage-delay converter circuit of claim 2, wherein the first boost capacitor is one of a first plurality of boost capacitors, the first plurality of boost capacitors each having a first terminal coupled to the first terminal of the first integrating capacitor and having a second terminal; wherein the second boost capacitor is one of a second plurality of boost capacitors, the second plurality of boost capacitors each having a first terminal coupled to the first terminal of the second integrating capacitor and having a second terminal; wherein the boost driver is one of a plurality of boost drivers, the plurality of boost drivers each having an output coupled to the second terminal of one of the first plurality of boost capacitors and one of the second plurality of boost capacitors; And the voltage-delay converter circuit further comprises: A decoder and timing logic having a plurality of outputs each coupled to an input of one of the plurality of boost drivers, having a clock input coupled to receive a boost clock signal, and having a digital input coupled to receive a calibration signal.

5. The voltage-delay converter circuit according to claim 4, further comprising: Calibration logic having one or more outputs coupled to the decoder and the digital inputs of timing logic, the calibration logic configured to generate the calibration signal in response to pulses at the first and second outputs of the pulse generator.

6. The voltage-delay converter circuit according to claim 1, further comprising: Multiple resistors; a plurality of switches, each switch coupled in series with one of the plurality of resistors across the first terminal and the second terminal of the discharge current source, each switch having a control terminal; as well as A decoder and timing logic having a plurality of outputs each coupled to a control terminal of one of the plurality of switches and having a digital input coupled to receive a calibration signal.

7. The voltage-delay converter circuit of claim 1 , wherein the pulse generator comprises: a first series inverter having an input coupled to the first terminal of the first integrating capacitor; And the voltage-delay converter circuit further comprises: a first plurality of kickback capacitors; a first plurality of switches each coupled in series with one of the first plurality of kickback capacitors between the first terminal of the first integrating capacitor and an output of one of the first series of inverters of the pulse generator, each switch having a control terminal; and A decoder and timing logic having a plurality of outputs each coupled to a control terminal of one of the first plurality of switches and having a digital input coupled to receive a calibration signal.

8. The voltage-delay converter circuit of claim 1 , wherein the pulse generator further comprises: a second series inverter having an input coupled to the first terminal of the second integrating capacitor; And the voltage-delay converter circuit further comprises: a second plurality of kickback capacitors; as well as a second plurality of switches each coupled in series with one of the second plurality of kickback capacitors between the first terminal of the second integrating capacitor and an output of one of the second series of inverters of the pulse generator, each switch having a control terminal; Wherein the decoder and timing logic have a plurality of outputs, each output coupled to a control terminal of one of the second plurality of switches.

9. The voltage-delay converter circuit according to claim 1, further comprising: a first clock transistor having a first terminal coupled to the first terminal of the first integrating capacitor, a second terminal coupled to the first terminal of the first input transistor, and having a first terminal coupled to receive a a gate terminal for a first clock signal; a second clock transistor having a first terminal coupled to the first terminal of the second integrating capacitor, a second terminal coupled to the first terminal of the second input transistor, and having a gate terminal coupled to receive the first clock signal; a third clock transistor having a first terminal and a second terminal coupled in series with the first current source between the first terminals of the first input transistor and the second input transistor and the common potential, and having a gate terminal coupled to receive a second clock signal; A clock circuit system is used to generate the first clock signal, the second clock signal and the reset signal.

10. The voltage-delay converter circuit according to claim 9, further comprising: a fourth clock transistor having a first terminal coupled to the second terminals of the first and second integrating capacitors, a second terminal coupled to the discharge current source, and a gate terminal coupled to receive a third clock signal; The clock circuit system is further configured to generate the third clock signal.

11. A method comprising: charging a first plate of each of the first integrating capacitor and the second integrating capacitor to a first voltage; applying a differential voltage across a first input and a second input, the first input being coupled to a gate terminal of a first transistor coupled between the first plate of the first integrating capacitor and a reference potential, and the second input being coupled to a gate terminal of a second transistor coupled between the first plate of the second integrating capacitor and the reference potential; discharging a second plate of each of the first integrating capacitor and the second integrating capacitor toward the reference potential; as well as then generating first and second pulses having relative delays corresponding to voltages at the first plates of the first and second integrating capacitors; as well as A digital output word is generated corresponding to the relative delay of the first pulse and the second pulse.

12. The method according to claim 11, further comprising: During the discharge, a boost voltage is applied to a second plate of each of a first boost capacitor and a second boost capacitor, each having a first plate coupled to the first plate of the first integrating capacitor and the second integrating capacitor, respectively.

13. The method of claim 12, wherein the first boost capacitor is one of a first plurality of boost capacitors, the first plurality of boost capacitors each having a first plate coupled to the first plate of the first integrating capacitor; wherein the second boost capacitor is one of a second plurality of boost capacitors, the second plurality of boost capacitors each having a first plate coupled to the first plate of the second integrating capacitor; and wherein said applying of a boost voltage applies said boost voltage to one or more selected boost capacitors of each of said first plurality of boost capacitors and said second plurality of boost capacitors; And the method further comprises: generating a calibration signal in response to the relative delay of the first pulse and the second pulse; as well as In response to the calibration signal, one or more boost capacitors are selected from each of the first plurality of boost capacitors and the second plurality of boost capacitors.

14. The method of claim 11, further comprising during the discharging: generating a calibration signal in response to the relative delay of the first pulse and the second pulse; selecting one or more of each of a first plurality of kickback capacitors and a second plurality of kickback capacitors in response to the calibration signal; coupling a selected one of the first plurality of kickback capacitors to the first plate of the first integrating capacitor; as well as A selected one of the second plurality of kickback capacitors is coupled to the first plate of the second integrating capacitor.

15. The method of claim 11, wherein the discharging comprises discharging the first integrating capacitor and the second plate of the second integrating capacitor via a discharge current source; And the method further comprises: generating a calibration signal in response to the relative delay of the first pulse and the second pulse; as well as In response to the calibration signal, one or more resistors are selected for coupling across the first terminal and the second terminal of the discharge current source.

16. An analog-to-digital converter, comprising: A voltage-delay converter comprising: a first reset transistor having a first terminal coupled to the power supply terminal and having a gate terminal coupled to receive a reset signal; a first integrating capacitor having a first terminal coupled to the second terminal of the first reset transistor and having a second terminal; a second reset transistor having a first terminal coupled to the power supply terminal and having a gate terminal coupled to receive the reset signal; a second integrating capacitor having a first terminal coupled to the second terminal of the second reset transistor and having a second terminal; a first current source having a first terminal coupled to a common potential; a first input transistor having a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the first integrating capacitor, and a gate terminal coupled to receive a first input voltage; a second input transistor having a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the second integrating capacitor, and a gate terminal coupled to receive a second input voltage; a discharge current source having a first terminal coupled to a second terminal of each of the first and second integrating capacitors, and a second terminal coupled to the common potential; and a pulse generator having a first input coupled to the first terminal of the first integrating capacitor, a second input coupled to the first terminal of the second integrating capacitor, and first and second outputs; and a delay-to-digital converter having first and second inputs coupled to the first and second outputs of the pulse generator, respectively, and having a digital output, the delay-to-digital converter being configured to produce a digital output word corresponding to a relative delay between pulses at the first and second outputs of the pulse generator.

17. The analog-to-digital converter of claim 16, wherein the voltage-delay converter further comprises: a first plurality of boost capacitors each having a first terminal coupled to the first terminal of the first integrating capacitor and having a second terminal; a second plurality of boost capacitors each having a first terminal coupled to the first terminal of the second integrating capacitor and having a second terminal; a plurality of boost drivers each having an output coupled to the second terminal of one of the first plurality of boost capacitors and one of the second plurality of boost capacitors; as well as A decoder and timing logic having a plurality of outputs each coupled to an input of one of the plurality of boost drivers, having a clock input coupled to receive a boost clock signal, and having a digital input coupled to receive a calibration signal.

18. The analog-to-digital converter of claim 16, wherein the voltage-delay converter further comprises: a first boost capacitor having a first terminal coupled to the first terminal of the first integrating capacitor and having a second terminal; a second boost capacitor having a first terminal coupled to the first terminal of the second integrating capacitor and having a second terminal; as well as A boost driver has an output coupled to the second terminal of each of the first boost capacitor and the second boost capacitor.

19. The analog-to-digital converter of claim 18, wherein the voltage-delay converter further comprises: Multiple resistors; a plurality of switches, each switch coupled in series with one of the plurality of resistors across the first terminal and the second terminal of the discharge current source, each switch having a control terminal; as well as A decoder and timing logic having a plurality of outputs each coupled to a control terminal of one of the plurality of switches and having a digital input coupled to receive a calibration signal.

20. The analog-to-digital converter of claim 16, wherein the pulse generator comprises: a first series inverter having an input coupled to the first terminal of the first integrating capacitor; as well as a second series inverter having an input coupled to the first terminal of the second integrating capacitor; And wherein the voltage-delay converter further comprises: a first plurality of kickback capacitors; a first plurality of switches each coupled in series with one of the first plurality of kickback capacitors between the first terminal of the first integrating capacitor and an output of one of the first series of inverters of the pulse generator, each switch having a control terminal; and a second plurality of kickback capacitors; and a second plurality of switches each coupled in series with one of the second plurality of kickback capacitors between the first terminal of the second integrating capacitor and an output of one of the second series of inverters of the pulse generator, each switch having a control terminal; A decoder and timing logic having a plurality of outputs each coupled to a control terminal of one of the first plurality of switches and the second plurality of switches and having a digital input coupled to receive a calibration signal.

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