System and method for multi-dimensional to analog converter (DAC)

Abstract

The invention relates to a system and method for a multi-dimensional to analog converter (DAC). An apparatus may include a DAC including: a current source; circuitry to mirror the current source, the circuitry including transistors coupled to the current source, and a plurality of output paths, each of the plurality of output paths including a first switch to selectively configure a first transistor to mirror the current source, and a second switch to selectively configure a second transistor to mirror the current source, wherein each output path corresponds to a value of a respective bit of the first digital signal; and a plurality of cells, each of the plurality of cells including a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, where each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.

Description

Technical Field

[0001] The present disclosure relates generally to systems and methods for digital-to-analog converters (DACs), and more particularly to multi-dimensional DACs implemented by mirroring current sources in a reliable and efficient manner. Background Art

[0002] In an integrated circuit system, a DAC (e.g., a current-steering DAC) can be implemented by mirroring or replicating the current flowing in a circuit branch and generating an output current in an output branch. A multidimensional DAC can generate an output current that is multiplied in terms of two or more input control words. Such a multidimensional DAC can be implemented using multiple input control signals and a continuous current mirror, however, it is susceptible to power supply noise and requires added area and power consumption. Summary of the invention

[0003] On the one hand, the present disclosure relates to a digital-to-analog converter (DAC), comprising: a current source; a circuit system for mirroring the current source, the circuit system comprising a transistor coupled to the current source, and a plurality of output paths; each of the plurality of output paths comprising a first switch to selectively configure a first transistor to mirror the current source, wherein each output path corresponds to a value of a corresponding bit of a first digital signal; and a plurality of cells, each of the plurality of cells comprising a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, wherein each of the plurality of cells corresponds to a value of a corresponding bit of a second digital signal.

[0004] On the other hand, the present disclosure relates to a system comprising: a current source; a transistor coupled to the current source; a first digital-to-analog converter (DAC) comprising a plurality of first cells, each of the plurality of first cells comprising a first switch to selectively configure a first transistor to mirror the current source corresponding to a value of a corresponding bit of a first digital signal; and a second DAC comprising a plurality of second cells, each of the plurality of second cells comprising a second switch to selectively couple a second transistor to a corresponding one of the plurality of first cells corresponding to a value of a corresponding bit of a second digital signal, wherein the first DAC and the second DAC are configured to output a current corresponding to a result of multiplying the value of the first digital signal by the value of the second digital signal.

[0005] On the other hand, the present disclosure relates to a circuit system comprising: a current source; a transistor coupled to the current source; an output path comprising a first switch to selectively configure the first transistor to mirror the current source corresponding to a bit of a first digital signal; and a plurality of cells, each of the plurality of cells comprising a second switch to selectively couple a second transistor to the output path, wherein each of the plurality of cells corresponds to a value of a corresponding bit of the second digital signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description in conjunction with the accompanying drawings, in which like reference characters always identify corresponding elements. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0007] Figure 1 is a schematic diagram of a conventional current mirror.

[0008] Figure 2 is a schematic diagram of an example apparatus according to some embodiments.

[0009] Figure 3 is an equivalent schematic diagram of an apparatus according to some embodiments.

[0010] Figure 4 is a schematic diagram of an example apparatus according to some embodiments.

[0011] Figure 5 is a flow chart of an example process for operating a device according to some embodiments.

[0012] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0013] The disclosure below provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, in various examples, the present disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0014] Various embodiments disclosed herein relate to a device, system, circuit system, or DAC, which includes a current source, a circuit system for mirroring the current source (e.g., the current generated by the current source), and a plurality of units. In some embodiments, the DAC may be or include a circuit, circuit system, device, system, or any component that can convert a digital signal into an analog signal.

[0015] In some embodiments, a current source may be or include a circuit, circuit system, or any component that generates a current (e.g., a reference current, an input current, etc.) that may be independent of a voltage across the current source. The current source may be electrically coupled to a transistor of the circuit system (hereinafter referred to as a reference transistor) and provide current thereto. In some embodiments, the current source may be electrically coupled to a voltage supply. For example, the current source may be electrically coupled to a gate voltage (e.g., an N bias voltage for an N metal oxide semiconductor (MOS) device, a P bias voltage for a P-MOS device, etc.). In some embodiments, the current source may generate a constant and / or precise current.

[0016] In some embodiments, the circuit system or current mirror circuit described herein may be or include a circuit, circuit system, or any circuit system component that can replicate a current (e.g., a reference current, an input current, etc.) through an active device by controlling a current in another active device, keeping an output current constant regardless of the load. The circuit system or current mirror circuit may include a reference transistor and multiple output paths. The circuit system may output an output current (e.g., a mirrored current) in response to the reference transistor receiving current from a current source.

[0017] In some embodiments, the reference transistor may be a semiconductor device (e.g., a bipolar junction transistor (BJT), a MOS field effect transistor (MOSFET), etc.) or any transistor that can control the current of a device. In some embodiments, the reference transistor may be coupled to a current source and receive current from the current source. In response to receiving current from the current source, the reference transistor may provide a signal (e.g., a voltage signal) to a plurality of output paths.

[0018] In some embodiments, any of the plurality of output paths may be or form a circuit, circuit system, or any component that outputs at least a portion of an output current (e.g., a mirrored current) in response to a reference transistor receiving current from a current source. The plurality of output paths may combine to output the output current to mirror a current (e.g., an input current, a reference current) from a current source. Each of the plurality of output paths may include a switch (e.g., a first switch) and a transistor (e.g., a first transistor). In some examples, the output current may be an output signal of a DAC that is an output in response to receiving an input current.

[0019] In some embodiments, the first transistor may be a semiconductor device (e.g., a BJT, a MOSFET, etc.), or any transistor that can control the current flowing in the corresponding output path. In some embodiments, the first transistor may be substantially similar or identical to the reference transistor. The first transistor may control the flow of current in response to receiving a signal (e.g., a voltage signal) from the reference transistor. In some embodiments, the first transistor may be coupled to the second transistor.

[0020] In some embodiments, the first switch may be any semiconductor device (e.g., BJT, MOSFET, etc.), any semiconductor diode, any semiconductor switch, or any component that can control the flow of current of the corresponding output path to which the first switch is coupled. The first switch can control the flow of current in the corresponding output path, thereby selectively configuring the first transistor (or a group of transistors including the first transistor and the second transistor) to output a portion of the output current (e.g., a mirrored current), which can be combined into the output current. The first switch can be controlled to determine whether the corresponding output path is closed or open (e.g., allowing the current in the corresponding output path to flow or not flow). When the first switch is closed (or turned on), the first switch allows the corresponding current (e.g., the current from the first transistor, the sum of the currents from the first transistor and the second transistor, etc.) to flow through the corresponding output path and be combined into the output current (e.g., the mirrored current). When the first switch is open (or turned off), the first switch disconnects the corresponding output path and prevents the corresponding current (e.g., the current from the first transistor, the sum of the currents from the first transistor and the second transistor, etc.) from being combined into the output current (e.g., the mirrored current). By controlling which first switches are open or closed, the device can output an output current (eg, a current mirrored to the input current) by the sum of currents from the output paths in which the first switches are closed.

[0021] In some embodiments, each of the plurality of output paths may correspond to the value of a corresponding bit of the first signal. In some embodiments, the first signal may be a digital signal, a logic signal, a binary signal, or any signal that can represent data as a sequence of discrete values. The first signal may include a corresponding bit to control a first switch of each of the plurality of output paths. The first signal may control the output current of the current mirror circuit. In some embodiments, the circuit system or current mirror circuit described herein may form a DAC. The first signal may be an input signal of the DAC and may control the output signal of the DAC (e.g., the output current of the current mirror circuit). When the DAC includes X output paths, the output of the DAC (e.g., the output current of the current mirror circuit) may be controlled by the input signal of the DAC, e.g., the first signal DAC1<1:x>. For example, the first output path may be controlled by the first signal (e.g., DAC1 <1> ) and the xth output path can be controlled by the xth signal (e.g., DAC1 <x>For example, the output current may be an output signal of a DAC, which is an output in response to receiving an input current.

[0022] In some examples, the first switch may be configured to selectively couple the first transistor to the corresponding output path so that the first transistor outputs a current corresponding to the value of the corresponding bit of the first digital signal. In some embodiments, the output current (e.g., mirrored current) may be output by selectively configuring each first transistor of the plurality of output paths. In some embodiments, the first signal indicates a unary code, which may be a thermometer code, a prefix-free code, a self-synchronizing code, or any code representing a natural number having a length code.

[0023] In some embodiments, each of the plurality of output paths may include a plurality of cells electrically coupled to a corresponding first transistor. As described herein, any of the plurality of cells may be or include a circuit, a circuit system, or any circuit system component including a pair of transistors and a switch. Each of the plurality of cells includes a second switch and a second transistor. The second transistor may be a semiconductor device (e.g., a BJT, a MOSFET, etc.), or any transistor that can control the flow of current in response to a received signal (e.g., a voltage signal). In some embodiments, the second transistor may be substantially similar or identical to the first transistor and / or the reference transistor. The second transistor may provide the generated signal to the corresponding output path to which the second transistor is coupled. For example, the second transistor may be controlled to output a second current, which may be combined with the first current output from the first transistor coupled in the corresponding output path. By closing (or turning on) the first switch, the combined current may flow into the corresponding output path.

[0024] The second switch may be any semiconductor device (e.g., BJT, MOSFET, etc.), any semiconductor diode, any semiconductor switch, or any component that can control the flow of current in the current path to which the second switch is coupled. As described herein, the current path may be or include a circuit, a circuit system, or any circuit system component through which current can flow. The second switch may be coupled to the second transistor and may control the flow of current in the corresponding path, thereby selectively configuring whether the current output from the second transistor is combined into the output current in the corresponding output path (e.g., mirrored current). That is, the second switch may selectively couple the second transistor to the corresponding output path and allow the current output from the second transistor to be combined with the current output from the first transistor. The second switch may be controlled to determine whether the corresponding path is closed or open (e.g., allowing the current in the corresponding path to flow or not flow). When the second switch is closed, the second switch allows the corresponding current (e.g., the current from the second transistor) to flow through the corresponding output path and is combined with the current from the first transistor, thereby outputting a portion of the output current (e.g., mirrored current), which flows from the corresponding output path in a plurality of paths. When the second switch is open, the second switch disconnects the corresponding output path and prevents the corresponding current (e.g., the current from the second transistor) from combining with the current from the first transistor (or combining into the output current). By controlling which second switches are open or closed, the device can determine the amount of current that combines with the current from the first transistor.

[0025] In some embodiments, each of the plurality of cells may correspond to a value of a corresponding bit of a second signal (e.g., a second digital signal, etc.). In some embodiments, the second signal may be a digital signal, a logic signal, a binary signal, or any signal that can represent data as a sequence of discrete values. The second switch of each of the plurality of cells may be controlled by a second signal (e.g., a second digital signal), which may include a corresponding bit to control a corresponding switch (e.g., a second switch). In some embodiments, when an output path in the plurality of paths includes a first transistor and a first switch coupled to Y cells including Y second transistors and Y second switches, a current from a first transistor of the Y second transistors (and / or a first switch of the Y second switches) may be controlled by a signal DAC2 <1> The current from the yth transistor among the Y second transistors (and / or the yth switch among the Y second switches) can be controlled by the signal DAC2 <y>In some embodiments, in response to the second switch of each of the plurality of cells selectively coupling the second transistor to a corresponding one of the plurality of output paths, the second transistor may be configured to output a current based on a value of a corresponding bit of the first digital signal and / or a value of a corresponding bit of the second digital signal. In some embodiments, the second signal indicates a unary code.

[0026] In some embodiments, the second switches in the plurality of cells of the plurality of output paths may share the same digital signal. For example, the plurality of cells in the first output path of the plurality of output paths may receive the second signal DAC2<1:y>, and the plurality of cells in any output path of the plurality of output paths may receive the same second signal DAC2<1:y>. For example, each of the first cells in the plurality of output paths may receive DAC2 <1> , each of the second units in the plurality of output paths may receive DAC2 <2> , and each of the y-th second units in the plurality of output paths can receive DAC2 <y>As discussed above, the current contribution of multiple cells in each of the multiple output paths to the output current (e.g., the mirrored current) can be controlled by a first signal, such as DAC1<1:x>. For example, multiple cells in a first output path of the multiple output paths can be controlled by the first signal DAC1<1:x>. <1> Control, the plurality of units in the second output path of the plurality of output paths can be controlled by the first signal DAC1 <2> The first signal DAC1 is used to control the multiple units in the x-th output path of the multiple output paths. <x>control.

[0027] In some examples, multiple cells within each of the multiple output paths may be integrated into a macro cell or a structure including a first corresponding transistor and a first corresponding switch.

[0028] In some embodiments, the plurality of output paths and the plurality of cells may be configured to output a current corresponding to the result of multiplying the value of the first digital signal by the value of the second digital signal (e.g., DAC1·DAC2). For example, the output current may be a function of the result of multiplying the value of the first digital signal by the value of the second digital signal. For example, the output current I out Can where M is the ratio constant associated with the transistor, and I in is the current generated by a current source (eg, a reference source). This allows multi-dimensional control of the output current by independently adjusting signals DAC1 and DAC2.

[0029] In some embodiments, the plurality of output paths and the plurality of cells may be configured to output current by weighting at least one of the current from any of the plurality of output paths or the current from any of the plurality of cells. The weighting may be controlled by a first signal (received by a first switch, such as DAC1) and / or a second signal (received by a second switch, such as DAC2). For example, the weighting may be controlled by at least one of a step size, a relative signal size, a signal range, etc. The output current I output by weighting out Can be defined as:

[0030]

[0031] Where x is the DAC1 input code indicating the first signal (e.g., DAC1), y is the DAC2 input code indicating the second signal (e.g., DAC2), I unit isI in / M, N is the gain factor of DAC1, P is the gain factor of DAC2, α j is the weight of the jth DAC1 of multiple output paths, and α k is the weight of the kth of the multiple units.

[0032] In some embodiments, the devices disclosed herein may be or include a DAC configured to output a mirrored current of a current source (e.g., a reference current, an input signal, etc.). In response to receiving as input a first signal (e.g., DAC1) and a second signal (e.g., DAC2), the DAC may output the mirrored current as an output. For example, the first signal may be a first digital signal for coarsely tuning the output of the DAC, and the second signal may be a second digital signal for finely tuning the output of the DAC.

[0033] In some embodiments, a plurality of output paths and / or a plurality of cells may include a first circuit system and a second circuit system. The first circuit system includes a third transistor coupled to a plurality of third switches corresponding to the plurality of cells. For example, each of the plurality of third switches may be electrically coupled to each corresponding cell in the plurality of cells. The first circuit system may mirror a current flowing through a first current path, which may be used to output an output current (e.g., a mirrored current). Each of the plurality of third switches may be configured to selectively couple a corresponding cell in the plurality of cells to the first current path based on the value of a corresponding bit of the second digital signal, so that the output current may be provided to the corresponding output path through the first current path.

[0034] The second circuit system includes a fourth transistor coupled to a plurality of fourth switches corresponding to the plurality of cells. For example, each of the plurality of fourth switches may be electrically coupled to each corresponding cell in the plurality of cells. The second circuit system may provide a second current path. Each of the plurality of fourth switches may be configured to selectively couple a corresponding cell in the plurality of cells to the second current path based on the value of a corresponding bit of the second digital signal. The current provided by the second current path may not be used.

[0035] In some embodiments, when a cell among the plurality of cells receives a bit of a second digital signal having a first value (e.g., 1, 0), a third switch in the cell may be configured to couple a corresponding cell among the plurality of cells to the first current path, and a fourth switch in the cell may be configured to disconnect a corresponding cell among the plurality of cells from the second current path. That is, in response to determining that the bit of the second digital signal has the first value, a third switch among the plurality of third switches corresponding to the bit of the second digital signal may be configured to couple a corresponding cell among the plurality of cells to the first current path, and a fourth switch among the plurality of fourth switches corresponding to the bit of the second digital signal may be configured to disconnect a corresponding cell among the plurality of cells from the second current path.

[0036] In some embodiments, when a cell among the plurality of cells receives a bit of a second digital signal having a second value (e.g., 0, 1), a third switch in the cell may be configured to disconnect a corresponding cell among the plurality of cells from the first current path, and a fourth switch in the cell may be configured to couple a corresponding cell among the plurality of cells to the second current path. That is, in response to determining that the bit of the second digital signal has the second value, a third switch among the plurality of third switches corresponding to the bit of the second digital signal may be configured to disconnect a corresponding cell among the plurality of cells from the first current path, and a fourth switch among the plurality of fourth switches corresponding to the bit of the second digital signal may be configured to couple a corresponding cell among the plurality of cells to the second current path.

[0037] Various embodiments disclosed herein are directed to a system comprising: a current source; a transistor coupled to the current source; a first digital-to-analog converter (DAC) comprising a plurality of first cells, each of the plurality of first cells comprising a first switch to selectively configure the first transistor to mirror the current source corresponding to the value of a corresponding bit of a first digital signal; and a second DAC comprising a plurality of second cells, each of the plurality of second cells comprising a second switch to selectively couple the second transistor to a corresponding one of the plurality of first cells corresponding to the value of a corresponding bit of a second digital signal. The first DAC and the second DAC are configured to output a current corresponding to a result of multiplying the value of the first digital signal by the value of the second digital signal.

[0038] In some embodiments, each of the first digital signal and the second digital signal indicates a unary code.

[0039] In some embodiments, when the first transistor is selectively configured to mirror the current source, the first switch is configured to selectively couple the first transistor to the output path so that the first transistor outputs a current corresponding to the value of a corresponding bit of the first digital signal through the output path.

[0040] In some embodiments, in response to the second switch of each of the plurality of second cells selectively coupling the second transistor to a corresponding one of the plurality of first cells, the second transistor is configured to output a current based on a value of a corresponding bit of the first digital signal and a value of a corresponding bit of the second digital signal.

[0041] In some embodiments, the system may include: a first circuit system for mirroring the current flowing through the first current path, the first circuit system including a third transistor coupled to a plurality of third switches corresponding to the plurality of second cells, and a second circuit system for providing a second current path, the second circuit system including a fourth transistor coupled to a plurality of fourth switches corresponding to the plurality of second cells. Each of the plurality of third switches is configured to selectively couple a corresponding one of the plurality of second cells to the first current path based on the value of a corresponding bit of the second digital signal, and each of the plurality of fourth switches is configured to selectively couple a corresponding one of the plurality of second cells to the second current path based on the value of a corresponding bit of the second digital signal.

[0042] In some embodiments, in response to determining that the bit of the second digital signal has the first value, a switch in the plurality of third switches corresponding to the bit of the second digital value is configured to couple the corresponding unit in the plurality of second cells to the first current path, and a switch in the plurality of second switches corresponding to the bit of the second digital value is configured to disconnect the corresponding unit in the plurality of second cells from the second current path. In some embodiments, in response to determining that the bit of the second digital signal has the second value, a switch in the plurality of third switches corresponding to the bit of the second digital signal is configured to disconnect the corresponding unit in the plurality of second cells from the first current path, and a switch in the plurality of fourth switches corresponding to the bit of the second digital signal is configured to couple the corresponding unit in the plurality of second cells to the second current path.

[0043] Various embodiments disclosed herein are directed to a circuit system comprising: a current source; a transistor coupled to the current source; an output path comprising a first switch to selectively configure the first transistor to mirror the current source corresponding to a bit of a first digital signal; and a plurality of cells, each of the plurality of cells comprising a second switch to selectively couple a second transistor to the output path. Each of the plurality of cells corresponds to a value of a corresponding bit of the second digital signal.

[0044] In some embodiments, each of the first digital signal and the second digital signal indicates a unary code.

[0045] In some embodiments, when the first transistor is selectively configured to mirror the current source, the first switch is configured to selectively couple the first transistor to the output path such that the first transistor outputs a current corresponding to a value of a bit of the first digital signal.

[0046] In some embodiments, in response to the second switch of each of the plurality of cells selectively coupling a second transistor to the output path, the second transistor is configured to output a current based on a value of a bit of the first digital signal and a value of a corresponding bit of the second digital signal.

[0047] In some embodiments, the output path and the plurality of cells are configured to output a current corresponding to a result of multiplying a value of a bit of the first digital signal by a value of the second digital signal.

[0048] In some embodiments, the circuit system may include: a first circuit system for mirroring the current flowing through the first current path, the first circuit system including a third transistor coupled to a plurality of third switches corresponding to the plurality of cells, and a second circuit system for providing a second current path, the second circuit system including a fourth transistor coupled to a plurality of fourth switches corresponding to the plurality of cells. Each of the plurality of third switches is configured to selectively couple a corresponding one of the plurality of cells to the first current path based on the value of a corresponding bit of the second digital signal. Each of the plurality of fourth switches is configured to selectively couple a corresponding one of the plurality of cells to the second current path based on the value of a corresponding bit of the second digital signal.

[0049] In some embodiments, in response to determining that the bit of the second digital signal has a first value, a switch in a plurality of third switches corresponding to the bit of the second digital signal is configured to couple a corresponding cell in the plurality of cells to the first current path, and a switch in a plurality of fourth switches corresponding to the bit of the second digital signal is configured to disconnect a corresponding cell in the plurality of cells from the second current path. In response to determining that the bit of the second digital signal has a second value, a switch in a plurality of third switches corresponding to the bit of the second digital signal is configured to disconnect a corresponding cell in the plurality of cells from the first current path, and a switch in a plurality of fourth switches corresponding to the bit of the second digital signal is configured to couple a corresponding cell in the plurality of cells to the second current path.

[0050] As disclosed herein, one or more transistors may be configured to mirror a current source. In some embodiments, the one or more transistors may be configured to accurately replicate the current source. However, in some other embodiments, the one or more transistors may be configured to replicate the current source within an acceptable tolerance of deviations (e.g., noise, settling time, etc., for example). That is, one or more transistors are not required to accurately replicate the current source.

[0051] Embodiments in the present disclosure have at least the following advantages and benefits. In particular, the techniques disclosed herein provide improvements to multi-dimensional DACs configured to mirror a current source to an output.

[0052] First, embodiments in the present disclosure may provide useful techniques for preventing noise from a voltage supply and thus producing a reliable and accurate output current. By coupling one or more cells to a first transistor and a first switch (or integrating one or more cells into a macrocell including a first transistor and a first switch), the output current may not be affected by noise that may be carried from a voltage supply. This allows accurate and reliable operation of a multi-dimensional DAC.

[0053] Second, embodiments in the present disclosure may provide useful techniques for efficiently utilizing the device area (e.g., fewer components, flexible device arrangement, etc.) of a multi-dimensional DAC. By incorporating multiple output paths (each of which includes multiple cells) into a single current mirror, rather than operating multiple mirror circuits (e.g., continuous current mirrors), the techniques disclosed herein reduce the device area (e.g., fewer components, flexible device arrangement, etc.) while allowing efficient operation of a multi-dimensional DAC.

[0054] Third, embodiments in the present disclosure may provide useful techniques for reducing leakage current. The cells (e.g., the second switch and the second transistor) integrated into each of the multiple output paths may output mirrored current based on a weighting factor and / or length scaling (e.g., instead of width scaling) of each cell. This may reduce leakage current while improving the accuracy of the DAC and the power efficiency of the device.

[0055] Fourth, embodiments in the present disclosure may provide useful techniques for improving settling time and switching performance. Using a second switch to control each of a plurality of cells in each of a plurality of output paths, and using a first switch to control each of a plurality of output paths, may improve the settling time and switching performance of a current mirror. Individual control of the first and second switches may reduce the settling time for charging and discharging a transistor. Alternatively, by controlling individual first and / or second switches, the state of a current mirror (e.g., output path) may be quickly switched from one to another.

[0056] Embodiments of the present disclosure may be applicable to and / or compatible with a variety of technologies, including but not limited to numerically controlled oscillators (NCOs) within phase-locked loop (PLL) products, and numerically controlled oscillators (NCOs).

[0057] Figure 1 is a schematic diagram of a conventional current mirror 10. The conventional current mirror 10 includes a voltage supply 102 and a plurality of transistors 110, 112, 114, 116, 118. The voltage supply 102 can provide an input current 104 to the conventional current mirror 10. The conventional current mirror 10 can generate an output current 106 in response to receiving the input current 104, a first DAC signal 122, and a second DAC signal 124.

[0058] A plurality of transistors 110, 112, 114, 116, 118 are connected in series to form a two-dimensional DAC. This continuous current mirror produces an output current that is susceptible to noise originating from a power supply. For example, an overhead structure (including transistor 114 and transistor 116) is connected to a voltage supply 102, which makes the signal carried by the transistors (e.g., 114, 116, etc.) susceptible to noise from the voltage supply 102, and thus makes the output current 106 susceptible to noise. In addition, as shown, the overhead structure requires additional area, which increases the total area of ​​the current mirror and thus hinders efficient control of the device. In addition, the conventional current mirror 10 suffers from a delayed settling time to produce the output current 106. Since the plurality of transistors 110, 112, 114, 116, 118 are connected in series, when the current mirror 10 does not produce the output current 106, the plurality of transistors 110, 112, 114, 116, 118 are completely turned off (e.g., fully discharged). This takes time to charge and causes delays in switching from one state to another (eg, switching from one path to another).

[0059] Figure 2 is a schematic diagram of an example device 20 according to some embodiments. Device 20 includes a current source 202, circuitry to mirror the current source (eg, a current generated by the current source), and a plurality of units. In some examples, device 20 may be a DAC configured to output a mirrored current as an output.

[0060] refer to Figure 2 , current source 202 may be or include a circuit, circuit system, or any component that generates a current (e.g., a reference current, an input current, etc.). The current source may be electrically coupled to a transistor 204 (hereinafter referred to as reference transistor 204) of the circuit system and provide current thereto. In some embodiments, the current source may be electrically coupled to a voltage supply. For example, the current source may be electrically coupled to a gate voltage (e.g., an N bias voltage for an N metal oxide semiconductor (MOS) device, a P bias voltage for a P-MOS device, etc.). In some embodiments, the current source may generate a constant and / or precise current.

[0061] refer to Figure 2 , the circuit system or current mirror circuit described herein may be or include a circuit, circuit system, or any circuit system component that can replicate a current (e.g., a reference current, an input current, etc.) through an active device by controlling a current in another active device, keeping an output current constant regardless of the load. The circuit system or current mirror circuit may include a reference transistor 204 and a plurality of output paths 210, 220, 230. The circuit system may output an output current 206 (e.g., a mirrored current) in response to the reference transistor 204 receiving current from the current source 202. Although depicted as showing only three paths, the plurality of output paths 210, 220, and 230 may include any number of output paths.

[0062] In some embodiments, reference transistor 204 may be a semiconductor device (e.g., a bipolar junction transistor (BJT), a MOS field effect transistor (MOSFET), etc.) or any transistor that can control the current of device 20. In some embodiments, reference transistor 204 may be coupled to current source 202 and receive current from current source 202. In response to receiving current from current source 202, reference transistor 204 may provide a signal (e.g., a voltage signal) to multiple output paths 210, 220, 230.

[0063] refer to Figure 2 , any of the plurality of output paths 210, 220, 230 and / or combinations thereof may be or form a circuit, circuit system, or any component that outputs at least a portion of an output current 206 (e.g., a mirrored current) in response to the reference transistor 204 receiving current from the current source 202. The plurality of output paths 210, 220, 230 may combine to output the output current 206 to mirror the current (e.g., input current, reference current) from the current source 202. Each of the plurality of output paths 210, 220, 230 may include a switch (e.g., 213, 223, 233) and a transistor (e.g., 211, 221, 231). In some examples, the output current 206 may be an output signal of a DAC output in response to receiving an input current.

[0064] refer to Figure 2 , the first transistor (e.g., 211, 221, 231) may be a semiconductor device (e.g., BJT, MOSFET, etc.), or any transistor that can control the current flowing in the corresponding output path (e.g., 210, 220, 230). In some embodiments, the first transistor (e.g., 211, 221, 231) may be substantially similar to or the same as the reference transistor 204. The first transistor (e.g., 211, 221, 231) may control the flow of current in response to receiving a signal (e.g., a voltage signal) from the reference transistor 204. In some embodiments, the first transistor (e.g., 211, 221, 231) may be coupled to a second transistor (e.g., 215, 225, 235) in a corresponding path in a plurality of output paths (e.g., 210, 220, 230).

[0065] refer to Figure 2 , the first switch (e.g., 213, 223, 233) may be any semiconductor device (e.g., BJT, MOSFET, etc.), any semiconductor diode, any semiconductor switch, or any component that can control the current flow of the corresponding output path (e.g., 210, 220, 230) to which the first switch is coupled. The first switch (e.g., 213, 223, 233) may control the current flow in the corresponding output path, thereby selectively configuring the corresponding first transistor (e.g., 211, 221, 231) or a group of transistors including the first transistor (e.g., 211, 221, 231) and the second transistor (e.g., 215, 225, 235) to output a portion of the output current 206 (e.g., mirrored current), which may be combined into the output current 206. The first switch (e.g., 213, 223, 233) may be controlled to determine whether the corresponding output path (e.g., 210, 220, 230) is closed or open (e.g., allowing the current in the corresponding output path to flow or not flow). When the first switch (e.g., 213, 223, 233) is closed (or turned on), the first switch (e.g., 213, 223, 233) allows the corresponding current (e.g., the current from the first transistor, the sum of the currents from the first transistor and the second transistor, etc.) to flow through the corresponding output path (e.g., 210, 220, 230) and combine into the output current 206 (e.g., mirrored current). When the first switch (e.g., 213, 223, 233) is opened (or turned off), the first switch (e.g., 213, 223, 233) disconnects the corresponding output path (e.g., 210, 220, 230) and prevents the corresponding current (e.g., the current from the first transistor, the sum of the currents from the first transistor and the second transistor, etc.) from combining into the output current 206 (e.g., mirrored current). By controlling which first switches are open or closed, the device can output an output current 206 (eg, a current mirrored to the input current) by the sum of currents from output paths where the first switches (eg, 213, 223, 233) are closed.

[0066] In some embodiments, each of the plurality of output paths may correspond to the value of a corresponding bit of a first signal (e.g., 218, 228, 238). In some embodiments, the first signal (e.g., 218, 228, 238) may be a digital signal, a logic signal, a binary signal, or any signal that can represent data as a sequence of discrete values. The first switch (e.g., 213, 223, 233) of each of the plurality of output paths may be controlled by a first signal (e.g., a first digital signal) (e.g., 218, 228, 238), which may include a corresponding bit to control the corresponding switch. The first signal (e.g., 218, 228, 238) may control the output current 206 of the current mirror circuit. In some embodiments, the first signal (e.g., 218, 228, 238) may be an input signal of a DAC and may control the output signal of the DAC (e.g., the output current 206 of the current mirror circuit). For example, when the device includes X output paths, the first output path (e.g., 210) may be controlled by, for example, a DAC1. <1> The xth output path (eg, 230) may be controlled by a first signal of the DAC1. <x>The first switch may be controlled by a signal (e.g., 238). In some examples, the first switch may be configured to selectively couple the first transistor to the corresponding output path so that the first transistor outputs a current corresponding to the value of the corresponding bit of the first signal (e.g., 218, 228, 238). In some embodiments, the output current 206 (e.g., a mirrored current) may be output by selectively configuring each first transistor of the plurality of output paths. For example, the output current 206 may be an output signal of a DAC output in response to receiving an input current. In some embodiments, the first signal (e.g., 218, 228, 238) indicates a unary code.

[0067] refer to Figure 2 , each of the plurality of output paths may include a plurality of cells (e.g., 214, 224, 234) electrically coupled to a corresponding first transistor (e.g., 211, 221, 231). As described herein, any of the plurality of cells (e.g., 214, 224, 234) may be or include a circuit, circuit system, or any circuit system component including a pair of transistors and a switch. Although in each of the plurality of paths (e.g., 210, 220, 230), the cells (e.g., 214, 224, 234) are shown only with dashed boxes, each of the plurality of output paths may include any number of cells, as shown. Each of the plurality of cells includes a second switch (e.g., 217, 227, 237) and a second transistor (e.g., 215, 225, 235). The second transistor (e.g., 215, 225, 235) may be a semiconductor device (e.g., BJT, MOSFET, etc.), or any transistor that can control the flow of current in response to receiving a signal (e.g., a voltage signal). In some embodiments, the second transistor (e.g., 215, 225, 235) may be substantially similar or identical to the first transistor (e.g., 211, 221, 231) and / or the reference transistor 204. The second transistor (e.g., 215, 225, 235) may provide the generated signal to the corresponding output path to which the second transistor is coupled. For example, the second transistor (e.g., 215, 225, 235) may be controlled to output a second current, which may be combined with the first current output from the first transistor (e.g., 211, 221, 231) coupled in the corresponding output path (e.g., 210, 220, 230). By closing (or turning on) the first switch (e.g., 213, 223, 233), the combined current may flow into the corresponding output path.

[0068] refer to Figure 2 , the second switch (e.g., 217, 227, 237) can be any semiconductor device (e.g., BJT, MOSFET, etc.), any semiconductor diode, any semiconductor switch, or any component that can control the flow of current of the current path to which the second switch is coupled. As described herein, the current path can be or include a circuit, a circuit system, or any circuit system component through which current can flow. The second switch (e.g., 217, 227, 237) can be coupled to the second transistor (e.g., 215, 225, 235) and can control the flow of current in the corresponding path, thereby selectively configuring whether to combine the current output from the second transistor (e.g., 215, 225, 235) into the output current 206 (e.g., mirrored current) in the corresponding output path. That is, the second switch (e.g., 217, 227, 237) can selectively couple the second transistor (e.g., 215, 225, 235) to the corresponding output path and allow the current output from the second transistor (e.g., 215, 225, 235) to be combined with the current output from the first transistor (e.g., 211, 221, 231). The second switch (e.g., 217, 227, 237) can be controlled to determine whether the corresponding path is closed or open (e.g., allowing the current in the corresponding path to flow or not flow). When the second switch (e.g., 217, 227, 237) is closed, the second switch (e.g., 217, 227, 237) allows the corresponding current (e.g., the current from the second transistor) to flow through the corresponding output path and combine with the current from the first transistor (e.g., 211, 221, 231), thereby outputting a portion of the output current 206 (e.g., mirrored current) that flows through the corresponding output path of the plurality of output paths (e.g., 210, 220, 230). When the second switch (e.g., 217, 227, 237) is open, the second switch (e.g., 217, 227, 237) disconnects the corresponding output path and prevents the corresponding current (e.g., the current from the second transistor) from combining with the current from the first transistor (or combining into the output current 206). By controlling which second switches (e.g., 217, 227, 237) are open or closed, the device can determine the amount of current that is combined with the current from the first transistor.

[0069] In some embodiments, each of the plurality of cells may correspond to the value of a corresponding bit of a second signal (e.g., a second digital signal, etc.) (e.g., 219, 229, 239). In some embodiments, the second signal may be a digital signal, a logic signal, a binary signal, or any signal that can represent data as a sequence of discrete values. The second switch (e.g., 217, 227, 237) of each of the plurality of cells (e.g., 214, 224, 234) may be controlled by the second signal (e.g., a second digital signal) (e.g., 219, 229, 239), which may include a corresponding bit to control the corresponding switch (e.g., the second switch). In some embodiments, when an output path among the plurality of output paths (e.g., 210, 220, 230) includes a first transistor (e.g., 211) coupled to Y cells (the cells include cell 214, i.e., include Y second transistors and Y second switches) and a first switch (e.g., 213), a current from a first one of the Y second transistors (e.g., 214) (and / or a first one of the Y second switches (e.g., 217)) may be controlled by the signal DAC2. <1> 219 is controlled, and the current from the yth of the Y second transistors (and / or the yth of the Y second switches) can be controlled by the signal DAC2 <y>In some embodiments, in response to a second switch (e.g., 217, 227, 237) of each of the plurality of cells (e.g., 214, 224, 234) selectively coupling the second transistor to a corresponding one of the plurality of output paths, the second transistor (e.g., 215, 225, 235) may be configured to output a current based on a value of a corresponding bit of the first digital signal (e.g., 218, 228, 238) and / or a value of a corresponding bit of the second digital signal (e.g., 219, 229, 239). In some embodiments, the second signal indicates a unary code.

[0070] In some embodiments, the second switches (e.g., 217, 227, 237) in the plurality of cells (e.g., 214, 224, 234) of the plurality of output paths (e.g., 210, 220, 230) may share the same digital signal. For example, the plurality of cells in the first output path (e.g., 210) of the plurality of output paths may receive the second signal DAC2<1:y>, and the plurality of cells in any output path (e.g., 220, 230) of the plurality of output paths may receive the same second signal DAC2<1:y>. That is, the second signal 219 of the output path 210 may be the same as the second signal 229 (and / or the second signal 239) of the output path 220 (and / or the output path 230). For example, each of the first cells in the plurality of output paths may receive the DAC2 <1> , each of the second units in the plurality of output paths may receive DAC2 <2> , and each of the y-th second units in the plurality of output paths can receive DAC2 <y>As discussed above, the current contribution of the plurality of cells (e.g., 214, 224, 234) in each of the plurality of output paths (e.g., 210, 220, 230) to the output current 206 (e.g., mirrored current) may be controlled by a first signal (e.g., 218, 228, 238) such as DAC1<1:x>. For example, the plurality of cells in a first output path of the plurality of output paths may be controlled by the first signal DAC1<1:x>. <1> Control, the plurality of units in the second output path of the plurality of output paths can be controlled by the first signal DAC1 <2> The first signal DAC1 is used to control the multiple units in the x-th output path of the multiple output paths. <x>control.

[0071] In some examples, multiple cells (e.g., 214, 224, 234) within each of the multiple output paths (e.g., 210, 220, 230) may be integrated into a macro cell or a structure including a first corresponding transistor (e.g., 211, 221, 231) and a first corresponding switch (e.g., 213, 223, 233).

[0072] In some embodiments, a plurality of output paths (e.g., 210, 220, 230) and a plurality of units (e.g., 214, 224, 234) may be configured to output an output current 206 corresponding to a result of multiplying a value of a first digital signal (e.g., 218, 228, 238) by a value of a second digital signal (e.g., 219, 229, 239), for example, the output signal is DAC1·DAC2. For example, the output current 206 may be a function of a result of multiplying a value of a first digital signal (e.g., 218, 228, 238) by a value of a second digital signal (e.g., 219, 229, 239). For example, the output current 206I out Can where M is the ratio constant associated with the transistor, and I in is the current generated by current source 202 (eg, reference source). This allows multi-dimensional control of output current 206 by independently adjusting signals DAC1 and DAC2.

[0073] In some embodiments, a plurality of output paths (e.g., 210, 220, 230) and a plurality of cells (e.g., 214, 224, 234) may be configured to output an output current 206 by weighting at least one of the current from any of the plurality of output paths (e.g., 210, 220, 230) or the current from any of the plurality of cells (e.g., 214, 224, 234). The weighting may be controlled by a first signal (received by a first switch, e.g., DAC1) and / or a second signal (received by a second switch, e.g., DAC2). For example, the weighting may be controlled by at least one of a step size, a relative signal size, a signal range, etc. The output current 206I output by weighting out Can be defined as:

[0074]

[0075] Where x is the DAC1 input code indicating the first signal (e.g., DAC1), y is the DAC2 input code indicating the second signal (e.g., DAC2), I unit isI in / M, N is the gain factor of DAC1, P is the gain factor of DAC2, α j is the weight of the jth DAC1 of multiple output paths (e.g., 210, 220, 230), and α k is the weight of the kth one among the plurality of units (eg, 214, 224, 234).

[0076] In some embodiments, device 20 may be or include a DAC configured to output a mirrored current of a current source (e.g., a reference current, an input signal, a current from current source 202, etc.). In response to receiving as input a first signal (e.g., DAC1) and a second signal (e.g., DAC2), the DAC may output the mirrored current as an output. For example, the first signal may be a first digital signal (e.g., an output signal of the DAC) for coarse tuning of output current 206, and the second signal may be a second digital signal (e.g., an output signal of the DAC) for fine tuning of output current 206.

[0077] Figure 3 30 is an equivalent schematic diagram of device 20 according to some embodiments. More specifically, equivalent output path 304 may represent multiple output paths (e.g., 210, 220, 230) and act as a current mirror. Equivalent output path 304 may be controlled by a first signal 318 (e.g., 218, 228, 238) and a second signal 319 (e.g., 219, 229, 239). Output current 206I out Can where M is the ratio constant associated with the transistor, and I in is the current generated by current source 202 (e.g., a reference source). In some embodiments, FIG. 30 may be an equivalent circuit of a multidimensional DAC configured to output a mirrored current as an output signal. The DAC may be controlled by a first signal 318 and a second signal 319 to output output current 206 as the output signal of the DAC. The multidimensional DAC may be controlled by independently adjusting the first signal 318 and the second signal 319.

[0078] Figure 4 4 is a schematic diagram of an example device 40 according to some embodiments. Device 40 may be a device, circuit, circuitry, or any component that may be integrated into device 20. Device 40 may include an example DAC receive circuit 401. DAC receive circuit 401 is a non-limiting example, and it should be understood that device 40 may be implemented with a variety of DAC receive circuits while remaining within the scope of the present disclosure.

[0079] refer to Figure 4 , the DAC receiving circuit 401 may include multiple output paths (e.g., 210, 220, 230) and / or multiple cells (e.g., 214, 224, 234), and may further include a first circuit system 402 and a second circuit system 412. The first circuit system 402 includes a third transistor 404 coupled to a plurality of third switches (e.g., 405, 406) corresponding to the plurality of cells (e.g., 214, 224, 234). For example, each of the plurality of third switches (e.g., 405, 406) may be electrically coupled to each corresponding cell in the plurality of cells (e.g., 214, 224, 234). The first circuit system 402 may mirror a current flowing through a first current path 409, which may be used to output an output current (e.g., a mirrored current) (e.g., 206). Each of the plurality of third switches (e.g., 405, 406) may be configured to selectively couple a corresponding unit among a plurality of units (e.g., 214, 224, 234) to the first current path 409 based on the value of a corresponding bit of the second digital signal (e.g., 219, 229, 239), so that an output current (e.g., 206) may be provided to a corresponding output path (e.g., 210, 220, 230) through the first current path 409.

[0080] The second circuit system 412 includes a fourth transistor 414 coupled to a plurality of fourth switches (e.g., 415, 416) corresponding to a plurality of cells (e.g., 214, 224, 234). For example, each of the plurality of fourth switches (e.g., 415, 416) may be electrically coupled to each corresponding cell in the plurality of cells (e.g., 214, 224, 234). The second circuit system 412 may provide a second current path 419. Each of the plurality of fourth switches (e.g., 415, 416) may be configured to selectively couple a corresponding cell in the plurality of cells (e.g., 214, 224, 234) to the second current path 419 based on the value of a corresponding bit of a second digital signal (e.g., 219, 229, 239). The current provided by the second current path 419 may not be used.

[0081] In some embodiments, when a cell among multiple cells (e.g., 214, 224, 234) receives a bit of a second digital signal (e.g., 219, 229, 239) having a first value (e.g., 1, 0), a third switch (e.g., 405, 406) in the cell may be configured to couple a corresponding cell among the multiple cells (e.g., 214, 224, 234) to a first current path 409, and a fourth switch (e.g., 415, 416) in the corresponding cell may be configured to disconnect the corresponding cell among the multiple cells (e.g., 214, 224, 234) from the second current path 419. That is, in response to determining that a bit of the second digital signal (e.g., 219, 229, 239) has a first value, a third switch (e.g., 405, 406) of a plurality of third switches corresponding to the bit of the second digital signal (e.g., 219, 229, 239) may be configured to couple a corresponding cell of a plurality of cells (e.g., 214, 224, 234) to a first current path 409, and a fourth switch (e.g., 415, 416) of a plurality of fourth switches corresponding to the bit of the second digital signal (e.g., 219, 229, 239) may be configured to disconnect a corresponding cell of a plurality of cells (e.g., 214, 224, 234) from a second current path 419.

[0082] In some embodiments, when a cell among multiple cells (e.g., 214, 224, 234) receives a bit of a second digital signal (e.g., 219, 229, 239) having a second value (e.g., 0, 1), a third switch (e.g., 405, 406) in the cell may be configured to disconnect the corresponding cell among the multiple cells (e.g., 214, 224, 234) from the first current path 409, and a fourth switch (e.g., 415, 416) in the cell may be configured to couple the corresponding cell among the multiple cells (e.g., 214, 224, 234) to the second current path 419. That is, in response to determining that a bit of the second digital signal (e.g., 219, 229, 239) has a second value, a third switch (e.g., 405, 406) of a plurality of third switches corresponding to the bit of the second digital signal (e.g., 219, 229, 239) may be configured to disconnect a corresponding cell of a plurality of cells (e.g., 214, 224, 234) from the first current path 409, and a fourth switch (e.g., 415, 416) of a plurality of fourth switches corresponding to the bit of the second digital signal (e.g., 219, 229, 239) may be configured to couple a corresponding cell of a plurality of cells (e.g., 214, 224, 234) to the second current path 419.

[0083] Figure 5 is a flow chart of an example process 50 for operating a device according to some embodiments. In some embodiments, process 50 is performed by any of the devices, systems, or components thereof discussed above. For example, process 50 may be performed using device 20. In other embodiments, process 50 is performed by other entities. Figure 5 Process 50 may include more, fewer, or different steps than those shown in FIG.

[0084] At step 502, a current source (eg, Figure 2 The current source 202 in the example can provide an input current. The current source can provide a current to the transistor (eg, Figure 2 The reference transistor 204 in provides the input current.

[0085] At 504, in response to receiving an input current, a transistor (eg, Figure 2 The reference transistor 204 in FIG. 204 may provide a plurality of output paths (eg, Figure 2 The output paths 210, 220, 230 in the circuit may provide a signal (eg, a voltage signal). Each of the plurality of output paths may include a first transistor (eg, Figure 2 The first transistors 211, 221, 231) and the first switch (eg, Figure 2 Each of the plurality of output paths may include a second transistor (eg, a transistor electrically coupled to a corresponding first transistor and a corresponding first switch) . Figure 2 The second crystal 215, 225, 235) and the second switch (for example, Figure 2 Each of the second switches and the corresponding second transistors coupled thereto may form a unit (e.g., 214). Each of the first transistor and the second transistor may be responsive to a slave transistor (e.g., Figure 2 The reference transistor 204 in FIG. 1 receives a signal (eg, a voltage signal) and generates a current.

[0086] At step 506, each of the first transistors and each of the second transistors may receive a first signal (eg, Figure 2 The first signal 218, 228, 238) and the second signal (for example, Figure 2 In response to receiving the second signal, the second switch (eg, Figure 2 Each of the second switches 217, 227, 237 in the embodiment may control a corresponding second transistor (eg, Figure 2 In each of the plurality of cells included in each of the plurality of output paths, when the corresponding second signal includes a value to close the corresponding second switch, current is allowed to be output from the corresponding second transistor to the corresponding first switch (e.g., Figure 2 , and from the corresponding first transistor (eg, Figure 2 When the corresponding second signal includes a value for turning off the corresponding second switch, the current is not allowed to be output from the corresponding second transistor to the corresponding first switch.

[0087] In each of the plurality of output paths, when the corresponding first signal includes a signal for closing the corresponding first switch (eg, Figure 2 When the value of the first switch 213, 223, 233 in the first transistor 213, 223, 233 is set, the value of the first switch 213, 223, 233 in the first transistor ...3 Figure 2 211, 221, 231) and / or from the corresponding second transistor (eg, Figure 2 When the corresponding first signal includes a value for disconnecting the corresponding first switch, the current is not allowed to flow into the corresponding output path.

[0088] At step 508, in response to controlling the first switch and the second switch in the plurality of output paths, one or more of the plurality of output paths may provide a corresponding current (e.g., a current from a corresponding first transistor and / or a current from a corresponding second transistor) to generate an output current (e.g., Figure 2 The output current 206 in FIG. 1 ). The output current may be the sum of the currents from one or more output paths whose corresponding first switches are closed.

[0089] The term "coupled" and its variations include two components directly or indirectly joined to one another. The term "electrically coupled" and its variations include two components directly or indirectly joined to one another through a conductive material (e.g., a metal or copper trace). This joining (for both the terms "coupled" and "electrically coupled") may be static (e.g., permanent or fixed) or movable (e.g., movable or releasable). This joining (for both the terms "coupled" and "electrically coupled") may be achieved by two components being directly coupled to one another or directly coupled to one another, wherein the two components are coupled to one another using a separate intervening component and any additional intermediate components that are coupled to one another, or wherein the two components are coupled to one another using an intervening component that is integrally formed as a single entity with one of the two components. If "coupled" or its variations are modified by an additional term (e.g., directly coupled), then the general definition of "coupled" provided above is modified by the ordinary language meaning of the additional term (e.g., "directly coupled" means joining two components without any separate intervening components), resulting in a narrower definition than the general definition of "coupled" provided above. This coupling may be mechanical, electrical or fluid.

[0090] The above summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0091] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in conjunction with transmission spatial streams, sounding frames, responses, and subsets of devices for identification or distinction from each other or other purposes. These terms are not intended to relate entities (e.g., first device and second device) in time or according to sequence, although in some cases, these entities may contain such a relationship. These terms also do not limit the number of possible entities that can operate within a system or environment. It should be understood that the system described above may provide multiple of any one or each of the components, and these components may be provided on a stand-alone machine, or in some embodiments, on multiple machines in a distributed system. In addition, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions, which are embodied on or in one or more articles of manufacture, such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or tapes. The programs may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any byte code language (e.g., JAVA). A software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0092] Although the foregoing written description of the methods and systems enables one of ordinary skill to make and use embodiments thereof, one of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of the present disclosure.< / x> < / y> < / y> < / x> < / x> < / y> < / y> < / x>

Claims

1. A digital / analog converter DAC, comprising: Current source; a circuit system for mirroring the current source, the circuit system comprising a transistor coupled to the current source, and a plurality of output paths; each output path of the plurality of output paths includes a first switch to selectively configure a first transistor to mirror the current source, wherein each output path corresponds to a value of a corresponding bit of the first digital signal; and A plurality of cells, each of the plurality of cells comprising a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, wherein each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.

2. The DAC according to claim 1, wherein Each of the first digital signal and the second digital signal indicates a unary code.

3. The DAC according to claim 1, wherein When the first transistor is selectively configured to mirror the current source, the first switch is configured to selectively couple the first transistor to the output path such that the first transistor outputs a current corresponding to the value of the corresponding bit of the first digital signal.

4. The DAC according to claim 1, wherein In response to the second switch of each of the plurality of cells selectively coupling the second transistor to the corresponding one of the plurality of output paths, the second transistor being configured to output a current based on the value of the corresponding bit of the first digital signal and the value of the corresponding bit of the second digital signal.

5. The DAC according to claim 1, wherein The plurality of output paths and the plurality of cells are configured to output a current corresponding to a result of multiplying a value of the first digital signal and a value of the second digital signal.

6. The DAC of claim 1 , further comprising: a first circuit system to mirror a current flowing through the first current path, the first circuit system comprising a third transistor coupled to a plurality of third switches corresponding to the plurality of cells; and a second circuit system for providing a second current path, the second circuit system comprising a fourth transistor coupled to a plurality of fourth switches corresponding to the plurality of cells, wherein Each of the plurality of third switches is configured to selectively couple a corresponding one of the plurality of cells to the first current path based on the value of the respective bit of the second digital signal, and Each of the plurality of fourth switches is configured to selectively couple the corresponding one of the plurality of cells to the second current path based on the value of the respective bit of the second digital signal.

7. The DAC according to claim 6, wherein In response to determining that the bit of the second digital signal has a first value, the switches of the plurality of third switches corresponding to the bit of the second digital signal are configured to couple the corresponding cell of the plurality of cells to the first current path, and the switches of the plurality of fourth switches corresponding to the bit of the second digital signal are configured to disconnect the corresponding cell of the plurality of cells from the second current path, and in response to determining that the bit of the second digital signal has a second value, the switches of the plurality of third switches corresponding to the bit of the second digital signal are configured to disconnect the corresponding cell of the plurality of cells from the first current path, and the switches of the plurality of fourth switches corresponding to the bit of the second digital signal are configured to couple the corresponding cell of the plurality of cells to the second current path.

8. A system comprising: Current source; a transistor coupled to the current source; a first digital-to-analog converter DAC comprising a plurality of first cells, each of the plurality of first cells comprising a first switch to selectively configure a first transistor to mirror the current source corresponding to a value of a corresponding bit of a first digital signal; and a second DAC including a plurality of second cells, each of the plurality of second cells including a second switch to selectively couple a second transistor to a corresponding one of the plurality of first cells corresponding to a value of a corresponding bit of a second digital signal, Wherein the first DAC and the second DAC are configured to output a current corresponding to a result of multiplying the first digital signal by a value of the second digital signal.

9. The system according to claim 8, wherein Each of the first digital signal and the second digital signal indicates a unary code.

10. The system according to claim 8, wherein When the first transistor is selectively configured to mirror the current source, the first switch is configured to selectively couple the first transistor to an output path so that the first transistor outputs a current corresponding to the value of the corresponding bit of the first digital signal through the output path.

11. The system according to claim 8, wherein In response to the second switch of each of the plurality of second cells, the second transistor is selectively coupled to the corresponding one of the plurality of first cells, the second transistor being configured to output a current based on the value of the corresponding bit of the first digital signal and the value of the corresponding bit of the second digital signal.

12. The system of claim 8, further comprising: a first circuit system to mirror a current flowing through a first current path, the first circuit system comprising a third transistor coupled to a plurality of third switches corresponding to the plurality of second cells; and a second circuit system for providing a second current path, the second circuit system comprising a fourth transistor coupled to a plurality of fourth switches corresponding to the plurality of second cells, wherein Each of the plurality of third switches is configured to selectively couple a corresponding one of the plurality of second cells to the first current path based on the value of the corresponding bit of the second digital signal, and each of the plurality of fourth switches is configured to selectively couple the corresponding one of the plurality of second cells to the second current path based on the value of the corresponding bit of the second digital signal.

13. The system of claim 12, wherein In response to determining that a bit of the second digital signal has a first value, a switch in the plurality of third switches corresponding to the bit of the second digital value is configured to couple a corresponding cell in the plurality of second cells to the first current path, and a switch in the plurality of second switches corresponding to the bit of the second digital value is configured to disconnect the corresponding cell in the plurality of second cells from the second current path, and In response to determining that the bit of the second digital signal has a second value, the switch of the plurality of third switches corresponding to the bit of the second digital signal is configured to disconnect the corresponding cell of the plurality of second cells from the first current path, and the switch of the plurality of fourth switches corresponding to the bit of the second digital signal is configured to couple the corresponding cell of the plurality of second cells to the second current path.

14. A circuit system comprising: Current source; a transistor coupled to the current source; an output path including a first switch to selectively configure a first transistor to mirror the current source corresponding to a bit of a first digital signal; and A plurality of cells, each of the plurality of cells comprising a second switch to selectively couple a second transistor to the output path, wherein each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.

15. The circuit system of claim 14, wherein Each of the first digital signal and the second digital signal indicates a unary code.

16. The circuit system of claim 14, wherein When the first transistor is selectively configured to mirror the current source, the first switch is configured to selectively couple the first transistor to the output path such that the first transistor outputs a current corresponding to the value of the bit of the first digital signal.

17. The circuit system of claim 14, wherein The second switch of each of the plurality of cells selectively couples the second transistor to the output path in response to the second switch, the second transistor configured to output a current based on the value of the bit of the first digital signal and the value of the corresponding bit of the second digital signal.

18. The circuit system of claim 14, wherein The output path and the plurality of cells are configured to output a current corresponding to a result of multiplying the value of the bit of the first digital signal by a value of the second digital signal.

19. The circuit system of claim 14, further comprising: a first circuit system to mirror a current flowing through the first current path, the first circuit system comprising a third transistor coupled to a plurality of third switches corresponding to the plurality of cells; and a second circuit system for providing a second current path, the second circuit system comprising a fourth transistor coupled to a plurality of fourth switches corresponding to the plurality of cells, wherein Each of the plurality of third switches is configured to selectively couple a corresponding one of the plurality of cells to the first current path based on the value of the respective bit of the second digital signal, and Each of the plurality of fourth switches is configured to selectively couple the corresponding one of the plurality of cells to the second current path based on the value of the respective bit of the second digital signal.

20. The circuit system of claim 19, wherein In response to determining that the bit of the second digital signal has a first value, the switches of the plurality of third switches corresponding to the bit of the second digital signal are configured to couple the corresponding cell of the plurality of cells to the first current path, and the switches of the plurality of fourth switches corresponding to the bit of the second digital signal are configured to disconnect the corresponding cell of the plurality of cells from the second current path, and in response to determining that the bit of the second digital signal has a second value, the switches of the plurality of third switches corresponding to the bit of the second digital signal are configured to disconnect the corresponding cell of the plurality of cells from the first current path, and the switches of the plurality of fourth switches corresponding to the bit of the second digital signal are configured to couple the corresponding cell of the plurality of cells to the second current path.

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