Multi-phase Clock Calibration Method and Device for SerDes Transmitter

Abstract

According to an embodiment of the present disclosure, a multi-phase clock calibration apparatus and method for a SerDes transmitter are provided. The apparatus includes a replicated output driver stage for generating a replicated signal proportional to an output signal of the output driver stage; a filter connected to an output end of the replicated output driver stage; an analog-to-digital converter for receiving the filtered analog signal output by the filter and converting the filtered analog signal into a digital signal; a phase error detection unit for calculating an autocorrelation function between adjacent output signals and generating a phase adjustment signal according to a comparison result of the autocorrelation function; and a clock phase adjustment unit for adjusting a phase of a multi-phase clock signal according to the phase adjustment signal, where the multi-phase clock signal is used to drive a multiplexer of the SerDes transmitter to serialize parallel digital information. The embodiment of the present disclosure can ensure the accuracy of the output signal of the SerDes transmitter by adjusting the multi-phase clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technologies, and more particularly, to a multi-phase clock calibration method and apparatus for a SerDes transmitter. Background Art

[0002] With the continuous development of high-speed serial data transmission technologies, the single-channel data rate of SerDes (Serializer / Deserializer) has been increased to 112 GHz or even 224 GHz. At such high signal rates, in order to reduce the power consumption of the clock path, a 1 / 4-rate or 1 / 8-rate clock is usually adopted. However, using a low-rate clock places more stringent requirements on the offset (skew) between clock phases. If the clock phase offset is large, it will affect the accuracy of data transmission.

[0003] In the existing SerDes transmitters, a multiplexer (MUX) is generally used to convert parallel data into serial data. The clock management circuit at the transmitter generally uses buffer stages to transmit clock signals and relies on a phase error detection circuit for calibration. The phase error detection circuit is usually implemented using logic gates. If there are mismatches in the buffer stages connected to different paths, there will be a phase error between the clock signals output from each path, and this error cannot be detected by the existing phase error detection circuit. Therefore, ultimately, the accuracy of the calibration signal will be affected.

[0004] In addition, due to different signal delays in different paths inside the multiplexer, the output data pulse widths may be uneven. Taking a four-phase clock as an example, as Figure 4 shown, after the clock signals of different phases reach the multiplexer, different output pulse widths will be generated due to delay differences, and an ideal output result cannot be obtained. Even if the multi-phase clock itself is calibrated, the error caused by the multiplexer cannot be solved, which further affects the accuracy of the analog signal output by the output driver stage.

[0005] The above problems limit the output signal accuracy of the existing SerDes transmitters and affect the reliability of high-speed data transmission. Therefore, it is necessary to improve the existing technologies to optimize clock phase calibration and improve the SerDes signal transmission quality. Summary of the Invention

[0006] In view of the problems existing in the prior art, embodiments of the present disclosure provide a multi-phase clock calibration method and apparatus for a SerDes transmitter, which can achieve real-time dynamic calibration and ensure the accuracy of the output signal of the SerDes transmitter.

[0007] The first aspect of the embodiments of the present disclosure provides a multi-phase clock calibration device for a SerDes transmitter, which includes a replicated output driver stage for generating a replicated signal proportional to the output signal of the output driver stage; a filter connected to the output of the replicated output driver stage; an analog-to-digital converter for receiving the filtered analog signal output by the filter and converting the filtered analog signal into a digital signal; a phase error detection unit for calculating the autocorrelation function between adjacent output signals based on the output signal of the analog-to-digital converter and generating a phase adjustment signal according to the comparison result of the autocorrelation function; a clock phase adjustment unit for receiving the phase adjustment signal from the phase error detection unit and adjusting the phase of the multi-phase clock signal, where the multi-phase clock signal is used to drive a multiplexer of the SerDes transmitter to serialize parallel digital information.

[0008] After the multi-phase clock signal is adjusted by the clock phase adjustment unit, it is output to the multiplexer via a clock buffer stage to drive the multiplexer to serialize multiple digital data into one digital data and convert it into an analog signal for output through the output driver stage. Thus, the replicated output driver stage, filter, analog-to-digital converter, phase error detection unit, and clock phase adjustment unit connected between the output of the multiplexer and the clock buffer stage form a closed-loop feedback path for calibrating the multi-phase clock signal. Since the closed-loop feedback path includes the clock buffer stage and the multiplexer of the SerDes transmitter, the errors brought by the clock buffer stage and the multiplexer are also calibrated simultaneously, ensuring the accuracy of the output data to the greatest extent.

[0009] The input end of the replicated output driver stage can be connected in parallel with the input end of the output driver stage of the SerDes transmitter, and the output signal is adjusted by adjusting the number of transistors and load value of the replicated output driver stage.

[0010] Optionally, according to the first aspect of the embodiments of the present disclosure, the number of phases of the multi-phase clock signal is 2 N , where N is a positive integer. The phase error detection unit calculates the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter starting from the output signal of the analog-to-digital converter corresponding to the reference clock signal; generating a phase adjustment signal according to the comparison result of the autocorrelation function includes repeatedly executing the following steps until i ranges from 1 to N: dividing the calculated 2 N autocorrelation functions into 2 i-1 groups in sequence, each group containing 2 N-i+1 autocorrelation functions, comparing the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions in each group, and generating an adjusted phase of (2k - 1)*360 / 2 iThe phase adjustment signal of the clock signal, where k = 1, 2, ..., 2 i-1 , and the phase adjustment signal is used to indicate adjusting the clock signal forward or backward so that the sum of the autocorrelation functions of the first half in the group is equal to the sum of the autocorrelation functions of the second half.

[0011] If each group contains one autocorrelation function after grouping, the sum of the autocorrelation functions is the value of the autocorrelation function. The above method of detecting and adjusting the phase difference using the autocorrelation function has a fast convergence speed and higher accuracy, and is applicable to different modulation formats and rates.

[0012] Optionally, according to the first aspect of the embodiments of the present disclosure, the multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is:

[0013] y 12 =E[x1(n)*x2(n)]

[0014] y 23 =E[x2(n)*x3(n)]

[0015] y 34 =E[x3(n)*x4(n)]

[0016] y 41 =E[x4(n)*x1(n + 1)]

[0017] where x1, x2, x3, and x4 are the output signals of the analog-to-digital converter, corresponding to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal respectively, n represents the period of the four-phase clock signal, y 12 、y 23、 y 34 、y 41 are the autocorrelation functions between adjacent output signals, and generating the phase adjustment signal according to the comparison result of the autocorrelation functions includes generating the phase adjustment signal corresponding to the clock signal delayed by 180 degrees according to the comparison result of |y 12 | + |y 23 | and |y 34 | + |y 41 |; generating the phase adjustment signal corresponding to the clock signal delayed by 90 degrees according to the comparison result of |y 12 | and |y 23 |, and generating the phase adjustment signal corresponding to the clock signal delayed by 270 degrees according to the comparison result of |y 34 | and |y 41 |.

[0018] Optionally, according to the first aspect of the embodiments of the present disclosure, the number of phases of the multi-phase clock signal is 2 N , and the operating frequency of the analog-to-digital converter is 1 / (M * 2 N + 1) of the operating frequency of the SerDes transmitter, where M is an integer not less than 1.

[0019] Optionally, according to the first aspect of the embodiments of the present disclosure, the multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is:

[0020] y 12 = E[x1(n) * x2(n + 1)]

[0021] y 23 = E[x2(n + 1) * x3(n + 2)]

[0022] y 34 = E[x3(n + 2) * x4(n + 3)]

[0023] y 41 = E[x4(n + 3) * x1(n + 4)]

[0024] where x1, x2, x3, and x4 respectively correspond to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, n represents the period of the four-phase clock signal, and generating a phase adjustment signal according to the comparison result of the autocorrelation function includes generating a phase adjustment signal for the clock signal delayed by 180 degrees according to the comparison result of |y 12 | + |y 23 | and |y 34 | + |y 41 |; generating a phase adjustment signal for the clock signal delayed by 90 degrees according to the comparison result of |y 12 | and |y 23 |, and generating a phase adjustment signal for the clock signal delayed by 270 degrees according to the comparison result of |y 34 | and |y 41 |.

[0025] Optionally, according to the first aspect of the embodiments of the present disclosure, the filter is a low-pass filter, and the cut-off frequency of the low-pass filter is related to the magnitude of the value of the autocorrelation function.

[0026] A second aspect of the embodiments of the present disclosure provides a multi-phase clock calibration method for a SerDes transmitter, which includes generating a replicated analog signal proportional to the analog signal output by the output driver stage of the SerDes transmitter; performing low-pass filtering on the replicated analog signal; converting the filtered replicated analog signal into a digital signal through an analog-to-digital converter as an output signal; calculating the autocorrelation function of adjacent output signals, and generating a phase adjustment signal according to the comparison result of the autocorrelation function; adjusting the phase of the multi-phase clock signal according to the phase adjustment signal, where the multi-phase clock signal is used to drive a multiplexer of the SerDes transmitter to serialize parallel digital data.

[0027] According to the second aspect of the embodiments of the present disclosure, the number of phases of the multi-phase clock signal is 2 N , where N is a positive integer, and the calculating the autocorrelation function of adjacent output signals includes taking the output signal of the analog-to-digital converter corresponding to the reference clock signal as a starting point, and calculating the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; the generating a phase adjustment signal according to the comparison result of the autocorrelation function includes repeatedly executing the following steps until i ranges from 1 to N: dividing the calculated 2 N autocorrelation functions into 2 i-1 groups in sequence, each group containing 2 N-i+1 autocorrelation functions, comparing the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generating a phase adjustment signal for adjusting the phase of the clock signal by (2k - 1)*360 / 2 i , where k = 1, 2,..., 2 i-1 , and the phase adjustment signal is used to indicate adjusting the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

[0028] According to the second aspect of the embodiments of the present disclosure, the number of phases of the multi-phase clock signal is 2 N , and the operating frequency of the analog-to-digital converter is 1 / (M*2 N + 1) of the operating frequency of the SerDes transmitter, where M is an integer not less than 1.

[0029] According to the second aspect of the embodiments of the present disclosure, the filter is a low-pass filter, and the cut-off frequency of the low-pass filter is related to the magnitude of the value of the autocorrelation function.

[0030] Implementing any device or method of the present disclosure does not necessarily require achieving all the above - mentioned advantages simultaneously. Other features and advantages of the present disclosure will be described in the following embodiments of the specification, and will be partly obvious from the embodiments of the specification, or will be understood by implementing the present disclosure. The objectives and advantages of the embodiments of the present disclosure can be realized and obtained through the structures pointed out in the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0032] Figure 1 A schematic block diagram showing a calibration device for a SerDes transmitter multi - phase clock according to an embodiment of the present disclosure;

[0033] Figure 2 Show Figure 1 A schematic diagram showing the output signal of the analog - to - digital converter of the calibration device for the SerDes transmitter multi - phase clock of the shown embodiment and its corresponding clock signal;

[0034] Figure 3 A schematic flowchart showing a method for calibrating the error of a four - phase clock signal according to an embodiment of the present disclosure;

[0035] Figure 4 A comparison schematic diagram showing the output pulse width generated by a multiplexer in the prior art and the ideal pulse width. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Combinations can be made between different embodiments to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in the specification and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not necessarily denote a quantity limitation. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to represent relative position relationships, and when the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0038] Figure 1 FIG. shows a schematic block diagram of a multi-phase clock calibration device for a SerDes transmitter according to an embodiment of the present disclosure. Figure 1 An example is shown in which the SerDes transmitter converts 64 parallel signals into a single serial digital signal through a 64:4 multiplexer 110 and a 4:1 multiplexer 120. The four-phase clock signal is input to the 4:1 multiplexer 120 via a clock buffer stage 140 to drive it to serialize four digital signals into a single digital signal. The 4:1 multiplexer 120 outputs the generated single serial digital signal to an output driver stage 130. The output driver stage 130 converts the digital signal into an analog signal for output.

[0039] The multi-phase clock calibration device 100 for the SerDes transmitter includes a replicated output driver stage 101, a filter 102, an analog-to-digital converter (ADC) 103, a phase error detection unit 104, and a clock phase adjustment unit 105. Figure 1 A four-phase clock signal is shown as an example of a multi-phase clock signal.

[0040] The four-phase clock signal is represented by ck0, ck90, ck180, and ck270, corresponding to the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees, respectively. Each phase signal lags 90° relative to the previous phase, and it is input to the clock phase adjustment unit 105. The clock signal after phase adjustment is transmitted to the 4:1 multiplexer 120 via the clock buffer stage 140 to sample the four digital signals output by the multiplexer 110, realizing the serialization of parallel data.

[0041] To ensure that the 4:1 multiplexer 120 outputs an accurate signal, a replicated output driver stage 101 is connected in parallel at the input of the output driver stage 130 to obtain an output signal Vcp that is the same as or proportional to the output signal Vout of the output driver stage 130. For example, the output driver stage 130 can be implemented using a transistor driver. The replicated output driver stage can obtain an output signal proportional to the output driver stage by adjusting the number of transistors and the load value.

[0042] The output signal Vcp is input to the filter 102 for filtering. The filter 102 is a low-pass filter, which can adjust the amplitude of the signal input to the analog-to-digital converter 103. By adjusting the cut-off frequency of the filter, the magnitude of the autocorrelation function value calculated by the phase error detection unit 104 can be adjusted. For example, the cut-off frequency of the low-pass filter can be set to 3 dB.

[0043] The analog signal output by the filter 102 is input to the analog-to-digital converter 103. Figure 2 Shows Figure 1 A schematic diagram of the output signal of the analog-to-digital converter and its corresponding clock signal of the SerDes transmitter multi-phase clock calibration device of the illustrated embodiment. When the operating frequency of the analog-to-digital converter 103 is the operating frequency of the transmitter, as Figure 2 shown, the digital signals obtained by the analog-to-digital converter 103 are x1(n), x2(n), x3(n), x4(n), x1(n + 1), x2(n + 1), x3(n + 1)..., which can respectively correspond to the rising edges of the clock signals ck0, ck90, ck180, ck270, and n represents the signal period.

[0044] The phase error detection unit 104 extracts the phase deviation of the four-phase clock by calculating the autocorrelation function of adjacent output signals of the analog-to-digital converter. The calculation method of the autocorrelation function between every two adjacent signals can be specifically as follows:

[0045] y 12 =E[x1(n)*x2(n)]

[0046] y 23 =E[x2(n)*x3(n)]

[0047] y 34 =E[x3(n)*x4(n)]

[0048] y 41 =E[x4(n)*x1(n+1)]

[0049] The autocorrelation function between every two adjacent signals is obtained thereby. When the signals output by the 4:1 multiplexer are ideal signals, y12 = y23 = y34 = y41. If the signals output by the 4:1 multiplexer are not ideal signals, this equation does not hold, and the phases of the multi-phase clock signals can be adjusted according to the magnitude relationship between the calculated autocorrelation functions. The phase error detection unit 104 sends a phase adjustment signal to the clock phase adjustment unit 105 according to the magnitude relationship between the autocorrelation functions. The clock phase adjustment unit 105 adjusts the phases of the input four-phase clocks according to the phase adjustment signal. Thus, the clock phases are adjusted according to the relative magnitudes of each autocorrelation function, and the clock phase adjustment unit 105 can calibrate the output signals of the 4:1 multiplexer into accurate signals.

[0050] The multiplexer in the embodiments of the present disclosure is not limited to the above multiplexer, and an 8:1 multiplexer can also be used as required. The multi-phase clock signals correspond to the multiplexer. The calibration device in the embodiments of the present disclosure is not limited to calibrating four-phase clock signals, and can also be applicable to calibrating the phases of other multi-phase clock signals.

[0051] Figure 3 A schematic flowchart of a method for error calibration of four-phase clock signals according to the magnitude relationship of autocorrelation functions according to an embodiment of the present disclosure is shown.

[0052] In step 301, the autocorrelation function y is calculated according to the output signal of the analog-to-digital converter 12 、y 23、 y 34 、y 41 .

[0053] In step 302, compare the magnitudes of |y 12 | + |y 23 | and |y 34 | + |y 41 |. If |y 12 | + |y 23 | is larger, then move the rising edge of ck180 backward. If |y 34 | + |y 41 | is larger, then move the rising edge of ck180 forward until |y 12 | + |y 23 | = |y 34 | + |y 41 |.

[0054] In step 303, compare the magnitudes of |y 12 | and |y 23 |. If |y 12 | is larger, then move the rising edge of ck90 backward. If |y23 If it is relatively large, then adjust the rising edge of ck90 forward until|y 12 |=|y 23 |.

[0055] Similarly, compare|y 34 |with|y 41 |. If|y 34 |is relatively large, then adjust the rising edge of ck270 backward. If|y 41 |is relatively large, then adjust the rising edge of ck270 forward until|y 34 |=|y 41 |.

[0056] After the above adjustments, the signal output by the 4:1 multiplexer is accurate, avoiding errors in the signal output by the transmitter.

[0057] According to a further embodiment of the present disclosure, the power consumption of phase error calibration can be reduced by reducing the operating frequencies of the analog-to-digital converter and the error detection circuit. Since the 4:1 multiplexer outputs a high-speed signal, the power consumption will be relatively large when using background calibration. By changing the calculation method of the autocorrelation function as shown below, the operating frequencies of the analog-to-digital converter and the error detection circuit only need to be 1 / 5 of that of the transmitter. The following calculation method still calculates the autocorrelation function between each group of adjacent outputs of the analog-to-digital converter, except that the delay between two adjacent output signals is greater.

[0058] y 12 =E[x1(n)*x2(n + 1)]

[0059] y 23 =E[x2(n + 1)*x3(n + 2)]

[0060] y 34 =E[x3(n + 2)*x4(n + 3)]

[0061] y 41 =E[x4(n + 3)*x1(n + 4)]

[0062] The above autocorrelation function is also applicable to the phase error calibration method described above, thereby enabling the calibration of the four-phase clock signal.

[0063] According to a still further embodiment of the present disclosure, the above method is also applicable to two-phase clock signals, eight-phase clock signals, or more-phase clock signals. If the number of phases is 2 N, where N is a positive integer, and the adjustment steps are as follows: (1) Starting from the output of the analog-to-digital converter corresponding to the reference clock signal, calculate the autocorrelation function between each group of adjacent outputs of the analog-to-digital converter. Each group of adjacent outputs corresponds to two adjacent clock signals in the multi-phase clock signal; (2) Let i range from 1 to N, and loop through the following steps: Sequentially divide the calculated autocorrelation function into 2 i-1 groups, each group contains 2 N-i+1 autocorrelation functions. Compare the sum of the first half of the autocorrelation functions with the sum of the second half of the autocorrelation functions in each group. Generate a phase adjustment signal for the clock signal with a corresponding phase of (2k - 1)*360 / 2 i where k = 1, 2,...2 i-1 . The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in this group is equal to the sum of the second half of the autocorrelation functions. The clock phase adjustment unit adjusts the phase according to the phase adjustment signal.

[0064] Considering reducing the power consumption of phase error calibration, for a multi-phase clock signal with a phase number of 2 N , the operating frequency of the analog-to-digital converter can be set to 1 / (2 N + 1) of the operating frequency of the SerDes transmitter, or the operating frequency of the analog-to-digital converter can be set to 1 / (M*2 N + 1), where M is an integer not less than 1. By adjusting the value of M, the operating frequency of the analog-to-digital converter can be further reduced.

[0065] The disclosed embodiment can calibrate all the errors of the clock transmission path and the multiplexer used for digital signal serialization while calibrating the clock signal, and can improve and ensure the accuracy of the output signal to the greatest extent. The disclosed embodiment can be used for both foreground calibration and background calibration. In addition, the frequencies of the analog-to-digital converter and the phase error detection circuit can be flexibly configured to reduce the power consumption and chip area of background calibration.

[0066] The above description is only an exemplary embodiment of the present disclosure, and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A multi-phase clock calibration device for a SerDes transmitter, characterized in that include: A duplicate output driver stage connected in parallel with the output driver stage of the SerDes transmitter, the output driver stage of the SerDes transmitter converts a digital signal into an analog signal, and the duplicate output driver stage generates a duplicate analog signal proportional to the analog signal output by the output driver stage of the SerDes transmitter; a filter connected to an output of the replicated output driver stage; an analog-to-digital converter, which receives the filtered analog signal output by the filter and converts the filtered analog signal into a digital signal; a phase error detection unit, which calculates an autocorrelation function between adjacent output signals based on the output signal of the analog-to-digital converter, and generates a phase adjustment signal according to a comparison result of the autocorrelation function; A clock phase adjustment unit receives a phase adjustment signal from the phase error detection unit and adjusts the phase of a multi-phase clock signal according to the phase adjustment signal. The multi-phase clock signal is used to drive a multiplexer at a SerDes transmitter to serialize parallel digital data into the digital signal.

2. The multi-phase clock calibration device according to claim 1, characterized in that: The number of phases of the multi-phase clock signal is 2 N , wherein N is a positive integer, the phase error detection unit takes the output signal of the analog-to-digital converter corresponding to the reference clock signal as the starting point, and calculates the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; the phase adjustment signal is generated according to the comparison result of the autocorrelation function, including cyclically executing the following steps until i is taken from 1 to N: N The autocorrelation function is divided into two i-1 Groups, each containing 2 N-i+1 autocorrelation functions, compare the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generate the corresponding phase (2k-1)*360 / 2 according to the comparison result. i The phase adjustment signal of the clock signal, where k=1,2,...,2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

3. The multi-phase clock calibration device according to claim 1 or 2, characterized in that: The multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is: y 12 =E[x1(n)*x2(n)], y 23 =E[x2(n)*x3(n)], y 34 =E[x3(n)*x4(n)], y 41 =E[x4(n)*x1(n+1)]? Where x1, x2, x3, and x4 are the output signals of the analog-to-digital converter, corresponding to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively. n represents the period of the four-phase clock signal, and y 12 ,y 23、 y 34 ,y 41 is an autocorrelation function between adjacent output signals, and generating a phase adjustment signal according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

4. The multi-phase clock calibration device according to claim 1 or 2, characterized in that: The number of phases of the multi-phase clock signal is 2 N The operating frequency of the analog-to-digital converter is 1 / (M*2 N +1), M is an integer not less than 1.

5. The multi-phase clock calibration device according to claim 4, characterized in that The multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is: y 12 =E[x1(n)*x2(n+1)], y 23 =E[x2(n+1)*x3(n+2)], y 34 =E[x3(n+2)*x4(n+3)], y 41 =E[x4(n+3)*x1(n+4)]? Wherein x1, x2, x3, and x4 correspond to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively, and n represents the period of the four-phase clock signal. The phase adjustment signal generated according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

6. The multi-phase clock calibration device according to claim 1, characterized in that The filter is a low-pass filter, and the cut-off frequency of the low-pass filter is related to the value of the autocorrelation function.

7. The multi-phase clock calibration device according to claim 1, characterized in that The input end of the duplicated output driver stage is connected in parallel with the input end of the output driver stage of the SerDes transmitter, and the output signal thereof is adjusted by adjusting the number of transistors and the load value of the duplicated output driver stage.

8. A multi-phase clock calibration method for a SerDes transmitter, characterized in that include: Generate a replica analog signal proportional to an analog signal output by an output driver stage of a SerDes transmitter, wherein the output driver stage of the SerDes transmitter converts a digital signal into an analog signal for output; low-pass filtering the copied analog signal; converting the filtered replicated analog signal into a digital signal as an output signal through an analog-to-digital converter; Calculating autocorrelation functions of adjacent output signals, and generating a phase adjustment signal according to a comparison result of the autocorrelation functions; The phase of the multi-phase clock signal is adjusted according to the phase adjustment signal, and the multi-phase clock signal is used to drive the multiplexer at the SerDes transmitting end to serialize the parallel digital data into the one digital signal.

9. The multi-phase clock calibration method according to claim 8, characterized in that The number of phases of the multi-phase clock signal is 2 N , wherein N is a positive integer, the calculating of the autocorrelation function of adjacent output signals includes taking the output signal of the analog-to-digital converter corresponding to the reference clock signal as the starting point, calculating the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; the generating of the phase adjustment signal according to the comparison result of the autocorrelation function includes cyclically executing the following steps until i is taken from 1 to N: taking the calculated 2 N The autocorrelation function is divided into two i-1 Groups, each containing 2 N-i+1 autocorrelation functions, compare the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generate an adjustment phase of (2k-1)*360 / 2 based on the comparison result. i The phase adjustment signal of the clock signal, where k=1,2,...,2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

10. The multi-phase clock calibration method according to claim 8 or 9, characterized in that The multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is: y 12 =E[x1(n)*x2(n)], y 23 =E[x2(n)*x3(n)], y 34 =E[x3(n)*x4(n)], y 41 =E[x4(n)*x1(n+1)]? Where x1, x2, x3, and x4 are the output signals of the analog-to-digital converter, corresponding to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively. n represents the period of the four-phase clock signal, and y 12 ,y 23、 y 34 ,y 41 is an autocorrelation function between adjacent output signals, and generating a phase adjustment signal according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

11. The multi-phase clock calibration method according to claim 8 or 9, characterized in that: The number of phases of the multi-phase clock signal is 2 N The operating frequency of the analog-to-digital converter is 1 / (M*2 N +1), M is an integer not less than 1.

12. The multi-phase clock calibration method according to claim 8 or 9, characterized in that: The copied analog signal is low-pass filtered using a low-pass filter having a cutoff frequency related to the magnitude of the value of the autocorrelation function.

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