Working mode switching and resetting circuit of non-network management switch

Abstract

The invention discloses a working mode switching and resetting circuit of a non-network-management switch, and the circuit comprises a mode selection switch unit which is used for selecting a working mode and comprises a dial switch; the reset signal generation unit is used for generating a reset signal when the working mode of the mode selection switch unit changes, and comprises comparators U1A, U1B, U1C and U1D; the mode switching unit is used for selecting a corresponding EEPROM channel and connecting the EEPROM channel to an I2C interface of the switching chip based on the working mode of the mode selection switch unit, and comprises EEPROM chips U31, U32, U33 and U34 and a multiplexer chip U35; and the switching chip is used for restarting and loading EEPROM channel configuration data selected by the mode switching unit after receiving the reset signal of the reset signal generation unit. According to the invention, flexible switching and automatic configuration loading of the working modes of the non-network management switch are realized, an external microcontroller is not needed, the system configuration efficiency and stability are improved, and the requirements of diversified application scenes can be met.

Description

Technical Field

[0001] The present invention relates to the field of Ethernet switches, and more particularly to a working mode switching and resetting circuit for a non-network-managed switch. Background Art

[0002] Non-network managed Ethernet switches (referred to as non-network managed switches) are widely used in traffic monitoring, power transmission, industrial manufacturing and other fields due to their ease of use and low cost. Such devices usually only have basic network transmission functions. In scenarios where more management functions are required, external microcontroller chips are added to achieve functions such as VLAN division and port isolation. Users can select and change functions through panel switches or host computer interfaces.

[0003] However, the working mode configuration of existing unmanaged switches usually relies on the switch chip to read the EEPROM connected to the I2C bus to load the configuration data when the device is powered on and reset. This method is suitable for products with a single function, but it cannot meet the selection and switching requirements of multiple working modes. When the working mode needs to be changed, traditional devices often involve a cumbersome manual reset process, which not only increases the difficulty of user operation, but also easily leads to configuration errors. At the same time, the lack of an automated reset mechanism may cause initialization failure, affecting the stable operation of the network.

[0004] In addition, although the use of external microcontroller chips can achieve more flexible mode configuration functions, this requires the switch chip and the microcontroller to have specific functional interfaces (such as SMI serial management interface). In order to reduce product costs, most of the switch chips used in unmanaged switches only provide I2C interfaces, which makes it more complicated and expensive to achieve multi-mode support and quickly adapt to environmental changes. Therefore, the existing technology has obvious deficiencies in flexibility, cost-effectiveness and user experience.

[0005] Therefore, how to design a working mode switching and reset circuit for an unmanaged switch to achieve flexible switching of the working mode and automatic configuration loading of the unmanaged switch without the need for an external microcontroller is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0006] In view of this, the present invention provides a working mode switching and reset circuit for an unmanaged switch, which integrates a mode selection switch unit, a reset signal generating unit and a mode switching unit to achieve flexible manual mode switching and automatic configuration loading, thereby reducing manual intervention while improving the stability and reliability of the system, and ensuring that each mode switch can be correctly initialized to meet the needs of diverse application scenarios.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A working mode switching and resetting circuit of a non-network-managed switch comprises: a mode selection switch unit, a reset signal generating unit, a mode switching unit and a switching chip;

[0009] The mode selection switch unit is used to select the working mode, and includes a dip switch; the pins P11 and P12 of the dip switch are connected to the positive electrode VCC of the power supply, and the pins P13 and P14 are used as output ports SW_A and SW_B respectively;

[0010] The reset signal generating unit is used to generate a reset signal when the working mode of the mode selection switch unit changes, and includes comparators U1A, U1B, U1C and U1D; the inverting input ends of the comparators U1A and U1B are respectively connected to the output ports SW_A and SW_B of the mode selection switch unit, and the output ends OUT3 and OUT4 of the comparators U1C and U1D are connected to each other as output ports, and connected to the input port RESET of the switching chip;

[0011] The mode switching unit is used to select the corresponding EEPROM channel based on the working mode of the mode selection switch unit and connect it to the I2C interface of the switching chip, including EEPROM chips U31, U32, U33, U34 and a multiplexer chip U35; the control input terminals A and B of the multiplexer chip U35 are respectively connected to the output ports SW_A and SW_B of the mode selection switch unit, and the X channel output terminal and the Y channel output terminal are respectively connected to the input ports IIC_SCL and IIC_SDA of the switching chip;

[0012] The switching chip is used to restart and load the EEPROM channel configuration data selected by the mode switching unit after receiving the reset signal from the reset signal generating unit.

[0013] Preferably, the mode selection switch unit further includes resistors R11 and R12; wherein,

[0014] One end of the resistors R11 and R12 is connected to the negative electrode GND of the power supply, and the other end is connected to the pin P13 and the pin P14 respectively.

[0015] Preferably, the reset signal generating unit further includes: resistors R21, R22, R23, R24, R25, R26, R27, R28, R29, and capacitors C21 and C22; wherein,

[0016] The non-inverting input terminals of the comparators U1A and U1B are connected to each other and in combination with the series-connected resistors R24 and R25 form a reference voltage node VREF1, which is connected to the non-inverting input terminal of the comparator U1D;

[0017] The output terminal OUT1 of the comparator U1A is connected to the resistor R21, the capacitor C21, the reference voltage node VREF2 connected in series by the resistors R22 and R23, and the non-inverting input terminal of the comparator U1C and the inverting input terminal of the comparator U1D;

[0018] The output terminal OUT2 of the comparator U1B is connected to the resistor R29, the capacitor C22, and the reference voltage node VREF2;

[0019] The resistors R26 and R27 connected in series form a reference voltage node VREF3, which is connected to the inverting input terminal of the comparator U1C;

[0020] The resistor R28 is connected to the output terminals OUT3 and OUT4 of the comparators U1C and U1D.

[0021] Preferably, the resistors R21, R22, R24, R26, R28, and R29 are also connected to the positive power supply electrode VCC, and the resistors R23, R25, and R27 are also connected to the negative power supply electrode GND.

[0022] Preferably, the mode switching unit further includes resistors R31 and R32; wherein,

[0023] One end of the resistors R31 and R32 is connected to the positive electrode VCC of the power supply, and the other end is connected to the X channel output end and the Y channel output end respectively.

[0024] It can be seen from the above technical solution that compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] Beneficial effects:

[0026] 1. This technical solution integrates multiplexers and EEPROM chips to achieve flexible switching of the working mode of non-managed switches without an external microcontroller. It not only reduces product costs, but also simplifies circuit design and shortens product development cycles. At the same time, by increasing the number of EEPROM chips and the channels of the multiplexer chip, the functions of the switch can be easily expanded to meet the needs of diverse application scenarios.

[0027] 2. When the working mode changes, the reset signal generating unit can automatically detect and generate a reset signal, triggering the switch chip to restart and load new configuration data. This mechanism ensures that the switch can quickly and accurately apply the new configuration after the mode is switched, improving the stability and reliability of the system. Compared with the traditional manual restart or complex software configuration method, this technical solution significantly improves work efficiency and user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0029] Figure 1 A schematic diagram of the structure of the working mode switching and resetting circuit of the unmanaged switch provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the structure of a mode selection switch unit provided in an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of the structure of a reset signal generating unit provided in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a working state waveform of the output port SW_A provided in an embodiment of the present invention;

[0033] Figure 5 A schematic diagram of a working state waveform of the output port SW_B provided in an embodiment of the present invention;

[0034] Figure 6 A schematic diagram of the structure of a mode switching unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] like Figure 1 As shown, this embodiment provides a working mode switching and reset circuit of an unmanaged switch, including: a mode selection switch unit 1, a reset signal generating unit 2, a mode switching unit 3 and a switching chip 4;

[0037] The mode selection switch unit 1 is used to select the working mode;

[0038] The reset signal generating unit 2 is used to generate a reset signal when the working mode of the mode selection switch unit 1 changes;

[0039] The mode switching unit 3 is used to select the corresponding EEPROM channel based on the working mode of the mode selection switch unit 1 and connect to the I2C interface of the switching chip 4;

[0040] The switching chip 4 is used for restarting and loading the EEPROM channel configuration data selected by the mode switching unit 3 after receiving the reset signal from the reset signal generating unit 2 .

[0041] It realizes the flexible switching and automatic reset function of the working mode of the unmanaged switch, without the need for an external microcontroller, reducing product costs and simplifying circuit design. At the same time, when the working mode changes, it can automatically trigger the reset signal, allowing the switch to quickly load the new configuration, improving system stability and work efficiency. Compared with existing technologies, it has significant advantages in low cost and efficient configuration.

[0042] The following is a further detailed description of each unit and related features in the above technical solution;

[0043] like Figure 2 As shown, in this embodiment, the mode selection switch unit 1 includes a dip switch;

[0044] Pins P11 and P12 of the dip switch are connected to the positive power supply VCC, and pins P13 and P14 are used as output ports SW_A and SW_B respectively; resistors R11 and R12 are also included; one end of the resistors R11 and R12 is connected to the negative power supply GND, and the other end is connected to the pins P13 and P14 respectively.

[0045] The mode selection switch unit 1 realizes the selection of different working modes through a dip switch. Pins P11 and P12 of the dip switch are connected to the positive power supply VCC to ensure that a high-level signal (logic 1) is provided when the mode is selected; and pins P13 and P14 are used as output ports SW_A and SW_B to transmit mode selection information.

[0046] In order to prevent the output port from being in an uncertain state when no mode is selected, resistors R11 and R12 are used as pull-down resistors, one end of which is connected to the negative power supply GND, and the other end is connected to pins P13 and P14 respectively, ensuring that the output port remains at a low level (logic 0) in the absence of other voltage drive, thereby ensuring the stability and reliability of the circuit.

[0047] like Figure 3 As shown, in this embodiment, the reset signal generating unit 2 includes comparators U1A, U1B, U1C and U1D; the inverting input terminals of the comparators U1A and U1B are respectively connected to the output ports SW_A and SW_B of the mode selection switch unit 1, and the output terminals OUT3 and OUT4 of the comparators U1C and U1D are connected to each other as output ports, and connected to the input port RESET of the switching chip 4;

[0048] The reset signal generating unit 2 further includes: resistors R21, R22, R23, R24, R25, R26, R27, R28, R29, and capacitors C21, C22; wherein,

[0049] The non-inverting input terminals of the comparators U1A and U1B are connected to each other and in combination with the series-connected resistors R24 and R25 form a reference voltage node VREF1, which is connected to the non-inverting input terminal of the comparator U1D;

[0050] The output terminal OUT1 of the comparator U1A is connected to the resistor R21, the capacitor C21, the reference voltage node VREF2 connected in series by the resistors R22 and R23, and the non-inverting input terminal of the comparator U1C and the inverting input terminal of the comparator U1D;

[0051] The output terminal OUT2 of the comparator U1B is connected to the resistor R29, the capacitor C22, and the reference voltage node VREF2;

[0052] The resistors R26 and R27 connected in series form a reference voltage node VREF3, which is connected to the inverting input terminal of the comparator U1C;

[0053] The resistor R28 is connected to the output terminals OUT3 and OUT4 of the comparators U1C and U1D.

[0054] Furthermore, the resistors R21, R22, R24, R26, R28, and R29 are also connected to the positive power supply electrode VCC, and the resistors R23, R25, and R27 are also connected to the negative power supply electrode GND.

[0055] The reset signal generating unit 2 generates a reset signal by monitoring the state changes of the output ports SW_A and SW_B of the mode selection switch unit 1 through a group of comparators (U1A, U1B, U1C and U1D). When the mode selection changes, the comparator detects the change of the input voltage and decides whether to trigger the reset signal through logical judgment.

[0056] The working principle of the reset signal generating unit 2 is described in detail below:

[0057] 1) Signal input and inverting output;

[0058] When the output terminal SW_A of the mode selection switch unit 1 is at a high level, the voltage at the inverting input terminal of the comparator U1A of the reset signal generating unit 2 is equal to the power supply voltage and higher than the VERF1 voltage at the same-direction input terminal. After the internal logic judgment processing, its output terminal OUT1 outputs a low level. When SW_A is at a low level, the voltage at the inverting input terminal of the comparator U1A is 0V and lower than the VERF1 voltage at the same-direction input terminal, and its output terminal OUT1 outputs a high level. This design in which the input and output are in opposite states realizes the function of the signal's inverted drive output and the isolation of the input and output signals.

[0059] 2) Capacitor charging and discharging and reference voltage changes;

[0060] When the SW_A state changes from high level to low level, the output terminal OUT1 of the comparator U1A changes from low level to high level, and a charging current is generated across the capacitor C1 at the output terminal of OUT1, which increases the current of the resistors R21 and R23. The voltage of the reference voltage node VREF2 increases due to the increase of the current of R23. When the charging of the capacitor C1 is gradually completed, the current of the resistor R23 decreases, and the reference voltage node VREF2 returns to a balanced state.

[0061] On the contrary, when the state of SW_A changes from low level to high level, the output terminal OUT1 of the comparator U1A changes from high level to low level, a discharge current is generated across the capacitor C1, and the current flowing through the resistors R21 and R22 increases. The voltage of the reference voltage node VREF2 decreases due to the increase in the current of R22. When the discharge of the capacitor C1 is gradually completed, the current of the resistor R22 decreases, and the reference voltage node VREF2 returns to a balanced state.

[0062] Since the output structure of U1A and U1B is in "open drain" mode, resistors R21 and R29 are required to provide a high-level pull-up.

[0063] 3) Comparator detection and reset signal generation:

[0064] Resistors R24 and R25 form a stable reference voltage VREF1 through voltage division, resistors R22 and R23 form a stable reference voltage VREF2 through voltage division, and resistors R26 and R27 form a stable reference voltage VREF3 through voltage division.

[0065] Comparator U1D detects the level relationship between reference voltage nodes VREF2 and VREF1. When VREF2 is higher than VREF1, U1D outputs a low level. Comparator U1C detects the level relationship between VREF2 and VREF3. When VREF2 is lower than VREF3, U1C outputs a low level.

[0066] Since the output structure of U1C and U1D is in "open drain" mode, resistor R28 is required to provide a high level pull-up. When any comparator outputs a low level, the total output signal RESET is a low level. When the RESET signal is a low level, the switching chip 4 is reset and restarted under control, and the configuration data of the EEPROM chip connected to the mode switching unit 3 is read to complete the system reset process.

[0067] In addition, the working principle of the resistor R29 and the capacitor C22 in cooperation with the comparator U1B is the same as that of U1A, and is used to process the state change of SW_B.

[0068] Specifically, Figure 4 As shown, in the working state waveform diagram of SW_A of the reset signal generating unit 2 in this embodiment, the X-axis is the level amplitude (u) of the key signal in the figure, and the Y-axis represents the waveform change time (t). The key signal points of the reset signal generating unit 2 are marked on the figure: OUT1, VREF1, VREF2, VREF3 and RESET.

[0069] At time t0, the initial state of SW_A is low level. At this time, the voltage of the inverting input terminal SW_A of the comparator U1A of the reset signal generating unit 2 is lower than the voltage of the non-inverting input terminal VERF1. After the internal logic judgment processing, its output terminal OUT1 outputs a high level. In the initial state, the levels of the three reference points VREF1, VREF2 and VREF3 are in a stable state. The level of the non-inverting input terminal VREF1 of the comparator U1D of the reset signal generating unit 2 is higher than the reverse input terminal VREF2. The level of the non-inverting input terminal VREF2 of the comparator U1C of the reset signal generating unit 2 is higher than the reverse input terminal VREF3. The total output signal RESET is high level.

[0070] At time t1, the P13 and P11 pin switches of the mode selection switch unit 2 are closed, and the state of SW_A changes from low level to high level. At this time, the voltage of the inverting input terminal SW_A of the comparator U1A of the reset signal generating unit 2 is higher than the voltage of the VERF1 of the same-direction input terminal, and its output terminal OUT1 outputs a low level, discharging the C21 capacitor, and the current flowing through the R22 resistor increases, causing the VREF2 level to drop. At this time, the VREF2 level of the comparator U1C of the reset signal generating unit 2 is lower than VREF3, and the comparator U1C outputs a low level after internal logic comparison. Since the output structure of U1C and U1D is in "open drain" mode, the total output signal RESET is a low level, and the switching chip 4 is reset and restarted under control.

[0071] At time t2, the discharge of capacitor C21 of reset signal generating unit 2 is gradually completed, and the current flowing through resistor R22 gradually decreases. At this time, the VREF2 level of comparator U1C of reset signal generating unit 2 is higher than VREF3, the reset output signal RESET becomes high, and the reset of switching chip 4 is completed.

[0072] At time t3, the capacitor C21 of the reset signal generating unit 2 is discharged, the current flowing through the resistor R22 returns to normal, and the VREF2 level returns to a stable state.

[0073] At time t4, the P13 and P11 pin switches of the mode selection switch unit 2 are disconnected, and the state of SW_A changes from high level to low level. At this time, the voltage of the inverting input terminal SW_A of the comparator U1A of the reset signal generating unit 2 is lower than the voltage of the non-inverting input terminal VERF1, and its output terminal OUT1 outputs a high level. Since the output structure of U1A is in the "open drain" mode, the current passes through R21 and R23 to charge the C21 capacitor. As the current of R23 increases, the VREF2 level increases.

[0074] At time t5, when the VREF1 level of the comparator U1D of the reset signal generating unit 2 is lower than VREF2, the comparator U1D outputs a low level after internal logic comparison. Since the output structure of U1C and U1D is in the "open drain" mode, the total output signal RESET is a low level, and the switching chip 4 is reset and restarted under control.

[0075] At time t6, the charging of capacitor C21 of reset signal generating unit 2 is gradually completed, and the current flowing through resistor R23 gradually decreases. At this time, the VREF1 level of comparator U1D of reset signal generating unit 2 is higher than VREF2, the reset output signal RESET becomes high, and the reset of switching chip 4 is completed.

[0076] At time t7, the capacitor C21 of the reset signal generating unit 2 is fully charged, the current flowing through the resistor R23 returns to normal, and the VREF2 level returns to a stable state.

[0077] In addition, if Figure 5 As shown, the working state waveform of SW_B is Figure 4 The working state waveform of SW_A is consistent with that of FIG. 1 , and will not be repeated here.

[0078] The reset signal generating unit 2 in this embodiment receives the output signal of the mode selection switch unit 1, uses the internal comparator unit to detect the change of the reference voltage, and generates a corresponding reset signal to control the reset operation of the switch chip 4. The design of this unit realizes the function of automatic reset after the working mode is switched, ensuring the stable operation of the switch.

[0079] The reset signal generating unit 2 in this embodiment receives the output signal of the mode selection switch unit 1, uses the internal comparator unit to detect the change of the reference voltage, and generates a corresponding reset signal to control the reset operation of the switch chip 4. The design of this unit realizes the function of automatic reset after the working mode is switched, ensuring the stable operation of the switch.

[0080] like Figure 6 As shown, in this embodiment, the mode switching unit 3 includes EEPROM chips U31, U32, U33, U34 and a multiplexer chip U35; the control input terminals A and B of the multiplexer chip U35 are respectively connected to the output ports SW_A and SW_B of the mode selection switch unit 1, and the X channel output terminal and the Y channel output terminal are respectively connected to the input ports IIC_SCL and IIC_SDA of the switching chip 4; the mode switching unit 3 also includes resistors R31 and R32; one end of the resistors R31 and R32 is connected to the positive electrode VCC of the power supply, and the other end is respectively connected to the X channel output terminal and the Y channel output terminal.

[0081] The working principle of the mode switching unit 3 is described in detail below:

[0082] When the mode selection switch unit 1 sends specific signals to the control input terminals A and B of the multiplexer chip U35, the multiplexer chip U35 will select the corresponding EEPROM chip (one of U31, U32, U33, U34) for communication according to these signals. The specific rules are:

[0083] 00 switches to the EEPROM chip U31 of channel X0 and Y0, 01 switches to the EEPROM chip U32 of channel X1 and Y1, 10 switches to the EEPROM chip U33 of channel X2 and Y2, and 11 switches to the EEPROM chip U34 of channel X3 and Y3, realizing configuration data switching of multiple working modes.

[0084] Further, the selected EEPROM chip will be connected to the input ports IIC_SCL and IIC_SDA of the switch chip 4 through the X channel output terminal and the Y channel output terminal of the multiplexer chip U35.

[0085] In addition, resistors R31 and R32 are respectively connected between the positive power supply VCC and the X channel output terminal and the Y channel output terminal of the multiplexer chip U35. Because the I2C bus structure is in "open drain" mode, R31 and R32 provide a high level pull-up for the I2C bus to ensure the correct judgment of the I2C bus logic level.

[0086] By changing the output signal of the mode selection switch unit 1, the working mode of the mode switching unit 3 can be dynamically switched, thereby realizing access to different EEPROM chips and data exchange. The mode switching unit 3 realizes flexible selection and data exchange of different EEPROM chips through the coordinated work of the multiplexer chip U35 and the mode selection switch unit 1.

[0087] In this embodiment, the switching chip 4 is used to restart and load the EEPROM channel configuration data selected by the mode switching unit 3 after receiving the reset signal from the reset signal generating unit 2 .

[0088] Specifically, when the reset signal generating unit 2 detects that the working mode of the mode selection switch unit 1 changes, it generates a reset signal and transmits it to the reset input interface (RESET) of the switching chip 4. After receiving the reset signal, the switching chip 4 will perform a restart operation.

[0089] After the restart is completed, the switch chip 4 reads the configuration data from the EEPROM channel selected by the mode switching unit 3 through the I2C bus interface (IIC_SCL and IIC_SDA), and reconfigures its working mode according to the data.

[0090] The switching chip 4 is usually composed of a system circuit composed of an Ethernet switching PHY chip. However, in the solution of the present invention, only its reset input interface (RESET) and I2C bus interface (IIC_SCL and IIC_SDA) are involved, and the rest of the parts are not directly related to the working mode switching and reset circuit solution of a non-network management switch of the present invention, so they are not described in detail in this embodiment.

[0091] In this way, the switching chip 4 can automatically load the corresponding configuration according to the different working modes selected by the user, ensuring that the device can be correctly initialized and run stably after each mode switch.

[0092] This embodiment provides a working mode switching and reset circuit of a non-network-managed switch, including a mode selection switch unit 1, a reset signal generating unit 2, a mode switching unit 3 and a switching chip 4. The mode selection switch unit 1 realizes the selection of different working modes through a dip switch and a pull-down resistor; the reset signal generating unit 2 uses a group of comparators to monitor the mode change and generate a reset signal; the mode switching unit 3 selects the corresponding configuration data channel according to the mode selection result based on a multiplexer and multiple EEPROM chips; the switching chip 4 restarts after receiving the reset signal and loads the selected EEPROM configuration data through the I2C bus. It realizes the automatic reset and mode switching function without the need for an external microcontroller, reduces the cost and improves the stability and work efficiency of the system.

[0093] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0094] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A working mode switching and resetting circuit for an unmanaged switch, characterized in that: include: A mode selection switch unit (1), a reset signal generating unit (2), a mode switching unit (3) and a switching chip (4); The mode selection switch unit (1) is used to select the working mode and comprises a dip switch; the pins P11 and P12 of the dip switch are connected to the positive electrode VCC of the power supply, and the pins P13 and P14 are used as output ports SW_A and SW_B respectively; The reset signal generating unit (2) is used to generate a reset signal when the working mode of the mode selection switch unit (1) changes, and comprises comparators U1A, U1B, U1C and U1D; the inverting input ends of the comparators U1A and U1B are respectively connected to the output ports SW_A and SW_B of the mode selection switch unit (1); the output ends OUT3 and OUT4 of the comparators U1C and U1D are connected to each other as output ports and connected to the input port RESET of the switching chip (4); The mode switching unit (3) is used to select a corresponding EEPROM channel based on the working mode of the mode selection switch unit (1) and connect it to the I2C interface of the switching chip (4), and comprises EEPROM chips U31, U32, U33, U34 and a multiplexer chip U35; the control input terminals A and B of the multiplexer chip U35 are respectively connected to the output ports SW_A and SW_B of the mode selection switch unit (1), and the X channel output terminal and the Y channel output terminal are respectively connected to the input ports IIC_SCL and IIC_SDA of the switching chip (4); The switching chip (4) is used to restart and load the EEPROM channel configuration data selected by the mode switching unit (3) after receiving the reset signal from the reset signal generating unit (2).

2. The working mode switching and resetting circuit of an unmanaged switch according to claim 1, characterized in that: The mode selection switch unit (1) further comprises resistors R11 and R12; wherein: One end of the resistors R11 and R12 is connected to the negative electrode GND of the power supply, and the other end is connected to the pin P13 and the pin P14 respectively.

3. The working mode switching and resetting circuit of an unmanaged switch according to claim 1, characterized in that: The reset signal generating unit (2) further comprises: resistors R21, R22, R23, R24, R25, R26, R27, R28, R29, and capacitors C21, C22; wherein, The non-inverting input terminals of the comparators U1A and U1B are connected to each other and in combination with the series-connected resistors R24 and R25 form a reference voltage node VREF1, which is connected to the non-inverting input terminal of the comparator U1D; The output terminal OUT1 of the comparator U1A is connected to the resistor R21, the capacitor C21, the reference voltage node VREF2 connected in series by the resistors R22 and R23, and the non-inverting input terminal of the comparator U1C and the inverting input terminal of the comparator U1D; The output terminal OUT2 of the comparator U1B is connected to the resistor R29, the capacitor C22, and the reference voltage node VREF2; The resistors R26 and R27 connected in series form a reference voltage node VREF3, which is connected to the inverting input terminal of the comparator U1C; The resistor R28 is connected to the output terminals OUT3 and OUT4 of the comparators U1C and U1D.

4. The working mode switching and resetting circuit of the unmanaged switch according to claim 3, characterized in that: The resistors R21, R22, R24, R26, R28, and R29 are also connected to the positive power supply electrode VCC, and the resistors R23, R25, and R27 are also connected to the negative power supply electrode GND.

5. The working mode switching and resetting circuit of an unmanaged switch according to claim 1, characterized in that: The mode switching unit (3) further includes resistors R31 and R32; Among them, one end of the resistors R31 and R32 is connected to the positive electrode VCC of the power supply, and the other end is connected to the X channel output end and the Y channel output end respectively.

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