Superscalar packet processing

Abstract

The disclosed systems and methods provide superscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating the plurality of network packets to a plurality of packet processing blocks including one or more full processing blocks and one or more restricted processing blocks based at least in part on an arbitration policy. The method also includes processing the plurality of network packets in parallel via the plurality of packet processing blocks, where each of the one or more full processing blocks processes a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks processes a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets. The method also includes transmitting the processed network packet over a data bus.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application of the invention patent application with application date of October 26, 2020, application number 202011153323.6, and invention name “Superscalar Packet Processing”. Technical Field

[0003] The present invention relates generally to packet processing, and more particularly to methods and systems for providing superscalar packet processing to optimize circuit integration, reduce power consumption and latency, and improve performance. Background Art

[0004] In packet processing devices such as network switches and routers, switching to smaller processing nodes is often sufficient to meet increasing performance targets. However, as the feature size of processing nodes approaches physical limits, it becomes more difficult to achieve performance improvements from process shrinking alone. At the same time, high performance computing and other demanding scale-out applications in data centers continue to require higher performance that conventional packet processing devices cannot meet. Delay-sensitive applications further require specialized hardware features such as ternary content addressable memory ("TCAM"), which in turn imposes performance constraints, which cause more obstacles in meeting performance targets. Summary of the invention

[0005] One embodiment of the present invention relates to a method, comprising: receiving multiple network packets from multiple data paths; arbitrating the multiple network packets to multiple packet processing blocks including one or more full processing blocks and one or more restricted processing blocks based at least in part on an arbitration strategy; processing the multiple network packets in parallel via the multiple packet processing blocks, wherein each of the one or more full processing blocks processes a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks processes a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets; and sending the processed network packets through multiple data buses.

[0006] Another embodiment of the present invention relates to a system: comprising: a first shared bus having a first arbitrator configured to receive multiple network packets from multiple data paths; multiple packet processing blocks, including one or more full processing blocks and one or more restricted processing blocks, wherein each of the one or more full processing blocks is configured to process a first number of network packets during a clock cycle, and each of the one or more restricted processing blocks is configured to process a second number of network packets during the clock cycle, and the second number of network packets is greater than the first number of network packets; wherein the first arbitrator is configured to arbitrate the multiple network packets at least in part based on an arbitration strategy for parallel processing by the multiple packet processing blocks; and a second shared bus having a second arbitrator configured to arbitrate the processed multiple network packets to multiple data buses at least in part based on the arbitration strategy.

[0007] Another embodiment of the present invention relates to a non-temporary storage medium comprising instructions, which, when read by one or more processors, produces a method comprising: receiving multiple network packets from multiple data paths; arbitrating the multiple network packets to multiple packet processing blocks comprising one or more full processing blocks and one or more restricted processing blocks based at least in part on an arbitration strategy; processing the multiple network packets in parallel via the multiple packet processing blocks, wherein each of the one or more full processing blocks processes a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks processes a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets; and sending the processed multiple network packets via multiple data buses. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various objects, features and advantages of the present invention may be more fully understood with reference to the following detailed description when considered in conjunction with the following drawings, in which like reference numerals identify like elements. The following drawings are for illustrative purposes only and are not intended to limit the present invention, the scope of which is set forth in the following claims.

[0009] Figure 1A Depicted is an example network environment in which superscalar packet processing may be implemented in accordance with various aspects of the present technology.

[0010] Figure 1B A logical block diagram depicting ingress / egress packet processing within an example network switch for providing superscalar packet processing in accordance with various aspects of the present technology.

[0011] Figure 2A An example system for processing a single packet from a single data path in accordance with various aspects of the present technology is depicted.

[0012] Figure 2B An example system for processing dual packets from two data paths in accordance with various aspects of the present technology is depicted.

[0013] Figure 2C An example system for logically grouping two dual packet processing blocks together in accordance with various aspects of the present technology is depicted.

[0014] Figure 2D An example system for enforcing an arbitration policy using an arbitrator on a shared bus in accordance with various aspects of the present technology is depicted.

[0015] Figure 2E An example system for arbitrating data paths through individual packet processing pipelines in accordance with various aspects of the present technology is depicted.

[0016] Figure 2F An example system for arbitrating data paths through aggregating packet processing pipelines according to various aspects of the present technology is depicted.

[0017] Figure 2G Describes various aspects of the technology according to the present invention Figure 2C Logical grouping and Figure 2F An example of an aggregation packet processing pipeline for the system.

[0018] Figure 2H Describes various aspects of the technology according to the present invention Figures 2A to 2G Features are presented to provide an example system for superscalar packet processing.

[0019] Figure 3A An example system supporting eight data paths through four packet processing blocks is depicted in accordance with various aspects of the present technology.

[0020] Figure 3B An example system is depicted to reduce latency by providing a slot event queue and a scheduler to read out events according to various aspects of the present technology.

[0021] Figure 4 An example process is depicted for using superscalar packet processing to optimize circuit integration, reduce power consumption and latency, and improve performance in accordance with various aspects of the present technology.

[0022] Figure 5 Illustrated is an electronic system with which one or more implementations of the present technology may be implemented. DETAILED DESCRIPTION

[0023] Although several aspects of the present technology are described herein with reference to illustrative examples for specific applications, it should be understood that the present technology is not limited to those specific applications. Those skilled in the art who can use the teachings provided herein will recognize additional modifications, applications, and aspects within the scope thereof, as well as additional areas in which the present technology will have significant utility.

[0024] In order to meet the growing performance demands of modern data centers and high-performance computing applications, device architecture improvements are needed to maintain performance momentum given the slow process node improvements. In particular, packet processing devices such as switches can be configured to use superscalar packet processing, which enables high-performance packet processing of multiple packets simultaneously using efficient hardware implementations. In this application, the term superscalar packet processing refers to the use of a combination of architectural features to enable hardware-accelerated processing of multiple network packets simultaneously in a given clock cycle. For example, instead of using the same packet processing for all packets, packets can be processed by limited processing blocks (LPBs) or full processing blocks (FPBs) depending on the complexity of the packets. In addition, processing blocks can be placed in a physical circuit group layout that implements intelligent sharing of logic and lookups to reduce the total circuit area, thereby reducing power consumption and reducing die size.

[0025] Superscalar packet processing may be particularly relevant to high performance computing (HPC) applications that may generate a large number of small control packets with stringent latency requirements. These control packets may not require the same packet processing volume as data packets. By utilizing multiple LPBs, such control packets may be processed quickly at a high rate while providing very low latency. Furthermore, since the LPBs may support a limited set of features, the LPBs may be configured to process more than one packet during one clock cycle, further improving bandwidth and performance, compared to an FPB that processes one packet through a full feature pipeline.

[0026] Figure 1A An example network environment 100 is depicted for providing superscalar packet processing in accordance with various aspects of the present technology. However, not all depicted components may be used in all embodiments, and one or more embodiments may include additional or different components than those shown in the figures. The arrangement and types of components may be varied without departing from the spirit or scope of the claims as set forth herein. Additional, different, or fewer components may be provided.

[0027] The network environment 100 includes one or more electronic devices 102A-102C connected via a network switch 104. The electronic devices 102A-102C may be connected to the network switch 104 so that the electronic devices 102A-102C may be able to communicate with each other via the network switch 104. The electronic devices 102A-102C may be connected to the network switch 104 via wires (e.g., Ethernet cables) or wirelessly. The network switch 104 may be and / or may include the following descriptions of the electronic devices 102A-102C. Figure 1B The ingress / egress packet processing 105 of the network switch discussed below with respect to Figure 5 All or part of the electronic system discussed. Electronic devices 102A-102C are presented as examples, and in other implementations, other devices may replace one or more of electronic devices 102A-102C.

[0028] For example, the electronic devices 102A-102C may be computing devices such as laptop computers, desktop computers, servers, peripheral devices (e.g., printers, digital cameras), mobile devices (e.g., mobile phones, tablet computers), fixed devices (e.g., set-top boxes), or other suitable devices capable of communicating via a network. In FIG. 1 , by way of example, the electronic devices 102A-102C are depicted as network servers. The electronic devices 102A-102C may also be network devices such as other network switches, etc.

[0029] The network switch 104 may implement the superscalar packet processing described herein. Figure 1B Further discussion of the ingress / egress packet processing 105 of an example network switch 104 implementing the system of the present invention is provided below with respect to Figure 4 An example process for implementing the network switch 104 of the present system is further discussed.

[0030] The network switch 104 can implement superscalar packet processing, which refers to a combination of several features that optimize circuit integration, reduce power consumption and latency, and improve packet processing performance. Packet processing can include several different functions, such as determining the correct port to forward the packet to its destination, collecting diagnostic and performance data such as network counters, and performing packet inspection and service classification to implement quality of service (QoS), as well as other load balancing and service prioritization functions. Some of these functions may require more complex processing than other functions. Therefore, one feature of superscalar packet processing is to provide two different packet processing blocks and arbitrate the packets accordingly: limited processing block (LPB) and full processing block (FPB). Since packets can vary greatly in the required processing volume, it is wasteful to use a size-fits-all packet processing block to process all types of packets. By utilizing LPB, smaller packets with less processing requirements can be quickly processed to provide extremely low latency. In addition, since LPB can support a limited feature set, LPB can be configured to process more than one packet during a clock cycle compared to FPB that processes one packet, thereby improving bandwidth and performance.

[0031] The number of LPBs and FPBs can be adjusted according to the workload. The LPBs and FPBs can correspond to the logical packet processing blocks in the figure. However, in some embodiments, the LPBs and FPBs can correspond to physical packet processing blocks or some combination thereof. For example, latency-sensitive applications and transactional databases may prefer a design with a large number of LPBs to handle bursts of smaller control packets. On the other hand, applications that require sustained bandwidth for large packets (such as content delivery networks or cloud backups) may prefer a design with a large number of FPBs.

[0032] Another feature is organizing the processing blocks into physical groups, providing a single logic structure with circuitry such as logic and lookup that is shared between the processing blocks to optimize circuit area and power consumption. Such grouped processing blocks may be able to process packets from multiple data paths, with corresponding data structures provided to allow for coherent and stateful processing of packets. This may also enable the aggregated processing blocks to provide greater bandwidth to better absorb bursty traffic and provide reliable response times compared to individual processing blocks with independent pipelines (which may become easily saturated, especially with increasing port speed requirements).

[0033] Another feature is that all interfaces use a single shared bus and arbiter, resulting in efficient use of available system bus bandwidth. The arbiter can enforce packet spacing rules and allow auxiliary commands to be processed when no packets are being processed during a cycle.

[0034] Another feature is to provide slot event queues for the data path and scheduler to enforce spacing rules and control the publication of events. By providing these features, events are not blocked by worst-case data path delays, which helps further reduce delays and improve response times.

[0035] Figure 1B A logical block diagram depicting ingress / egress packet processing 105 of an example network switch 104 for providing superscalar packet processing in accordance with various aspects of the present technology is depicted. Although ingress packet processing is discussed in the following example, ingress / egress packet processing 105 may also be applicable to egress packet processing. Ingress / egress packet processing 105 includes: group 120A, group 120B, group 140A, first-in-first-out (FIFO) queue 142, shared bus 180A, shared bus 180B, column 190A, column 190B, column 190C, and column 190D. Group 120A includes LPB 130A and LPB 130B. Group 120B includes LPB 130C and LPB 130D. Group 140A includes FPB 150A and FPB 150B. It should be understood that Figure 1B The specific layout shown in is illustrative, but any combination, grouping, and number of LPBs and FPBs may be provided in other implementations.

[0036] like Figure 1B , data paths 110A, 110B, 110C, and 110D may receive data packets arbitrated by various packet processing and publishing blocks via shared bus 180A and shared bus 180B. Shared bus 180A and 180B may achieve more efficient bandwidth utilization across high-speed interconnects compared to separate individual buses with less bandwidth capabilities. For example, packets may be analyzed based on packet size. If a packet is determined to be at or below a threshold packet size, such as 64 bytes, 290 bytes, or another value, the packet may be arbitrated to one of the restricted processing blocks or LPBs 130A to 130D. This threshold packet size may be stored as a rule for an arbitration policy. In addition to packet size, arbitration policy rules may also be based on fields in the packet header, such as a packet type field, a source port number, or any other field for arbitration. For example, if the type field indicates that the packet is a barrier or control packet rather than a data packet, the packet may be arbitrated to one of the restricted processing blocks. Additional arrows that bypass LPBs 130A-130D in groups 120A-120B may correspond to, for example, Figure 3B A data path 350 is provided in which the data payload is separated and transmitted on a path separate from the packet processing pipeline.

[0037] Otherwise, if the packet is determined to exceed a threshold packet size, or if arbitration policy rules otherwise indicate that the packet should be sent to a full processing block, the packet may be arbitrated to a full processing block or one of FPBs 150A-150B. The arbitration policy may also assign data paths to specific processing blocks. For example, data path 110A may be assigned to Figure 1B However, in other embodiments, the data path may be arbitrated to any available processing block. Enforcement of the arbitration policy may be performed by an arbitrator of shared buses 180A and 180B, as described below. Figure 2D Described in .

[0038] As discussed above, each LPB 130A-130D may be able to process multiple packets in a single clock cycle, or two packets in the specific example shown. For example, each LPB 130A-130D may support a restricted packet processing feature set, such as by ignoring deep packet inspection and other features that require analysis of the packet payload. Since the data payload does not need to be analyzed, the data payload may be sent separately outside the LPB 130A-130D. In this way, the processing pipeline may be simplified and reduced in length and complexity, allowing multiple restricted signature packet processing pipelines to be implemented within a physical circuit area that may be equal to that of a single full signature packet processing pipeline. Thus, the LPB 130A-130D may process up to 8 packets, with each LPB 130A-130D sending two processed packets to a respective post 190A-190D.

[0039] On the other hand, each FPB 150A-150B can process a single packet in a single clock cycle. Therefore, FPB 150A-150B can process a maximum of 2 packets, where FPB 150A can send the processed packet to pillar 190A or pillar 190B, and FPB 150B can send the processed packet to pillar 190C or 190D. Pillars 190A-190D can perform post-processing by, for example, reassembling the processed packet with the separated data payload, and if necessary further preparing the assembled packet for sending on the data bus (which can include serialized data packets). After pillars 190A-190D, the serialized and processed packets can be sent on the respective data buses 1-4, which can be further connected to a memory management unit (MMU).

[0040] The data paths 110A to 110D may specifically correspond to Figure 1B190A to 190D may output to a corresponding egress data bus, which may be further connected to an upstream network data port.

[0041] Groups 120A, 120B, and 140A may be organized to more efficiently share and utilize circuitry between or within processing blocks contained in each group. In this way, circuit integration may be optimized, power consumption and latency may be reduced, and performance may be improved. For example, groups 120A, 120B, and 140A may share logic and lookups within each group to reduce overall circuit area, such as Figure 2C The reduced circuit area may consume less power. Group 140A may provide a data structure to allow for coherent and stateful processing of packets in an aggregated pipeline, such as Figure 2F Groups 120A to 120B and 140A may further utilize Figure 2C , Figure 3A and Figure 3B The shared buses 180A and 180B may include separate data and processing pipelines as described in Figure 2D Arbiter 250 described in .

[0042] Figure 2A An example system for processing a single packet from a single data path according to various aspects of the present technology is depicted. Figure 2A As shown in FIG. 1 , a single data path or data path 110A is processed by a single full processing block or FPB 150A. FPB 150A includes a single packet processing 210 capable of processing a single packet of any size for each clock cycle. Data path 110A and single packet processing 210 may share the same clock signal frequency. In a packet processing device, Figure 2A The system can be replicated to support several data paths that can correspond to several network ports.

[0043] The packet to be processed may include: a header of a packet (HOP), which includes a start of packet (SOP) indication and a number of bytes to be processed, a payload, and a tail of a packet (TOP), which includes the packet size and error information. The portion of the packet to be processed may be referred to as the start and end of packet (SEOP), and the payload may be bypassed using a separate non-processing pipeline.

[0044] Figure 2BDescribe the example system for processing dual packets from data paths 110A and 110B according to various aspects of the present technology. As discussed above, a key point is that packets can vary greatly in required processing volume. When packets are below a processing threshold (which can correspond to a packet size threshold), a limited processing block such as LPB 130A can be used to process packets. Compared with FPB 150A, which supports all possible functionalities of all packets, LPB 130A can be implemented using a much simpler circuit design. Therefore, LPB 130A can provide dedicated hardware to process multiple packets from multiple data paths in a single clock cycle. Dual packet processing 212 can process packets from each of data paths 110A and 110B in a single clock cycle. In addition, since LPB 130A is a block separated from FPB 150A, packets processed by LPB 130A can be completed faster with lower latency. For example, as discussed above, the processing pipeline for LPB 130A may be significantly shorter than the processing pipeline for FPB 150A. In one embodiment, the minimum latency for processing a packet through LPB 130A may be approximately 25 ns, while the minimum latency for processing a packet through FPB 150A may be approximately 220 ns. Figure 2B There are two (2) data paths shown in Figure 2B The concept can be extended to multiple data paths, such as Figure 3A The eight (8) data paths shown in FIG.

[0045] Figure 2C An example system for logically grouping together dual packet processes 212A and 212B according to various aspects of the present technology is depicted. Group 120A includes dual packet processes 212A and 212B that may be physically close in circuit layout. This proximity allows dual packet processes 212A and 212B to share logic and lookups to optimize circuit area. At the same time, group 120A may also be logically grouped together to present a single logical processing block, for example, by sharing a logical data structure such as a table structure. Incoming data packets from data paths 110A to 110D may be sent to the data path 110A through 110D, for example, by Figure 1B To determine which processing block to route the data packet, for example, Figure 2D The arbiter of 250 is an arbiter.

[0046] Figure 2DDescribe the example system for enforcing arbitration strategy using arbitrator 250 on shared bus according to various aspects of the present technology. Although arbitrator 250 is shown as including two input interfaces 230A to 230B and two output interfaces 232A to 232B, it should be understood that the number of interfaces can be adjusted in proportion according to bus arbitration requirements in shared buses 180A and 180B, for example. Therefore, shared buses 180A and 180B can include corresponding arbitrator 250. Arbitrator 250 can receive packets from multiple data paths or interfaces 230A and 230B. Therefore, arbitrator 250 can be used to arbitrate multiple data paths through a single shared bus to improve interconnection bandwidth utilization. Based on the packet size arbitration rules and packet interval rules defined in the arbitration strategy, arbitrator 250 can output packets to be processed via interfaces 232A and 232B, which can be further connected to packet processing blocks. Packet interval rules can be enforced on a per-group basis. For example, packet interval rules can enforce minimum intervals between certain packets according to data dependencies, business management, pipeline rules or other factors. For example, to reduce circuit complexity and power consumption, the pipeline may be simplified to support a specific type of consecutive commands, such as a table initialization command, only after completing a full pipeline of, for example, 20 cycles. Thus, when such a table initialization command is encountered, the packet spacing rule may enforce a minimum spacing of 20 cycles before another table initialization command may be processed. The arbitration strategy may also force the data paths to be assigned to certain interfaces, which may allow the table access structure to be implemented in a simplified manner, such as by reducing multiplexer and demultiplexer lines.

[0047] When there are no packets to be processed in the group, such as during free slots 234A, 234B, and 234C, arbiter 250 may output ancillary or auxiliary commands received from command input 222, which may be received from centralized control circuitry. For example, ancillary commands may perform bookkeeping, maintenance, diagnostics, and other functions outside of normal packet processing functionality.

[0048] Figure 2E An example system is depicted for routing data paths 110A-110D through individual packet processing pipelines or pipelines 260A-260D that arbitrate into packet processing (PP) 262A-262B according to various aspects of the present technology. Pipes 260A-260D may correspond to Figure 1B Each PP 262A-262B may include a complete processing block similar to FPB 150A. The amount of packet data sent through each data path 110A-110D may be visually represented by the thickness of the arrow. Figure 2E , due to the large burst of packet data from data path 110C, this can cause packet congestion at pipe 260C. As a result, packets may be significantly delayed or lost before reaching PP 262B.

[0049] Figure 2F An example system is depicted for arbitrating data paths 110A through 110D by aggregating packet processing pipelines or pipelines 260E in accordance with various aspects of the present technology. Figure 2F , rather than processing through independent pipes 260A-260D, a single aggregate pipe 260E is provided that can support a combined bandwidth corresponding to the sum of pipes 260A-260D. This allows pipe 260E to better handle bursty traffic from any of the data paths 110A-110D, thereby helping to avoid delayed or lost packets. However, this can result in group 240 processing multiple packets from the same flow or data path in a single cycle. To support this, data structures can be provided to enable coherent and stateful processing of packets in group 240.

[0050] For example, hardware data structures may be provided so that counters, meters, elephant traps (ETRAPs), and other structures may be accessed for concurrent reads and writes across PPs 262A-262B even when processing packets from the same data path. Such hardware data structures for group 240 may include four 4-read, 1-write structures, or two 4-read, 2-write structures, or one 4-read, 4-write structure.

[0051] Figure 2G Describes various aspects of the technology according to the present invention Figure 2C Logical grouping and Figure 2F An example of an aggregation packet processing pipeline system. Figure 2G As shown in FIG. 1 , any of the data paths 110A to 110D may be handled by a single packet process 210A or 210B. For example, a shared bus may be provided such as Figure 2D The arbiter 250 shown in FIG. 1 is used to arbitrate packets into group 140A. Figure 2F Like group 240 in FIG. 1 , group 140A may receive packets from the aggregated pipeline. Thus, group 140A may include similar hardware data structures to support coherent and stateful processing.

[0052] Figure 2H Describes various aspects of the technology according to the present invention Figures 2A to 2G The features shown in the example system are used to provide superscalar packet processing. Figure 2H As shown in FIG. 1 , the four data paths 110A to 110D may be implemented by Figures 2A to 2G The ingress / egress packet processing 105 of the network switch 104 may be processed to provide superscalar packet processing. For example, referring to Figure 1B , the network switch 104 can process a maximum of 10 packets in a single cycle.

[0053] Figure 3A An example system is depicted for supporting eight data paths or data paths 110A-110H through four packet processing blocks or PPs 312A-312D in accordance with various aspects of the present technology. PPs 312A-312D may correspond to LPBs. Figure 3A , the data path may be separated into a packet first-in-first-out (FIFO) 330A-330H for payload, and a FIFO into the scheduler 310 for packet data to be processed. The packet FIFOs 330A-330H may provide a path for packet data to be transmitted without processing, while the scheduler 310 may receive the SEOP data into the FIFO queue for processing. Each PP 312A-312D may process two packets in a single cycle, which are then output to the demultiplexer 320 to be sent separately to the posts 190A-190H. The processed SEOPs may be reassembled at the respective posts 190A-190H with the output from the corresponding packet FIFO 330A-330H for output to the respective data bus.

[0054] Figure 3B Describes an example system for reducing latency by providing a slot event queue 352 and a scheduler 354 to read out events according to various aspects of the present technology. For example, Figure 3B The system can be implemented in an FPB such as FPB 150A or FPB 150B. Ldp represents the total delay of data path 350, and Lpp represents the total delay of pipeline processing 360. Packets can be read from inlet data buffer 340, where the payload advances through data path 350, and SEOP advances through input event FIFO 342 for pipeline processing 360. By providing slot event queue 352 and scheduler 354, additional delay from the worst case occupancy of emptying input event FIFO 342 can be avoided. For example, scheduler 354 can be configured to publish SOP events to column 370 only when SOP events exist in both output event FIFO 362 and slot event queue 352. Other events in slot event queue 352 can be published when on the head.

[0055] Figure 4Describe the example process 400 that uses superscalar packet processing to optimize circuit integration, reduce power consumption and delay and improve performance according to various aspects of the present technology. For explanatory purposes, various blocks of the example process 400 are described herein with reference to Figures 1 to 3B and the components and / or processes described herein. One or more of the blocks of process 400 may be implemented, for example, by a computing device, including a processor and other components utilized by the device. In some embodiments, one or more of the blocks may be separated from other blocks and implemented by one or more different processors or devices. Further for explanatory purposes, the blocks of the example process 400 are described as occurring in series or linearly. However, multiple blocks of the example process 400 may occur in parallel. In addition, the blocks of the example process 400 do not need to be implemented in the order shown, and / or one or more blocks in the example process 400 do not need to be implemented.

[0056] In the example flow chart depicted, a network packet is received from a data path (411). Figure 1B , which may correspond to receiving network packets from data paths 110A to 110D.

[0057] Process 400 may continue by arbitrating the network packet to a packet processing block including one or more full processing blocks and one or more restricted processing blocks based at least in part on the arbitration policy (412). Thus, for example, the network packet may be arbitrated to FPBs 150A-150B and / or LPBs 130A-130D using arbitrator 250 in shared bus 180A. Figure 1B As shown in , a FIFO queue 142 may be provided for FPBs 150A-150B.

[0058] Process 400 may continue by processing network packets in parallel via packet processing blocks, wherein each of the one or more full processing blocks processes a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks processes a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets (413). For example, the first number may correspond to one, and the second number may correspond to at least twice the first number, such as two. Thus, within a given clock cycle, FPBs 150A-150B and LPBs 130A-130D may process a maximum of 10 packets.

[0059] Process 400 may continue with the following operations: sending the processed network packets over multiple data buses (414). For example, the processed network packets may be reassembled and serialized via pillars 190A-190D for sending via respective data buses 1-4. An arbiter similar to arbiter 250 may be provided to enforce packet spacing rules at pillars 190A-190D within shared bus 180B.

[0060] Many aspects of the example process 400 described above, as well as related features and applications, may also be implemented as a software process that is specified as a set of instructions recorded on a computer-readable storage medium (also referred to as a computer-readable medium) and that can be automatically executed (e.g., without user intervention). When these instructions are executed by one or more processing units (e.g., one or more processors, processor cores, or other processing units), they cause the processing units to perform the actions indicated in the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, EPROMs, etc. Computer-readable media do not include carrier waves and electronic signals transmitted wirelessly or via wired connections.

[0061] Where appropriate, the term "software" means firmware residing in a read-only memory or an application stored in a magnetic storage device, which can be read into a memory to be processed by a processor. In addition, in some embodiments, multiple software aspects of the present invention can be implemented as sub-parts of a larger program while retaining different software aspects of the present invention. In some embodiments, multiple software aspects can also be implemented as separate programs. Finally, any combination of separate programs that implement the software aspects described herein together is within the scope of the present invention. In some embodiments, when a software program is installed to operate on one or more electronic systems, it defines one or more specific machine implementations that execute and implement the operation of the software program.

[0062] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may correspond to a file in a file system, but need not correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store portions of one or more modules, subroutines, or code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0063] Figure 5 An electronic system 500 is illustrated that can be used to implement one or more embodiments of the present technology. Figure 1B500 and / or a portion of the network switch 104 shown in . The electronic system 500 may include various types of computer-readable media and interfaces for various other types of computer-readable media. The electronic system 500 includes a bus 508, one or more processing units 512, a system memory 504 (and / or buffers), a ROM 510, a permanent storage device 502, an input device interface 514, an output device interface 506, and one or more network interfaces 516, or subsets and variations thereof.

[0064] Bus 508 collectively represents all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of electronic system 500. In one or more implementations, bus 508 communicatively connects one or more processing units 512 with ROM 510, system memory 504, and permanent storage 502. One or more processing units 512 retrieve instructions to execute and data to process from these various memory units in order to perform the processes of the present invention. In different implementations, one or more processing units 512 may be a single processor or a multi-core processor.

[0065] ROM 510 stores static data and instructions required by one or more processing units 512 and other modules of electronic system 500. On the other hand, permanent storage 502 can be a read-write memory device. Permanent storage 502 can be a non-volatile memory unit that stores instructions and data even when electronic system 500 is turned off. In one or more implementations, a mass storage device (such as a magnetic disk or optical disk and its corresponding disk drive) can be used as permanent storage 502.

[0066] In one or more embodiments, a removable storage device (such as a floppy disk, a flash drive and its corresponding disk drive) may be used as the permanent storage device 502. Like the permanent storage device 502, the system memory 504 may be a read-write memory device. However, unlike the permanent storage device 502, the system memory 504 may be a volatile read-write memory, such as a random access memory. The system memory 504 may store any instructions and data that may be required by the one or more processing units 512 when running. In one or more embodiments, the processes of the present invention are stored in the system memory 504, the permanent storage device 502, and / or the ROM 510. The one or more processing units 512 retrieve instructions to be executed and data to be processed from these various memory units in order to perform the processes of one or more embodiments.

[0067] The bus 508 is also connected to an input device interface 514 and an output device interface 506. The input device interface 514 enables a user to convey information and select commands to the electronic system 500. Input devices that can be used with the input device interface 514 can include, for example, an alphanumeric keyboard and a pointing device (also referred to as a "cursor control device"). The output device interface 506 can enable, for example, the display of images generated by the electronic system 500. Output devices that can be used with the output device interface 506 can include, for example, a printer and a display device, such as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic light emitting diode (OLED) display, a flexible display, a flat panel display, a solid-state display, a projector, or any other device for outputting information. One or more implementations can include a device that serves as both an input and output device, such as a touch screen. In these implementations, the feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and the input from the user can be received in any form, including sound, voice, or tactile input.

[0068] Finally, if Figure 5 , bus 508 also couples electronic system 500 to one or more networks and / or one or more network nodes through one or more network interfaces 516. In this manner, electronic system 500 may be part of a computer network such as a LAN, a wide area network ("WAN"), or an intranet, or one of several networks such as the Internet. Any or all components of electronic system 500 may be used in conjunction with the present invention.

[0069] Implementations within the scope of the present invention may be implemented in part or in whole using a tangible computer-readable storage medium (or multiple tangible computer-readable storage media of one or more types) encoding one or more instructions. The tangible computer-readable storage medium may also be non-transitory in nature.

[0070] Computer-readable storage media may be any storage media that can be read, written, or otherwise accessed by a general purpose or special purpose computing device, including any processing electronics and / or processing circuitry capable of executing instructions. For example, computer-readable media may include, but are not limited to, any volatile semiconductor memory, such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. Computer-readable media may also include any non-volatile semiconductor memory, such as ROM, PROM, EPROM, EEPROM, NVRAM, flash, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, racetrack memory, FJG, and Millipede memory.

[0071] Furthermore, the computer-readable storage medium may include any non-semiconductor memory, such as optical disk storage, magnetic disk storage, magnetic tape, other magnetic storage, or any other medium capable of storing one or more instructions. In one or more implementations, the tangible computer-readable storage medium may be directly coupled to the computing device, while in other implementations, the tangible computer-readable storage medium may be indirectly coupled to the computing device, such as via one or more wired connections, one or more wireless connections, or any combination thereof.

[0072] Instructions may be directly executable or may be used to develop executable instructions. For example, instructions may be implemented as executable or non-executable machine code, or as instructions in a high-level language that may be compiled to produce executable or non-executable machine code. In addition, instructions may also be implemented as data or may include data. Computer executable instructions may also be organized in any format, including routines, subroutines, programs, data structures, objects, modules, applications, applets, functions, etc. As recognized by those skilled in the art, details including but not limited to the number, structure, sequence, and organization of instructions may vary significantly without changing the underlying logic, functions, processing, and output.

[0073] Although the above discussion mainly refers to a microprocessor or multi-core processor that executes software, one or more implementations are implemented by one or more integrated circuits such as ASICs or FPGAs. In one or more implementations, these integrated circuits execute instructions stored on the circuit itself.

[0074] Those skilled in the art will appreciate that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have generally been described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The described functionality may be implemented in varying ways by a technician for each specific application. The various components and blocks may be arranged in different ways (e.g., arranged in different orders or partitioned in different ways), all without departing from the scope of the present technology.

[0075] It should be understood that any particular order or hierarchy of blocks in the disclosed process is a diagrammatic illustration of an example method. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the process can be rearranged, or all of the illustrated blocks can be implemented. Any of the blocks can be implemented simultaneously. In one or more implementations, multitasking and parallel processing can be advantageous. In addition, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0076] As used in this specification and any claims of this application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technical devices. These terms exclude people or groups of people. For the purposes of this specification, the term "display" or "display" means displaying on an electronic device.

[0077] As used herein, the phrase "at least one of..." preceding a series of items using the terms "and" or "or" to separate any of the items modifies the list as a whole, rather than modifying each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each of the listed items; rather, the phrase allows for the following meanings: including at least one of any of the items, and / or at least one of any combination of the items, and / or at least one of each of the items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0078] The predicates "configured to," "operable to," and "programmed to" do not imply any particular tangible or intangible modification of an object, but are intended to be used interchangeably. In one or more embodiments, a processor configured to monitor and control the operation of a component may also mean a processor programmed to monitor and control the operation or a processor operable to monitor and control the operation. Similarly, a processor configured to execute code may be constructed as a processor programmed to execute code or operable to execute code.

[0079] Phrases such as on the one hand, the aspect, on the other hand, some aspects, one or more aspects, an embodiment, the embodiment, another embodiment, some embodiments, one or more embodiments, an example, the example, another example, some examples, one or more examples, a configuration, the configuration, another configuration, some configurations, one or more configurations, the technology of the present invention, the disclosure, the present invention, other variations thereof, etc. are for convenience and do not imply that the disclosure associated with these (these) phrases is essential to the technology of the present invention, or that this disclosure applies to all configurations of the technology of the present invention. The disclosure associated with these (these) phrases may apply to all configurations or one or more configurations. The disclosure associated with these (these) phrases may provide one or more examples. Phrases such as on the one hand or some aspects may refer to one or more aspects and vice versa, and this applies similarly to the other aforementioned phrases.

[0080] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, to the extent the terms "including," "having," and the like are used in the description or claims, such terms are intended to be inclusive in a manner similar to how the term "comprising" is interpreted when "comprising" is used as a transitional term in a claim.

[0081] All structural and functional equivalents to the elements of various aspects described throughout the present invention that are known or later known to those skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether the invention is explicitly recited in the claims. Any claim element will not be interpreted under the provisions of 35 U.S.C. §112, item 6, unless the element is explicitly recited using the phrase "means for..." or, in the case of a method claim, the element is recited using the phrase "step for..."

[0082] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. It will be readily apparent to those skilled in the art that various modifications to these aspects are possible, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the language claims, wherein the reference to an element in the singular is not intended to mean "one and only one" (unless specifically stated), but to mean "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. Male pronouns (e.g., his) include female and neutral genders (e.g., her and its), and vice versa. If any, the title and subtitle are only used for convenient purposes and do not limit the present invention.

Claims

1. A method comprising: receiving a plurality of network packets from a plurality of data paths; arbitrating the plurality of network packets to a plurality of packet processing blocks including one or more full processing blocks and one or more restricted processing blocks based at least in part on an arbitration policy; processing the plurality of network packets in parallel via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks processes a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets, the first number of network packets corresponding to data packets and the second number of network packets corresponding to control packets; and sending the processed plurality of network packets via a plurality of data buses; and Wherein the one or more constrained processing blocks are grouped into a shared logic constrained processing engine, the shared logic constrained processing engine including at least two of the one or more constrained processing blocks having shared logic and lookup hardware.

2. The method of claim 1, wherein the processing corresponds to processing of start-of-packet and end-of-packet SEOPs of the plurality of network packets.

3. The method of claim 1 , wherein arbitrating the plurality of network packets based at least in part on the arbitration policy comprises: For each respective packet in the plurality of network packets: determining a packet size for each corresponding packet; routing each respective packet to the one or more full processing blocks when the packet size exceeds a threshold packet size of the arbitration policy; and When the packet size does not exceed the threshold packet size of the arbitration policy, each respective packet is routed to the one or more restricted processing blocks.

4. The method of claim 1, wherein the arbitration comprises: Ancillary operations are queued to the plurality of packet processing blocks that did not process any of the plurality of network packets. The method of claim 1 , wherein the second number of network packets is at least twice the first number of network packets. The method according to claim 1 , wherein the first number of network packets is one.

7. The method of claim 1 , wherein arbitrating the plurality of network packets comprises: Arbitrating to at least one first-in-first-out FIFO queue for each of the one or more fully processed blocks.

8. The method of claim 1, wherein the one or more full processing blocks are grouped into a shared full processing engine, the shared full processing engine comprising at least two of the one or more full processing blocks having shared circuitry.

9. The method of claim 8, wherein each of the shared full processing engines utilizes an aggregated packet processing pipeline having a coherent data access structure.

10. A system comprising: a first shared bus having a first arbiter configured to receive a plurality of network packets from a plurality of data paths; a plurality of packet processing blocks including one or more full processing blocks and one or more restricted processing blocks, wherein each of the one or more full processing blocks is configured to process a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks is configured to process a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets, the first number of network packets corresponding to data packets and the second number of network packets corresponding to control packets; wherein the first arbitrator is configured to arbitrate the plurality of network packets for parallel processing by the plurality of packet processing blocks based at least in part on an arbitration policy, and wherein the one or more restricted processing blocks are grouped into a shared logic restricted processing engine that includes at least two of the one or more restricted processing blocks having shared logic and lookup hardware; and A second shared bus has a second arbitrator configured to arbitrate the processed plurality of network packets to a plurality of data buses based at least in part on the arbitration policy.

11. The system of claim 10, wherein the plurality of packet processing blocks are configured to process start-of-packet and end-of-packet SEOPs of the plurality of network packets.

12. The system of claim 10, wherein the first arbitrator is configured to: For each respective packet in the plurality of network packets: determining a packet size for each corresponding packet; When the packet size exceeds a threshold packet size of the arbitration policy, arbitrating each respective packet to the one or more fully processed blocks; and When the packet size does not exceed the threshold packet size of the arbitration policy, each respective packet is routed to the one or more restricted processing blocks.

13. The system of claim 10, wherein the one or more full processing blocks are grouped into a shared logic full processing engine, the shared logic full processing engine comprising at least two of the one or more full processing blocks having shared logic and lookup hardware.

14. The system of claim 13, wherein each of the shared full processing engines comprises an aggregated packet processing pipeline having a coherent data access structure.

15. The system of claim 10, wherein the first arbitrator is configured to queue an auxiliary operation to the plurality of packet processing blocks that did not process any of the plurality of network packets.

16. The system of claim 10, wherein the second number of network packets is at least twice the first number of network packets. The system of claim 10 , wherein the first number of network packets is one.

18. The system of claim 10, wherein each of the one or more full processing blocks is further coupled to at least one first-in-first-out (FIFO) queue.

19. A non-transitory storage medium comprising instructions which, when read by one or more processors, produce a method comprising: receiving a plurality of network packets from a plurality of data paths; arbitrating the plurality of network packets to a plurality of packet processing blocks including one or more full processing blocks and one or more restricted processing blocks based at least in part on an arbitration policy; processing the plurality of network packets in parallel via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first number of network packets during a clock cycle, and wherein each of the one or more restricted processing blocks processes a second number of network packets during the clock cycle, the second number of network packets being greater than the first number of network packets, the first number of network packets corresponding to data packets and the second number of network packets corresponding to control packets; and sending the processed plurality of network packets via a plurality of data buses; and Wherein the one or more constrained processing blocks are grouped into a shared logic constrained processing engine, the shared logic constrained processing engine including at least two of the one or more constrained processing blocks having shared logic and lookup hardware.

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