In-loop memory bandwidth compression in video coding

Abstract

The invention relates to in-loop memory bandwidth compression in video coding. A video decoder includes decoding logic configured to decode an encoded bitstream to produce a reference block of video data, and configured to compress the reference block of video data based on a selection between a first compression algorithm and a second compression algorithm, or memory bandwidth compression logic that copies the reference block without compression. The selection is based on at least one of the first block size, the second block size, or the uncompressed block size. The selected block is written to off-chip memory, and a compression algorithm indicator associated with the selected block is written to on-chip memory.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for memory management during video encoding. Background Art

[0004] For UHD video applications that transfer large amounts of data between on-chip memory buffers and off-chip memory buffers, memory bandwidth becomes a bottleneck for video encoding and decoding. In conventional video decoding, due to the limited size of on-chip memory, the reconstructed blocks after in-loop filtering are written to an off-chip memory buffer (also referred to as a decoded picture buffer (DPB) for storing decoded pictures). Reference picture data is extracted from the DPB by the decoder through inter-frame prediction logic for motion compensation, and is extracted from the DPB for display by display processing.

[0005] Therefore, in conventional video encoding methods, memory bandwidth is consumed when reconstructed picture data is written from an on-chip memory buffer to an off-chip memory buffer, and when decoded picture data is extracted from an off-chip memory buffer to an on-chip buffer for motion compensation / inter-frame prediction and display processing.

[0006] Therefore, an in-loop memory bandwidth compression architecture is provided for reducing memory bandwidth consumption. Summary of the invention

[0007] In one aspect, the disclosure relates to an apparatus comprising: a processor; and a non-transitory computer-readable medium in communication with the processor, the non-transitory computer-readable medium having encoded thereon a set of instructions executable by the processor to: generate a reference block of video data, wherein the reference block is generated based at least in part on an encoded bitstream; select one of the first compressed block, the second compressed block, or the uncompressed block based at least in part on at least one of a first block size of a first compressed block, a second block size of a second compressed block, or an uncompressed block size of an uncompressed block, wherein the first compressed block is the reference block after applying a first compression algorithm, wherein the second compressed block is the reference block after applying a second compression algorithm, and wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block size is equal to the size of the reference block; writing a selected block of the first compressed block, the second compressed block, or the uncompressed block to an off-chip memory; and writing a compression algorithm indicator associated with the selected block of the first compressed block, the second compressed block, or the uncompressed block to an on-chip memory, wherein the compression algorithm indicator is configured to indicate whether the selected block is compressed or uncompressed.

[0008] In another aspect, the disclosure relates to a video decoder comprising: decoding logic configured to decode an encoded bitstream, wherein decoding the encoded bitstream includes generating a reference block of video data; and memory bandwidth compression logic configured to compress the reference block of video data, the memory bandwidth compression logic further comprising: first compression logic configured to generate a first compressed block by applying a first compression algorithm to the reference block, wherein the first compressed block is the reference block after applying the first compression algorithm, and wherein the first compressed block has a first block size; second compression logic configured to generate a second compressed block by applying a second compression algorithm to the reference block, wherein the second compressed block is the reference block after applying the second compression algorithm, and wherein the second compressed block has a second a block size; copy logic configured to generate an uncompressed block, wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block has an uncompressed block size equal to the size of the reference block; selection logic configured to select one of the first compressed block, the second compressed block, and the uncompressed block based at least in part on at least one of the first block size, the second block size, or the uncompressed block size; and wherein the memory bandwidth compression logic is configured to write the selected one of the first compressed block, the second compressed block, or the uncompressed block to an off-chip memory and write a compression algorithm indicator associated with the selected one of the first compressed block, the second compressed block, or the uncompressed block to an on-chip memory, wherein the compression algorithm indicator is configured to indicate whether the selected block is compressed or uncompressed.

[0009] In another aspect, the present disclosure relates to a media encoding system, comprising: an off-chip memory buffer; an on-chip memory buffer; a video decoder coupled to the off-chip memory buffer and the on-chip memory buffer, the video decoder configured to decode an encoded bitstream to generate a reference block, the video decoder comprising: memory bandwidth compression logic configured to compress the reference block of video data, the memory bandwidth compression logic further comprising: first compression logic configured to generate a first compressed block by applying a first compression algorithm to the reference block, wherein the first compressed block is the reference block after applying the first compression algorithm, and wherein the first compressed block has a first block size; second compression logic configured to generate a second compressed block by applying a second compression algorithm to the reference block, wherein the second compressed block is the reference block after applying the second compression algorithm a reference block, wherein the second compressed block has a second block size; copy logic configured to generate an uncompressed block, wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block has an uncompressed block size equal to the size of the reference block; selection logic configured to select one of the first compressed block, the second compressed block, and the uncompressed block based at least in part on at least one of the first block size, the second block size, or the uncompressed block size; and wherein the memory bandwidth compression logic is configured to write the selected one of the first compressed block, the second compressed block, or the uncompressed block to the off-chip memory buffer and write a compression algorithm indicator associated with the selected one of the first compressed block, the second compressed block, or the uncompressed block to the on-chip memory buffer, wherein the compression algorithm indicator is configured to indicate whether the selected block is compressed or uncompressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and the accompanying drawings, in which the same reference numerals are used to refer to similar components. In some cases, a sub-label is associated with a reference numeral to represent one of a plurality of similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such plurality of similar components.

[0011] Figure 1 is a schematic block diagram of a decoder with in-loop memory bandwidth compression according to various embodiments;

[0012] Figure 2 is a schematic block diagram of in-loop memory bandwidth compression logic according to various embodiments;

[0013] Figure 3is a schematic diagram of a memory storage layout for a reconstructed picture after memory bandwidth compression according to various embodiments;

[0014] Figure 4 is a schematic block diagram of in-loop memory bandwidth decompression logic according to various embodiments;

[0015] Figure 5 is a schematic block diagram of sample-based reference block compression logic according to various embodiments;

[0016] Figure 6 is a schematic block diagram of sample-based reference block decompression logic according to various embodiments; and

[0017] Figure 7 is a schematic diagram of a lossy reference block compression algorithm according to various embodiments;

[0018] Figure 8 is a schematic block diagram of a computer system for in-loop memory bandwidth compression in video encoding according to various embodiments. DETAILED DESCRIPTION

[0019] Various embodiments describe an architecture for in-loop memory bandwidth compression in a video decoder.

[0020] In some embodiments, an apparatus for in-loop memory bandwidth compression is provided. The apparatus includes a processor and a non-transitory computer-readable medium in communication with the processor. The non-transitory computer-readable medium has a set of instructions encoded thereon, which can be executed by the processor to generate a reference block of video data, wherein the reference block is generated at least in part based on an encoded bitstream, and one of the first compressed block, the second compressed block, or the uncompressed block is selected at least in part based on at least one of a first block size of the first compressed block, a second block size of the second compressed block, or an uncompressed block size of the uncompressed block. The first compressed block may be the reference block after applying a first compression algorithm, the second compressed block may be the reference block after applying a second compression algorithm, and the uncompressed block may be a copy of the reference block, wherein the uncompressed block size is equal to the size of the reference block. The instructions can be further executed by the processor to write the selected block of the first compressed block, the second compressed block, or the uncompressed block to an off-chip memory, and write a compression algorithm indicator associated with the selected block of the first compressed block, the second compressed block, or the uncompressed block to an on-chip memory. The compression algorithm indicator may be configured to indicate whether the selected block is compressed or uncompressed.

[0021] In a further embodiment, a video decoder is provided. The video decoder includes: decoding logic configured to decode an encoded bitstream, wherein decoding the encoded bitstream includes generating a reference block of video data; and memory bandwidth compression logic configured to compress the reference block of video data. The memory bandwidth compression logic may include: first compression logic configured to generate a first compressed block by applying a first compression algorithm to the reference block, wherein the first compressed block is the reference block after applying the first compression algorithm, and wherein the first compressed block has a first block size; second compression logic configured to generate a second compressed block by applying a second compression algorithm to the reference block, wherein the second compressed block is the reference block after applying the second compression algorithm, wherein the second compressed block has a second block size; and copy logic configured to generate an uncompressed block, wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block has an uncompressed block size equal to the size of the reference block. The memory bandwidth compression logic further includes selection logic configured to select one of the first compressed block, the second compressed block, and the uncompressed block based at least in part on at least one of the first block size, the second block size, or the uncompressed block size. The memory bandwidth compression logic may be further configured to write a selected block of the first compressed block, the second compressed block, or the uncompressed block to an off-chip memory and write a compression algorithm indicator associated with the selected block of the first compressed block, the second compressed block, or the uncompressed block to an on-chip memory. The compression algorithm indicator may be configured to indicate whether the selected block is compressed or uncompressed.

[0022] In a further embodiment, a system for in-loop memory bandwidth compression is provided. The system includes an off-chip memory buffer, an on-chip memory buffer, and a video decoder coupled to the off-chip memory buffer and the on-chip memory buffer, the video decoder configured to decode an encoded bitstream to generate a reference block. The video decoder may include memory bandwidth compression logic configured to compress the reference block of video data. The memory bandwidth compression logic includes: first compression logic configured to generate a first compressed block by applying a first compression algorithm to the reference block, wherein the first compressed block is the reference block after applying the first compression algorithm, and wherein the first compressed block has a first block size; second compression logic configured to generate a second compressed block by applying a second compression algorithm to the reference block, wherein the second compressed block is the reference block after applying the second compression algorithm, wherein the second compressed block has a second block size; and copy logic configured to generate an uncompressed block, wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block has an uncompressed block size equal to the size of the reference block. The memory bandwidth compression logic may further include selection logic configured to select one of the first compressed block, the second compressed block, and the uncompressed block based at least in part on at least one of the first block size, the second block size, or the uncompressed block size. The memory bandwidth compression logic may be configured to write the selected one of the first compressed block, the second compressed block, or the uncompressed block to the off-chip memory buffer, and write a compression algorithm indicator associated with the selected one of the first compressed block, the second compressed block, or the uncompressed block to the on-chip memory buffer. The compression algorithm indicator may be configured to indicate whether the selected block is compressed or uncompressed.

[0023] In the following description, for the purpose of explanation, many details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be appreciated by those skilled in the art that other embodiments may be practiced without some of the specific details. Several embodiments are described herein, and although various features are attributed to different embodiments, it will be appreciated that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, any single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0024] When an element is referred to herein as being "connected" or "coupled" to another element (which includes mechanical, electrical, or communication connections or couplings), it is understood that the element may be directly connected to another element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0025] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, between, below, adjacent, or in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0026] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening layer that exists between the coupled or connected layers. In contrast, when an element is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may exist.

[0027] In addition, the terms left, right, front, back, top, bottom, forward, backward, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between various parts of an object and / or component.

[0028] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise dictates, intervening processes may occur before and / or after any portion of the described processes, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0029] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "approximately" in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms "and" and "or" means "and / or". In addition, the use of the terms "including" and "having" and other forms (such as "includes / included", "has / have and had") should be considered non-exclusive. Moreover, unless otherwise specifically stated, terms such as "element" or "component" cover both elements and components including one unit and elements and components including more than one unit.

[0030] As used herein, the phrase "at least one of..." preceding a series of items (where the terms "and" or "or" are used to separate any of the items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where the desired selection is "at least one of each of A, B, and C," or, alternatively, "at least one of A, at least one of B, and at least one of C," it is explicitly described as such.

[0031] As video applications move to higher and higher resolutions (e.g., 8K@120fps, etc.), writing data to and reading data from an off-chip memory buffer consumes limited memory bandwidth within the video encoding system. In conventional video encoding methods, memory bandwidth is consumed at various stages of the decoding process, such as by extracting data from an off-chip memory buffer for motion compensation / inter-frame prediction and display processing. In addition, reconstructed blocks are written to an off-chip memory buffer for later retrieval.

[0032] Therefore, a video encoding architecture for in-loop memory bandwidth compression is provided. With in-loop memory bandwidth compression, a reconstructed block can be selectively compressed according to a compression scheme and a compression algorithm indicator picture stored in an on-chip memory before being written to an off-chip memory buffer. When a compressed block is retrieved from the off-chip memory buffer, the compressed block can be decompressed according to the compression algorithm indicator picture.

[0033] As used herein, a block refers to a block of video data. Specifically, a picture (e.g., an image / frame of video data) may be divided into coding tree units (CTUs). Each CTU may be further divided into one or more coding units (CUs), which may represent square (or rectangular) subdivisions of a CTU. A block may represent a square or rectangular area of ​​pixels within a CU and / or a CTU. Thus, hierarchically, a CTU may include multiple CUs, and a CU includes multiple blocks. A CU may be as large as its root CTU and / or a subdivision of a CTU. For example, a CTU may be divided into subdivisions of up to 4x4 blocks (e.g., up to 16 total blocks). Thus, a CU may be the size of a single subdivision of a CTU.

[0034] "Block size" or the size of a block may refer to the size of a block of video data stored in memory (e.g., how much space a block takes up in memory, such as an allocated number of bits / bytes in memory). Thus, a "compressed block" may refer to a block of video data (including a reconstructed block of video data) that has been compressed by a compression algorithm, as will be described in more detail below. A compressed block size may refer to the size of a block (in memory) after a compression algorithm has been applied. An uncompressed block may refer to a block of video data that has not yet undergone compression (e.g., a compression algorithm has not yet been applied). Similarly, an uncompressed block size may refer to the size of an uncompressed block in memory.

[0035] Figure 1 1 is a schematic block diagram of a decoder 100 with in-loop memory bandwidth compression according to various embodiments. The decoder 100 includes entropy decoding logic 105, inverse quantization logic 110, inverse transform logic 115, prediction logic 120 (including motion estimation logic 125, inter prediction logic 130 and intra prediction logic 135), in-loop filter 140, memory bandwidth compression logic 145 and memory bandwidth decompression logic 150. It should be noted that the various elements of the decoder 100 are in Figure 1 1 is schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of decoder 100 may be possible and are made according to various embodiments.

[0036] In various embodiments, decoder 100 may be part of a media encoding system including a media decoder and a media encoder. In various embodiments, decoder 100 is a video decoder. In various examples, decoder 100 may be implemented in various types of hardware, such as one or more microprocessors, digital signal processors (DSPs), custom integrated circuits (ICs), programmable logic (e.g., field programmable gate arrays (FPGAs)), and / or discrete logic. Decoder 100 may be implemented at least in part with software, hardware, or a combination of software and hardware. As used herein, logic may refer to logic implemented in hardware (e.g., logic circuits, programmable logic, etc.), software, and / or hardware and software.

[0037] In various embodiments, the encoded video data may include a bitstream of encoded video blocks received by a decoder (e.g., from an encoder, storage device, streaming media, etc.). Thus, in various examples, entropy decoding logic 105 is configured to decode the encoded bitstream of video data. Specifically, entropy decoding logic 105 may be configured to decode the encoded bitstream and extract quantized elements from the encoded bitstream for further processing.

[0038] For example, the entropy decoding logic 105 may decode the incoming bitstream and deliver decoded elements (e.g., quantized elements), which may include, but are not limited to, quantized transform coefficients and control information such as incremental intra-prediction mode, inter-prediction mode, motion vector difference, merge index (merge_idx), quantization parameters, and in-loop filter parameters.

[0039] In some examples, quantized elements extracted from the bitstream may undergo inverse quantization (also interchangeably referred to as "inverse quantization") by inverse quantization logic 110. In some examples, inverse quantization of the quantized elements produces corresponding coefficients (e.g., transform coefficients), which are then further inverse transformed via inverse transform logic 115. In some examples, the transform may have been skipped for certain blocks. Thus, in some embodiments, the inverse transform may not be applied to those blocks. Once the inverse transform has been applied (or skipped as stated above), a residual block may be generated.

[0040] In various examples, the residual block may be added to a corresponding prediction block from the prediction logic 120. Combining the residual block with the prediction block produces a resulting "reconstructed block". The reconstructed block may be passed through one or more in-loop filters 140 and provided to the prediction logic 120 to produce a subsequent prediction block. After applying the in-loop filters 140, the reconstructed block may also be provided to the memory bandwidth compression logic 145 for compression.

[0041] Thus, the dequantized elements generated by the dequantization logic 110 may be used to generate a reconstructed block, and the reconstructed block may be filtered via the in-loop filter 140 and compressed for storage (e.g., in an off-chip memory buffer) via the memory bandwidth compression logic 145. In various examples, the prediction block may be generated by the prediction logic 120 based on the coding mode, intra-prediction parameters of the block as determined by the intra-prediction logic 135, and motion data as determined via the motion estimation logic 125. As previously described, selecting a coding mode may include specifying an intra-coding mode or an inter-prediction mode.

[0042] In some examples, the intra prediction mode for a given block may be reconstructed by deriving a most probable mode (MPM) list using the decoded incremental intra prediction mode, while the motion data (e.g., motion vectors, reference indices) may be reconstructed by deriving an advanced motion vector predictor (AMVP) list or a merge / skip list and using MVD. The decoded motion data for the current picture may be used as a temporal motion vector predictor (TMVP) for decoding future frames (e.g., images or pictures decoded from the corresponding block). Based on the signaled intra or inter prediction mode, the prediction logic 120 may perform intra prediction via the intra prediction logic 130, or perform inter prediction (e.g., motion compensation) via the inter prediction logic 130 to produce a prediction block.

[0043] In various examples, in-loop filtering may be applied via in-loop filter 140. In-loop filter 140 may include one or more filters such as, but not limited to, a deblocking filter, a SAO (sample adaptive offset) filter, and an adaptive loop filter (ALF). As previously described, in-loop filtering may be performed on the reconstructed block to produce a "reconstructed block after in-loop filter" which may also be interchangeably referred to as a "filtered reconstructed block". The reconstructed block after in-loop filter (e.g., a portion of a frame or image) may then be passed to memory bandwidth compression logic 145 for compression and storage in a storage device. The compressed video data from the storage device may then be retrieved and decompressed via memory bandwidth decompression logic 150 for display processing to be displayed.

[0044] For off-chip memory accesses, data is written or fetched in units of double data rate (DDR) bursts (e.g., 32 bytes, 64 bytes, etc.) of the off-chip memory. Thus, any data access greater than m-1 and less than or equal to m DDR burst sizes will be counted as m DDR bursts. In various examples, the uncompressed block size may be a multiple of a DDR burst (e.g., m times DDR burst size - 1 times DDR burst size, 2 times DDR burst size, etc.). Thus, in the case where the threshold block size T is set to half of the uncompressed block size, the memory bandwidth savings may be given as half of the percentage of blocks compressed to a size less than or equal to the threshold block size T.

[0045] Below about Figure 2 Provides details of the memory bandwidth compression logic 145 and Figure 3 Details of the memory bandwidth decompression logic 150 are set forth.

[0046] Figure 2 2 is a schematic block diagram of in-loop memory bandwidth compression logic 200 according to various embodiments. In-loop memory bandwidth compression logic 200 includes lossless compression logic 205, lossy compression logic 210, memory copy logic 215, compression type selection logic 220 coupled to on-chip memory buffer 225, switching logic 230, and compression block encoding logic 235 coupled to off-chip memory buffer 240. It should be noted that the various elements of in-loop memory bandwidth compression logic 200 are described in detail in detail. Figure 2 2. Modifications to the various components and other arrangements of the in-loop memory bandwidth compression logic 200 are schematically illustrated in FIG. 2 and may be possible and are made according to various embodiments.

[0047] In various examples, the in-loop memory bandwidth compression logic 200 may receive a reference block to be compressed according to one or more compression algorithms. In various examples, the term "reference block" refers to a block of video data being processed (e.g., to which a compression algorithm is applied). For example, the reference block may be a reconstructed block (e.g., a portion of a frame or image data) after an in-loop filter as described above.

[0048] In some embodiments, the in-loop memory bandwidth compression logic 200 may include lossless compression logic 205, lossy compression logic 210, and memory copy logic 215. The lossless compression logic 205 may include logic to apply one or more lossless compression algorithms to the reference blocks. The lossless compression algorithm may include any compression algorithm after which the compressed data can be reconstructed without loss of information. Thus, any suitable lossless compression algorithm may be applied. For example, Golomb encoding (e.g., exponential Golomb encoding) may be utilized, as will be described below with respect to Figure 5 Described in more detail.

[0049] Similarly, lossy compression logic 210 includes logic to apply one or more lossy compression algorithms to a reference block. Lossy compression is a compression algorithm in which information is lost during reconstruction (e.g., discrete cosine transform (DCT), etc.). It should be noted that both lossless compression algorithms and lossy compression algorithms include any suitable memory bandwidth compression algorithms. Memory copy logic 215 may include logic to make a copy of a reference block without applying a compression technique.

[0050] As previously mentioned Figure 1 As depicted, the in-loop memory bandwidth compression logic 200 is placed after the in-loop filter to compress the filtered reconstructed blocks before they are written to off-chip memory (eg, off-chip memory buffer 240).

[0051] The in-loop memory bandwidth compression logic 200 may be configured to select a memory bandwidth compression technique to be applied to the reference block. In various embodiments, the reference block (e.g., the reconstructed block) may be compressed using lossless compression (via lossless compression logic 205) to produce a lossless compressed block and lossy compression (via lossy compression logic 210) to produce a lossy compressed block. The compressed blocks (both lossless and lossy) and copies of the reference blocks may be buffered (e.g., stored in a buffer). The size of the lossless compressed block (S lossless ), the size of the lossy compressed block (S lossy ) and the size of the reference block copy (S copy ) may be further determined and output to the compression type selection logic 220.

[0052] In various embodiments, the compression type selection logic 220 may select a compression type based on the corresponding size S of the compressed block.lossless , S lossy and the size S of the copy of the reference block copy To select a compression algorithm (e.g., lossless, lossy, or memory copy). In some examples, the selection of a compression algorithm may be determined according to the following decision logic:

[0053]

[0054] Where T is a predefined threshold (e.g., a threshold block size). In one example, T can be set to half the original block size, or S copy / 2.

[0055] In some further embodiments, a flag may be signaled to indicate that in-loop memory bandwidth compression is not applied to a picture. This may be applicable to situations where no block in a picture can be compressed to a size less than or equal to a predefined threshold T, or memory bandwidth compression is disabled for a given picture. For example, in-loop memory bandwidth compression may only be applied to picture resolutions of 4K and above.

[0056] A 2-bit indicator may be used to encode the selected compression algorithm. The "indicator" may be interchangeably referred to as a "compression algorithm indicator." Thus, the 2-bit indicator indicates the selected compression algorithm, and the 2-bit indicator itself may be written to the on-chip memory buffer 225. For example, in some embodiments, the first bit of the 2-bit indicator may indicate whether the block is compressed or uncompressed (e.g., "1" indicates compression, and "0" indicates uncompressed). If compressed, the second bit may indicate whether the block is compressed with a lossless compression algorithm or a lossy compression algorithm (e.g., "1" indicates lossless compression, and "0" indicates lossy compression). In some examples, if the block is not compressed (e.g., memory copy), the second bit may be ignored.

[0057] The compression type selection logic 220 may further cause the switching logic 230 to select between lossless compression blocks, lossy compression blocks, or memory copy blocks (e.g., to select between the outputs of the lossless compression logic 205, the lossy compression logic 210, or the memory copy logic 215). In some examples, the switching logic 230 may include a switch controlled by the compression type selection logic 220 (e.g., a 2-bit compression algorithm indicator as described above). In other embodiments, the switching logic 230 may be implemented as a multiplexer controlled by a 2-bit compression algorithm indicator, for example.

[0058] Selected compressed or uncompressed blocks may be written to the off-chip memory buffer 240. In some examples, to ensure random access, each block (whether compressed or uncompressed) may be allocated the same storage space (e.g., the size of the original block) in the off-chip memory buffer.

[0059] Thus, as used herein, an on-chip memory buffer may refer to a buffer allocated in an on-chip memory. An on-chip memory includes, for example, a memory implemented on a chip (e.g., a processor chip). An on-chip memory (also referred to as an on-chip random access memory (OCRAM)) may, for example, include a static random access memory (SRAM). Conversely, as used herein, an off-chip memory buffer may refer to a buffer allocated in an off-chip memory. For example, an off-chip memory may include a dynamic random access memory (DRAM).

[0060] Figure 3 is a schematic diagram of a memory storage layout 300 for a reconstructed picture after memory bandwidth compression according to various embodiments. In the depicted embodiment, the reconstructed picture 305 is divided into non-overlapping blocks of equal block size (except at the right and bottom picture boundaries, where the block size may be smaller because the picture size may not be a multiple of the selected block size).

[0061] In various embodiments, an on-chip memory buffer (e.g., on-chip memory buffer 225) may be configured to store a corresponding compression algorithm indicator for each block of the reconstructed picture, as described above. Thus, a "compression algorithm indicator picture" corresponding to the reconstructed picture 305 may be stored in the on-chip memory buffer.

[0062] Similarly, in various embodiments, an off-chip memory buffer, such as the off-chip memory buffer 240, may be allocated to store compressed and / or uncompressed blocks output by the memory bandwidth compression logic 345. In this manner, combined compressed and / or uncompressed blocks may be combined to form a “compressed reference picture,” which may be stored by the off-chip memory buffer.

[0063] In various examples, each block may be configured to occupy the same amount of memory space in the respective on-chip and off-chip memory buffers. For example, 2 bits for the compression algorithm indicator in the on-chip memory buffer may occupy the same amount of memory space as a compressed block in the off-chip memory buffer, which may occupy the same space as an uncompressed block in the off-chip memory buffer.

[0064] In the depicted example, a lossless compression algorithm may be used to compress the first block. Therefore, a compression algorithm indicator "11" may be written to the on-chip memory buffer, and the lossless compressed block may be written to the off-chip data buffer (the compressed block data is depicted by the shaded area). The second block of the reconstructed block may be lossy compressed. Therefore, "10" may be written to the on-chip memory buffer, and the lossy compressed block may be written to the off-chip data buffer (the compressed block data is similarly shown as a shaded area). The third block may be uncompressed. Therefore, either "01" or "00" may be written to the on-chip memory buffer, and the uncompressed block (e.g., the reconstructed block after in-loop filtering) may be written to the off-chip data buffer, where the entire block is shown with hatching. In some examples, because each block is allocated the same amount of memory space between the first block and the second block and between the second block and the third block, there may be empty space (e.g., storage holes) in the corresponding buffers.

[0065] Figure 4 4 is a schematic block diagram of in-loop memory bandwidth decompression logic 400 according to various embodiments. In-loop memory bandwidth decompression logic 400 includes lossless decompression logic 405, lossy decompression logic 410, memory copy logic 415, decompression type selection logic 420 coupled to on-chip memory buffer 425, switching logic 430, and compression block 435 coupled to off-chip memory buffer 440 and on-chip memory buffer 425. It should be noted that the various elements of in-loop memory bandwidth decompression logic 400 are described in detail in detail. Figure 4 4. Modifications to the various components and other arrangements of the in-loop memory bandwidth decompression logic 400 are schematically illustrated in FIG. 4, and may be possible and are made according to various embodiments.

[0066] Memory bandwidth decompression logic 400 may be placed before prediction logic (eg, prediction logic 120) and display processing logic to decompress compressed block 435 data fetched from off-chip memory buffer 440. The decompressed block data may be used for motion compensation and display processing by the prediction logic.

[0067] Based on the current block position in the picture / frame, the compression algorithm indicator may be read from the on-chip memory buffer 425 for the corresponding compressed block 435. Based on the compression indicator, the decompression type selection logic 420 may be configured to control the switching logic 430 to select the appropriate decompression logic: the lossless decompression logic 405, the lossy decompression logic 410, or the memory copy logic 415.

[0068] For example, if the extracted compressed block 435 data is not compressed, then the block data of the uncompressed block size is extracted from the off-chip memory buffer 440 based on the current block position in the picture. Otherwise, the reduced block size T (where T is set to the uncompressed block size Scopy Block data (typically half of the uncompressed block size in the case of half of the block size) is extracted from the off-chip memory buffer 440 based on the current block position in the picture.

[0069] If the extracted block is compressed, then depending on the compression indicator, lossless or lossy decompression logic 405, 410 may be selected and the corresponding lossless or lossy decompression algorithm may be applied to reconstruct the compressed block 435. If the extracted compressed block 435 is not compressed, then the extracted compressed block 435 may be copied via memory copy logic 415. The reconstructed block (decompressed or copied) may be stored in an on-chip cache memory buffer for further processing. It should be understood that various suitable algorithms may be utilized for lossless and lossy compression / decompression, and embodiments are not limited to any particular compression / decompression algorithm.

[0070] It should be further noted that a "reconstructed block" in the context of decompression of the extracted compressed block 435 should be distinguished from a "reconstructed block" produced by a decoder from an encoded bitstream (as described above with respect to Figures 1 to 3 In both cases, the blocks are "reconstructed" and in some cases may refer to the same block. Figures 1 to 3 , the reconstructed block is reconstructed from the encoded bitstream. Thus, the reconstructed block itself may be compressed to form a compressed block 435. The compressed block is then "reconstructed" (e.g., decompressed) using a decompression algorithm as described above. This reconstructed block may be different from the original compressed reconstructed block (in Figure 2 ), this is because some information may be lost from the original reconstructed block (e.g., in the case of applying a lossy compression algorithm). To distinguish, in some instances, a "reconstructed block" before applying a compression algorithm may be referred to as Figure 2 in the Reference Block.

[0071] Reference below Figures 5 to 7 An example of a compression / decompression algorithm is described in more detail.

[0072] Figure 5 5 is a schematic block diagram of sample-based reference block compression logic 500 according to various embodiments. The reference block compression logic 500 includes sample-based prediction logic 505, residual quantization logic 510, residual encoding logic 515, residual inverse quantization logic 520, and sample reconstruction logic 525. It should be noted that the various elements of the sample-based reference block compression logic 500 are described in detail in detail. Figure 5 , and modifications to the various components and other arrangements of the sample-based reference block compression logic 500 may be possible and are made according to various embodiments.

[0073] In various embodiments, sample-based reference block compression logic 500 is an example of one implementation of a lossy compression algorithm. Sample-based prediction logic 505 may be configured to predict a current sample from neighboring samples reconstructed therefrom. As used herein, a current sample may refer to a different portion of a corresponding block being compressed based on neighboring samples (e.g., neighboring portions of a reference block). Thus, a sample may be predicted via sample-based prediction logic 505, and a prediction residual r may be quantized via residual quantization logic 510. The quantized residual r q It can then be sent to the residual encoding logic 515 to be encoded into a bitstream. For example, k-order exponential Grunbuh codes can be used to further compress r q The compressed residuals may be dequantized using residual dequantization logic 520 and added via sample reconstruction logic 525 to form adjacent reconstructed samples for prediction of the next sample.

[0074] In some embodiments, the upper left sample may not be compressed and copied to the output bitstream buffer. Thus, in some examples, the top left sample can always be encoded without compression. The current sample can be represented as "d" and the upper right sample as And the lower left sample is represented as Indications of relative direction (e.g., "top," "left," "upper left," etc.) are used to describe the location of the corresponding sample within a given reference block and relative to the current sample being processed. In various examples, the samples in the reference block may be processed in a raster scan order (e.g., a Z scan order). Thus, compression of the samples may be performed as follows.

[0075] A copy of the top left sample may be output to the output bitstream buffer, and and may be set to the value of the top left sample. Moving in raster scan order, the prediction of the current sample d may be performed via sample based prediction logic 505. If the current sample is located in the first row of the reference block, then the prediction of the current sample is set to the value of the left adjacent reconstructed sample. For example, the prediction pred of the current sample may be set to: Otherwise, if the current sample is located in the first column of the reference block, the prediction for the current sample can be set to the top neighbor value:

[0076] Otherwise, make and The minimum value in and the prediction of the current sample can be given by:

[0077]

[0078] Here (and hereafter)

[0079] Therefore, the prediction residual of the current sample can be given as: r = d-pred.

[0080] The prediction of the current sample may be provided by the sample based prediction logic 505 to the sample reconstruction logic 525 for further processing, and the prediction residual may be provided to the residual quantization logic 510 .

[0081] The residual quantization logic 510 may be configured to perform residual quantization of the prediction residual as follows.

[0082]

[0083] In various examples, the residual encoding logic 515 uses a k-order exponential Glumb code to compress the quantized prediction residual r q , where the signed residual r q Before applying compression using k-order exponential Glumb codes, e = |r q |-1 is converted to unsigned data. Some examples of exponential Grunbu codes are provided in Table 1 below.

[0084]

[0085] Table 1: Exponential Grunbu code k coding example

[0086] In various examples, the signaling of the exponential Grunbuh code order (i.e., k) may be implicit if a fixed order is used across the board, or if content-adaptive k is desired, k is signaled at a high level (e.g., sequence level, picture level, slice level, etc.) In some implementations, k may be made block-row adaptive, where the order of the exponential Grunbuh codes for the current block row is determined by the data statistics of the previous block row.

[0087] Residual dequantization may be performed via residual dequantization logic 520, where residual inverse quantization may be performed as:

[0088]

[0089] Then, dequantize the residual The sample reconstruction logic 525 may be used to reconstruct the current sample as: Processing of samples may proceed in raster scan order to the next sample in the reference block (or exit if the last sample has been reached).

[0090] Figure 66 is a schematic block diagram of sample-based reference block decompression logic 600 according to various embodiments. The sample-based reference block decompression logic 600 includes sample-based prediction logic 605, residual decoding logic 615, sample reconstruction logic 610, and residual dequantization logic 620. It should be noted that the various elements of the sample-based reference block decompression logic 600 are described in detail in detail. Figure 6 6, and modifications to the various components and other arrangements of the sample-based reference block decompression logic 600 may be possible and are made according to various embodiments.

[0091] In various examples, the sample-based prediction logic 605 may copy the top left sample from the bitstream buffer and and Set to the value of the upper left sample before moving to the next sample (in raster scan order). The prediction pred for the current sample d can be as described previously for Figure 5 2 and is generated as described and set forth in Equation 2. The prediction may be provided to sample reconstruction logic 610.

[0092] The residual decoding logic 615 may receive the encoded compressed bitstream and then decode the encoded compressed bitstream to obtain the quantized prediction residual r q As described above, in various embodiments, the bitstream may have been encoded using a k-order exponential Grunbu code. Let e ​​be the data decoded from the bitstream, the prediction residual r q Can be refactored as:

[0093]

[0094] Residual dequantization may then be performed on the reconstructed prediction residual via residual dequantization logic 620. Residual dequantization may be performed as previously described with respect to Figure 5 is performed as described and set forth in Equation 4.

[0095] The reconstructed sample for the current sample may then be determined via sample reconstruction logic 610, as previously described:

[0096] Figure 7 7 is a schematic diagram of a lossy reference block compression algorithm 700 according to various embodiments. Specifically, the lossy reference block compression algorithm 700 may include an algorithm for selecting a quantization parameter (qp) based on checking a condition at a decision block 710.

[0097] In various embodiments, the lossy reference block compression logic 705 may perform an initial lossy compression on the reference block, where the initial qp=1. The decision block 710 may then perform a check on the condition: S lossy ≤T or qp≥qp max, where T is a predefined threshold and described previously (e.g., half the original block size). In various examples, decision block 710 may be implemented as part of the lossy compression logic 210 described previously, for example. If any condition is met, qp and S may be lossy Output to on-chip memory buffer. If both conditions are not met, then in the example, qp may be incremented by setting: qp=qp+1. Lossy reference block compression 705 may perform lossy compression on the reference block again with the new qp, and repeat until the condition of decision block 710 is met.

[0098] The increase in Bjontegaard delta rate (BD rate) caused by lossy memory bandwidth compression can be reduced by optimizing the quantization parameter selection in the reference block compression algorithm. Therefore, the lossy reference block compression algorithm 700, and in particular, the conditions of the decision block 710, only provides an example of a brute force approach for selecting qp for the purpose of explanation. It should be understood that in other embodiments, other suitable algorithms for qp selection may be implemented, and other embodiments are not limited to the brute force approach set forth above.

[0099] In this approach, the qp selected for each block will need to be stored in an on-chip memory buffer. In some examples, the 2-bit compression algorithm indicator may alternatively be modified to a 1-bit flag to indicate whether the block is compressed, and if the block is compressed, then n bits may be used to signal the value of the qp, where n is determined by the predefined qp max OK. In some instances, if a single qp is used across the disk max (e.g. 31), then the maximum quantization parameter qp max It may be implicit (i.e., not signaled) or signaled at a high level in the bitstream (e.g., sequence level, picture level, or slice level). In some further examples, to reduce the storage size of the selected qp for each block, a qp to qp index table may be defined. For example, if qp max is set to 31, then a 5-bit value is required to represent the selected qp of the block. However, if a mapping table is defined (e.g., qp[8] = {0, 1, 2, 4, 8, 16, 24, 31}), then only a 3-bit value is required per block for qp storage, because qp indices in the range of [0:7] can be stored instead of qp with values ​​of [0:31].

[0100] The above-mentioned Figures 1 to 7The described embodiments may use custom hardware (e.g., programmable logic controllers, single board computers, FPGAs, custom ICs, and SoCs) and / or may implement specific elements in hardware, software, or both. Thus, some embodiments may employ a computer or hardware system (e.g., a signal processor or other video processing system) to perform processes and functionality according to various embodiments. According to one set of embodiments, some or all of the processes and / or methods may be performed in response to a processor executing one or more sequences of one or more instructions.

[0101] A set of these instructions and / or codes may be encoded and / or stored on a non-transitory computer-readable storage medium, such as an on-chip memory. In other embodiments, the storage medium may be separate from the computer system (i.e., a removable medium, such as an optical disk, etc.), and / or provided in an installation package, such that the storage medium may be used to program, configure, and / or adapt a computer or processor having the instructions / code stored thereon. These instructions may take the form of executable code that can be executed by a computer system and / or a processor of a computer system, which then takes the form of executable code after being compiled (e.g., using any of a variety of commonly available compilers, installers, compression / decompression utilities, etc.) and / or installed on a computer system.

[0102] As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any medium that participates in providing data that causes a machine to operate in a specific manner. In many implementations, computer-readable media is a non-transitory, physical, and / or tangible storage medium. In some embodiments, computer-readable media can take many forms, including but not limited to non-volatile media, volatile media, or the like. Non-volatile media include, for example, read-only memory, solid-state memory, optical and / or magnetic disks, and other non-volatile storage devices. Volatile media include, but are not limited to dynamic memory, such as DRAM.

[0103] Common forms of physical and / or tangible computer readable media include, for example, a floppy disk, a floppy disk, a hard disk, magnetic tape or any other magnetic media, a CD-ROM, any other optical media, punch cards, paper tape, any other physical media, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, the carrier wave described below, or any other media from which a computer can read instructions and / or code.

[0104] Figure 8 A schematic illustration of one embodiment of a computer system 800 (e.g., media decoder 100) or a subsystem thereof (e.g., decoding logic, prediction logic, memory bandwidth compression logic, memory bandwidth decompression logic, or a combination thereof) is provided that can perform methods provided by various other embodiments, as described herein. It should be noted that Figure 8 Only a general description of the various components is provided, one or more of each of which may be used as appropriate. Figure 8 It generally illustrates how individual system elements may be implemented in a relatively discrete or relatively more integrated manner.

[0105] The computer system 800 includes a plurality of hardware elements that may be electrically coupled (or may communicate in other ways, as appropriate) via a bus 805. The hardware elements may include one or more processors 810, including but not limited to one or more general-purpose processors and / or one or more special-purpose processors (e.g., microprocessors, digital signal processing chips, graphics acceleration processors, and microcontrollers); one or more input devices 815, including but not limited to a mouse, a keyboard, one or more sensors, and / or the like; and one or more output devices 820, including but not limited to a display device and / or the like.

[0106] The computer system 800 may further include (and / or communicate with) one or more storage devices 825, which may include, but are not limited to, local and / or network accessible memory, and / or may include, but are not limited to, disk drives, drive arrays, optical storage devices, solid-state storage devices such as random access memory ("RAM") and / or read-only memory ("ROM"), which may be programmable, flash-updatable, and / or the like. Such storage devices may be configured to implement any suitable data repository, including, but not limited to, various file systems, database structures, and / or the like.

[0107] The computer system 800 may also include a communication subsystem 830, which may include but is not limited to a modem, a network card (wireless or wired), an IR communication device, a wireless communication device, and / or a chipset (e.g., Bluetooth TM Devices, 802.11 devices, WiFi devices, WiMax devices, WWAN devices, Z-Wave devices, ZigBee devices, cellular communication facilities, etc.) and / or LP wireless devices, as previously described. The communication subsystem 830 can allow data to be exchanged with a network (such as the network described below, as an example), with other computer or hardware systems, between data centers or different cloud platforms, and / or with any other devices described herein. In many embodiments, the computer system 800 further includes a working memory 835, which can include RAM or ROM devices, as described above.

[0108] The computer system 800 may also include software elements shown as currently located within the working memory 835, including an operating system 840, device drivers, executable libraries, and / or other code, such as one or more application programs 845, which may include computer programs provided by various embodiments, and / or may be designed to implement methods provided by other embodiments and / or configure systems provided by other embodiments, as described herein. By way of example only, one or more programs described with respect to the methods discussed above may be implemented as code and / or instructions executable by a computer (and / or a processor within a computer); then, in one aspect, such code and / or instructions may be used to configure and / or adapt a general purpose computer (or other device) to perform one or more operations according to the described methods.

[0109] A set of these instructions and / or codes may be encoded and / or stored on a non-transitory computer-readable storage medium, such as the storage device 825 described above. In some cases, the storage medium may be incorporated into a computer system, such as the system 800. In other embodiments, the storage medium may be separate from the computer system (i.e., removable media, such as an optical disk, etc.), and / or provided in an installation package so that the storage medium can be used to program, configure, and / or adapt a general-purpose computer using the instructions / code stored thereon. These instructions may take the form of executable code that can be executed by the computer system 800 and / or may take the form of source code / installable code that then takes the form of executable code after being compiled and / or installed on the computer system 800 (e.g., using any of a variety of commonly available compilers, installers, compression / decompression utilities, etc.).

[0110] It will be apparent to those skilled in the art that substantial variations may be made depending on specific requirements. For example, customized hardware (e.g., programmable logic controllers, single board computers, FPGAs, ASICs, and SoCs) may also be used, and / or specific elements may be implemented in hardware, software (including portable software such as applets, etc.), or both. In addition, connections to other computing devices (e.g., network input / output devices) may be employed.

[0111] As mentioned above, in one aspect, some embodiments may employ a computer or hardware system (e.g., computer system 800) to perform methods according to various embodiments of the invention. According to one set of embodiments, some or all of the procedures of such methods are performed by computing system 800 in response to processor 810 executing one or more sequences of one or more instructions contained in working memory 835 (which may be incorporated into operating system 840 and / or other code (e.g., application program 845)). Such instructions may be read into working memory 835 from another computer-readable medium (e.g., one or more storage devices 825). By way of example only, execution of the sequences of instructions contained in working memory 835 may cause processor 810 to perform one or more procedures of the methods described herein.

[0112] In embodiments implemented using computer system 800, various computer-readable media may participate in providing instructions / code to processor 810 for execution and / or may be used to store and / or carry such instructions / code (e.g., as signals). In many embodiments, computer-readable media are non-transitory, physical, and / or tangible storage media. In some embodiments, computer-readable media may take many forms, including but not limited to non-volatile media, volatile media, or the like. Non-volatile media include, for example, optical and / or magnetic disks, such as storage device 825. Volatile media include, but are not limited to dynamic memory, such as working memory 835. In some alternative embodiments, computer-readable media may take the form of transmission media, including but not limited to coaxial cables, copper wires, and optical fibers, including wires comprising bus 805, and various components of communication subsystem 830 (and / or the media through which communication subsystem 830 provides communication with other devices). In one set of alternative embodiments, the transmission media may also take the form of waves (including but not limited to radio waves, sound waves, and / or light waves, such as waves generated during radio wave and infrared data communications).

[0113] Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to processor 810 for execution. By way of example only, the instructions may initially be carried on a magnetic disk and / or optical disk of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions as signals over a transmission medium to be received and / or executed by computer system 800. According to various embodiments of the invention, these signals, which may be in the form of electromagnetic signals, acoustic signals, optical signals, and / or the like, are examples of carrier waves on which instructions may be encoded.

[0114] The communication subsystem 830 (and / or its components) typically receives the signal, and the bus 805 may then carry the signal (and / or the data, instructions, etc. carried by the signal) to the working memory 835, from which the processor 810 retrieves and executes the instructions. The instructions received by the working memory 835 may optionally be stored on the storage device 825 before or after execution by the processor 810.

[0115] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, although various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context dictates otherwise, this functionality may be distributed among various other system components according to several embodiments.

[0116] In addition, although the processes of the methods and processes described herein are described in a particular order for ease of description, unless the context dictates otherwise, various processes may be reordered, added, and / or omitted according to various embodiments. In addition, processes described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without some features are described to facilitate description and explanation of aspects of these embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments, unless the context dictates otherwise. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: processor; and a non-transitory computer-readable medium in communication with the processor, the non-transitory computer-readable medium having encoded thereon a set of instructions executable by the processor to: generating a reference block of video data, wherein the reference block is generated based at least in part on an encoded bitstream; selecting one of the first compressed block, the second compressed block, or the uncompressed block based at least in part on at least one of a first block size of a first compressed block, a second block size of a second compressed block, or an uncompressed block size of an uncompressed block, wherein the first compressed block is the reference block after applying a first compression algorithm, wherein the second compressed block is the reference block after applying a second compression algorithm, and wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block size is equal to the size of the reference block; writing a selected block among the first compressed block, the second compressed block or the uncompressed block to an off-chip memory; and A compression algorithm indicator associated with the selected block of the first compressed block, the second compressed block, or an uncompressed block is written to an on-chip memory, wherein the compression algorithm indicator is configured to indicate whether the selected block is compressed or uncompressed.

2. The apparatus of claim 1, wherein the first compression algorithm is a lossless compression algorithm, and wherein the second compression algorithm is a lossy compression algorithm.

3. The apparatus of claim 2, wherein selecting one of the first compressed block, the second compressed block, and the uncompressed block further comprises: In response to determining that the first size is less than or equal to a threshold size, selecting the first compressed block; In response to determining that the first size is greater than the threshold size and the second size is less than or equal to the threshold size, selecting the second compressed block; and In response to determining that the first size and the second size are greater than a threshold size, the uncompressed block is selected. The apparatus of claim 3 , wherein the threshold size is equal to half of the uncompressed block size.

5. The apparatus of claim 1, wherein the compression algorithm indicator is further configured to indicate whether to use the first compression algorithm or the second compression algorithm.

6. The apparatus of claim 1 , wherein the set of instructions further comprises instructions executable by the processor to: fetching the selected block from the off-chip memory; extracting the compression algorithm indicator associated with the selected block from the on-chip memory; Generating a reconstructed block from the selected block, wherein generating the reconstructed block includes selecting one of a first decompression algorithm or a second decompression algorithm to apply to the selected block or copying the selected block based on the compression algorithm indicator; and The reconstructed block is written to the on-chip memory.

7. The apparatus of claim 1, wherein the second compression algorithm comprises setting a maximum quantization parameter.

8. The apparatus of claim 6, wherein applying the second compression algorithm comprises: applying the second compression algorithm to quantize the reference block using a first quantization parameter, determining whether the second size is less than or equal to a threshold size and determining whether the first quantization parameter is less than the maximum quantization parameter, and In response to determining that the quantization parameter is less than the maximum quantization parameter or the second size is less than or equal to the threshold size, the second compression algorithm is applied using a second quantization parameter that is greater than the first quantization parameter.

9. The apparatus of claim 1, wherein the selected block occupies the same space in the on-chip memory as the uncompressed block size.

10. The apparatus of claim 1, wherein the uncompressed block size is a multiple of a double data rate burst.

11. A video decoder, comprising: decoding logic configured to decode an encoded bitstream, wherein decoding the encoded bitstream comprises generating reference blocks of video data; and memory bandwidth compression logic configured to compress the reference blocks of video data, the memory bandwidth compression logic further comprising: first compression logic configured to generate a first compressed block by applying a first compression algorithm to the reference block, wherein the first compressed block is the reference block after applying the first compression algorithm, and wherein the first compressed block has a first block size; second compression logic configured to generate a second compressed block by applying a second compression algorithm to the reference block, wherein the second compressed block is the reference block after applying the second compression algorithm, wherein the second compressed block has a second block size; replication logic configured to generate an uncompressed block, wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block has an uncompressed block size equal to the size of the reference block; selection logic configured to select one of the first compressed block, the second compressed block, and the uncompressed block based at least in part on at least one of the first block size, the second block size, or an uncompressed block size; and wherein the memory bandwidth compression logic is configured to write the selected one of the first compressed block, the second compressed block, or the uncompressed block to an off-chip memory and write a compression algorithm indicator associated with the selected one of the first compressed block, the second compressed block, or the uncompressed block to an on-chip memory, Wherein the compression algorithm indicator is configured to indicate whether the selected block is compressed or uncompressed.

12. The video decoder of claim 11, wherein the first compression algorithm is a lossless compression algorithm, and wherein the second compression algorithm is a lossy compression algorithm.

13. The video decoder of claim 12, wherein selecting one of the first compressed block, the second compressed block, and the uncompressed block further comprises: In response to determining that the first size is less than or equal to a threshold size, selecting the first compressed block; In response to determining that the first size is greater than the threshold size and the second size is less than or equal to the threshold size, selecting the second compressed block; and In response to determining that the first size and the second size are greater than a threshold size, the uncompressed block is selected.

14. The video decoder of claim 13, wherein the threshold size is equal to half of the uncompressed block size.

15. The video decoder of claim 11, further comprising memory bandwidth decompression logic configured to: fetching the selected block from the off-chip memory; extracting the compression algorithm indicator associated with the selected block from the on-chip memory; Generating a reconstructed block from the selected block, wherein generating the reconstructed block includes selecting one of a first decompression algorithm or a second decompression algorithm to apply to the selected block or copying the selected block based on the compression algorithm indicator; and The reconstructed block is written to the on-chip memory.

16. A media encoding system, comprising: off-chip memory buffer; On-chip memory buffers; a video decoder coupled to the off-chip memory buffer and the on-chip memory buffer, the video decoder configured to decode an encoded bitstream to generate a reference block, the video decoder comprising: memory bandwidth compression logic configured to compress the reference blocks of video data, the memory bandwidth compression logic further comprising: first compression logic configured to generate a first compressed block by applying a first compression algorithm to the reference block, wherein the first compressed block is the reference block after applying the first compression algorithm, and wherein the first compressed block has a first block size; second compression logic configured to generate a second compressed block by applying a second compression algorithm to the reference block, wherein the second compressed block is the reference block after applying the second compression algorithm, wherein the second compressed block has a second block size; replication logic configured to generate an uncompressed block, wherein the uncompressed block is a copy of the reference block, wherein the uncompressed block has an uncompressed block size equal to the size of the reference block; selection logic configured to select one of the first compressed block, the second compressed block, and the uncompressed block based at least in part on at least one of the first block size, the second block size, or an uncompressed block size; and wherein the memory bandwidth compression logic is configured to write the selected one of the first compressed block, the second compressed block, or the uncompressed block to the off-chip memory buffer and write a compression algorithm indicator associated with the selected one of the first compressed block, the second compressed block, or the uncompressed block to the on-chip memory buffer, Wherein the compression algorithm indicator is configured to indicate whether the selected block is compressed or uncompressed.

17. The media encoding system of claim 16, wherein the first compression algorithm is a lossless compression algorithm, and wherein the second compression algorithm is a lossy compression algorithm.

18. The media encoding system of claim 17, wherein selecting one of the first compressed block, the second compressed block, and the uncompressed block further comprises: In response to determining that the first size is less than or equal to a threshold size, selecting the first compressed block; In response to determining that the first size is greater than the threshold size and the second size is less than or equal to the threshold size, selecting the second compressed block; and In response to determining that the first size and the second size are greater than a threshold size, the uncompressed block is selected.

19. The media encoding system of claim 18, wherein the threshold size is equal to half of the uncompressed block size.

20. The media encoding system of claim 16, wherein the video decoder further comprises: memory bandwidth decompression logic configured to extract the selected block from the off-chip memory buffer and the compression algorithm indicator associated with the selected block from the on-chip memory buffer; Generating a reconstructed block from the selected block, wherein generating the reconstructed block includes selecting one of a first decompression algorithm or a second decompression algorithm to apply to the selected block or copying the selected block based on the compression algorithm indicator; and The reconstructed block is written to the on-chip memory buffer.

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