Memory and forming method thereof

Abstract

The invention discloses a memory and a forming method thereof. The floating gate structure is located on the substrate; the selection gate structures are arranged on the substrate at the side parts of the floating gate structures at intervals, and each selection gate structure comprises a plurality of first gates which extend along the first direction and are arranged at intervals along the second direction; the first drain region is located in the substrate on one side of the first gate; the first source regions are located in the substrate on the other side of the first grid electrode, and the multiple first source regions are electrically connected; the second drain region is located in the substrate on one side of the floating gate structure and is electrically connected with the first source region; and the second source region is located in the substrate on the other side of the floating gate structure. The first grid electrode and the first drain regions and the first source regions on the two sides of the first grid electrode form selection transistors, the multiple selection transistors are connected in parallel due to the fact that the multiple first source regions are electrically connected, the current value input to the second drain region during writing is the sum of the output current values of the selection transistors, and more charges enter the floating gate structure during writing. Therefore, the writing state of the floating gate structure can be distinguished conveniently.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a memory and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three categories: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, memory devices are more widely used, and it is necessary to form the memory devices and other device areas on a chip at the same time to form an embedded semiconductor storage device. For example, if the memory device is embedded in a central processing unit, it is necessary to make the memory device compatible with the embedded central processing unit platform and maintain the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the storage device needs to be compatible with the embedded standard logic device. For embedded semiconductor devices, they are usually divided into a logic area and a storage area, the logic area usually includes a logic device, and the storage area includes a storage device. With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), one-time programmable read only memory (OTPROM) memory, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory (Flash). Since OTPROM memory belongs to non-volatile memory, it is only allowed to be programmed once during use, so it has high data reliability. Usually, OTPROM memory is mainly used for data such as initial information and key storage.

[0004] However, the performance of current memory still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a memory and a method for forming the same, so as to improve the performance of the memory.

[0006] To solve the above problems, an embodiment of the present invention provides a memory, comprising: a substrate; a floating gate structure located on the substrate; a selection gate structure arranged at intervals on the substrate at the side of the floating gate structure, the selection gate structure comprising a plurality of first gates extending along a first direction and arranged at intervals along a second direction, the second direction being perpendicular to the first direction; a first drain region located in the substrate on one side of the first gate; a first source region located in the substrate on the other side of the first gate, and the plurality of first source regions are electrically connected; a second drain region located in the substrate on one side of the floating gate structure and electrically connected to the first source region; and a second source region located in the substrate on the other side of the floating gate structure.

[0007] Optionally, adjacent first gates share the first drain region or the first source region.

[0008] Optionally, the second drain region is adjacent to the first source region closest to the floating gate structure and is an integral structure.

[0009] Optionally, the memory also includes: a source line plug located at the top of the first drain region and electrically connected to the first drain region; a word line plug located at the top of the selection gate structure and electrically connected to the selection gate structure; a bit line plug located at the top of the second source region and electrically connected to the second source region; and a first source region plug located at the top of the first source region and electrically connected to the first source region.

[0010] Optionally, there are multiple source line plugs located on the same first drain region and arranged in sequence along the first direction; there are multiple bit line plugs located on the same second source region and arranged in sequence along the first direction; there are multiple first source region plugs located on the same first source region and arranged in sequence along the first direction.

[0011] Optionally, the memory further includes: an interconnection structure, which is located on top of the first source region plug and connects a plurality of the first source region plugs, and the plurality of the first source regions are electrically connected via the interconnection structure.

[0012] Optionally, the source line plug and the first source region plug are staggered.

[0013] Optionally, the selection gate structure also includes a second gate connected to each of the first gates and extending along the second direction; the memory also includes: a word line plug located on top of the second gate, the word line plugs are multiple in number and arranged in sequence along the second direction.

[0014] Optionally, a material of the first gate includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride and titanium aluminum carbide.

[0015] Correspondingly, an embodiment of the present invention also provides a method for forming a memory, comprising: providing a substrate; forming a floating gate structure and a selection gate structure arranged at intervals on the substrate, the selection gate structure comprising a plurality of first gates extending along a first direction and arranged at intervals along a second direction, the second direction being perpendicular to the first direction; forming a first drain region and a first source region in the substrate on both sides of the first gate, respectively, and the plurality of first source regions are electrically connected; forming a second drain region and a second source region in the substrate on both sides of the floating gate structure, respectively, and the second drain region is electrically connected to the first source region.

[0016] Optionally, in the step of respectively forming a first drain region and a first source region in the substrate at both sides of the first gate, adjacent first gates share the first drain region or the first source region.

[0017] Optionally, in the step of forming the first source region and the second drain region, the second drain region is adjacent to the first source region closest to the floating gate structure and is an integral structure.

[0018] Optionally, after forming the first source region, the first drain region, the second source region and the second drain region, the formation method further includes: forming a source line plug on the top of the first drain region, and the source line plug is electrically connected to the first drain region; forming a first source region plug on the top of the first source region, and the first source region plug is electrically connected to the first source region; forming a word line plug on the top of the selection gate structure, and the word line plug is electrically connected to the selection gate structure; forming a bit line plug on the top of the second source region, and the bit line plug is electrically connected to the second source region.

[0019] Optionally, in the step of forming the source line plug, the number of source line plugs located on the same first drain region is multiple and arranged in sequence along the first direction; in the step of forming the first source region plug, the number of first source region plugs located on the same first source region is multiple and arranged in sequence along the first direction; in the step of forming the bit line plug, the number of bit line plugs located on the same second source region is multiple and arranged in sequence along the first direction.

[0020] Optionally, in the step of forming the selection gate structure, the selection gate structure also includes a second gate connected to each of the first gates and extending along the second direction; after forming the first source region, the first drain region, the second source region and the second drain region, the formation method also includes: forming a word line plug on the top of the second gate, the number of the word line plugs is multiple, and they are arranged in sequence along the second direction.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0022] The memory provided by an embodiment of the present invention includes a selection gate structure arranged at intervals on the substrate on the side of the floating gate structure, the selection gate structure includes multiple first gates, a first drain region in the substrate on one side of the first gates, a first source region in the substrate on the other side of the first gates, and the multiple first source regions are electrically connected to a second drain region in the substrate on one side of the floating gate structure, and the second drain region is electrically connected to the first source region, and a second source region in the substrate on the other side of the floating gate structure. The first gate, and the first drain region and the first source region on both sides thereof, constitute a selection transistor. Since the plurality of first source regions are electrically connected, the plurality of selection transistors are connected in parallel. By increasing the number of first gates, the total output current of the selection transistor can be increased, so that the current value input to the second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure include a plurality of first gates, the current value input to the second drain region during writing is increased, so that more charges can enter the floating gate structure during writing, thereby making it easy to reach the turn-on voltage during reading, and also making it easy to make the current value during reading larger, which is correspondingly convenient to distinguish the state of the floating gate structure during writing, that is, the readability of the memory is improved, thereby improving the performance of the memory.

[0023] In the method for forming a memory provided by an embodiment of the present invention, the floating gate structure and the selection gate structure are formed on the substrate, and the selection gate structure includes a plurality of first gates extending along a first direction and arranged at intervals along a second direction, and the second direction is perpendicular to the first direction. A first drain region and a first source region are respectively formed in the substrate on both sides of the first gate, and the plurality of first source regions are electrically connected. A second drain region and a second source region electrically connected to the first source are respectively formed in the substrate on both sides of the floating gate structure. The first gate, and the first drain region and the first source region on both sides thereof, constitute a selection transistor. Since the plurality of first source regions are electrically connected, the plurality of selection transistors are connected in parallel. By increasing the number of first gates, the total output current of the selection transistor can be increased, so that the current value input to the second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure include a plurality of first gates, the current value input to the second drain region during writing is increased, so that more charges can enter the floating gate structure during writing, thereby making it easy to reach the turn-on voltage during reading, and also making it easy to make the current value during reading larger, which is correspondingly convenient to distinguish the state of the floating gate structure during writing, that is, the readability of the memory is improved, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 to Figure 2 It is a schematic diagram of the structure of a memory;

[0025] Figure 3is a top view of an embodiment of a memory device of the present invention;

[0026] Figure 4 for Figure 3 Cross-sectional view at AA1;

[0027] Figures 5 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a memory of the present invention. DETAILED DESCRIPTION

[0028] At present, the performance of memory still needs to be improved. Now, combining a memory, the reasons why the performance of memory needs to be improved are analyzed.

[0029] Figure 1 to Figure 2 It is a schematic diagram of the structure of a memory. Figure 1 is a top view, Figure 2 for Figure 1 Cross-sectional view at AA1.

[0030] refer to Figure 1 to Figure 2 The memory includes: a substrate 10; a floating gate structure 11, located on the substrate 10; a selection gate structure 12, spaced apart on the substrate 10 at the side of the floating gate structure 11; a first drain region 14, located in the substrate 10 on one side of the selection gate structure 12; a first source region 15, located in the substrate 10 on the other side of the selection gate structure 12; a second drain region 16, located in the substrate 10 on one side of the floating gate structure 11 and electrically connected to the first source region 15; a second source region 17, located in the substrate 10 on the other side of the floating gate structure 11.

[0031] Through research, it is found that the above-mentioned memory can easily make the current value input to the second drain region 16 smaller during writing, and correspondingly make it easy to make less charge entering the floating gate structure 11 during writing, thereby increasing the difficulty of reaching the turn-on voltage during reading, or it can easily make the current value during reading smaller, and correspondingly, it is difficult to distinguish the state of the floating gate structure 11 during writing, thereby making the readability of the memory poor, and the performance of the memory needs to be improved.

[0032] In order to solve the above technical problems, an embodiment of the present invention provides a memory, including: a substrate; a floating gate structure located on the substrate; a selection gate structure arranged at intervals on the substrate at the side of the floating gate structure, the selection gate structure including a plurality of first gates extending along a first direction and arranged at intervals along a second direction, the second direction being perpendicular to the first direction; a first drain region located in the substrate on one side of the first gate; a first source region located in the substrate on the other side of the first gate, and the plurality of first source regions are electrically connected; a second drain region located in the substrate on one side of the floating gate structure and electrically connected to the first source region; a second source region located in the substrate on the other side of the floating gate structure.

[0033] The memory provided by an embodiment of the present invention includes a selection gate structure arranged at intervals on the substrate on the side of the floating gate structure, the selection gate structure includes multiple first gates, a first drain region in the substrate on one side of the first gates, a first source region in the substrate on the other side of the first gates, and the multiple first source regions are electrically connected to a second drain region in the substrate on one side of the floating gate structure, and the second drain region is electrically connected to the first source region, and a second source region in the substrate on the other side of the floating gate structure. The first gate, and the first drain region and the first source region on both sides thereof, constitute a selection transistor. Since the plurality of first source regions are electrically connected, the plurality of selection transistors are connected in parallel. By increasing the number of first gates, the total output current of the selection transistor can be increased, so that the current value input to the second drain region during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure include a plurality of first gates, the current value input to the second drain region during writing is increased, so that more charges can enter the floating gate structure during writing, thereby making it easy to reach the turn-on voltage during reading, and also making it easy to make the current value during reading larger, which is correspondingly convenient to distinguish the state of the floating gate structure during writing, that is, the readability of the memory is improved, thereby improving the performance of the memory.

[0034] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figure 3 is a top view of an embodiment of a memory device of the present invention; Figure 4 for Figure 3 Cross-sectional view at AA1.

[0036] It should be noted that in order to clearly show the structure of the memory, Figure 3 The shallow trench isolation structure, sidewalls and interconnect structures are omitted. Figure 4 The source line plug, the first source region plug, the word line plug, the bit line plug and the interconnection structure are simplified.

[0037] refer to Figure 3 to Figure 4In this embodiment, the memory includes: a substrate 100; a floating gate structure 130, which is located on the substrate 100; a selection gate structure 140, which is arranged on the substrate 100 at intervals on the side of the floating gate structure 130, and the selection gate structure 140 includes a plurality of first gates 143 extending along a first direction y and arranged at intervals along a second direction x, and the second direction x is perpendicular to the first direction y; a first drain region 161, which is located in the substrate 100 on one side of the first gate 143; a first source region 162, which is located in the substrate 100 on the other side of the first gate 143, and the plurality of first source regions 162 are electrically connected; a second drain region 166, which is located in the substrate 100 on one side of the floating gate structure 130, and is electrically connected to the first source region 162; and a second source region 167, which is located in the substrate 100 on the other side of the floating gate structure 130.

[0038] The substrate 100 is used to provide a process platform for forming a memory.

[0039] In this embodiment, the substrate 100 is used to form a field effect transistor.

[0040] In this embodiment, the memory includes a non-volatile memory.

[0041] Specifically, the non-volatile memory includes a one-time programmable memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory or a flash memory. In this embodiment, a one-time programmable memory is taken as an example for description.

[0042] As an example, the memory is a planar device, and accordingly, the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a substrate having a channel protrusion.

[0043] In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0044] In this embodiment, a shallow trench isolation (STI) structure 110 is formed in the substrate 100 .

[0045] The shallow trench isolation structure 110 is used to define an active area (AA) (not labeled) and an isolation area (not labeled). The area between the shallow trench isolation structures 110 is used as the active area, and the remaining area is used as the isolation area. Specifically, the material of the shallow trench isolation structure 110 is SiO2. In other embodiments, the material of the shallow trench isolation structure can also be other dielectric materials such as SiN or SiON.

[0046] In this embodiment, a well region 120 is formed in the substrate 100. The doping type of the well region 120 is different from the channel conductivity type of the MOS transistor. As an example, N-type ions are doped in the well region 120. In other embodiments, P-type ions may also be doped in the well region.

[0047] The floating gate structure 130 can capture and store electrons, and after power is off, the electrons stored in the floating gate structure 130 will not be lost, thereby achieving information storage.

[0048] In this embodiment, the floating gate structure 130 includes a first gate dielectric layer 131 located on the substrate 100 , and a floating gate (FG) layer 132 located on the first gate dielectric layer 131 .

[0049] The first gate dielectric layer 131 is a tunnel oxide layer of the memory, and is used to achieve electrical isolation between the floating gate layer 132 and the substrate 100 , so that electrons enter the floating gate layer 132 through the first gate dielectric layer 131 by utilizing the tunneling effect.

[0050] The floating gate layer 132 is used to store electrons in the memory, so that the memory can store data. Specifically, when the electrons in the channel are attracted to the floating gate layer 132, a programming operation is performed.

[0051] It should be noted that the material of the floating gate layer 132 includes polysilicon. Using polysilicon as the material of the floating gate layer 132 has the characteristics of high process maturity and low process cost.

[0052] It should also be noted that the material of the first gate dielectric layer 131 includes SiO 2. In other embodiments, the material of the first gate dielectric layer may also include HfO 2, ZrO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3, SiO 2, La 2 O 3 and the like.

[0053] The selection gate structure 140 is used to determine the memory cell to be edited and read. Specifically, the memory cell to be edited and read is determined by loading a third electrical signal on the selection gate structure 140.

[0054] As an example, the third electrical signal is a voltage signal.

[0055] In this embodiment, the select gate structure 140 includes a second gate dielectric layer 142 disposed on the substrate 100 and spaced apart from the side of the first gate dielectric layer 131 , and a select gate (SG) layer 141 disposed on the second gate dielectric layer 142 .

[0056] The second gate dielectric layer 142 is used to isolate the selection gate layer 141 from the channel.

[0057] Materials of the second gate dielectric layer 142 include HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, La2O3 and the like.

[0058] The selection gate layer 141 includes a plurality of first selection gate layers (not shown) extending along the first direction y and arranged at intervals along the second direction x. The first selection gate layer and the second gate dielectric layer 142 located at the bottom of the first selection gate layer form a first gate 143 .

[0059] The material of the selection gate layer 141 includes one or more of polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC). Specifically, the material of the selection gate layer 141 is determined according to the type of the selection gate structure 140.

[0060] In this embodiment, the type of the selection gate structure 140 is a polysilicon gate structure, and the material of the selection gate layer 141 is polysilicon. Using polysilicon as the material of the selection gate layer 141 has the characteristics of high process maturity and low process cost.

[0061] In other embodiments, the type of the selection gate structure is a metal gate structure, and accordingly, the material of the selection gate layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride and titanium aluminum carbide.

[0062] Accordingly, the material of the first gate 143 also includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0063] In this embodiment, the selection gate structure 140 further includes a second gate 144 connected to each of the first gates 143 and extending along the second direction x.

[0064] The selection gate structure 140 further includes a second gate 144 connected to each of the first gates 143 and extending along the second direction x, so as to increase the process window during the formation of the word line plug, thereby reducing the difficulty of forming the word line plug.

[0065] In this embodiment, the memory further includes: a spacer 150 located on the sidewall of the floating gate structure 130 and on the sidewall of the select gate structure 140 .

[0066] Specifically, the sidewall spacer 150 may be a single-layer structure or a stacked structure; the material of the sidewall spacer 150 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. As an example, the sidewall spacer 150 is a single-layer structure, and the material of the sidewall spacer 150 is silicon nitride.

[0067] The first gate 143, and the first drain region 161 and the first source region 162 located on both sides thereof, constitute a selection transistor. Since the multiple first source regions 162 are electrically connected, the multiple selection transistors are connected in parallel. By increasing the number of first gates 143, the total output current of the selection transistor can be increased, so that the current value input to the second drain region 166 during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure 140 include multiple first gates 143, the current value input to the second drain region 166 during writing is increased, so that more charges can enter the floating gate structure 130 during writing, so that it is easy to reach the turn-on voltage during reading, and it is also easy to make the current value during reading larger, which is correspondingly convenient to distinguish the state of the floating gate structure 130 during writing, that is, the readability of the memory is improved, and then the performance of the memory is improved.

[0068] The first drain region 161 is used as a drain of the selection transistor.

[0069] The first source region 162 is used as a source of the selection transistor.

[0070] It should be noted that, by applying the first electrical signal to each first drain region 161, multiple selection transistors are connected in parallel, and the memory can write or read data. As an example, the first electrical signal is a voltage signal.

[0071] Specifically, the first drain region 161 and the first source region 162 are both doped with P-type ions, including B, Ga or In. In other embodiments, the first drain region and the first source region may also be doped with N-type ions, including P, As or Sb.

[0072] In this embodiment, adjacent first gates 143 share the first drain region 161 or the first source region 162. Adjacent first gates 143 share the first drain region 161 or the first source region 162, which is beneficial to saving the area of ​​the substrate 100 occupied by the selection transistor.

[0073] The floating gate structure 130 and the second drain region 166 and the second source region 167 located on both sides thereof constitute a data storage transistor.

[0074] The second drain region 166 is used as a drain of the data storage transistor.

[0075] The second source region 167 is used as a source of the data storage transistor.

[0076] Specifically, P-type ions are doped in the second drain region 166 and the second source region 167. In other embodiments, N-type ions may also be doped in the second drain region and the second source region.

[0077] It should be noted that by controlling the second electrical signal loaded on the second source region 167, it is possible to control whether "0" or "1" is written into the data storage transistor.

[0078] As an example, the second electrical signal is a voltage signal. For example, when the data storage transistor needs to write "1", a voltage drop is created between the second source region 167 and the second drain region 166, so that the charge enters the floating gate structure 130, and the data storage transistor stores "1"; when the data storage transistor needs to write "0", there is no voltage drop between the second source region 167 and the second drain region 166, so that the charge cannot enter the floating gate structure 530, and the data storage transistor stores "0".

[0079] In the present embodiment, the second drain region 166 is adjacent to the first source region 162 which is closest to the floating gate structure 130 and is an integral structure.

[0080] The second drain region 166 is adjacent to the first source region 162 closest to the floating gate structure 130 and is an integral structure, which facilitates electrical connection between the second drain region 166 and the first source region 162 and reduces the difficulty of electrical connection between the second drain region 166 and the first source region 162 .

[0081] In this embodiment, the memory also includes: a source line plug 171, located at the top of the first drain region 161 and electrically connected to the first drain region 161; a word line plug 173, located at the top of the selection gate structure 140 and electrically connected to the selection gate structure 140; a bit line plug 174, located at the top of the second source region 167 and electrically connected to the second source region 167; and a first source region plug 172, located at the top of the first source region 162 and electrically connected to the first source region 162.

[0082] The first drain regions 161 are electrically connected to a source line (SL) through a source line plug 171 , so that a first electrical signal is applied to the plurality of first drain regions 161 .

[0083] The select gate structures 140 are electrically connected to the word lines (WL) through the word line plugs 173 , so that the third electrical signal is applied to the plurality of select gate structures 140 .

[0084] The second source region 167 is electrically connected to the bit line (BL) through the bit line plug 174 , so that the second electrical signal is applied to the second source region 167 .

[0085] The plurality of first source regions 162 are electrically connected through the first source region plugs 172 and the interconnection structure.

[0086] In this embodiment, the selection gate structure 140 further includes a second gate 144 connected to each first gate 143 and extending along the second direction x. Accordingly, a word line plug is located on the top of the second gate. There are multiple word line plugs, which are sequentially arranged along the second direction.

[0087] There are multiple word line plugs 173, which is beneficial to reducing the current value flowing through a single word line plug 173. Moreover, the word line plugs 173 are arranged in sequence along the second direction X, which is convenient for increasing the process window for forming the word line plugs 173, thereby reducing the difficulty of forming the word line plugs 173.

[0088] In this embodiment, there are multiple source line plugs 171 located on the same first drain region 161 and arranged in sequence along the first direction y; there are multiple bit line plugs 174 located on the same second source region 167 and arranged in sequence along the first direction y; there are multiple first source region plugs 172 located on the same first source region 162 and arranged in sequence along the first direction y.

[0089] There are multiple source line plugs 171, first source region plugs 172, and bit line plugs 174, which is beneficial to reducing the current value flowing through a single plug. Moreover, the source line plugs 171, first source region plugs 172, and bit line plugs 174 are arranged in sequence along the first direction y, which is convenient for increasing the process window for forming the plugs, thereby reducing the difficulty of forming the plugs.

[0090] Specifically, the source line plug 171 and the first source region plug 172 are staggered, which is beneficial to increase the distance between adjacent source line plugs 171 and first source region plugs 172, thereby reducing parasitic capacitance.

[0091] In this embodiment, the source line plug 171 , the first source region plug 172 , the word line plug 173 , and the bit line plug 174 are all made of conductive materials, such as copper, aluminum, and the like.

[0092] In this embodiment, the memory further includes: an interconnection structure 180 located on top of the first source region plug 172 and connecting the plurality of first source region plugs 172 , and the plurality of first source regions 162 are electrically connected via the interconnection structure 180 .

[0093] An interconnection structure 180 connecting the plurality of first source plugs 172 is formed on top of the first source plugs 172 , so that the plurality of first source regions 162 are electrically connected via the interconnection structure 180 .

[0094] Specifically, in the step of forming the interconnection structure 180, the interconnection structure 180 is also located at the top of the source line plug 171, the top of the word line plug 173, and the top of the bit line plug 174, the interconnection structure 180 located at the top of the source line plug 171 is connected to the source line plug 171, the interconnection structure 180 located at the top of the word line plug 173 is connected to the word line plug 173, the interconnection structure 180 located at the top of the bit line plug 174 is connected to the bit line plug 174, and the interconnection structure 180 at the top of the first source region plug 172, the interconnection structure 180 at the top of the source line plug 171, the interconnection structure 180 at the top of the word line plug 173, and the interconnection structure 180 at the top of the bit line plug 174 are separate from each other.

[0095] As an example, the material of the interconnection structure 180 is copper. In other embodiments, the material of the interconnection structure may also be other conductive materials, such as aluminum.

[0096] Correspondingly, the present invention also provides a method for forming a memory. Figures 5 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a memory of the present invention.

[0097] refer to Figures 5 and 6 , providing a substrate 500.

[0098] in, Figure 5 is a top view, Figure 6 for Figure 5 Cross-sectional view at AA1.

[0099] It should be noted that in order to clearly show the structure of the memory, Figure 5 The shallow trench isolation structure is omitted.

[0100] The substrate 500 is used to provide a process platform for subsequent process steps.

[0101] In this embodiment, the substrate 500 is used to form a field effect transistor.

[0102] In this embodiment, the memory formed by the forming method includes a non-volatile memory.

[0103] Specifically, the non-volatile memory includes a one-time programmable memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory or a flash memory. In this embodiment, the formation method for forming a one-time programmable memory is used as an example for description.

[0104] As an example, the memory is a planar device, and accordingly, the substrate 500 is a planar substrate. In other embodiments, the substrate may also be a substrate having a channel protrusion.

[0105] In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0106] In this embodiment, in the step of providing the substrate 500 , a shallow trench isolation structure 510 is formed in the substrate 500 .

[0107] The shallow trench isolation structure 510 is used to define an active area (not shown) and an isolation area (not shown). The area between the shallow trench isolation structures 510 is used as the active area, and the remaining area is used as the isolation area. Specifically, the material of the shallow trench isolation structure 510 is SiO2. In other embodiments, the material of the shallow trench isolation structure can also be other dielectric materials such as SiN or SiON.

[0108] In this embodiment, in the step of providing the substrate 500, a well region 520 is formed in the substrate 500, and the doping type of the well region 520 is different from the channel conductivity type of the MOS transistor. As an example, N-type ions are doped in the well region 520. In other embodiments, P-type ions may also be doped in the well region.

[0109] refer to Figures 7 and 8 A floating gate structure 530 and a selection gate structure 540 are formed on a substrate 500 . The selection gate structure 540 includes a plurality of first gate electrodes 543 extending along a first direction Y and arranged at intervals along a second direction X. The second direction X is perpendicular to the first direction Y.

[0110] in, Figure 7 is a top view, Figure 8 for Figure 7 Cross-sectional view at AA1.

[0111] It should be noted that in order to clearly show the structure of the memory, Figure 7 The shallow trench isolation structure and sidewalls are omitted.

[0112] The floating gate structure 530 can capture and store electrons, and after power is lost, the electrons stored in the floating gate structure 530 will not be lost, thereby achieving information storage.

[0113] In this embodiment, in the step of forming the floating gate structure 530 , the floating gate structure 530 includes a first gate dielectric layer 531 located on the substrate 500 , and a floating gate layer 532 located on the first gate dielectric layer 531 .

[0114] The first gate dielectric layer 531 is a tunneling oxide layer of the memory, and is used to achieve electrical isolation between the floating gate layer 532 and the substrate 500 , so that electrons enter the floating gate layer 532 through the first gate dielectric layer 531 by utilizing the tunneling effect.

[0115] The floating gate layer 532 is used to store electrons in the memory, so that the memory can store data. Specifically, when the electrons in the channel are attracted to the floating gate layer 532, a programming operation is performed.

[0116] It should be noted that the material of the floating gate layer 532 includes polysilicon. Using polysilicon as the material of the floating gate layer 532 has the characteristics of high process maturity and low process cost.

[0117] It should also be noted that the material of the first gate dielectric layer 531 includes SiO 2. In other embodiments, the material of the first gate dielectric layer may also include HfO 2, ZrO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3, SiO 2, La 2 O 3 and the like.

[0118] The selection gate structure 540 is used to determine the memory cells to be edited and to be read. Specifically, the memory cells to be edited and to be read are determined by loading the third electrical signal on the selection gate structure 540.

[0119] As an example, the third electrical signal is a voltage signal.

[0120] In this embodiment, in the step of forming the selection gate structure 540 , the selection gate structure 540 includes a second gate dielectric layer 542 on the substrate 500 spaced apart from the side of the first gate dielectric layer 531 , and a selection gate layer 541 on the second gate dielectric layer 542 .

[0121] The second gate dielectric layer 542 is used to isolate the selection gate layer 541 from the channel.

[0122] Materials of the second gate dielectric layer 542 include HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, La2O3 and the like.

[0123] The selection gate layer 541 includes a plurality of first selection gate layers (not shown) extending along the first direction Y and arranged at intervals along the second direction X. The first selection gate layer and the second gate dielectric layer 542 at the bottom of the first selection gate layer constitute a first gate 543 .

[0124] The material of the selection gate layer 541 includes one or more of polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC). Specifically, the material of the selection gate layer 541 is determined according to the type of the selection gate structure 540.

[0125] In this embodiment, the material of the selection gate structure 540 is a polysilicon gate structure, and the material of the selection gate layer 541 is polysilicon. Using polysilicon as the material of the selection gate layer 541 has the characteristics of high process maturity and low process cost.

[0126] In other embodiments, the type of the selection gate structure is a metal gate structure, and accordingly, the material of the selection gate layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride and titanium aluminum carbide.

[0127] Accordingly, the material of the first gate 543 also includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0128] In this embodiment, in the step of forming the selection gate structure 540 , the selection gate structure 540 further includes a second gate 544 connected to each of the first gates 543 and extending along the second direction X.

[0129] The selection gate structure 540 further includes a second gate 544 connected to each of the first gates 543 and extending along the second direction X, so as to increase the process window in the subsequent process of forming the word line plug, thereby reducing the difficulty of forming the word line plug.

[0130] In this embodiment, in order to reduce process steps, shorten manufacturing time, and save costs, the floating gate structure 530 and the select gate structure 540 are formed in the same process step. In other embodiments, the floating gate structure may be formed first, and then the select gate structure; or the select gate structure may be formed first, and then the floating gate structure.

[0131] In this embodiment, after forming the floating gate structure 530 and the select gate structure 540 , and before forming the first drain region, the first source region, the second drain region, and the second source region, the formation method further includes: forming sidewalls 550 on the sidewalls of the floating gate structure 530 and the select gate structure 540 .

[0132] The spacer 550 is used to protect the sidewalls of the floating gate structure and the select gate structure 540 .

[0133] Specifically, the sidewall spacer 550 may be a single-layer structure or a stacked structure; the material of the sidewall spacer 550 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, and boron carbonitride. As an example, the sidewall spacer 550 is a single-layer structure, and the material of the sidewall spacer 550 is silicon nitride.

[0134] refer to Figures 9 and 10 A first drain region 561 and a first source region 562 are respectively formed in the substrate 500 on both sides of the first gate 543, and the plurality of first source regions 562 are electrically connected.

[0135] in, Fig. 9 is a top view, Fig.10 for Fig. 9 Cross-sectional view at AA1.

[0136] It should be noted that in order to clearly show the structure of the memory, Fig. 9 The shallow trench isolation structure and sidewalls are omitted.

[0137] The first gate 543, and the first drain region 561 and the first source region 562 located on both sides thereof, constitute a selection transistor. Since the multiple first source regions 562 are electrically connected, the multiple selection transistors are connected in parallel. By increasing the number of first gates 543, the total output current of the selection transistor can be increased, so that the current value input to the second drain region formed subsequently during writing is the sum of the output current values ​​of each selection transistor. Therefore, by making the selection gate structure 540 include multiple first gates 543, the current value input to the second drain region during writing is increased, so that more charges can enter the floating gate structure 530 during writing, so that it is easy to reach the turn-on voltage during reading, and it is also easy to make the current value during reading larger, which is correspondingly convenient to distinguish the state of the floating gate structure during writing, that is, the readability of the memory is improved, and then the performance of the memory is improved.

[0138] The first drain region 561 is used as a drain of the selection transistor. The first source region 562 is used as a source of the selection transistor.

[0139] It should be noted that, by applying the first electrical signal to each first drain region 561, multiple selection transistors are connected in parallel, and the memory can write or read data. As an example, the first electrical signal is a voltage signal.

[0140] Specifically, the first drain region 561 and the first source region 562 are both doped with P-type ions, including B, Ga or In. In other embodiments, the first drain region and the first source region may also be doped with N-type ions, including P, As or Sb.

[0141] In this embodiment, in the step of forming the first drain region 561 and the first source region 562 in the substrate 500 on both sides of the first gate 543, adjacent first gates 543 share the first drain region 561 or the first source region 562. Adjacent first gates 543 share the first drain region 561 or the first source region 562, which is beneficial to saving the area of ​​the substrate 500 occupied by the selection transistor.

[0142] Continue to refer Figures 9 and 10 A second drain region 566 and a second source region 567 are respectively formed in the substrate on both sides of the floating gate structure 530 , and the second drain region 566 is electrically connected to the first source region 562 .

[0143] The floating gate structure 530 and the second drain region 566 and the second source region 567 located on both sides thereof constitute a data storage transistor.

[0144] The second drain region 566 is used as a drain of the data storage transistor. The second source region 567 is used as a source of the data storage transistor.

[0145] Specifically, P-type ions are doped in the second drain region 566 and the second source region 567. In other embodiments, N-type ions may also be doped in the second drain region and the second source region.

[0146] It should be noted that by controlling the second electrical signal loaded on the second source region 567, it is possible to control whether "0" or "1" is written into the data storage transistor.

[0147] As an example, the second electrical signal is a voltage signal. For example, when the data storage transistor needs to write "1", a voltage drop is created between the second source region 567 and the second drain region 566, so that the charge enters the floating gate structure 530, and the data storage transistor stores "1"; when the data storage transistor needs to write "0", there is no voltage drop between the second source region 567 and the second drain region 566, so that the charge cannot enter the floating gate structure 530, and the data storage transistor stores "0".

[0148] In the present embodiment, in the step of forming the first source region 562 and the second drain region 566 , the second drain region 566 is adjacent to the first source region 562 closest to the floating gate structure 530 and is an integral structure.

[0149] The second drain region 566 is adjacent to the first source region 562 closest to the floating gate structure 530 and is an integral structure, which facilitates electrical connection between the second drain region 566 and the first source region 562 and reduces the difficulty of electrical connection between the second drain region 566 and the first source region 562 .

[0150] In this embodiment, the first drain region 561, the first source region 562, the second drain region 566, and the second source region 567 are formed in the same step. Forming the first drain region 561, the first source region 562, the second drain region 566, and the second source region 567 in the same step is conducive to reducing process steps, shortening manufacturing time, and saving costs.

[0151] refer to Figure 11 to Figure 12In the present embodiment, after forming the first source region 562, the first drain region 561, the second source region 567 and the second drain region 566, the formation method further includes: forming a source line plug 571 on the top of the first drain region 561, and the source line plug 571 is electrically connected to the first drain region 561; forming a first source region plug 572 on the top of the first source region 562, and the first source region plug 572 is electrically connected to the first source region 562; forming a word line plug 573 on the top of the selection gate structure 540, and the word line plug 573 is electrically connected to the selection gate structure 540; forming a bit line plug 574 on the top of the second source region 567, and the bit line plug 574 is electrically connected to the second source region 567.

[0152] in, Fig.11 is a top view, Fig.12 for Fig.11 Cross-sectional view at AA1.

[0153] It should be noted that in order to clearly show the structure of the memory, Fig.11 The shallow trench isolation structure, sidewalls and interconnect structures are omitted. Fig.12 The source line plug, the first source region plug, the word line plug, the bit line plug and the interconnection structure are simplified.

[0154] The first drain regions 561 are electrically connected to a source line (SL) through a source line plug 571 , so that a first electrical signal is applied to the plurality of first drain regions 561 .

[0155] The plurality of first source regions 562 are electrically connected through the first source region plugs 572 and the subsequently formed interconnection structure.

[0156] The select gate structures 540 are electrically connected to the word lines (WL) through the word line plugs 573 , so that the third electrical signal is applied to the plurality of select gate structures 540 .

[0157] The second source region 567 is electrically connected to the bit line (BL) through the bit line plug 574 , so that the second electrical signal is applied to the second source region 567 .

[0158] In the present embodiment, in the step of forming the selection gate structure 540, the selection gate structure 540 further includes a second gate 544 connected to each of the first gates 543 and extending along the second direction X. Accordingly, a word line plug 573 is formed on the top of the second gate 544, and the number of the word line plug 573 is plural and arranged in sequence along the second direction X.

[0159] There are multiple word line plugs 573, which is beneficial to reducing the current value flowing through a single word line plug 573. Moreover, the word line plugs 573 are arranged in sequence along the second direction X, which is convenient for increasing the process window for forming the word line plugs 573, thereby reducing the difficulty of forming the word line plugs 573.

[0160] In this embodiment, in the step of forming the source line plugs 571, the number of the source line plugs 571 located on the same first drain region 561 is multiple and arranged in sequence along the first direction Y; in the step of forming the first source region plugs 572, the number of the first source region plugs 572 located on the same first source region 562 is multiple and arranged in sequence along the first direction Y; in the step of forming the bit line plugs 574, the number of the bit line plugs 574 located on the same second source region 567 is multiple and arranged in sequence along the first direction Y.

[0161] There are multiple source line plugs 571, first source region plugs 572, and bit line plugs 574, which is beneficial to reducing the current value flowing through a single plug. Moreover, the source line plugs 571, first source region plugs 572, and bit line plugs 574 are arranged in sequence along the first direction Y, which is convenient for increasing the process window for forming the plugs, thereby reducing the difficulty of forming the plugs.

[0162] Specifically, the source line plug 571 and the first source region plug 572 are staggered, which is beneficial to increase the distance between adjacent source line plugs 571 and first source region plugs 572, thereby reducing parasitic capacitance.

[0163] In this embodiment, the source line plug 571 , the first source region plug 572 , the word line plug 573 , and the bit line plug 574 are all made of conductive materials, such as copper, aluminum, and the like.

[0164] In this embodiment, the forming method further includes: forming an interconnection structure 580 on top of the first source region plug 572 , the interconnection structure 580 connecting the plurality of first source region plugs 572 , and the plurality of first source regions 562 are electrically connected via the interconnection structure 580 .

[0165] An interconnection structure 580 connecting the plurality of first source plugs 572 is formed on top of the first source plugs 572 , so that the plurality of first source regions 562 are electrically connected via the interconnection structure 580 .

[0166] Specifically, in the step of forming the interconnection structure 580, the interconnection structure 580 is also located at the top of the source line plug 571, the top of the word line plug 573, and the top of the bit line plug 574, the interconnection structure 580 located at the top of the source line plug 571 is connected to the source line plug 571, the interconnection structure 580 located at the top of the word line plug 573 is connected to the word line plug 573, and the interconnection structure 580 located at the top of the bit line plug 574 is connected to the bit line plug 574, and the interconnection structure 580 at the top of the first source region plug 572, the interconnection structure 580 at the top of the source line plug 571, the interconnection structure 580 at the top of the word line plug 573, and the interconnection structure 580 at the top of the bit line plug 574 are separate from each other.

[0167] It should be noted that the plug and the interconnection structure 580 may be formed by a dual damascene process or by a single damascene process. The interconnection structure 580 and the plug connected may be electrically connected, for example, by physical contact.

[0168] As an example, the material of the interconnection structure 580 is copper. In other embodiments, the material of the interconnection structure may also be other conductive materials, such as aluminum.

[0169] It should be noted that the memory may be formed by the forming method described in the above embodiment, or may be formed by other forming methods. For the specific description of the memory described in this embodiment, reference may be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0170] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory, characterized in that: include: substrate; A floating gate structure, located on the substrate; A select gate structure is disposed at intervals on the substrate at the side of the floating gate structure, the select gate structure comprising a plurality of first gates extending along a first direction and arranged at intervals along a second direction, the second direction being perpendicular to the first direction; A first drain region is located in the substrate on one side of the first gate; A first source region is located in the substrate on the other side of the first gate, and a plurality of the first source regions are electrically connected; a second drain region, located in the substrate on one side of the floating gate structure and electrically connected to the first source region; The second source region is located in the substrate at the other side of the floating gate structure.

2. The memory according to claim 1, wherein: Adjacent first gates share the first drain region or the first source region.

3. The memory according to claim 1, wherein: The second drain region is adjacent to the first source region closest to the floating gate structure and is an integral structure.

4. The memory according to claim 1, wherein: The memory also includes: a source line plug, located on top of the first drain region and electrically connected to the first drain region; a word line plug, located on top of the select gate structure and electrically connected to the select gate structure; A bit line plug, located on top of the second source region and electrically connected to the second source region; The first source region plug is located on the top of the first source region and is electrically connected to the first source region.

5. The memory according to claim 4, wherein: There are multiple source line plugs located on the same first drain region and they are arranged in sequence along the first direction; There are a plurality of bit line plugs located on the same second source region and the bit line plugs are arranged in sequence along the first direction; There are a plurality of first source region plugs located on the same first source region and the plugs are arranged in sequence along the first direction.

6. The memory according to claim 4, wherein: The memory further includes: an interconnection structure, which is located on top of the first source region plug and connects a plurality of the first source region plugs, and the plurality of the first source regions are electrically connected through the interconnection structure.

7. The memory according to claim 4 or 5, characterized in that: The source line plug and the first source region plug are staggered.

8. The memory according to claim 1, wherein: The select gate structure further includes a second gate connected to each of the first gates and extending along the second direction; The memory further includes: a word line plug located on the top of the second gate, and the word line plugs are multiple in number and arranged in sequence along the second direction.

9. The memory according to claim 1, wherein: The material of the first gate includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride and titanium aluminum carbide.

10. A method for forming a memory, characterized in that: include: providing a substrate; forming a floating gate structure and a selection gate structure spaced apart on the substrate, wherein the selection gate structure comprises a plurality of first gates extending along a first direction and spaced apart along a second direction, wherein the second direction is perpendicular to the first direction; forming a first drain region and a first source region in the substrate at both sides of the first gate respectively, and a plurality of the first source regions are electrically connected; A second drain region and a second source region are respectively formed in the substrate at both sides of the floating gate structure, and the second drain region is electrically connected to the first source region.

11. The method for forming a memory according to claim 10, wherein: In the step of respectively forming a first drain region and a first source region in the substrate at both sides of the first gate, adjacent first gates share the first drain region or the first source region.

12. The method for forming a memory according to claim 10, wherein: In the step of forming the first source region and the second drain region, the second drain region is adjacent to the first source region closest to the floating gate structure and is an integral structure.

13. The method for forming a memory according to claim 10, wherein: After forming the first source region, the first drain region, the second source region and the second drain region, the forming method further includes: forming a source line plug on the top of the first drain region, wherein the source line plug is electrically connected to the first drain region; forming a first source region plug on the top of the first source region, wherein the first source region plug is electrically connected to the first source region; forming a word line plug on the top of the select gate structure, wherein the word line plug is electrically connected to the select gate structure; A bit line plug is formed on the top of the second source region, and the bit line plug is electrically connected to the second source region.

14. The method for forming a memory according to claim 13, wherein: In the step of forming the source line plug, there are multiple source line plugs located on the same first drain region and the source line plugs are arranged in sequence along the first direction; In the step of forming the first source region plug, the number of the first source region plugs located on the same first source region is plural and arranged in sequence along the first direction; In the step of forming the bit line plugs, there are a plurality of bit line plugs located on the same second source region and the bit line plugs are arranged in sequence along the first direction.

15. The method for forming a memory according to claim 10, wherein: In the step of forming the selection gate structure, the selection gate structure further includes a second gate connected to each of the first gates and extending along the second direction; After forming the first source region, the first drain region, the second source region and the second drain region, the forming method further includes: forming a word line plug on the top of the second gate, the word line plug is in multiple numbers and arranged in sequence along the second direction.

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