Vertical GaN power device based on self-alignment dip angle injection process and preparation method thereof

Abstract

The invention discloses a vertical GaN power device based on a self-alignment dip angle injection process and a preparation method thereof. The device comprises a drain metal electrode, a low-resistance substrate, a low-doping channel layer and a high-doping channel layer from bottom to top, a source metal electrode is arranged on the upper surface of the highly-doped channel layer, a gate metal electrode is arranged around the source metal electrode, and an isolation passivation layer is arranged between the source metal electrode and the gate metal electrode; and inclination angle injection regions are arranged between the low-doped channel layer and the high-doped channel layer, are symmetrically distributed by taking the two ends of the source metal electrode as the center, and penetrate into the low-doped channel layer from the top of the high-doped channel layer. The vertical GaN power device structure is formed based on the self-alignment dip angle injection process, the self-alignment dip angle injection process is developed on the basis that a damaged etching process does not need to be carried out, a low-cost enhanced grid-control structure is achieved, meanwhile, relieving of a terminal peak electric field under high voltage is effectively achieved, and the reliability of the device is improved. Therefore, the high-breakdown vertical enhanced GaN transistor is obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a vertical GaN power device based on a self-aligned tilt-angle injection process and a preparation method thereof. Background Art

[0002] The third-generation semiconductor GaN material has excellent properties such as wide band gap, high breakdown field strength, high saturated electron drift velocity and high-concentration heterojunction two-dimensional electron gas. It is the preferred structure for preparing high-power, high breakdown voltage and high-frequency power electronic devices, and has important application prospects in wireless communications, power systems, detection and other fields.

[0003] Lateral power devices based on AlGaN / GaN heterostructures have achieved excellent performance in the past decade. Power devices with working voltage on silicon substrates have been available and applied. However, for high-voltage and high-current applications, vertical device structures have the following advantages: 1) The module unit area does not affect the breakdown voltage; 2) The surface is far away from the high electric field area, thereby minimizing the impact of the trap effect; 3) Due to the wider distribution of current and electric field, it has better thermal performance. However, vertical devices still face some problems. Common Fin-strip-based structures are strongly dependent on electron beam direct writing equipment, which greatly affects the efficiency of production and increases production costs, thus limiting their application scenarios. At the same time, the realization of various groove structures depends on the etching process, and the etching damage introduced by it greatly reduces the performance of the device. Therefore, the development of a vertical enhancement-mode GaN transistor with high breakdown that can be efficiently realized based on step-by-step lithography is of great significance for practical applications. Summary of the invention

[0004] Purpose of the invention: The first purpose of the present invention is to provide a vertical GaN power device based on a self-aligned tilt injection process with high breakdown voltage, low production cost and high preparation efficiency. The second purpose of the present invention is to provide a method for preparing the above-mentioned vertical GaN power device based on the self-aligned tilt injection process.

[0005] Technical solution: The vertical GaN power device based on the self-aligned tilted injection process described in the present invention includes a drain metal electrode, a low-resistance substrate, a low-doped channel layer and a high-doped channel layer from bottom to top; a source metal electrode is provided on the upper surface of the high-doped channel layer, a gate metal electrode is provided around the source metal electrode, an isolation passivation layer is provided between the source metal electrode and the gate metal electrode, and the isolation passivation layer fully covers the source metal electrode and the gate metal electrode to protect the metal contact; a tilted injection region is provided between the low-doped channel layer and the high-doped channel layer, the tilted injection region is symmetrically distributed with the two ends of the source metal electrode as the center, and penetrates from the top of the high-doped channel layer to the inside of the low-doped channel layer, and the top of the tilted injection region is the gate metal electrode and the isolation passivation layer.

[0006] Furthermore, the drain metal electrode and the source metal electrode are ohmic contacts formed by annealing low work function metal.

[0007] Furthermore, the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy.

[0008] Furthermore, the low-resistance substrate is any one of SiC and GaN self-supporting substrates, and the effective carrier concentration should be greater than 10 18 The low-doped channel layer has an n-type carrier concentration of less than 10 17 GaN material; the highly doped channel layer has an n-type carrier concentration greater than 10 18 GaN material.

[0009] Furthermore, the vertical injection depth of the tilt injection zone is greater than 1 um, and the injection angle θ is less than 45°.

[0010] Furthermore, the gate metal electrode is a high work function metal.

[0011] Furthermore, the high work function metal is one of W, Ni, Pt and TiN.

[0012] Furthermore, the isolation passivation layer is one or more of SiO2, Si3N4, and Al2O3 media.

[0013] The method for preparing the vertical GaN power device based on the self-aligned tilt implantation process comprises the following steps:

[0014] 1) Growing a low-doped channel layer and a high-doped channel layer in sequence on a low-resistance substrate by using an epitaxial growth method;

[0015] 2) depositing a low work function metal under the low resistance substrate by metal deposition, and forming a low resistance ohmic contact through high temperature annealing to form a drain metal electrode;

[0016] 3) Patterning is performed on the highly doped channel layer, and a low work function metal is deposited by metal deposition, and after stripping, high temperature annealing is performed to form a low resistance ohmic contact to form a source metal electrode;

[0017] 4) performing ion implantation on the highly doped channel layer, using the source metal electrode as a self-aligned mask to perform implantation at an angle of θ to form a tilted implantation region;

[0018] 5) Patterning is performed on the highly doped channel layer, and a high work function metal is deposited by metal deposition, and a gate metal electrode is formed after stripping, and the tilted injection region and the gate metal electrode form a gate control structure;

[0019] 6) An isolation passivation layer is grown on the highly doped channel layer to cover the source metal electrode and the gate metal electrode to protect the metal contact, thereby obtaining a vertical GaN power device based on a self-aligned tilt implantation process.

[0020] Furthermore, in step 1), the epitaxial growth method includes metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) and hydride vapor phase epitaxy (HVPE).

[0021] Furthermore, in step 4), the type of ion implantation is one of F ions forming a free electron depletion region, N ions etc. implanted to form a high resistance region, or Mg ions implanted to form a P-type region.

[0022] Furthermore, in step 4), the mask is manufactured by optical lithography or electron beam direct writing.

[0023] Furthermore, in step 6), the growth method of the isolation passivation layer includes low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD).

[0024] Principle of the invention: In the present invention, the structure of the vertical GaN power device based on the self-aligned tilted injection process includes a low-resistance substrate, a low-doped channel layer, a high-doped channel layer, a contact electrode, a tilted injection region, and an isolation passivation layer, wherein the source metal electrode and the source metal electrode are ohmic contacts formed by depositing a low work function metal on the high-doped channel layer and the low-resistance substrate and annealing, the gate metal electrode is a voltage control structure composed of a metal and a tilted injection region, and the isolation passivation layer covers the source metal electrode and the gate metal electrode to protect the metal contact. The vertical structure device designed by the present invention utilizes a longitudinal low-doped channel layer to improve the withstand voltage of the device, forming a vertical GaN power device controlled by a self-aligned injection gate control structure. The high-resistance region is formed by injection in a self-aligned manner, and the region can effectively alleviate the peak electric field edge concentration effect, so that the electric field distribution is more uniform under high voltage conditions, thereby obtaining a higher breakdown voltage. According to this technology, while fully utilizing the withstand voltage characteristics of the vertical structure, the process complexity is reduced and the efficiency is improved.

[0025] Beneficial effects: Compared with the prior art, the present invention has the following significant effects: (1) The conventional vertical enhancement-mode GaN transistor adopts a top Fin strip structure, the preparation of which needs to rely on electron beam direct writing to achieve a sufficiently thin structure for sidewall depletion to achieve enhancement. The complex process and the high cost and low efficiency of electron beam direct writing make it difficult to apply in a process production environment. The self-aligned tilt injection process of the present invention uses a self-aligned injection method to form depletion instead of relying on etching to form a narrow Fin strip structure, so that it can be completed using a stepper lithography machine, which has the huge advantages of high efficiency and low cost. The invention solves the key technical problems in practical applications of vertical devices; (2) the self-aligned tilted injection process adopted by the present invention can effectively avoid the use of high-energy plasma etching technology, thereby reducing the defects introduced by etching damage, reducing the gate current and the leakage current in the off state, and improving the performance of the device, thus solving the key technical problems in practical applications of vertical devices; (3) the self-aligned tilted injection process with the source metal electrode as a mask adopted by the present invention is simpler than the regrowth epitaxial technology required for the aperture-type vertical GaN device structure that requires a P-type or I-type GaN layer, and also greatly reduces the cost required for the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structure of a vertical GaN power device based on a self-aligned tilt implantation process, (a) is a cross-sectional view, (b) is a top view;

[0027] Figure 2 The flowchart for the preparation of vertical GaN power devices based on the self-aligned tilt implantation process. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below in conjunction with the embodiments and drawings.

[0029] Example 1: Figure 1 As shown, the vertical GaN power device based on the self-aligned tilted implantation process provided in this embodiment includes a drain metal electrode 1, a low-resistance substrate 2, a low-doped channel layer 3 and a high-doped channel layer 4 from bottom to top; a source metal electrode 5 is provided on the upper surface of the high-doped channel layer 4, and a gate metal electrode 7 is provided around the source metal electrode 5, and an isolation passivation layer 8 is provided between the source metal electrode 5 and the gate metal electrode 7, and the isolation passivation layer 8 fully covers the source metal electrode 5 and the gate metal electrode 7 to protect the metal contact; a tilted implantation region 6 is provided between the low-doped channel layer 3 and the high-doped channel layer 4, and the tilted implantation region 6 is symmetrically distributed with the two ends of the source metal electrode 5 as the center, and penetrates from the top of the high-doped channel layer 4 to the inside of the low-doped channel layer 3, and the top of the tilted implantation region 6 is the gate metal electrode 7 and the isolation passivation layer 8.

[0030] like Figure 2 As shown, the method for preparing the vertical GaN power device based on the self-aligned tilt implantation process comprises the following specific steps:

[0031] 1) If Figure 2 As shown in (a), a low-doped channel layer 3 and a high-doped channel layer 4 are sequentially grown on a low-resistance substrate 2 by an epitaxial growth method. The low-resistance substrate 2 is any one of a SiC and a GaN self-supporting substrate. The effective carrier concentration should be greater than 10 18 The low-doped channel layer 3 has an n-type carrier concentration of less than 10 17 GaN material; the highly doped channel layer 4 has an n-type carrier concentration greater than 10 18 GaN materials;

[0032] 2) If Figure 2 As shown in (b), a low work function metal is deposited under the low resistance substrate 2 by metal deposition, and a low resistance ohmic contact is formed by high temperature annealing to form a drain metal electrode 1, and the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy;

[0033] 3) If Figure 2 As shown in (b), the highly doped channel layer 4 is patterned, and a low work function metal is deposited by metal deposition, and a low resistance ohmic contact is formed by high temperature annealing after stripping to form a source metal electrode 5, wherein the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy;

[0034] 4) If Figure 2 As shown in (c), ion implantation is performed on the highly doped channel layer 4, and an implantation is performed at an angle of θ using the source metal electrode 5 as a self-aligned mask to form a tilted implantation region 6. The tilted implantation region 6 is formed by ion implantation. During the implantation process, the wafer needs to rotate at a constant speed, the vertical implantation depth should be greater than 1um, and the implantation angle θ should be less than 45°. The type of ion implantation can be one of F ions forming a free electron depletion region, N ions etc. implanted to form a high resistance region, and Mg ions implanted to form a P-type region.

[0035] 5) If Figure 2 As shown in (d), the highly doped channel layer 4 is patterned, and a high work function metal is deposited by metal deposition, and a gate metal electrode 7 is formed after stripping; the tilted implantation region 6 and the gate metal electrode 7 form a gate control structure, and the high work function metal is one of W, Ni, Pt, and TiN;

[0036] 6) If Figure 2 As shown in (e), on the highly doped channel layer 4, an isolation passivation layer 8 is grown to cover the source metal electrode 5 and the gate metal electrode 7 to protect the metal contact, and the isolation passivation layer 8 is one or more of SiO2, Si3N4, Al2O3 media with a thickness of 200-400nm obtained by different growth methods.

[0037] So far, the present embodiment has been described in detail in conjunction with the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the present invention "a vertical GaN power device based on a self-aligned tilt injection process and a method for preparing the same". Based on the preparation method proposed in the present invention, while having a lower production cost, the breakdown voltage of the device can be improved, thereby enabling efficient and reliable manufacture of vertical enhancement-mode GaN transistors with a high breakdown voltage.

[0038] It should be noted that the implementation methods not shown or described in the drawings or the text of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of various elements and methods are not limited to the various specific structures, shapes or methods mentioned in the embodiments. Ordinary technicians in this field can simply change or replace them. For example, the GaN layer can be replaced by an AlGaN layer.

[0039] It should also be noted that this document may provide demonstrations of parameters containing specific values, but these parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint. The directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only reference directions of the accompanying drawings and are not intended to limit the scope of protection of the present invention. In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to those listed above, and can be changed or rearranged according to the desired design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0040] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A vertical GaN power device based on a self-aligned tilt implantation process, characterized in that: It includes, from bottom to top, a drain metal electrode (1), a low-resistance substrate (2), a low-doped channel layer (3) and a high-doped channel layer (4); A source metal electrode (5) is provided on the upper surface of the highly doped channel layer (4), a gate metal electrode (7) is provided around the source metal electrode (5), an isolation passivation layer (8) is provided between the source metal electrode (5) and the gate metal electrode (7), and the isolation passivation layer (8) completely covers the source metal electrode (5) and the gate metal electrode (7) to protect the metal contact; An angled injection region (6) is provided between the low-doped channel layer (3) and the high-doped channel layer (4); the angled injection region (6) is symmetrically distributed with the two ends of the source metal electrode (5) as the center, and penetrates from the top of the high-doped channel layer (4) to the inside of the low-doped channel layer (3); the top of the angled injection region (6) is a gate metal electrode (7) and an isolation passivation layer (8).

2. The vertical GaN power device according to claim 1, characterized in that: The drain metal electrode (1) and the source metal electrode (5) are ohmic contacts formed by annealing low work function metals.

3. The vertical GaN power device according to claim 2, characterized in that: The low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy and Ti-Al-Mo-Au alloy.

4. The vertical GaN power device according to claim 1, characterized in that: The low-resistance substrate (2) is any one of SiC and GaN self-supporting substrates, and the effective carrier concentration should be greater than 10 18 The low-doped channel layer (3) has an n-type carrier concentration of less than 10 17 GaN material; the highly doped channel layer (4) has an n-type carrier concentration greater than 10 18 GaN material.

5. The vertical GaN power device according to claim 1, characterized in that: The vertical injection depth of the tilted injection zone (6) is greater than 1 um, and the injection angle θ is less than 45°.

6. The vertical GaN power device according to claim 1, characterized in that: The gate metal electrode (7) is a high work function metal.

7. The vertical GaN power device according to claim 6, characterized in that: The high work function metal is one of W, Ni, Pt and TiN.

8. The vertical GaN power device according to claim 1, characterized in that: The isolation passivation layer (8) is one or more of SiO2, Si3N4, and Al2O3 media.

9. A method for preparing a vertical GaN power device based on a self-aligned tilt implantation process according to claim 1, characterized in that: The following steps are involved: 1) growing a low-doped channel layer (3) and a high-doped channel layer (4) in sequence on a low-resistance substrate (2) by using an epitaxial growth method; 2) depositing a low work function metal under the low resistance substrate (2) by metal deposition, and forming a low resistance ohmic contact through high temperature annealing to form a drain metal electrode (1); 3) Patterning is performed on the highly doped channel layer (4), and a low work function metal is deposited by metal deposition, and after stripping, high temperature annealing is performed to form a low resistance ohmic contact, thereby forming a source metal electrode (5); 4) performing ion implantation on the highly doped channel layer (4), using the source metal electrode (5) as a self-aligned mask to perform implantation at an angle of θ to form a tilted implantation region (6); 5) Patterning is performed on the highly doped channel layer (4), and a high work function metal is deposited by metal deposition, and a gate metal electrode (7) is formed after stripping, and the tilted injection region (6) and the gate metal electrode (7) form a gate control structure; 6) An isolation passivation layer (8) is grown on the highly doped channel layer (4) to cover the source metal electrode (5) and the gate metal electrode (7) to protect the metal contact, thereby obtaining a vertical GaN power device based on a self-aligned tilt implantation process.

10. The preparation method according to claim 9, characterized in that: In step 4), the type of ion implantation is one of F ions forming a free electron depletion region, N ions etc. implanted to form a high resistance region, or Mg ions implanted to form a P-type region.

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