Phosphorus emitter passivation structure and preparation method thereof

Abstract

The invention provides a phosphorus emitter passivation structure and a preparation method thereof, the passivation structure comprises a phosphorus emitter, the phosphorus emitter comprises silicon, phosphorus, hydrogen, carbon and / or nitrogen, the surface of the phosphorus emitter is provided with a nano silicon oxide layer, the phosphorus emitter comprises an electric injection region and a doped region, the electric injection region is provided with a conductive layer at a corresponding position, and the doped region is provided with a conductive layer at a corresponding position. The conductive layer is used for being connected with a metal electrode, a passivation anti-reflection layer is arranged at the corresponding position of the doped region, and the carbon and / or nitrogen concentration of the electric injection region is higher than that of the electric injection region. Partitioned passivation is performed on the surface of the phosphorus emitter, and carbon and / or nitrogen atoms are introduced into the doped region, so that the interface passivation effect is improved; the electric injection region is not subjected to carbon and nitrogen doping and is not provided with a passive film, so that the influence of passivation on the contact resistivity is reduced; a conductive channel is introduced into the electric injection region for electric injection, so that the defect state of the phosphorus emitter can be further eliminated, and the recombination current is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of surface passivation of crystalline silicon solar cells, in particular to a phosphorus emitter passivation structure and a preparation method thereof. BACKGROUND

[0002] The surface passivation quality directly affects the photoelectric conversion efficiency of the cell. For the passivation of the phosphorus emitter of the P-type cell, the commonly used passivation structures in the prior art include: SiN x , SiO x / SiN x , etc. The saturation current density of the phosphorus emitter (150-200 Ω / sq) passivated by SiN x is usually 30-50 fA / cm 2 , and the saturation current density of the phosphorus emitter passivated by SiO x / SiN x is usually 25-35 fA / cm 2 . Obviously, the saturation current density of the phosphorus emitter passivated by the existing passivation technology is still large, which becomes the main source of cell recombination, and the existence of the passivation film adversely affects the specific contact resistance of the cell, thereby restricting the improvement of the cell efficiency. SUMMARY

[0003] In view of the deficiencies of the prior art, the technical problem to be solved by the present application is how to reduce the recombination loss of the phosphorus emitter of the P-type cell and improve the specific contact resistance of the electrode.

[0004] To solve the above problems, the present application provides a phosphorus emitter passivation structure, which comprises a phosphorus emitter, the composition of the phosphorus emitter comprising silicon, phosphorus, hydrogen, carbon and / or nitrogen, a nano-silicon oxide layer is arranged on the surface of the phosphorus emitter, the phosphorus emitter comprises an electrical injection area and a doped area, the electrical injection area is used to be connected with a metal electrode, a passivation and anti-reflection layer is arranged at the corresponding position of the doped area, and the carbon and / or nitrogen concentration of the non-contact electrical injection area is higher than that of the electrical injection area.

[0005] The present application performs zoned passivation on the surface of the phosphorus emitter, introduces carbon and / or nitrogen atoms in the doped area, improves the interface passivation effect, and at the same time, a nano-silicon oxide layer is arranged to improve the passivation and increase the hydrogen concentration of the interface; the electrical injection area is not doped with carbon and nitrogen, and no passivation film is arranged, so as to reduce the influence of passivation on the specific contact resistance; the electrical injection area introduces a conductive channel for electrical injection, which can further eliminate the defect states of the phosphorus emitter and reduce the recombination current.

[0006] Further, the carbon and / or nitrogen concentration of the doped area is higher than 1×10 19 cm -3 , and the hydrogen concentration is higher than 1×10 19 cm-3 , the carbon and / or nitrogen concentration of the electric injection region is less than 1×10 17 cm -3 Introducing high concentration of carbon and / or nitrogen doping in the doped region is beneficial to inhibit defects, increase hydrogen concentration and reduce surface saturation current density.

[0007] Further, the carbon and / or nitrogen element concentration in the doped region is lower the farther from the surface, and the carbon and / or nitrogen concentration in the near-surface part of the doped region is higher than 1×10 20 cm -3 The near-surface part refers to the region of the phosphor emitter close to the surface, generally refers to the region within 10nm or 20nm from the surface depth.

[0008] Further, the thickness of the phosphor emitter is 200-2000nm.

[0009] In order to reduce parasitic absorption, the carbon and / or nitrogen element in the phosphor emitter is injected later, which will produce element enrichment at the interface of the nanometer silicon oxide layer and the doped region, showing a downward trend from the surface to the body, and still has a high concentration at a certain depth, which can inhibit the defects of the emitter.

[0010] Further, the thickness of the nanometer silicon oxide layer is 1-5nm, and the absorption coefficient k of the nanometer silicon oxide layer at a wavelength of 500nm or more is less than 0.1cm -1 The nanometer silicon oxide layer mainly plays a role in improving passivation and increasing interface hydrogen concentration, and the thickness of the nanometer silicon oxide layer is small, and has little effect on optical absorption.

[0011] Further, the material of the conductive layer is phosphorus-doped polysilicon or transparent conductive oxide. The conductive layer is provided to reserve a conductive channel for subsequent electric injection to eliminate the defect states of the phosphor emitter.

[0012] Further, the passivation and anti-reflection layer is composed of one or more thin films of aluminum oxide, silicon nitride and silicon oxide. The passivation and anti-reflection layer plays a role in providing hydrogen elements and reducing reflection.

[0013] The preparation method of the above-mentioned phosphor emitter passivation structure comprises the following steps:

[0014] Prepare a P-type silicon wafer, and prepare a phosphor emitter on the surface;

[0015] Prepare a nanometer silicon oxide layer on the surface of the phosphor emitter;

[0016] Select the electric injection region and the doped region of the phosphor emitter, prepare a doped amorphous silicon layer doped with carbon and / or nitrogen elements on the doped region, and prepare a conductive layer on the electric injection region;

[0017] High temperature annealing is performed under inert gas atmosphere to diffuse carbon and / or nitrogen atoms in the doped amorphous silicon layer into the doped region of the phosphor emitter, and the doped amorphous silicon layer is converted into a doped polysilicon layer;

[0018] The doped polysilicon layer is etched and removed;

[0019] A passivation anti-reflection layer is prepared on the surface of the substrate, and then the passivation anti-reflection layer on the corresponding part of the conductive layer is removed;

[0020] The outer electrode acts on the conductive layer to perform electric injection under dark field condition or under strong light irradiation.

[0021] The above method uses a partition passivation technology to introduce carbon and / or nitrogen atoms into the doped region of the phosphor emitter, thereby improving the interface passivation effect, and the carbon and / or nitrogen atoms can also capture hydrogen atoms to passivate deep level defects through hydrogen atoms; an electrically conductive channel is provided in the electric injection region of the phosphor emitter to perform electric injection to further eliminate defects of the phosphor emitter and reduce recombination current, and at the same time, the partition passivation technology of the present application can avoid the influence of the passivation structure on the contact resistivity, which is beneficial to improve the cell efficiency.

[0022] The second aspect of the present application provides another phosphor emitter passivation structure, which is different from the above-mentioned phosphor emitter passivation structure in that a doped polysilicon layer is provided at the position corresponding to the doped region, and the doped polysilicon layer is located between the nanometer silicon oxide layer and the passivation anti-reflection layer; the doped polysilicon layer is composed of one or more layers of polysilicon thin film containing carbon and / or nitrogen.

[0023] The doped polysilicon layer is used to inject carbon and / or nitrogen atoms into the phosphor emitter, which not only improves the interface passivation effect, but also reduces the defects in the silicon body.

[0024] Further, the carbon and / or nitrogen content of each layer of polysilicon thin film in the doped polysilicon layer is 1at% to 50at%.

[0025] Further, the thickness of the doped polysilicon layer is 1 to 50 nm, the refractive index is 1.5 to 3.5, and the extinction coefficient is less than or equal to 1.

[0026] Further, the hydrogen concentration in the carbon-silicon layer is higher than 1×10 20 cm -3 .

[0027] The components in the polysilicon thin film can be adjusted to change the refractive index and extinction coefficient, and by adjusting the carbon and / or nitrogen content combination of each layer of polysilicon thin film, different atomic injection effects can be achieved in the phosphor emitter.

[0028] The preparation method of the above-mentioned phosphor emitter passivation structure comprises the following steps:

[0029] A P-type silicon wafer is prepared, and a phosphor emitter is prepared on the surface;

[0030] A nano-silicon oxide layer is prepared on the surface of the phosphor emitter;

[0031] An electric injection area and a doped area of the phosphor emitter are selected, a doped amorphous silicon layer doped with carbon and / or nitrogen elements is prepared on the doped area, and a conductive layer is prepared on the electric injection area;

[0032] High-temperature annealing is performed in an inert gas atmosphere, so that carbon and / or nitrogen atoms in the doped amorphous silicon layer diffuse into the doped area of the phosphor emitter, and the doped amorphous silicon layer is converted into a doped polysilicon layer;

[0033] A passivation anti-reflection layer is prepared on the surface of the substrate, and then the passivation anti-reflection layer on the corresponding part of the conductive layer is removed;

[0034] The outer electrode acts on the conductive layer to perform electric injection under dark field conditions or under strong light irradiation.

[0035] In summary, the present application has the following beneficial effects relative to the prior art:

[0036] (1) The present application uses a partition passivation technology to introduce carbon and / or nitrogen elements into the doped area of the phosphor emitter, which can achieve excellent passivation effect and reduce surface recombination.

[0037] (2) The present application introduces a conductive channel in the electric injection area of the phosphor emitter for electric injection, which can further eliminate defect states of the phosphor emitter, reduce recombination current, and reduce the surface saturation current density of the phosphor emitter (150-200 Ω / sq) from the original 25-50 fA / cm 2 to 14 fA / cm 2 below.

[0038] (3) The present application uses a partition passivation technology to not actively introduce carbon and / or nitrogen elements into the electric injection area of the phosphor emitter, and does not set a passivation film, but directly sets a conductive layer to reduce the adverse effects of the passivation structure on the specific resistance of the electrode contact.

[0039] (4) The passivation technology of the present application injects a large number of carbon and / or nitrogen atoms into the phosphor emitter, which increases the optical bandgap, reduces the concentration of free carriers, and reduces parasitic absorption.

[0040] (5) In the passivation structure of the present application, the doped amorphous silicon layer has small thickness, large optical bandgap, and small parasitic absorption, which does not significantly affect the short-circuit current of the cell.

[0041] (6) The passivation technology of the present application is fully compatible with existing cell production lines, has good industrial application prospects, and can further stack other transparent dielectric films on the passivation structure to form a more complex film system structure, and has strong technical expandability. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 Structure diagram of the passivated wafer prepared for Example 2 of the present application.

[0043] Figure 2 Structure diagram of the passivated wafer prepared for Comparative Example 2 of the present application.

[0044] Figure 3 Structure diagram of the TOPCon cell prepared for Example 7 of the present application.

[0045] Figure 4 Structure diagram of the TOPCon cell prepared for Comparative Example 3 of the present application.

[0046] Explanation of reference signs:

[0047] 1-silicon wafer, 2-phosphorous emitter, 3-nanometer silicon oxide layer, 4-doped polysilicon layer, 5-conductive layer, 6-aluminum oxide layer, 7-silicon nitride layer, 8-tunneling oxide layer, 9-boron-doped polysilicon layer. DETAILED DESCRIPTION

[0048] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation method and typical parameters of the present application, and are not used to limit the parameter range described in the present application, and any reasonable changes derived therefrom are still within the protection scope of the claims of the present application.

[0049] It should be noted that the endpoints of the ranges and any values disclosed herein are not limited to the precise values stated. The ranges and values should be interpreted as approximately between the stated values. For ranges of values, the endpoints of the ranges are included in the range, and the endpoints of the ranges and the individual points within the ranges can be combined to form one or more new ranges, which are to be considered as disclosed herein.

[0050] The embodiment of the present application provides a phosphor emitter passivation structure, which comprises a phosphor emitter, the phosphor emitter can be located on the front surface or back surface of a P-type silicon wafer, and the phosphor emitter is divided into an electrical injection area and a doped area. A nanometer silicon oxide layer is arranged on the surface of the phosphor emitter, a doped polysilicon layer (optional) and a passivation anti-reflection layer are arranged on the nanometer silicon oxide layer at positions corresponding to the doped area, and a conductive layer is arranged at a position corresponding to the electrical injection area and used for connecting with a metal electrode. The doped area of the phosphor emitter, the nanometer silicon oxide layer and the doped polysilicon layer all contain high-concentration hydrogen elements, carbon and / or nitrogen, which can reduce the interface state density of the surface area of the doped area and improve the passivation performance of the phosphor emitter; the electrical injection area is not doped with carbon and / or nitrogen, which is beneficial to improving the contact resistivity of the electrical injection area; and a conductive channel is reserved in the electrical injection area for electrical injection, which can further eliminate the defect states of the phosphor emitter and reduce the recombination current.

[0051] The typical process of the preparation method of the above phosphor emitter passivation structure comprises the following steps:

[0052] (1) A P-type silicon wafer is prepared, RCA cleaning is performed, phosphor diffusion is performed, and a phosphor emitter is prepared on the surface of the silicon wafer, the thickness of the phosphor emitter is 100-2000 nm, and the thickness range is preferably 600-1000 nm.

[0053] (2) A nanometer silicon oxide layer is prepared on the surface of the phosphor emitter. The preparation method of the nanometer silicon oxide layer can be selected from wet chemical method, plasma-assisted oxidation method, thermal oxidation method and ozone gas oxidation method, and the thickness range can be 1-5 nm, and the thickness range is preferably 1-2 nm, and the absorption coefficient k of the nanometer silicon oxide layer at a wavelength of 500 nm or above is less than 0.1 cm -1 . The nanometer silicon oxide layer can improve surface passivation and increase the hydrogen concentration of the interface.

[0054] (3) The electrical injection area and the doped area of the phosphor emitter are selected, a new type of doped amorphous silicon layer is prepared on the doped area, and a conductive layer is prepared on the electrical injection area. The doped amorphous silicon layer is composed of one or more carbon and / or nitrogen-containing amorphous silicon thin films. The typical preparation method of the doped amorphous silicon layer is PECVD, the proportion of carbon and / or nitrogen elements in each layer of carbon silicon thin film can be adjusted, and the proportion is preferably 1at%-50at%. The thickness range of the doped amorphous silicon layer can be 1-50 nm, and the thickness range is preferably 1-5 nm, the refractive index range is 1.5-3.5, the extinction coefficient is generally below 1, and the composition can be adjusted. The conductive layer can be selected from boron-doped polysilicon and transparent conductive oxide.

[0055] (4) high temperature annealing is performed to convert the doped amorphous silicon layer into a doped polysilicon layer, and carbon and / or nitrogen elements in the doped polysilicon layer diffuse to the phosphorus emitter, thereby inhibiting defects and facilitating subsequent increase of hydrogen element concentration. The high temperature annealing is typically performed at a temperature ranging from 600°C to 1100°C in a nitrogen atmosphere. After the high temperature annealing, the carbon and / or nitrogen concentration in the near-surface region of the phosphorus emitter is higher than 1×1019cm-3, and can be higher than 1×1020cm-3. The near-surface region refers to a region of the phosphorus emitter close to the surface, and typically refers to a region within 10 nm from the surface, or a region within 20 nm from the surface. The carbon and / or nitrogen elements in the doped region are injected later, and have a downward trend from the surface to the bulk. The carbon and / or nitrogen concentration is higher than 2×1019cm-3 at a depth of 100 nm below the surface of the doped region, and the carbon and / or nitrogen concentration in the entire doped region is higher than 1×1020cm-3. The electrically injected region does not actively introduce carbon and / or nitrogen atoms, and the carbon and / or nitrogen concentration in the electrically injected region is lower than 1×1019cm-3. 20 cm -3 21 cm -3 19 cm -3 19 cm -3 17 cm -3 .

[0056] (5) a passivation and anti-reflection layer is prepared on the surface of the substrate, and the passivation and anti-reflection layer is removed from the conductive layer. The passivation and anti-reflection layer provides hydrogen elements and reduces reflection. The passivation and anti-reflection layer can be composed of one or more thin films of aluminum oxide, silicon nitride, or silicon oxide. The common thickness of the aluminum oxide thin film is 3-30 nm, the common thickness of the silicon nitride thin film is 10-200 nm, and the common thickness of the silicon oxide thin film is 10-200 nm.

[0057] (6) the external electrode acts on the conductive layer to perform electric injection under dark field conditions or under strong light irradiation.

[0058] In some embodiments, after the high temperature annealing in step (4), the doped polysilicon layer is etched to avoid parasitic absorption.

[0059] ​​​​The present application introduces high-concentration carbon and / or nitrogen atoms into the doped region of the phosphorus emitter by using the partition passivation technology, and forms a multi-layer passivation structure to reduce the interface state density of the surface region; the electrically injected region is introduced with a conductive channel and is subjected to electric injection and / or light injection, which can further eliminate defect states and reduce recombination current, and together achieve the effect of improving the passivation performance of the phosphorus emitter; and the electrically injected region is not subjected to carbon and nitrogen doping, and no passivation film is provided, which is conducive to improving the contact resistivity of the electrically injected region. The passivation method described above is used to prepare a P-type tunnel oxide passivated contact cell, which can improve the cell efficiency, and the passivation technology is fully compatible with the existing cell production line, and has good industrial application prospect.

[0060] The technical solutions and effects of the present application are described below through specific examples.

[0061] Example 1

[0062] (1) A P-type textured silicon wafer with a thickness of 170 μm and a resistivity of 1 Ω·cm is taken.

[0063] (2) The silicon wafer is transferred to a diffusion furnace for double-sided phosphorus diffusion to prepare a phosphorus emitter with a sheet resistance of 150-200 Ω / sq.

[0064] (3) After standard RCA cleaning, the silicon wafer is placed in a PECVD chamber, and a 1 nm thick nanometer silicon oxide layer is deposited on the phosphorus emitter using N2O plasma.

[0065] (4) A 10 nm thick nitrogen-doped amorphous silicon layer is deposited on the nanometer silicon oxide layer, and the nitrogen content in the nitrogen-doped amorphous silicon layer is 20 at%.

[0066] (5) The sample is placed in an annealing furnace for high-temperature annealing at 900℃ for 30 min, and the protective atmosphere is nitrogen, and the nitrogen-doped amorphous silicon layer is converted into a nitrogen-doped polysilicon layer.

[0067] (6) The nitrogen-doped polysilicon layer is etched clean, and the substrate surface is cleaned.

[0068] (7) The cleaned sample is placed in an ALD, and a 10 nm thick aluminum oxide layer is deposited on both sides.

[0069] (8) The sample is placed in a PECVD, and a 60 nm thick silicon nitride layer is deposited on both sides to obtain a passivated wafer.

[0070] The passivated wafer prepared in this example is subjected to Sinton test, and the implied open-circuit voltage is 716 mV, and the single-sided saturation current density is 13 fA / cm 2 .

[0071] Example 2

[0072] (1) Take P-type textured silicon wafer with thickness of 170 μm and resistivity of 1 Ω-cm.

[0073] (2) Transfer the silicon wafer 1 to a diffusion furnace for double-side phosphorus diffusion to prepare a phosphorus emitter 2 with a sheet resistance of 150-200 Ω / sq.

[0074] (3) After standard RCA cleaning, place the silicon wafer 1 in a PECVD chamber, and deposit a nanometer silicon oxide layer 3 with a thickness of 2 nm on the phosphorus emitter using N2O plasma.

[0075] (4) Select the electrical injection area and the doped area of the phosphorus emitter 2, and prepare a doped nitrogen amorphous silicon layer on the doped area with a thickness of 10 nm and a nitrogen content of 20 at%; and prepare a doped phosphorus amorphous silicon film as a conductive layer 5 on the electrical injection area.

[0076] (5) Place the sample in an annealing furnace for high-temperature annealing at 920 ℃ for 30 min in a nitrogen atmosphere, and convert the doped nitrogen amorphous silicon layer into a doped polysilicon layer 4, and convert the doped phosphorus amorphous silicon into a doped polysilicon.

[0077] (6) Place the cleaned sample in an ALD, and deposit an aluminum oxide layer 6 on both sides.

[0078] (7) Place the sample in a PECVD, and deposit a silicon nitride layer 7 on both sides to obtain a passivated wafer, and the structure is as shown in Figure 1 .

[0079] (8) Apply voltage to the conductive layer 5 for electrical injection.

[0080] Perform Sinton test on the passivated wafer prepared in this embodiment, and the implied open-circuit voltage is 717 mV, and the single-side saturation current density is 12.6 fA / cm 2 .

[0081] Example 3

[0082] (1) Take P-type textured silicon wafer with thickness of 170 μm and resistivity of 1 Ω-cm.

[0083] (2) Transfer the silicon wafer to a diffusion furnace for double-side phosphorus diffusion to prepare a phosphorus emitter, and the sheet resistance is 150-200 Ω / sq.

[0084] (3) After standard RCA cleaning, place the silicon wafer in a PECVD chamber, and deposit a nanometer silicon oxide layer with a thickness of 1.5 nm on the phosphorus emitter using N2O plasma.

[0085] (4) Deposit a doped carbon and nitrogen amorphous silicon layer with a thickness of 10 nm on the nanometer silicon oxide layer, and the carbon content in the doped carbon and nitrogen amorphous silicon layer is 15 at%, and the nitrogen content is 15 at%.

[0086] (5) Put the sample into the annealing furnace for high-temperature annealing at 930℃ for 30min, and the protective atmosphere is nitrogen. The carbon and nitrogen doped amorphous silicon layer is converted into a doped polysilicon layer.

[0087] (6) Etch the doped crystalline silicon layer clean and clean the surface of the substrate.

[0088] (7) Put the cleaned sample into the ALD for double-sided deposition of a 10nm aluminum oxide layer.

[0089] (8) Put the sample into the PECVD for double-sided deposition of a 60nm silicon nitride layer to obtain a passivated wafer.

[0090] The passivated wafer prepared in this embodiment is subjected to Sinton test, and the implied open circuit voltage is 717mV, and the single-sided saturation current density is 12.5fA / cm 2 .

[0091] Example 4

[0092] (1) Take a P-type textured silicon wafer with a thickness of 170μm and a resistivity of 1Ω·cm.

[0093] (2) Transfer the silicon wafer to the diffusion furnace for double-sided phosphorus diffusion to prepare a phosphorus emitter with a sheet resistance of 150-200Ω / sq.

[0094] (3) After standard RCA cleaning, place the silicon wafer in the PECVD chamber, and deposit a 1.5nm thick nanometer silicon oxide layer on the phosphorus emitter using N2O plasma.

[0095] (4) Deposit a 10nm thick carbon and nitrogen doped amorphous silicon layer on the nanometer silicon oxide layer, and the carbon content in the carbon and nitrogen doped amorphous silicon layer is 15at%, and the nitrogen content is 15at%.

[0096] (5) Put the sample into the annealing furnace for high-temperature annealing at 930℃ for 30min, and the protective atmosphere is nitrogen. The carbon and nitrogen doped amorphous silicon layer is converted into a doped polysilicon layer.

[0097] (6) Put the cleaned sample into the ALD for double-sided deposition of a 10nm aluminum oxide layer.

[0098] (7) Put the sample into the PECVD for double-sided deposition of a 60nm silicon nitride layer to obtain a passivated wafer.

[0099] (8) Transfer the sample to the tube furnace for hydrogenation post-treatment under a nitrogen atmosphere, and anneal at 430℃ for 30min.

[0100] The passivated wafer prepared in this embodiment is subjected to Sinton test, and the implied open circuit voltage is 718mV, and the single-sided saturation current density is 11.6fA / cm2 .

[0101] Example 5

[0102] (1) A P-type textured silicon wafer with a thickness of 170 μm and a resistivity of 1 Ω-cm was taken.

[0103] (2) The silicon wafer was transferred to a diffusion furnace for double-side phosphorus diffusion to prepare a phosphorus emitter with a sheet resistance of 150-200 Ω / sq.

[0104] (3) After standard RCA cleaning, the silicon wafer was placed in a PECVD chamber, and a nanometer silicon oxide layer with a thickness of 1 nm was deposited on the phosphorus emitter using N2O plasma.

[0105] (4) The electrical injection area and the doped area of the phosphorus emitter were selected, and a carbon and nitrogen doped amorphous silicon layer with a thickness of 10 nm was prepared on the doped area, wherein the content of carbon element was 15 at%, and the content of nitrogen element was 15 at%; a TCO conductive layer was prepared on the electrical injection area.

[0106] (5) The sample was placed in an annealing furnace for high-temperature annealing at 900℃ for 30 min, and the protective atmosphere was nitrogen, and the carbon and nitrogen doped amorphous silicon layer was converted into a doped polysilicon layer.

[0107] (6) The cleaned sample was placed in an ALD, and a 10 nm aluminum oxide layer was deposited on both sides.

[0108] (7) The sample was placed in a PECVD, and a 60 nm silicon nitride layer was deposited on both sides to obtain a passivated wafer.

[0109] (8) The conductive layer was subjected to electrical injection under the irradiation of a xenon lamp.

[0110] The passivated wafer prepared in this example was subjected to Sinton test, and the implied open-circuit voltage was 720 mV, and the single-side saturation current density was 10.2 fA / cm 2 .

[0111] Example 6

[0112] (1) A P-type textured silicon wafer with a thickness of 170 μm and a resistivity of 1 Ω-cm was taken.

[0113] (2) The silicon wafer was transferred to a diffusion furnace for double-side phosphorus diffusion to prepare a phosphorus emitter with a sheet resistance of 150-200 Ω / sq.

[0114] (3) After standard RCA cleaning, the silicon wafer was placed in a PECVD chamber, and a nanometer silicon oxide layer with a thickness of 1 nm was deposited on the phosphorus emitter using N2O plasma.

[0115] (4) Select the phosphorus emitter of the electric injection area and the doped area, prepare a carbon and nitrogen doped amorphous silicon layer with a thickness of 10 nm on the doped area, wherein the carbon content is 15 at%, and the nitrogen content is 15 at%; prepare a phosphorus-doped amorphous silicon film as a conductive layer on the electric injection area.

[0116] (5) Put the sample into the annealing furnace for high-temperature annealing at 900°C for 30 min, the protective atmosphere is nitrogen, the carbon and nitrogen doped amorphous silicon layer is converted into a doped polysilicon layer, and the phosphorus-doped amorphous silicon is converted into a phosphorus-doped polysilicon.

[0117] (6) Put the cleaned sample into the ALD, and deposit 10 nm of aluminum oxide layer on both sides.

[0118] (7) Put the sample into the PECVD, and deposit 60 nm of silicon nitride layer on both sides to obtain a passivation sheet.

[0119] (8) Apply voltage to the conductive layer for electric injection.

[0120] The passivation sheet prepared in this embodiment is tested by Sinton, and the implied open circuit voltage is 719 mV, and the single-side saturation current density is 11.0 fA / cm 2 .

[0121] Comparative Example 1

[0122] (1) Take a P-type textured silicon wafer with a thickness of 170 μm and a resistivity of 1 Ω·cm.

[0123] (2) Transfer the silicon wafer to the diffusion furnace for double-sided phosphorus diffusion to prepare a phosphorus emitter, and the sheet resistance is 150-200 Ω / sq.

[0124] (3) After standard RCA cleaning, place the silicon wafer in the PECVD chamber to deposit a 60 nm thick silicon nitride layer on the phosphorus emitter to obtain a passivation sheet.

[0125] The passivation sheet prepared in this comparative example is tested by Sinton, and the implied open circuit voltage is 694 mV, and the single-side saturation current density is 40.8 fA / cm 2 .

[0126] Comparative Example 2

[0127] (1) Take a P-type textured silicon wafer 1 with a thickness of 170 μm and a resistivity of 1 Ω·cm.

[0128] (2) Transfer the silicon wafer 1 to the diffusion furnace for double-sided phosphorus diffusion to prepare a phosphorus emitter 2, and the sheet resistance is 150-200 Ω / sq.

[0129] (3) After standard RCA cleaning, place the silicon wafer 1 in the PECVD chamber to deposit a 2 nm thick nano-silicon oxide layer 3 on the phosphorus emitter 2.

[0130] (4) Depositing a silicon nitride layer 7 with a thickness of 60 nm on the nano-silicon oxide layer 3 to obtain a passivated wafer, the structure of which is shown in Figure 2 .

[0131] The passivated wafer prepared in the present comparative example was subjected to Sinton test, and the implied open circuit voltage was 699 mV, and the single-side saturation current density was 29.3 fA / cm 2 .

[0132] The properties of the samples prepared in Examples 1-6 and Comparative Examples 1-2 are shown in Table 1 below, and the results prove that excellent passivation effect can be achieved on the phosphorus emitter by using the present technology, the surface saturation current density is reduced, and the cell performance is improved.

[0133] Table 1: Comparison of passivation properties of samples of examples and comparative examples

[0134]

[0135]

[0136] Example 7

[0137] (1) A P-type textured silicon wafer 1 with a thickness of 170 μm and a resistivity of 1 Ω-cm was taken.

[0138] (2) The silicon wafer 1 was transferred into a diffusion furnace for phosphorus diffusion to prepare a phosphorus emitter 2, and the sheet resistance was 150-200 Ω / sq.

[0139] (3) The back surface of the silicon wafer 1 was polished, and was transferred into a PECVD for deposition of a tunnel oxide layer 8 and a boron-doped amorphous silicon layer on the back surface.

[0140] (4) The silicon wafer 1 was placed in a PECVD chamber, and a nano-silicon oxide layer 3 with a thickness of 2 nm was deposited on the phosphorus emitter 2 by using N2O plasma.

[0141] (5) The electrical injection area and the doped area of the phosphorus emitter 2 were selected, a doped amorphous silicon layer was deposited on the doped area, the doped amorphous silicon layer was composed of a 4 nm nitrogen-doped amorphous silicon film, and the content of nitrogen element in the nitrogen-doped amorphous silicon film was 15 at%; a phosphorus-doped amorphous silicon film was deposited on the electrical injection area as a conductive layer 5.

[0142] (6) The sample was placed in an annealing furnace for high-temperature annealing at 920 ℃ for 30 min, and the protective atmosphere was nitrogen, the doped amorphous silicon layer was converted into a doped polysilicon layer 4, the phosphorus-doped amorphous silicon was converted into a phosphorus-doped polysilicon, and the boron-doped amorphous silicon layer was converted into a boron-doped polysilicon layer 9.

[0143] (7) The cleaned sample was placed in an ALD, and an aluminum oxide layer 6 was deposited on both sides.

[0144] (8) The sample is placed in the PECVD, and a silicon nitride layer 7 is deposited on both sides to obtain a passivated wafer.

[0145] (9) The conductive layer 5 is subjected to voltage injection under xenon lamp irradiation.

[0146] (10) The passivated wafer is subjected to screen printing of electrode grid lines, in which the positive electrode grid lines are printed on the conductive layer 5, pre-sintering, and then LECO forms electrode contact.

[0147] (11) The sample is transferred to a tube furnace, and post-treatment is performed under a mixed atmosphere of nitrogen and hydrogen, and annealing is performed at 450℃ for 30 min to obtain a TOPCon cell, the structure of which is shown in Figure 3 .

[0148] The performance of the cell prepared in this embodiment is tested, and the surface saturation current density is 10.5 fA / cm 2 , the open circuit voltage is 719 mV, the contact resistivity of the electrode injection area is about 1 mΩ·cm 2 , and the cell efficiency is 25.2%.

[0149] The performance of the cell prepared in this embodiment is tested, and the surface saturation current density is 11.7 fA / cm 2 , the open circuit voltage is 715 mV, the contact resistivity of the electrode is about 1 mΩ·cm 2 , and the cell efficiency is 24.9%.

[0150] Embodiment 8

[0151] The difference between this embodiment and embodiment 1 is that the doped amorphous silicon layer prepared in step (5) is composed of three layers of nitrogen-doped amorphous silicon films with a thickness of 1 nm, and the carbon content in the three layers of nitrogen-doped amorphous silicon films is 15 at%, 20 at% and 25 at% respectively, and the higher the carbon content in the nitrogen-doped amorphous silicon film closer to the nano-silicon oxide layer. The other steps and processes are the same.

[0152] The performance of the cell prepared in this embodiment is tested, and the surface saturation current density is 10.9 fA / cm 2 , the open circuit voltage is 719 mV, the contact resistivity of the electrode is about 1 mΩ·cm 2 , and the cell efficiency is 25.1%.

[0153] Embodiment 9

[0154] (1) A P-type textured silicon wafer with a thickness of 170 μm and a resistivity of 1 Ω·cm is taken.

[0155] (2) The silicon wafer is transferred to a diffusion furnace for phosphorus diffusion to prepare a phosphorus emitter with a sheet resistance of 150-200 Ω / sq.

[0156] (3) Polishing the back surface of the silicon wafer and transferring into the PECVD to deposit a tunnel oxide layer and a boron-doped amorphous silicon layer on the back surface.

[0157] (4) Placing the silicon wafer into the PECVD chamber, and depositing a 2-nm-thick nanometer silicon oxide layer on the phosphorus emitter by N2O plasma.

[0158] (5) Selecting the electrical injection area and the doped area of the phosphorus emitter, depositing a doped amorphous silicon layer on the doped area, and preparing an ITO conductive layer on the electrical injection area, wherein the doped amorphous silicon layer is composed of a 10-nm-thick carbon and nitrogen-doped amorphous silicon film, the content of carbon in the carbon and nitrogen-doped amorphous silicon film is 15 at%, and the content of nitrogen is 15 at%.

[0159] (6) Placing the sample into an annealing furnace for high-temperature annealing at 930℃ for 30 min, and using nitrogen as the protective atmosphere, so that the doped amorphous silicon layer is converted into a doped polysilicon layer, and the boron-doped amorphous silicon layer is converted into a boron-doped polysilicon layer.

[0160] (7) Etching the doped polysilicon layer clean and cleaning the surface of the substrate.

[0161] (8) Placing the cleaned sample into an ALD to deposit an aluminum oxide layer on both surfaces.

[0162] (9) Placing the sample into a PECVD to deposit a silicon nitride layer on both surfaces, so as to obtain a passivated wafer.

[0163] (10) Carrying out electrical injection by applying voltage to the conductive layer.

[0164] (11) Carrying out screen printing of electrode grid lines on the passivated wafer, wherein the electrode grid lines on the front surface are printed on the electrical injection area of the phosphorus emitter 2, pre-sintering is performed, and then LECO is used to form electrode contact.

[0165] (12) Transferring the sample to a tube furnace, and performing hydrogenation post-processing in a mixed atmosphere of nitrogen and hydrogen, and annealing at 450℃ for 30 min, so as to obtain a TOPCon cell.

[0166] The performance of the cell prepared in this embodiment is tested, and the surface saturation current density is 11.7 fA / cm 2 , the open-circuit voltage is 715 mV, the contact resistance of the electrode is about 1 mΩ·cm 2 , and the cell efficiency is 24.9%.

[0167] Comparative Example 3

[0168] (1) Taking a P-type textured silicon wafer 1 with a thickness of 170 μm and a resistivity of 1 Ω·cm.

[0169] (2) The silicon wafer 1 is transferred to a diffusion furnace for phosphorus diffusion to prepare a phosphorus emitter 2 with a sheet resistance of 150-200 Ω / sq.

[0170] (3) The back surface of the silicon wafer 1 is polished and transferred into a PECVD for deposition of a tunnel oxide layer 8 and a boron-doped amorphous silicon layer on the back surface.

[0171] (4) The sample is placed in an annealing furnace for high-temperature annealing at 920℃ for 30 min in a nitrogen atmosphere, and the boron-doped amorphous silicon layer is converted into a boron-doped polysilicon layer 8.

[0172] (5) The cleaned sample is placed in an ALD for deposition of an aluminum oxide layer 6 on both sides.

[0173] (6) The sample is placed in a PECVD for deposition of a silicon nitride layer 7 on both sides to obtain a passivated wafer.

[0174] (7) The passivated wafer is subjected to screen printing of electrode grid lines, pre-sintering, and then LECO to form electrode contacts.

[0175] (8) The sample is transferred to a tube furnace for hydrogenation post-processing in a mixed atmosphere of nitrogen and hydrogen, annealing at 450℃ for 30 min to obtain a TOPCon cell, which has a structure as shown in Figure 4 .

[0176] The performance of the cell prepared in the present comparative example is tested, and the surface saturation current density of the phosphorus emitter is 40.8 fA / cm 2 , the open-circuit voltage is 694 mV, the contact resistivity of the electrode is about 1 mΩ·cm 2 , and the cell efficiency is 24.2%.

[0177] Comparative Example 4

[0178] (1) A P-type textured silicon wafer with a thickness of 170 μm and a resistivity of 1 Ω·cm is taken.

[0179] (2) The silicon wafer is transferred to a diffusion furnace for phosphorus diffusion to prepare a phosphorus emitter with a sheet resistance of 150-200 Ω / sq.

[0180] (3) The back surface of the silicon wafer is polished and transferred into a PECVD for deposition of a tunnel oxide layer and a boron-doped amorphous silicon layer on the back surface.

[0181] (4) The silicon wafer is placed in a PECVD chamber, and a nanometer silicon oxide layer with a thickness of 2 nm is deposited on the entire area of the phosphorus emitter surface using N2O plasma.

[0182] (5) A doped amorphous silicon layer is deposited on the nanometer silicon oxide layer, and the doped amorphous silicon layer is composed of a 4 nm nitrogen-doped amorphous silicon film, and the nitrogen content in the nitrogen-doped amorphous silicon film is 15 at%.

[0183] (6) Put the sample into the annealing furnace for high-temperature annealing at 920℃ for 30min, the protective atmosphere is nitrogen, the doped amorphous silicon layer is converted into a doped polysilicon layer, and the boron-doped amorphous silicon layer is converted into a boron-doped polysilicon layer.

[0184] (7) Put the cleaned sample into the ALD, and deposit an aluminum oxide layer on both sides.

[0185] (8) Put the sample into the PECVD, and deposit a silicon nitride layer on both sides to obtain a passivation sheet.

[0186] (9) Screen-print the passivation sheet with electrode grid lines, pre-sinter, and then form an electrode contact by LECO.

[0187] (10) Transfer the sample to the tube furnace, and perform hydrogenation post-processing in a mixed atmosphere of nitrogen and hydrogen, annealing at 450℃ for 30min to obtain a TOPCon cell.

[0188] The performance of the cell prepared in the present comparative example is tested, and the surface saturation current density of the phosphorus emitter is 13.5A / cm 2 , the open-circuit voltage is 713mV, the contact resistivity of the electrode is ~2mΩ·cm 2 , and the cell efficiency is 24.5%.

[0189] The performance of the P-type TOPCon cell prepared in Examples 7-9 and Comparative Examples 3-4 is shown in Table 2 below, and the results prove that the method of the present application can achieve excellent passivation effect on the phosphorus emitter, reduce the surface saturation current density, and improve the contact resistivity, thereby improving the cell efficiency.

[0190] Table 2 Comparison of cell performance of examples and comparative examples

[0191] Sample J 0,s (fA / cm 2 )]]> iV oc (mV) ρ c (mΩ·cm 2 )]]> PEC Example 7 10.5 719 ～1 25.2％ Example 8 10.9 719 ～1 25.1％ Example 9 11.7 715 ～1 24.9％ Comparative Example 3 40.8 694 ～1 24.2％ Comparative Example 4 13.5 713 ～2 24.5％

[0192] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A phosphorus emitter passivation structure, characterized in that, The device includes a phosphorus emitter, the phosphorus emitter being composed of silicon, phosphorus, hydrogen, carbon and / or nitrogen, the surface of the phosphorus emitter being provided with a nano-silicon oxide layer, the phosphorus emitter including an electrical injection region and a doped region, a conductive layer being provided at the corresponding position of the electrical injection region, the conductive layer being used to connect to a metal electrode, a passivation antireflection layer being provided at the corresponding position of the doped region, and the carbon and / or nitrogen concentration of the doped region being higher than the carbon and / or nitrogen concentration of the electrical injection region.

2. The phosphorus emitter passivation structure according to claim 1, characterized in that, The carbon and / or nitrogen concentration in the doped region is higher than 1 × 10⁻⁶. 19 cm -3 Hydrogen concentration higher than 1×10 19 cm -3 The carbon and / or nitrogen concentration in the electro-injection region is less than 1 × 10⁻⁶. 17 cm -3 .

3. The phosphorus emitter passivation structure according to claim 2, characterized in that, In the doped region, the carbon and / or nitrogen concentration decreases with distance from the surface, while the carbon and / or nitrogen concentration near the surface of the doped region is higher than 1 × 10⁻⁶. 20 cm -3 .

4. The phosphorus emitter passivation structure according to claim 1, characterized in that, The thickness of the phosphorus emitter is 100–2000 nm.

5. The phosphorus emitter passivation structure according to claim 1, characterized in that, The thickness of the nano-silicon oxide layer is 1–5 nm, and the absorption coefficient k of the nano-silicon oxide layer at wavelengths above 500 nm is less than 0.1 cm. -1 .

6. The phosphorus emitter passivation structure according to claim 1, characterized in that, The conductive layer is made of phosphorus-doped polycrystalline silicon or transparent conductive oxide.

7. The phosphorus emitter passivation structure according to claim 1, characterized in that, The passivation antireflection layer consists of one or more thin films of aluminum oxide, silicon nitride, and silicon oxide.

8. The phosphorus emitter passivation structure according to any one of claims 1-7, characterized in that, A doped polycrystalline silicon layer is provided at the corresponding position of the doped region. The doped polycrystalline silicon layer is located between the nano-silicon oxide layer and the passivation antireflection layer. The doped polycrystalline silicon layer is composed of one or more polycrystalline silicon thin films containing carbon and / or nitrogen.

9. The phosphorus emitter passivation structure according to claim 8, characterized in that, The carbon and / or nitrogen content of each polycrystalline silicon thin film in the doped polycrystalline silicon layer is 1 at% to 50 at%.

10. The phosphorus emitter passivation structure according to claim 8, characterized in that, The thickness of the doped polycrystalline silicon layer is 1–50 nm, the refractive index is 1.5–3.5, and the extinction coefficient is less than or equal to 1.

11. The phosphorus emitter passivation structure according to claim 8, characterized in that, The hydrogen concentration in the doped polycrystalline silicon layer is higher than 1×10⁻⁶. 20 cm -3 .

12. A method for preparing a phosphorus emitter passivation structure as described in any one of claims 1-7, characterized in that, Includes the following steps: Prepare a P-type silicon wafer and fabricate a phosphorus emitter on its surface; A nano-silicon oxide layer was prepared on the surface of a phosphorus emitter; Select the injection region and doping region of the phosphorus emitter, prepare a doped amorphous silicon layer doped with carbon and / or nitrogen elements on the doped region, and prepare a conductive layer on the injection region. High-temperature annealing is performed in an inert gas atmosphere to allow carbon and / or nitrogen atoms in the doped amorphous silicon layer to diffuse into the doped region of the phosphorus emitter, thus transforming the doped amorphous silicon layer into a doped polycrystalline silicon layer. Etching removes the doped polysilicon layer; A passivation and antireflection layer is prepared on the substrate surface, and then the passivation and antireflection layer at the corresponding part of the conductive layer is removed; The external electrode is applied to the conductive layer for electro-injection under dark field conditions or under strong light irradiation.

13. A method for preparing a phosphorus emitter passivation structure as described in any one of claims 8-11, characterized in that, Includes the following steps: Prepare a P-type silicon wafer and fabricate a phosphorus emitter on its surface; A nano-silicon oxide layer was prepared on the surface of a phosphorus emitter; Select the injection region and doping region of the phosphorus emitter, prepare a doped amorphous silicon layer doped with carbon and / or nitrogen elements on the doped region, and prepare a conductive layer on the injection region. High-temperature annealing is performed in an inert gas atmosphere to allow carbon and / or nitrogen atoms in the doped amorphous silicon layer to diffuse into the doped region of the phosphorus emitter, thus transforming the doped amorphous silicon layer into a doped polycrystalline silicon layer. A passivation and antireflection layer is prepared on the substrate surface, and then the passivation and antireflection layer at the corresponding part of the conductive layer is removed; The external electrode is applied to the conductive layer for electro-injection under dark field conditions or under strong light irradiation.

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