SOI substrate structure, PDSOI device and preparation method thereof

Abstract

The embodiment of the invention provides an SOI substrate structure and a PDSOI device, and the method comprises the steps: forming a first boss at a first preset position of a first surface of top-layer silicon, so as to enable the thickness of the top-layer silicon at the first preset position to be larger than the thickness of the top-layer silicon at other parts; when a semiconductor device is subsequently formed on the second surface of the top layer silicon, a grid electrode of the semiconductor device is positioned right above the first boss; the first boss is communicated with the body contact region, so that carriers accumulated in the well region of the PDSOI device during working can be released through the body contact region, and the floating body effect of the PDSOI device can be effectively inhibited.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an SOI substrate structure, a PDSOI device and a preparation method thereof. Background Art

[0002] As device feature sizes continue to shrink, Silicon-On-Insulator (SOI) technology has emerged. SOI technology is an advanced semiconductor manufacturing technology that can effectively reduce parasitic capacitance and leakage current, thereby improving device performance and has great development potential.

[0003] The conventional SOI substrate structure includes bottom silicon, buried oxide layer and top silicon from bottom to top. Due to the difference in the thickness of the top silicon film and the thickness of the depletion layer when the device is working, SOI devices can be divided into partially depleted SOI devices (PDSOI, Partially Depleted Silicon-On-Insulator) and fully depleted SOI devices (FDSOI, Fully Depleted Silicon-On-Insulator). Among them, the top silicon film thickness of the PDSOI device is relatively large. When the device works in the saturation region, the depletion layer thickness is less than the top silicon film thickness. There are some undepleted areas in the well region, and this part of the area is not connected to the voltage and is in an electrically floating state, resulting in negative floating body effects such as warping effect and parasitic bipolar transistor effect. One way to solve this problem is to reduce the thickness of the top silicon so that it is in a fully depleted state when working. This method results in an FDSOI device, but the cost of FDSOI devices is high and the threshold voltage is difficult to control.

[0004] Therefore, how to effectively suppress the floating body effect of PDSOI devices has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The embodiment of the present invention provides an SOI substrate structure, a PDSOI device and a preparation method thereof, so as to suppress the floating body effect of the PDSOI device.

[0006] According to a first aspect of the present invention, there is provided an SOI substrate structure, comprising a top silicon layer, a buried oxide layer and a bottom silicon layer arranged in sequence from top to bottom; wherein:

[0007] A first boss is formed at a first preset position on the first surface of the top silicon layer;

[0008] The buried oxide layer is in contact with the first surface of the top silicon layer, and the thickness of the first boss is smaller than the thickness of the buried oxide layer;

[0009] The bottom silicon is bonded to the buried oxide layer;

[0010] The second surface of the top silicon layer opposite to the first surface is used to form a semiconductor device, and the gate of the semiconductor device is located directly above the first boss.

[0011] Optionally, the thickness of the top silicon layer is 10 nm to 1000 nm.

[0012] Optionally, the buried oxide layer has a thickness of 10 nm to 5000 nm.

[0013] Optionally, an alignment groove is further formed at a second preset position of the top silicon layer, and the alignment groove penetrates the top silicon layer; and the buried oxide layer is filled in the alignment groove.

[0014] According to a second aspect of the present invention, there is provided a method for preparing an SOI substrate structure, for forming the SOI substrate structure according to the first aspect, the method comprising:

[0015] Providing a top silicon layer, wherein a first boss is formed at a first preset position on a first surface of the top silicon layer;

[0016] forming a buried oxide layer on the first surface of the top silicon layer; wherein the thickness of the first protrusion is less than the thickness of the buried oxide layer;

[0017] An underlying silicon layer is provided and bonded to the buried oxide layer.

[0018] Optionally, before forming the buried oxide layer, the method further comprises:

[0019] An alignment groove is formed at a second predetermined position on the first surface of the top silicon layer.

[0020] Optionally, forming a buried oxide layer on the first surface of the top silicon layer includes:

[0021] Depositing an oxide layer on the first surface of the top silicon; the oxide layer filling the alignment groove and covering the first surface of the top silicon and the first boss;

[0022] The oxide layer is subjected to a surface planarization process to form a buried oxide layer.

[0023] Optionally, after bonding the bottom silicon layer to the buried oxide layer, the method further comprises:

[0024] The second surface of the top silicon layer is thinned to make the thickness of the top silicon layer reach a preset value and expose the buried oxide layer in the alignment groove.

[0025] According to a third aspect of the present invention, a PDSOI device is provided, comprising the SOI substrate structure provided in the first aspect, a semiconductor device formed on the SOI substrate structure, and a body contact region; wherein:

[0026] The semiconductor device is formed on a second surface of the top silicon layer opposite to the first surface, and a gate of the semiconductor device is located directly above the first protrusion;

[0027] The body contact region is formed in a third preset position of the SOI substrate structure and is located at the periphery of the semiconductor device; the first boss is connected to the body contact region.

[0028] Optionally, a width of the first boss is less than or equal to a length of a channel of the semiconductor device.

[0029] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0030] The SOI substrate structure and PDSOI device provided by the technical solution of the present invention form a first boss at a first preset position on the first surface of the top silicon so that the thickness of the top silicon at this position is greater than the thickness of the top silicon in other parts; when a semiconductor device is subsequently formed on the second surface of the top silicon, the gate of the semiconductor device is located directly above the first boss; the first boss is connected to the body contact area, so that the carriers accumulated in the well area of ​​the PDSOI device during operation can be released through the body contact area, thereby effectively suppressing the floating body effect of the PDSOI device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A-Figure 1C Top views of NMOS structures using body contact to suppress floating body effect provided in three implementations respectively;

[0032] Figure 1D for Figure 1A The top view of the actual structure of the NMOS structure prepared by the actual process;

[0033] Figure 2 A schematic structural diagram of an SOI substrate structure provided in one embodiment of the present invention;

[0034] Figure 3 A flow chart of a method for preparing an SOI substrate structure provided in one embodiment of the present invention;

[0035] Figure 4A-4G A schematic structural diagram corresponding to each step of a method for preparing an SOI substrate structure provided in an embodiment of the present invention;

[0036] Figure 5A schematic diagram of a PDSOI device formed by using an SOI substrate structure provided by an embodiment of the present invention;

[0037] Figure 6 A top view of a PDSOI device provided by an embodiment of the present invention;

[0038] Fig. 7A for Figure 6 The cross-section along the A1-A2 direction;

[0039] Figure 7B for Figure 6 The cross-section along the B1-B2 direction;

[0040] Figure 7C for Figure 6 Cross-sectional view along the C1-C2 direction.

[0041] Figure 1A-Figure 1C Description of the labels in:

[0042] 10-body contact area;

[0043] 21- source area;

[0044] 22-drain area;

[0045] 23- Gate.

[0046] Figure 2-7C Description of the labels in:

[0047] 100-SOI substrate structure;

[0048] 110 - bottom silicon;

[0049] 121- oxide layer;

[0050] 120- buried oxygen layer;

[0051] 130-top silicon;

[0052] 131- first boss;

[0053] 132-alignment groove;

[0054] 141-gate;

[0055] 142-Source area;

[0056] 143-drain area;

[0057] 150-heavily doped region;

[0058] 160-body contact area;

[0059] 170-STI structure;

[0060] 180-well region. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] As described in the background technology, the technical solution of the present invention aims to solve the problem of suppressing the floating body effect of PDSOI devices. Before proposing the technical solution of the embodiment of the present invention, the applicant has studied various possible solutions to suppress the floating body effect of PDSOI devices, which will be described below with reference to the accompanying drawings.

[0063] Figure 1A-Figure 1C The top views of NMOS structures using body contact to suppress floating body effect are provided in three implementation modes respectively; wherein, Figure 1A It is a top view of the T-gate PDSOI device structure; Figure 1B It is a top view of the H-gate PDSOI device structure; Figure 1C A top view of a BTS-type gate PDSOI device structure.

[0064] Please combine Figure 1A-Figure 1C In order to suppress the floating body effect of PDSOI devices, the applicant has studied the structures of three body contact methods, that is, all three methods connect the well region to a fixed potential through the body contact region to release the accumulated carriers (such as holes). Figure 1A-Figure 1C The PDSOI devices in the embodiment respectively include a source region 21, a drain region 22, a gate 23 and a body contact region 10, the difference being the structure of the gate 23 and the position of the body contact region 10; wherein, Figure 1A The gate in is a T-type gate. Figure 1B The gate in is an H-type gate. Figure 1CThe gate in the circuit is a BTS (Body-Tied-to-Source) type gate. All three structures can connect the well region to control the change of body potential.

[0065] After in-depth research on the above three methods, the applicant found that the above three methods have at least the following problems:

[0066] 1) For Figure 1A For the T-type gate structure in the embodiment, the source and drain regions on both sides of the gate will have arc-shaped corners in the actual process (such as Figure 1D The body contact region 10 only exists at the top of the T-type gate structure, which causes asymmetry, resulting in poor uniformity of the device and edge effects. In addition, since the T-type gate has a lateral gate portion (such as Figure 1D The gate portion does not generate a channel, but forms a parasitic capacitor with the oxide layer and the active region below, thereby increasing the parasitic effect.

[0067] 2) For Figure 1B The H-type gate structure also has a lateral gate portion, which will also cause an increase in parasitic effects.

[0068] 3) For Figure 1C As for the BTS-type gate structure, due to its asymmetric structure, the source region and the drain region cannot be interchanged, resulting in inflexible circuit design.

[0069] In view of this, an embodiment of the present invention provides an SOI substrate structure, a PDSOI device and a preparation method thereof, wherein the SOI substrate structure includes a top silicon, a buried oxide layer and a bottom silicon arranged in sequence from top to bottom; a first boss is formed at a first preset position on the first surface of the top silicon, so that the thickness of the top silicon at this position is greater than the thickness of the top silicon in other parts; the buried oxide layer is in contact with the first surface of the top silicon, and the thickness of the first boss is less than the thickness of the buried oxide layer; the bottom silicon is bonded to the buried oxide layer; the second surface of the top silicon opposite to the first surface is used to form a semiconductor device, and the gate of the semiconductor device is located directly above the first boss.

[0070] The SOI substrate structure and PDSOI device provided by the technical solution of the present invention form a first boss at a first preset position on the first surface of the top silicon so that the thickness of the top silicon at this position is greater than the thickness of the top silicon in other parts; when a semiconductor device is subsequently formed on the second surface of the top silicon, the gate of the semiconductor device is located directly above the first boss; the first boss is connected to the body contact area, so that the carriers accumulated in the well area of ​​the PDSOI device during operation can be released through the body contact area, thereby effectively suppressing the floating body effect of the PDSOI device.

[0071] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the technical scheme of the present invention is described in detail below with reference to the accompanying drawings.

[0072] Figure 2 FIG. 1 is a schematic diagram of a SOI substrate structure provided in one embodiment of the present invention. Figure 2 As shown, the SOI substrate structure 100 provided in the embodiment of the present invention includes a top silicon layer 130, a buried oxide layer 120 and a bottom silicon layer 110 arranged in sequence from top to bottom; wherein:

[0073] A first boss 131 is formed at a first preset position on the first surface of the top silicon layer 130 , so that the thickness of the top silicon layer at this position is greater than the thickness of the top silicon layer at other portions.

[0074] The buried oxide layer 120 is formed on the first surface of the top silicon layer 130 ; and a thickness d1 of the first protrusion 131 is smaller than a thickness d2 of the buried oxide layer 120 .

[0075] The bottom silicon layer 110 is bonded to the buried oxide layer 120 .

[0076] The second surface of the top silicon 130 opposite to the first surface is used to form a semiconductor device, and the gate of the semiconductor device is located directly above the first boss 131. The first preset position can be understood as a position directly opposite to the gate of the semiconductor device formed subsequently.

[0077] In this embodiment, the bottom silicon layer 110 is bonded to a side of the buried oxide layer 120 away from the top silicon layer 130 .

[0078] The SOI substrate structure provided by an embodiment of the present invention forms a first boss at a first preset position on the first surface of the top silicon so that the thickness of the top silicon at this position is greater than the thickness of the top silicon in other parts; when a semiconductor device is subsequently formed on the second surface of the top silicon, the gate of the semiconductor device is located directly above the first boss; by connecting the first boss to the body contact area, the carriers accumulated in the well area of ​​the PDSOI device during operation can be released through the body contact area, thereby effectively suppressing the floating body effect of the PDSOI device.

[0079] Furthermore, the thickness d1 of the first boss 131 can be set according to the thickness d2 of the buried oxide layer 120, as long as it does not exceed the thickness of the buried oxide layer 120 and can ensure that the first boss 131 can be connected to the body contact area; that is, the thickness d1 of the first boss 131 is greater than 0 and less than the thickness d2 of the buried oxide layer 120; if the thickness d1 of the first boss 131 is greater than the thickness d2 of the buried oxide layer 120, the isolation effect of the buried oxide layer 120 will be lost.

[0080] Furthermore, the width b of the first boss 131 is less than or equal to the length of the channel of the semiconductor device formed subsequently; that is, the width b of the first boss 131 is greater than 0 and does not exceed the length of the channel of the semiconductor device formed subsequently. This is because if the width of the first boss 131 is too narrow, the process difficulty of etching to form the first boss will increase. If the width of the first boss 131 is too wide to be wider than the channel length, the area directly above the first boss 131 cannot be completely covered by the gate, and there is a risk of a decrease in the breakdown voltage of the source, drain and well regions; in addition, if the width of the first boss is wide enough to include the source and drain regions, then the traditional SOI device structure is obtained at this time, the structural characteristics of the PDSOI device are lost, and the PN junction parasitic capacitance increases.

[0081] As an example, the thickness of the top silicon 130 is 10nm to 1000nm; this thickness range ensures that the depletion layer depth after ion implantation is less than the thickness of the top silicon layer, so that the device exhibits PDSOI device characteristics and avoids the problem of difficult-to-control threshold voltage caused by the top silicon being too thin to form an FDSOI device.

[0082] Of course, it should be appreciated that the thickness of the top silicon layer 130 in the embodiment of the present invention is not limited to the aforementioned range, and those skilled in the art may select the thickness of the top silicon layer according to actual conditions.

[0083] As an example, the thickness of the buried oxide layer 120 is 10 nm to 5000 nm. Of course, it should be appreciated that the thickness of the buried oxide layer 120 in the embodiment of the present invention is not limited to the aforementioned range, and those skilled in the art can select the thickness of the buried oxide layer according to actual conditions.

[0084] As a preferred embodiment, an alignment groove is further formed at the second preset position of the top silicon 130, and the alignment groove penetrates the first surface and the second surface of the top silicon; and the buried oxide layer is filled in the alignment groove, such as Figure 2 As shown in the dotted box on the left side of the figure. The buried oxide layer filled in the alignment groove can be used as an alignment mark, so that in the subsequent process of preparing semiconductor devices, the photolithography machine can accurately locate the position of the active area and the shallow trench isolation structure (STI) through the alignment mark, and perform exposure and development to etch the STI groove; in the subsequent process of depositing the gate, the active area and STI are used as alignment references to ensure that the gate is prepared directly above the first boss 131. By setting an alignment groove on the top silicon 130, this solution can improve the accuracy of the photolithography machine during exposure and development, and avoid the problem of inaccurate positioning during exposure, compared with no alignment groove.

[0085] In this embodiment, the second preset position is a position on the top silicon layer 130 that does not overlap with the first preset position. Preferably, the second preset position may be a region on the top silicon layer 130 that is away from a region where semiconductor devices are formed.

[0086] Those skilled in the art can understand that, in practical applications, the second preset position can also be a position area between dies (crystal grains) of semiconductor devices formed on a wafer.

[0087] Please continue to refer to Figure 3 as well as Figure 4A-4G ,in, Figure 3 is a flow chart of a method for preparing an SOI substrate structure provided in one embodiment of the present invention, Figure 4A-4G A schematic diagram of the structure corresponding to each step of the method for preparing an SOI substrate structure provided in one embodiment of the present invention; Figure 3 as well as Figure 4A-4G As shown, an embodiment of the present invention further provides a method for preparing an SOI substrate structure, which is used to form the aforementioned SOI substrate structure. The method may include:

[0088] S1: providing a top silicon layer 130, and forming a first protrusion 131 at a first preset position on a first surface of the top silicon layer 130; the initial structure of the top silicon layer 130 is as follows: Figure 4A As shown, the structure after forming the first boss 131 is as follows Figure 4B shown.

[0089] The initial structure of the top silicon 130 is specifically a first silicon wafer; the first boss 131 is formed by etching the first surface of the top silicon 130. Specifically, for example, other areas outside the first preset position of the top silicon 130 are etched to form the first boss 131 at the first preset position. As an example, the specific method of forming the first boss 131 is, for example, forming a first patterned mask layer at the first preset position of the top silicon 130, etching the top silicon 130 with the first patterned mask layer as a mask until etching to a preset depth, so as to form the first boss 131 at the first preset position of the top silicon 130. The preset depth of etching is determined according to the thickness of the first boss 131. The first preset position can be understood as a position directly opposite to the gate of the semiconductor device to be formed subsequently.

[0090] As a preferred embodiment, after forming the first boss 131, the following steps may also be included:

[0091] S11: forming an alignment groove 132 at a second preset position on the first surface of the top silicon 130, such as Figure 4C It should be noted that Figure 4CThe following schematic diagrams are all illustrated with alignment grooves formed on the top silicon layer, but this does not mean that the alignment grooves must be formed.

[0092] In addition, it should be noted that the order of forming the alignment groove 132 and the first boss 131 is not strictly limited, and the present invention does not impose any restrictions on this. In other embodiments, the alignment groove 132 can also be formed before forming the first boss 131, that is, the alignment groove 132 is formed first, and then the first boss 131 is formed.

[0093] S2: forming a buried oxide layer 120 on the first surface of the top silicon 130; wherein the thickness of the first protrusion is less than the thickness of the buried oxide layer 120; the structure after this step is completed is as follows Figure 4E shown.

[0094] As an example, step S2 may specifically include:

[0095] S21: depositing an oxide layer 121 on the first surface of the top silicon 130; the oxide layer 121 fills the alignment groove and covers the first surface of the top silicon 130 and the first protrusion; Figure 4D shown.

[0096] Specifically, the oxide layer 121 may conformally cover the first surface of the top silicon layer 130 .

[0097] In other embodiments, the surface of the formed oxide layer 121 that is not in contact with the top silicon layer 130 may also be a flat surface or an incompletely flat surface, and the present application does not impose any limitation on this.

[0098] S22: performing surface planarization treatment on the oxide layer to form a buried oxide layer 120; Figure 4E shown.

[0099] As an example, the surface planarization method for the oxide layer is chemical mechanical polishing (CMP). Of course, the present invention is not limited to this, and other surface planarization methods are also within the protection scope of the present invention.

[0100] S3: providing a bottom silicon layer 110, and bonding the bottom silicon layer 110 to the buried oxide layer 120; Figure 4F shown.

[0101] Furthermore, after bonding the bottom silicon 110 to the buried oxide layer 120, the following steps may be further included:

[0102] S31: thinning the second surface of the top silicon 130 so that the thickness of the top silicon 130 reaches a preset value and the buried oxide layer in the alignment groove is exposed; Figure 4G As shown, the thickness of the top silicon layer 130 reaching the preset value can be understood as making the thickness of the top silicon layer meet the aforementioned range of 10 nm to 1000 nm.

[0103] As an example, the method for thinning the top silicon 130 is smart-cut technology or back etching, which is a conventional processing method in the art and will not be described in detail here. However, it should be appreciated that the present invention is not limited to this, and other methods for thinning the top silicon are also within the scope of protection of the present invention.

[0104] Please continue to refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a PDSOI device formed by using an SOI substrate structure provided by an embodiment of the present invention; Figure 5 As shown, the embodiment of the present invention also provides a PDSOI device, which includes Figure 4G The SOI substrate structure, the semiconductor device formed on the SOI substrate structure and the body contact region are shown; wherein:

[0105] The semiconductor device is formed on a second surface of the top silicon 130 opposite to the first surface, and the semiconductor device may specifically include a source region 142, a drain region 143, and a gate 141, and the gate 141 is located directly above the first protrusion 131. The term "directly above" in the present application may be understood as:

[0106] If the width of the gate 141 is equal to the width of the first protrusion 131 , the gate 141 and the first protrusion 131 are vertically opposite to each other.

[0107] If the width of the gate 141 is greater than the width of the first boss 131, the gate 141 is located above the first boss 131, and the gate 141 completely covers the first boss 131. In addition, as a preferred embodiment, the central axis of the gate 141 in the width direction overlaps the central axis of the first boss 131 in the width direction, that is, the gate 141 is symmetrically distributed on the left and right sides of the first boss 131; thereby making the structure of the semiconductor device symmetrical. Of course, it should be noted that even if the gate 141 is asymmetrically distributed on the left and right sides of the first boss 131, it is also within the protection scope of the present invention.

[0108] The body contact region is formed in the third preset position of the SOI substrate structure, and the body contact region is located at the periphery of the semiconductor device; the first boss is connected to the body contact region. It can be understood that the body contact region is a doped region formed in the top silicon 130, which is used to connect to an external voltage. Figure 5 It is not shown in the figure and will be described below in conjunction with the accompanying drawings.

[0109] Furthermore, the width b of the first protrusion 131 is less than or equal to the length of the channel of the semiconductor device; the reason is as described above and will not be repeated here.

[0110] in, Figure 5 It is only used to illustrate the positional relationship between the semiconductor device and the first boss 131 in the PDSOI device. In order to have a more comprehensive understanding of the PDSOI device in the embodiment of the present invention, please continue to refer to Figure 6-7C ,in, Figure 6 A top view of a PDSOI device provided by an embodiment of the present invention;

[0111] Fig. 7A for Figure 6 The cross-section along the A1-A2 direction; Figure 7B for Figure 6 The cross-section along the B1-B2 direction; Figure 7C for Figure 6 Cross-sectional view along the C1-C2 direction.

[0112] like Figure 6-7C As shown, the PDSOI device in the embodiment of the present invention may include an SOI substrate structure, wherein the SOI substrate structure is specifically as follows Figure 4G As shown. For example, the top silicon 130 in the SOI substrate structure 100 is P-type silicon, then a well region 180 is formed in the top silicon 130, and a semiconductor device is formed in the heavily doped region 150 in the well region 180, wherein the semiconductor device specifically includes a gate 141, a source region 142, and a drain region 143, wherein the gate 141 is located directly above the first protrusion 131; and the gate 141, the source region 142, and the drain region 143 are respectively connected through corresponding contact holes (such as Figure 6 The periphery of the semiconductor device is isolated by a shallow trench isolation structure (STI, Shallow Trench Isolation) 170, and a P-type heavily doped body contact region 160 is formed on the periphery of the shallow trench isolation structure 170. The first boss 131 is connected to the body contact region 160 in the length direction, so that by connecting the body contact region 160 to a fixed potential, the carriers (specifically holes) accumulated in the well region of the PDSOI device during operation can be released through the body contact region, thereby effectively suppressing the floating body effect of the PDSOI device.

[0113] Of course, it should be appreciated that the implementation of the present invention only takes the top silicon 130 in the SOI substrate structure 100 as P-type silicon for illustration, and does not specifically limit the type of the top silicon. The type of the top silicon can also be N-type silicon. On this basis, the doping type of each functional area can be adaptively changed.

[0114] Moreover, the PDSOI device provided by the embodiment of the present invention is Figure 1A-Figure 1C As for the three methods of suppressing the floating body effect, there are at least the following advantages:

[0115] 1) Compared to Figure 1A The T-gate structure and Figure 1B As for the H-type gate structure in the PDSOI device provided by the embodiment of the present invention, there are no arc-shaped corners in the source region and the drain region on both sides of the gate, so there is no edge effect.

[0116] 2) Compared with Figure 1A The T-gate structure and Figure 1B As for the H-type gate structure in the embodiment of the present invention, the PDSOI device provided by the embodiment of the present invention has no lateral gate portion, so the parasitic effect is greatly reduced.

[0117] 3) Compared with Figure 1C As for the BTS-type gate structure in the embodiment of the present invention, the PDSOI device provided by the embodiment of the present invention is a symmetrical structure, and the source region and the drain region can be interchanged, thereby improving the flexibility of circuit design.

[0118] 4) The PDSOI device provided in the embodiment of the present invention cleverly forms a first boss on the top silicon, so that the thickness of the first boss part is greater than the thickness of other parts, and the first boss is connected to the outer body contact area, so that the accumulated carriers can be released through the body contact area. Furthermore, since the thickness of the top silicon at the first boss is thicker than the thickness of the top silicon in other parts, the thickness of the buried oxide layer directly below the first boss is thinner than the thickness of the buried oxide layer in other parts, and the buried oxide layer directly below the first boss is located directly below the semiconductor device, thereby improving the heat dissipation performance of the semiconductor device. This is because the thermal conductivity of the oxide layer is poor. When the thickness of the top silicon is thinner and the thickness of the buried oxide layer is thicker, the SOI semiconductor device is more seriously affected by the self-heating effect. The thickness of the buried oxide layer directly below the semiconductor device in the embodiment of the present invention is thinner than the thickness of the buried oxide layer in other parts, and the thickness of the top silicon directly below the semiconductor device is thicker than the thickness of the top silicon in other parts, which is more conducive to heat dissipation.

[0119] 5) The method for suppressing the floating body effect of the PDSOI device provided in the embodiment of the present invention does not require changing the structure and preparation process of the semiconductor device, but can be achieved by only changing the SOI substrate structure, which is simple and convenient.

[0120] To summarize, the SOI substrate structure and the PDSOI device provided by the technical solution of the present invention form a first boss at a first preset position on the first surface of the top silicon so that the thickness of the top silicon at this position is greater than the thickness of the top silicon in other parts; when a semiconductor device is subsequently formed on the second surface of the top silicon, the gate of the semiconductor device is located directly above the first boss; by connecting the first boss to the body contact area, the carriers accumulated in the well area of ​​the PDSOI device during operation can be released through the body contact area, thereby effectively suppressing the floating body effect of the PDSOI device.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A SOI substrate structure, characterized in that: It includes a top silicon layer, a buried oxide layer and a bottom silicon layer arranged in sequence from top to bottom; wherein: A first boss is formed at a first preset position on the first surface of the top silicon layer; The buried oxide layer is in contact with the first surface of the top silicon layer, and the thickness of the first boss is smaller than the thickness of the buried oxide layer; The bottom silicon is bonded to the buried oxide layer; The second surface of the top silicon layer opposite to the first surface is used to form a semiconductor device, and the gate of the semiconductor device is located directly above the first boss.

2. The SOI substrate structure according to claim 1, characterized in that: The thickness of the top silicon layer is 10nm-1000nm.

3. The SOI substrate structure according to claim 1, characterized in that: The thickness of the buried oxide layer is 10nm to 5000nm.

4. The SOI substrate structure according to any one of claims 1 to 3, characterized in that: An alignment groove is also formed at a second preset position of the top silicon layer, and the alignment groove penetrates through the top silicon layer; and the buried oxide layer is filled in the alignment groove.

5. A method for preparing a SOI substrate structure, characterized in that: For forming the SOI substrate structure according to any one of claims 1 to 4, the method comprises: Providing a top silicon layer, wherein a first boss is formed at a first preset position on a first surface of the top silicon layer; forming a buried oxide layer on the first surface of the top silicon layer; wherein the thickness of the first protrusion is less than the thickness of the buried oxide layer; An underlying silicon layer is provided and bonded to the buried oxide layer.

6. The method for preparing the SOI substrate structure according to claim 5, characterized in that: Before forming the buried oxide layer, the method further comprises: An alignment groove is formed at a second predetermined position on the first surface of the top silicon layer.

7. The method for preparing the SOI substrate structure according to claim 6, characterized in that: Forming a buried oxide layer on the first surface of the top silicon layer includes: Depositing an oxide layer on the first surface of the top silicon; the oxide layer filling the alignment groove and covering the first surface of the top silicon and the first boss; The oxide layer is subjected to a surface planarization process to form a buried oxide layer.

8. The method for preparing the SOI substrate structure according to claim 7, characterized in that: After bonding the bottom silicon to the buried oxide layer, the method further comprises: The second surface of the top silicon layer is thinned to make the thickness of the top silicon layer reach a preset value and expose the buried oxide layer in the alignment groove.

9. A PDSOI device, characterized in that: The method comprises the SOI substrate structure according to any one of claims 1 to 4, a semiconductor device formed on the SOI substrate structure, and a body contact region; wherein: The semiconductor device is formed on a second surface of the top silicon layer opposite to the first surface, and a gate of the semiconductor device is located directly above the first protrusion; The body contact region is formed in a third preset position of the SOI substrate structure and is located at the periphery of the semiconductor device; the first boss is connected to the body contact region.

10. The PDSOI device according to claim 9, characterized in that: The width of the first protrusion is less than or equal to the length of the channel of the semiconductor device.

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