Chip packaging method and chip packaging structure

Abstract

The invention discloses a chip packaging method and a chip packaging structure. A soft metal bulge is arranged on a chip to be electrically connected with a circuit substrate; the soft metal protrusions can be manually controlled to deform for multiple times in the chip inversion process, before the open-type plastic packaging process and in the open-type plastic packaging process so as to reduce or eliminate height tolerance between different chips and eliminate the current situation that the chips are attached to the surface of the circuit substrate and are uneven. Therefore, the plastic package material overflow problem of the open type plastic package process is solved, the function of the original chip is maintained, and the chip package yield is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a chip packaging method and a chip packaging structure. Background Art

[0002] Chips usually have fragile structures, and plastic packaging can be used to seal and protect the chips to improve structural strength and reliability. Sensor chips (such as optical image sensor chips) usually have a sensing area that cannot be contaminated or blocked, so a cover plate is required and open plastic packaging technology is used to protect it.

[0003] The open-type plastic encapsulation technology is to cover the surface of the cover plate of the mounted chip with a layer of film for protection. The upper mold of the plastic encapsulation is in direct contact with the film and pressed tightly against the surface of the cover plate of the chip. The plastic encapsulation resin enters the mold cavity from the side injection port and is cured under high temperature and high pressure to achieve plastic encapsulation. The surface of the chip cover plate will not be contaminated by the plastic encapsulation material due to the protection of the film. After the plastic encapsulation material is completely cured, the film on the cover plate surface is removed to achieve open-type plastic encapsulation.

[0004] However, in actual application, due to the height tolerance between the chips after the cover is set, the cover surface of the chip actually mounted on the circuit substrate is not on the same horizontal line. The thin film covering cannot completely protect the thinner chip cover surface, causing the plastic packaging material to overflow and contaminate the chip cover surface, affecting the packaging yield and chip function.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a chip packaging method and a chip packaging structure, which can solve the problem of plastic packaging material overflow in an open plastic packaging process, maintain the function of the original chip, and improve the chip packaging yield.

[0007] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0008] A chip packaging method, comprising:

[0009] Providing a wafer, the wafer comprising a plurality of chips, each of the chips having a first surface and a second surface arranged opposite to each other, and a functional area and a pad being formed on the first surface;

[0010] Providing a cover plate, and arranging the cover plate on the first surface to cover the functional area;

[0011] forming a soft metal protrusion electrically connected to the pad on the second surface, wherein the soft metal protrusion has a preset height and deformation capability;

[0012] cutting the wafer to form chip packages;

[0013] Providing a circuit substrate, and flip-mounting a plurality of chip packages on the circuit substrate;

[0014] Placing a circuit substrate provided with a plurality of chip packages in a packaging mold;

[0015] The pressure applied by the packaging mold to the chip package is regulated, and the corresponding soft metal protrusion is deformed to change its height, so that the cover plates of all chip packages abut against the packaging mold;

[0016] Injecting a plastic encapsulation material into the encapsulation mold to form a plastic encapsulation body, wherein the plastic encapsulation body at least covers the connection between the circuit substrate and the chip package;

[0017] The packaging structure formed with the plastic package body is demoulded and cut to form a plurality of chip packaging structures.

[0018] In one or more embodiments of the present invention, during the process of flipping multiple chip packages onto the circuit substrate, the pressure applied to the chip packages is regulated, and the corresponding soft metal protrusions are deformed to change their own heights, so that the relative heights of the multiple chip packages on the circuit substrate tend to be consistent.

[0019] In one or more embodiments of the present invention, before the step of placing the circuit substrate provided with a plurality of chip packages in a packaging mold, the step further includes:

[0020] A parallel plate is used to apply pressure to the multiple chip packages on the circuit substrate, and the pressure applied to the chip packages is regulated, so that the corresponding soft metal protrusions are deformed to change their own heights, so that the relative heights of the multiple chip packages on the circuit substrate tend to be consistent.

[0021] In one or more embodiments of the present invention, parallel plates are used to apply pressure to the plurality of chip packages on the circuit substrate in a direction perpendicular to the circuit substrate to eliminate height tolerance.

[0022] In one or more embodiments of the present invention, the pressure applied by the packaging mold to the chip package is regulated so that the soft metal protrusions on the chip package with a relatively high height are squeezed and deformed to reduce their own height and are supported on the packaging mold together with the chip package with a relatively low height.

[0023] In one or more embodiments of the present invention, the packaging mold includes an upper mold and a lower mold that cooperate with each other;

[0024] The pressure applied by the upper mold of the packaging mold to the chip package is regulated, and the corresponding soft metal protrusion is deformed to change its own height, so that the cover plates of all chip packages are in contact with the inner surface of the upper mold of the packaging mold.

[0025] In one or more embodiments of the present invention, a release film is provided on the inner surface of the upper mold.

[0026] In one or more embodiments of the present invention, a circuit substrate is provided, and a plurality of chip packages are flip-mounted on the circuit substrate, including:

[0027] Providing a circuit substrate, and disposing solder on the surface of the circuit substrate;

[0028] A plurality of chip packages are flipped onto the circuit substrate, and the soft metal protrusion of each chip package is soldered onto the circuit substrate through the solder.

[0029] In one or more embodiments of the present invention, a preset height of the soft metal protrusion is higher than a height tolerance of the plurality of chip packages.

[0030] A chip packaging structure, comprising:

[0031] Circuit substrate;

[0032] A chip is arranged on the surface of the circuit substrate, the chip has a first surface and a second surface arranged opposite to each other, a functional area and a welding pad are formed on the first surface, a soft metal protrusion electrically connected to the welding pad is formed on the second surface, and the chip is electrically connected to the circuit substrate through the soft metal protrusion;

[0033] A cover plate, disposed on the first surface of the chip to cover the functional area;

[0034] The plastic package is arranged on the surface of the circuit substrate and at least covers the connection between the circuit substrate and the chip.

[0035] In one or more embodiments of the present invention, the chip packaging structure further includes solder, and the soft metal protrusions of the chip are fixed on the circuit substrate through the solder.

[0036] Compared with the prior art, the chip packaging method and chip packaging structure of the present invention complete electrical interconnection with the circuit substrate by setting soft metal protrusions on the chip. The soft metal protrusions can be deformed during the open plastic packaging process to reduce or eliminate the height tolerance between different chips. It has stronger operability and better effect. There is no need to add additional structures on the chip surface, and the chip functional area is not occupied, which reduces the impact on chip performance.

[0037] The chip packaging method and chip packaging structure of the present invention complete electrical interconnection with a circuit substrate by arranging soft metal protrusions on the chip. The soft metal protrusions can be deformed during the chip flip-chip process to reduce or eliminate the height tolerance between different chips, eliminate the uneven surface of the circuit substrate when the chip is mounted, thereby solving the problem of plastic packaging material overflow in the open plastic packaging process, maintaining the function of the original chip, and improving the chip packaging yield.

[0038] The chip packaging method and chip packaging structure of the present invention complete electrical interconnection with a circuit substrate by arranging soft metal protrusions on the chip. The soft metal protrusions can be artificially controlled to undergo multiple deformations before the open plastic packaging process to reduce or eliminate the height tolerance between different chips and eliminate the uneven surface of the circuit substrate when the chip is mounted, thereby solving the problem of plastic packaging material overflow in the open plastic packaging process and improving the chip packaging yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A flowchart of a chip packaging method according to an embodiment of the present invention;

[0041] Figure 2a-2k A step structure diagram of a chip packaging method according to an embodiment of the present invention;

[0042] Figure 3 FIG. 4 is a cross-sectional view of a chip packaging structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] As mentioned in the background technology, there is a height tolerance between chips. After being mounted on the circuit substrate surface, the top of the chip cover is not on the same horizontal line and the height is inconsistent. In the chip open molding process, the higher chip will lift the film and the upper mold of the packaging mold, resulting in the film covering the lower chip cover surface cannot be fully protected, the upper mold cannot press each chip cover surface, resulting in a gap between the top surface of the cover of some chips and the packaging mold. During injection molding, the plastic molding compound overflows into the gap and contaminates the chip, affecting the packaging yield and chip function, and even worse, causing delamination problems.

[0045] The existing solution is to add a protective silk screen on the surface of the chip cover. However, the setting of the protective silk screen occupies the area of ​​the chip functional area, which affects the chip function and increases the difficulty of chip design.

[0046] Based on this, the present invention provides a chip packaging method and a chip packaging structure, in which soft metal protrusions are arranged on the chip to complete electrical interconnection with a circuit substrate. The soft metal protrusions can be artificially controlled to undergo multiple deformations during the chip flip-chip process, before the open plastic packaging process, and during the open plastic packaging process to reduce or eliminate the height tolerance between different chips, eliminate the current situation where the chip is mounted on the uneven surface of the circuit substrate, thereby solving the problem of plastic packaging material overflow in the open plastic packaging process, maintaining the function of the original chip, and improving the chip packaging yield.

[0047] like Figure 1 As shown, the chip packaging method in one embodiment of the present invention specifically includes the following steps:

[0048] S1: Provide a wafer, wherein the wafer includes a plurality of chips, each chip has a first surface and a second surface that are opposite to each other, and a functional area and a pad are formed on the first surface.

[0049] S2: Provide a cover plate, and arrange the cover plate on the first surface to cover the functional area.

[0050] The cover plate and the first surface of the chip can be bonded by a glue bonding layer. The glue bonding layer is formed on the periphery of the functional area and together with the cover plate, forms a sealed chamber surrounding the functional area.

[0051] S3: forming a soft metal protrusion for electrically connecting the pad on the second surface, wherein the soft metal protrusion has a preset height and deformation capability.

[0052] For example, a hole can be opened on the second surface of the chip by TSV (Through Silicon Via) technology to expose the pad. A conductive layer electrically connected to the pad is then formed in the through hole, and the conductive layer extends to the second surface of the chip. A soft metal protrusion is formed on the conductive layer on the second surface. The preset height of the soft metal protrusion needs to be higher than the maximum height tolerance of multiple chip packages subsequently packaged on the same circuit substrate, so that the soft metal protrusion can be deformed and lowered by applying pressure to the soft metal protrusion to maintain the consistency of the relative height of the multiple chip packages on the circuit substrate.

[0053] S4: Slicing the wafer to form chip packages.

[0054] S5: providing a circuit substrate, and flipping a plurality of chip packages onto the circuit substrate.

[0055] Conductive connection points are formed on the surface of the circuit substrate. Solder, such as solder paste, is placed at the conductive connection points on the surface of the circuit substrate. Soft metal protrusions of multiple chip packages are soldered to the conductive connection points on the circuit substrate through solder to complete the electrical interconnection between the chip package and the circuit substrate.

[0056] In the process of flip-mounting the plurality of chip packages on the circuit substrate, the height tolerance of the plurality of chip packages can be initially reduced or eliminated.

[0057] For example, the pressure applied to the chip package can be adjusted so that the corresponding soft metal protrusions are deformed to change their own heights, so that the relative heights of multiple chip packages on the circuit substrate tend to be consistent.

[0058] Subsequently, the parallel plates may be used to apply pressure to the plurality of chip packages on the circuit substrate to perform secondary reduction or elimination of height tolerances of the plurality of chip packages.

[0059] Exemplarily, in a direction perpendicular to the circuit substrate, parallel plates are used to apply pressure to multiple chip packages on the circuit substrate, and the pressure applied to the chip packages is regulated, so that the corresponding soft metal protrusions deform to change their own heights, so that the relative heights of the multiple chip packages on the circuit substrate tend to be consistent.

[0060] S6: placing the circuit substrate provided with a plurality of chip packages in a packaging mold.

[0061] In this step, the height tolerance of multiple chip packages can be eliminated again. By adjusting the pressure applied by the packaging mold to the chip package, the corresponding soft metal protrusions are deformed to change their own heights. The soft metal protrusions on the chip packages with relatively high heights are squeezed to reduce their own heights and are held against the packaging mold together with the chip packages with relatively low heights, so that the cover plates of all chip packages are kept in contact with the packaging mold.

[0062] It is understood that the packaging mold includes an upper mold and a lower mold that cooperate with each other. A release film is provided on the inner surface of the upper mold, and the release film can contact the cover plate of the chip package during the subsequent plastic packaging process to protect the chip package. By adjusting the pressure applied to the chip package by the upper mold of the packaging mold, the height tolerance of the chip package is eliminated.

[0063] S7: injecting a plastic packaging material into the packaging mold to form a plastic packaging body, wherein the plastic packaging body at least covers the connection between the circuit substrate and the chip package.

[0064] In order to further improve the structural strength of the chip package, the plastic package covers the surface of the circuit substrate, the connection between the circuit substrate and the chip package, and the peripheral surface of the chip package, and only the top surface of the chip package is completely exposed.

[0065] S8: demoulding and cutting the packaging structure formed with the plastic packaging body to form a plurality of chip packaging structures.

[0066] Figure 2a-2k The schematic diagram of the specific steps of the chip packaging method of the present invention is as follows. Figure 2a-2k , the chip packaging method of the present invention is elaborated in detail to facilitate a further understanding of the technical solution of the present invention.

[0067] refer to Figure 2a As shown, a wafer 10 is provided, and the wafer 10 includes a plurality of chips 11 and dicing lanes 12 formed between adjacent chips 11. The chip 11 has a first surface and a second surface oppositely disposed, and a functional area 111 and a bonding pad 112 coupled to the functional area are formed on the first surface.

[0068] It is understandable that the cutting lanes 12 between adjacent chips 11 are used for cutting after wafer-level packaging. The chip 11 may be an optical image sensor chip, etc. The functional area 111 is an optical sensing area, for example, it may be formed by a plurality of photodiode arrays, and the photodiodes may convert the optical signals irradiated to the functional area 111 into electrical signals. The pads 112 serve as input and output terminals for connecting the devices in the functional area 111 to external circuits.

[0069] refer to Figure 2b As shown, a cover plate 20 is provided. The cover plate 20 is preferably a transparent substrate, such as glass. The cover plate 20 is bonded to the first surface of the chip 11 by bonding glue, and the cover plate 20 covers the functional area 111. For example, a glue bonding layer A can be formed on the surface of the cover plate 20 and / or the first surface of the chip 11 by spraying, spin coating or gluing, and the glue bonding layer A is located at the periphery of the functional area 111. Then, the cover plate 20 and the first surface of the chip 11 are pressed relative to each other and combined by bonding glue.

[0070] The bonding glue can not only achieve bonding, but also play the role of insulation and sealing. The bonding glue can be a polymer bonding material, such as silicone, epoxy resin, benzocyclobutene and other polymer materials.

[0071] refer to Figure 2c As shown, the chip 11 is etched from the second surface of the chip 11 to form a through hole (not shown), and the through hole exposes the bonding pad 112 on one side of the first surface of the chip 11.

[0072] An insulating layer 113 is formed on the second surface of the chip 11 and on the sidewalls of the through hole, and the insulating layer 113 exposes the pad 112 at the bottom of the through hole. The insulating layer 113 can provide electrical insulation for the second surface of the chip 11. The material of the insulating layer 113 can be silicon oxide, silicon nitride, silicon oxynitride or insulating resin.

[0073] A conductive layer 114 connected to the pad 112 is formed on the surface of the insulating layer 113. The conductive layer 114 can be used as a rewiring layer to lead the pad 112 to the second surface of the chip 11 and then connect to an external circuit. The conductive layer 114 is formed by depositing and etching a metal film.

[0074] A solder resist layer 115 having openings (not shown) is formed on the surfaces of the conductive layer 114 and the insulating layer 113 , the openings exposing a portion of the surface of the conductive layer 114 . The solder resist layer 115 is made of insulating dielectric materials such as silicon oxide and silicon nitride and is used to protect the conductive layer 114 .

[0075] A soft metal protrusion 116 is formed on the surface of the solder resist layer 115. The soft metal protrusion 116 fills the opening and protrudes out of the opening. The soft metal protrusion 116 has a preset height and deformation ability, and can deform and change its height under stress. The radial dimension of the soft metal protrusion 116 can gradually decrease in the direction away from the chip 11. The material of the soft metal protrusion 116 can be a soft metal such as gold, and the soft metal protrusion 116 is prone to self-deformation as the pressure and / or temperature change during the pressure application process.

[0076] refer to Figure 2d As shown, the wafer 10 and the cover plate 20 are cut along the dicing streets 12 to form chip packages 100 .

[0077] refer to Figure 2e As shown, a circuit substrate 30 is provided. Conductive connection points are formed on the surface of the circuit substrate 30. Solder 31, such as solder paste, is provided at the conductive connection points on the surface of the circuit substrate 30.

[0078] refer to Figure 2fAs shown, the soft metal protrusions 116 of the multiple chip packages 100 are soldered to the conductive connection points on the circuit substrate 30 through solder 31 to complete the electrical interconnection between the chip package 100 and the circuit substrate 30. In the initial state, there is a certain height tolerance H after the multiple chip packages 100 are formed on the circuit substrate 30.

[0079] refer to Figure 2g As shown, the process parameters of the chip package 100 are controlled to be constant during the flip-chip process, and the pressure applied to the chip package 100 is adjusted so that the corresponding soft metal protrusion 116 is deformed to change its own height. For example, when the higher chip package 100 is flipped, the soft metal protrusion 116 is squeezed and deformed, and the height is reduced to the same as the lower chip package 100. The soft metal protrusion 116 of the lower chip package 100 is subjected to less pressure, deformed less, and the height is almost unchanged, so that the relative heights of multiple chip packages 100 on the circuit substrate 30 tend to be consistent, completing the first reduction or even elimination of the height tolerance H.

[0080] refer to Figure 2h-Figure 2i As shown, the height tolerance between the chip packages 100 that may still exist after the flip-chip process can be further eliminated by pressing through the parallel plate 40 after the flip-chip process is completed.

[0081] In a direction perpendicular to the circuit substrate 30, a parallel plate 40 is used to squeeze all chip packages 100 on the circuit substrate 30. The pressure applied to the chip package 100 is regulated so that the corresponding soft metal protrusion 116 is deformed to change its own height. The taller chip package 100 is squeezed first, and the soft metal protrusion 116 is deformed after being pressed, so that the chip package 100 is reduced in height. Then the parallel plate 40 touches the chip package 100 of medium height, and squeezes the original taller chip package 100 and the chip package 100 of medium height at the same time, so that the soft metal protrusion 116 is further deformed, and finally keeps the same height as the shorter chip package 100.

[0082] refer to Figure 2j As shown, a release film 220 is pasted on the inner top surface of the upper mold 210 of the packaging mold 200, and a circuit substrate 30 provided with a plurality of chip packages 100 is placed in the packaging mold 200, and an open plastic packaging process is performed.

[0083] In the open plastic packaging process, after the flat upper mold 210 presses the release film 220, it can still exert an extrusion effect on the chip package 100 and deform the soft metal protrusion 116. The taller chip package 100 is squeezed first, and the soft metal protrusion 116 is deformed and reduced in height, and the upper mold 210 is pressed against the shorter chip package 100, ultimately achieving height consistency.

[0084] The encapsulation material is filled into the encapsulation mold 200 through the injection port. The encapsulation material is a polymer composite material such as epoxy resin, polyimide, and dry mold. The encapsulation material is then cured under high temperature and high pressure to form a encapsulation body 50. The encapsulation body 50 provides physical support for the encapsulation structure and plays a role in sealing and protecting the chip package 100, the circuit substrate 10, and the soft metal protrusion 116.

[0085] refer to Figure 2k As shown, the plastic package body 50 after demolding covers the side walls of the cover plate 20 and is flush with the top surface of the cover plate 20. The top surface of the cover plate 20 does not form the plastic package body 50. The packaging structure after the plastic package body 50 is formed is cut along the dotted line position in the figure to form multiple chip packaging structures.

[0086] The present invention also provides a chip packaging structure, which is packaged by the above chip packaging method. Figure 2a-2k The description of the chip packaging method may be incorporated herein.

[0087] refer to Figure 3 As shown, the chip packaging structure includes a circuit substrate 30 , a chip 11 , a cover plate 20 and a plastic package 50 .

[0088] The chip 11 is arranged on the surface of the circuit substrate 30. The chip 11 has a first surface and a second surface arranged opposite to each other. A functional area 111 and a pad 112 are formed on the first surface, and a soft metal protrusion 116 electrically connected to the pad 112 is formed on the second surface. The soft metal protrusion 116 of the chip 11 is electrically connected to the circuit substrate 30 through the solder 31. The cover plate 20 is arranged on the first surface of the chip 11 to cover the functional area 111. The plastic package 50 is arranged on the surface of the circuit substrate 30 and at least covers the connection between the circuit substrate 30 and the chip 10.

[0089] Compared with the prior art, the chip packaging method and chip packaging structure of the present invention complete electrical interconnection with the circuit substrate by setting soft metal protrusions on the chip. The soft metal protrusions can be deformed during the open plastic packaging process to reduce or eliminate the height tolerance between different chips. It has stronger operability and better effect. There is no need to add additional structures on the chip surface, and the chip functional area is not occupied, which reduces the impact on chip performance.

[0090] The chip packaging method and chip packaging structure of the present invention complete electrical interconnection with a circuit substrate by arranging soft metal protrusions on the chip. The soft metal protrusions can be deformed during the chip flip-chip process to reduce or eliminate the height tolerance between different chips, eliminate the uneven surface of the circuit substrate when the chip is mounted, thereby solving the problem of plastic packaging material overflow in the open plastic packaging process, maintaining the function of the original chip, and improving the chip packaging yield.

[0091] The chip packaging method and chip packaging structure of the present invention complete electrical interconnection with a circuit substrate by arranging soft metal protrusions on the chip. The soft metal protrusions can be artificially controlled to undergo multiple deformations before the open plastic packaging process to reduce or eliminate the height tolerance between different chips and eliminate the uneven surface of the circuit substrate when the chip is mounted, thereby solving the problem of plastic packaging material overflow in the open plastic packaging process and improving the chip packaging yield.

[0092] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0093] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A chip packaging method, characterized in that: include: Providing a wafer, the wafer comprising a plurality of chips, each of the chips having a first surface and a second surface arranged opposite to each other, and a functional area and a pad being formed on the first surface; Providing a cover plate, and arranging the cover plate on the first surface to cover the functional area; forming a soft metal protrusion electrically connected to the pad on the second surface, wherein the soft metal protrusion has a preset height and deformation capability; cutting the wafer to form chip packages; Providing a circuit substrate, and flip-mounting a plurality of chip packages on the circuit substrate; Placing a circuit substrate provided with a plurality of chip packages in a packaging mold; The pressure applied by the packaging mold to the chip package is regulated, and the corresponding soft metal protrusion is deformed to change its height, so that the cover plates of all chip packages abut against the packaging mold; Injecting a plastic encapsulation material into the encapsulation mold to form a plastic encapsulation body, wherein the plastic encapsulation body at least covers the connection between the circuit substrate and the chip package; The packaging structure formed with the plastic package body is demoulded and cut to form a plurality of chip packaging structures.

2. The chip packaging method according to claim 1, characterized in that: In the process of flipping multiple chip packages onto the circuit substrate, the pressure applied to the chip packages is regulated, and the corresponding soft metal protrusions are deformed to change their own heights, so that the relative heights of the multiple chip packages on the circuit substrate tend to be consistent.

3. The chip packaging method according to claim 1, characterized in that: Before the step of placing the circuit substrate provided with a plurality of chip packages in the packaging mold, the method further includes: A parallel plate is used to apply pressure to the multiple chip packages on the circuit substrate, and the pressure applied to the chip packages is regulated, so that the corresponding soft metal protrusions are deformed to change their own heights, so that the relative heights of the multiple chip packages on the circuit substrate tend to be consistent.

4. The chip packaging method according to claim 3, characterized in that: In a direction perpendicular to the circuit substrate, a parallel plate is used to apply pressure to a plurality of chip packages on the circuit substrate to eliminate height tolerance.

5. The chip packaging method according to claim 1, characterized in that: The pressure applied by the packaging mold to the chip package is regulated so that the soft metal protrusions on the chip package with a relatively high height are squeezed and deformed to reduce their own height and are supported on the packaging mold together with the chip package with a relatively low height.

6. The chip packaging method according to claim 1, characterized in that: The packaging mold includes an upper mold and a lower mold that cooperate with each other; The pressure applied by the upper mold of the packaging mold to the chip package is regulated, and the corresponding soft metal protrusion is deformed to change its own height, so that the cover plates of all chip packages are in contact with the inner surface of the upper mold of the packaging mold.

7. The chip packaging method according to claim 6, characterized in that: A release film is provided on the inner surface of the upper mold.

8. The chip packaging method according to claim 1, characterized in that: Providing a circuit substrate, and flip-mounting a plurality of chip packages on the circuit substrate, comprising: Providing a circuit substrate, and disposing solder on the surface of the circuit substrate; A plurality of chip packages are flipped onto the circuit substrate, and the soft metal protrusion of each chip package is soldered onto the circuit substrate through the solder.

9. The chip packaging method according to claim 1, characterized in that: The preset height of the soft metal protrusion is higher than the height tolerance of the plurality of chip packages.

10. A chip packaging structure, characterized in that: include: Circuit substrate; A chip is arranged on the surface of the circuit substrate, the chip has a first surface and a second surface arranged opposite to each other, a functional area and a welding pad are formed on the first surface, a soft metal protrusion electrically connected to the welding pad is formed on the second surface, and the chip is electrically connected to the circuit substrate through the soft metal protrusion; A cover plate, disposed on the first surface of the chip to cover the functional area; The plastic package is arranged on the surface of the circuit substrate and at least covers the connection between the circuit substrate and the chip.

11. The chip packaging structure according to claim 10, characterized in that: It also includes solder, and the soft metal protrusions of the chip are fixed on the circuit substrate through the solder.

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