Back contact photovoltaic cell and preparation method thereof, solar cell module and solar cell system

Abstract

The invention relates to the technical field of solar cells, particularly provides a back contact photovoltaic cell, and aims to solve the problem that an existing back contact photovoltaic cell cannot give consideration to passivation performance and reduce contact resistance at the same time. The back contact photovoltaic cell comprises a semiconductor substrate containing a first dopant, floating emitter region structures arranged at intervals are arranged on the front surface of the semiconductor substrate, each floating emitter region structure contains a second dopant, and the conduction type of the second conductive dopant is opposite to that of the first conductive dopant. According to the back contact photovoltaic cell disclosed by the invention, the high compounding ratio of the FFE is reduced by arranging the FFE on the front surface of the N-type substrate at intervals, the excellent passivation performance of the front surface of the cell is maintained, and the FFE provides a high-speed transmission channel for holes, so that the loss of the holes in the substrate transmission process is reduced. According to the invention, by reducing the proportion of FFE high compounding, the proportion of the N-type doped region on the back surface of the battery can be properly increased under the condition of reaching the same current, and the passivation performance of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and specifically provides a back-contact photovoltaic cell, a solar cell assembly and a solar cell system. Background Art

[0002] The positive and negative electrodes of the IBC cell (interdigitated back contact cell) are both on the back of the cell, so that a higher conversion efficiency can be achieved with the same area. Based on the existing IBC technology, the TBC cell (tunneling back contact cell) was developed by introducing the Topcon (tunneling oxide passivation contact) technology, which can significantly reduce the recombination loss of the emitter and base, especially the metal contact area. At present, there are a large number of technical developments for the development of TBC cell passivation technology. Since the polysilicon structure on the back of the cell accounts for too large a proportion (more than 90%), how to balance the passivation performance while reducing the contact resistance is one of the key points of improving cell efficiency and process development.

[0003] The TBC cell has no junction on the front, which is the mainstream cell structure at present. Taking the N-type substrate as an example, its advantage lies in the passivation effect of the substrate after texturing and the good auxiliary effect for the high Voc (open circuit voltage) of the cell. However, the disadvantage is that the proportion of N-type polysilicon on the back is about 30%-40%, the open circuit voltage is about 743mV, and the proportion of P-type polysilicon is high, so the passivation effect is not good, the open circuit voltage is about 725mV, so the cell conversion efficiency is limited.

[0004] Accordingly, the art needs a new back-contact photovoltaic cell to solve the problem that existing back-contact photovoltaic cells cannot achieve both passivation performance and reduced contact resistance. Summary of the invention

[0005] The present invention aims to solve the above technical problem, that is, to solve the problem that existing back-contact photovoltaic cells cannot achieve both passivation performance and reduced contact resistance.

[0006] In a first aspect, the present invention provides a back-contact photovoltaic cell, comprising a semiconductor substrate containing a first dopant, wherein a front surface of the semiconductor substrate is provided with a floating emitter region structure arranged at intervals, and the floating emitter region structure contains a second dopant, and the conductivity type of the second dopant is opposite to that of the first dopant.

[0007] When adopting the above technical solution, the back-contact photovoltaic cell of the present invention reduces the proportion of the floating emitter structure by setting a floating emitter structure on the front surface of the semiconductor substrate, maintains the excellent passivation performance of the front side of the cell, and at the same time provides a high-speed transmission channel for carriers, reduces the loss of carriers during transmission on the substrate, and reduces the contact resistance.

[0008] In the optional technical solution of the above-mentioned back-contact photovoltaic cell, the semiconductor substrate is an N-type substrate, and the corresponding floating emitter region structure is a P-type floating emitter region structure; or, the semiconductor substrate is a P-type substrate, and the corresponding floating emitter region structure is an N-type floating emitter region structure.

[0009] In the case of adopting the above technical solution, by setting the P-type floating emitter region structure at intervals on the front side of the N-type substrate, the proportion of the P-type floating emitter region structure is reduced, and the excellent passivation performance of the front side of the battery is maintained. The P-type floating emitter region structure can provide a high-speed transmission channel for holes and reduce the loss of holes in the substrate transmission process.

[0010] In addition, in order to generate more photogenerated current carriers, the P-type doping area on the back of the back contact battery is generally larger than the N-type doping area. The present invention reduces the high recombination ratio of the P-type floating emitter structure, and can appropriately increase the ratio of the N-type doping area of ​​the battery when the current is equal, thereby improving the battery passivation performance and the conversion efficiency.

[0011] Alternatively, by setting an N-type floating emitter region structure at intervals on the front side of the P-type substrate, the excellent passivation performance of the front side of the battery is maintained, and a high-speed transmission channel can be provided for electrons, thereby reducing the loss of electrons during substrate transmission.

[0012] In the optional technical solution of the above-mentioned back-contact photovoltaic cell, the back surface of the semiconductor substrate is provided with an N-type doped layer and a P-type doped layer separated by an isolation region, and in the thickness direction of the semiconductor substrate, the setting position of the floating emitter region structure corresponds to the isolation region.

[0013] When the above technical solution is adopted, the transmission path of holes is improved by the floating emitter region structure, thereby reducing the accumulation of holes in the isolation region, thereby promoting the flow of holes.

[0014] In the optional technical solution of the above-mentioned back-contact photovoltaic cell, the junction depth of the floating emitter region structure is 2μm-5μm; and / or, a suede layer is also provided on the front surface of the semiconductor substrate, the suede layer and the floating emitter region structure are arranged alternately, and a front passivation layer is provided on the front surface of the suede layer and the floating emitter region structure.

[0015] In the case of adopting the above technical solution, the junction depth of the floating emitter structure is 2μm-5μm, which can prevent the junction depth from being too deep, resulting in an increase in surface defects, and increase the probability of carrier recombination on the surface, affecting the incidence and absorption of light. At the same time, it also prevents the problem of insufficient electric field strength and reduced carrier collection efficiency caused by the junction depth being too shallow. The front passivation layer and the velvet layer improve the passivation performance of the front side of the battery.

[0016] In the optional technical solution of the above-mentioned back-contact photovoltaic cell, the area of ​​the floating emitter region structure occupies 10%-50% of the area of ​​the front surface of the semiconductor substrate.

[0017] In the case of adopting the above technical solution, the loss of the open circuit voltage of the battery caused by the introduction of boron is reduced by setting the P-type floating emitter region structure at intervals. Due to the transmission effect of the P-type floating emitter region structure on holes, the proportion of the back N-type doped layer can be appropriately increased by about 10%-20%, thereby improving the passivation performance of the battery.

[0018] In an optional technical solution of the above-mentioned back-contact photovoltaic cell, a first tunneling layer is provided between the N-type doped layer and the N-type substrate, and a second tunneling layer is provided between the P-type doped layer and the N-type substrate.

[0019] When the above technical solution is adopted, the tunneling layer can improve the interface properties of the rear surface of the substrate and effectively transfer the generated carriers through tunneling to promote photoelectric conversion.

[0020] In an optional technical solution of the above-mentioned back-contact photovoltaic cell, a first back passivation layer is provided on the back surface of the P-type doped layer, and a second back passivation layer is provided on the back surface of the N-type doped layer.

[0021] When the above technical solution is adopted, the passivation performance of the back side of the battery is improved.

[0022] In a second aspect, the present invention further provides a method for preparing a back-contact photovoltaic cell, the steps of the preparation method comprising:

[0023] Depositing a thin film containing a second dopant on the front surface of the semiconductor substrate containing the first dopant;

[0024] Selectively retaining the film to form a spaced film;

[0025] The second dopant in the thin film is doped into the front surface of the semiconductor substrate to form a floating emitter structure arranged at intervals.

[0026] When the above technical solution is adopted, the position and dosage of doping can be accurately controlled, thereby ensuring battery performance while reducing costs.

[0027] In a third aspect, the present invention further provides a solar cell assembly, comprising a back-contact photovoltaic cell according to any one of the above technical solutions.

[0028] In a fourth aspect, the present invention further provides a solar cell system, comprising a back-contact photovoltaic cell according to any one of the above technical solutions.

[0029] It can be understood by those skilled in the art that the back-contact photovoltaic cell of the present invention includes a semiconductor substrate containing a first dopant, the front surface of the semiconductor substrate is provided with a floating emitter region structure arranged at intervals, the floating emitter region structure contains a second dopant, and the conductivity type of the second dopant is opposite to that of the first dopant.

[0030] In the case of adopting the above technical solution, by setting the P-type floating emitter region structure at intervals on the front side of the N-type substrate, the high recombination ratio of the P-type floating emitter region structure is reduced, and the excellent passivation performance of the front side of the battery is maintained. The P-type floating emitter region structure can provide a high-speed transmission channel for holes and reduce the loss of holes in the substrate transmission process.

[0031] In addition, in order to generate more photogenerated current carriers, the P-type doping area on the back of the back contact battery is generally larger than the N-type doping area. The present invention reduces the high recombination ratio of the P-type floating emitter structure, and can appropriately increase the ratio of the N-type doping area of ​​the battery when the current is equal, thereby improving the battery passivation performance and the conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a schematic cross-sectional view of a first possible embodiment of a back-contact photovoltaic cell of the present invention;

[0034] Figure 2 is a schematic cross-sectional view of a second possible embodiment of the back-contact photovoltaic cell of the present invention.

[0035] List of reference numerals:

[0036] 10. N-type substrate; 11. P-type substrate;

[0037] 20. P-type floating emitter structure; 21. N-type floating emitter structure;

[0038] 31. suede layer; 32. first aluminum oxide layer; 33. first silicon nitride layer;

[0039] 41. first tunneling layer; 42. N-type doping layer; 43. second aluminum oxide layer; 44. second silicon nitride layer;

[0040] 51. second tunneling layer; 52. P-type doping layer; 53. third aluminum oxide layer; 54. third silicon nitride layer;

[0041] 60. Isolation area;

[0042] 71. First electrode; 72. Second electrode. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. Those skilled in the art can make adjustments as needed to adapt to specific applications. For example, although the present application is described in conjunction with TBC photovoltaic cells, this is not restrictive, and the back contact cell of the present invention may also be other types of photovoltaic cells, such as IBC cells, HBC cells, MWT cells, and the like.

[0044] It should be noted that in the description of the present invention, the terms "upper", "lower", "inner", "outer", etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. This is only for the convenience of description, and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention. "Inner" refers to the direction toward the semiconductor substrate, and "outer" refers to the direction away from the semiconductor substrate. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The front of the battery is the side exposed to the sun, and the back of the battery is the side opposite to the side exposed to the sun (front).

[0045] Reference Figure 1 In order to solve the problem that the existing back-contact photovoltaic cell cannot take into account the passivation performance and reduce the contact resistance at the same time, the present invention provides a back-contact photovoltaic cell. The back-contact photovoltaic cell includes a semiconductor substrate containing a first dopant, and the front surface of the semiconductor substrate is provided with a floating emitter region structure arranged at intervals, and the floating emitter region structure contains a second dopant, and the conductivity type of the second dopant is opposite to that of the first dopant.

[0046] The semiconductor substrate of the back contact photovoltaic cell of the present invention is a crystalline silicon substrate, which can be an N-type substrate containing an N-type dopant, or a P-type substrate containing a P-type dopant. When the semiconductor substrate is an N-type substrate, the floating emitter region structure is a P-type floating emitter region structure, and when the semiconductor substrate is a P-type substrate, the floating emitter region structure is an N-type floating emitter region structure.

[0047] When the semiconductor substrate is an N-type substrate, the first dopant is an N-type dopant. That is, it is formed by doping pentavalent elements (such as phosphorus, arsenic, and antimony) into the semiconductor. These pentavalent elements provide additional electrons in the silicon lattice. Therefore, the N-type substrate uses free electrons as the majority carriers, thereby giving the region N-type conductivity. When the semiconductor substrate is a P-type substrate, the first dopant is a P-type dopant, that is, it is formed by doping trivalent elements (such as boron, indium, and gallium) into the semiconductor material; the trivalent elements introduce holes into the silicon lattice, and these holes become the majority carriers, thereby giving the region P-type conductivity.

[0048] The floating emitter structure is formed by doping a semiconductor with a low concentration of a second dopant. Optionally, when the floating emitter structure is a P-type floating emitter structure, the second dopant is a P-type dopant, such as boron, and the boron doping concentration of the P-type floating emitter structure is lower than the boron doping concentration of the back P-type doping region. The difference in the concentration gradient of the boron doping element is used to provide a good transport channel for holes and reduce the hole recombination rate.

[0049] When the floating emitter structure is an N-type floating emitter structure, the N-type dopant is an N-type dopant, such as phosphorus. The phosphorus doping concentration of the N-type floating emitter structure is lower than that of the back N-type doping region. The difference in phosphorus doping concentration gradient is used to provide a good transport channel for electrons and reduce the electron recombination rate.

[0050] The back-contact photovoltaic cell of the present invention reduces the proportion of the floating emitter structure by setting a floating emitter region structure on the front surface of the semiconductor substrate, maintains the excellent passivation performance of the front side of the cell, and at the same time provides a high-speed transmission channel for carriers, reduces the loss of carriers during transmission on the substrate, and reduces contact resistance.

[0051] In a first possible implementation:

[0052] Reference Figure 1 The back-contact photovoltaic cell includes an N-type substrate 10 , and a front surface of the N-type substrate 10 is provided with P-type floating emitter region structures 20 arranged at intervals.

[0053] By using the method of setting the P-type floating emitter region structure 20 at intervals on the front side of the N-type substrate 10, the high recombination ratio of the P-type floating emitter region structure 20 is reduced, and the excellent passivation performance of the front side of the battery is maintained. The P-type floating emitter region structure 20 can provide a high-speed transmission channel for holes and reduce the loss of holes in the substrate transmission process.

[0054] In addition, in order to generate more photogenerated current carriers, the P-type doping area on the back of the back contact battery is generally larger than the N-type doping area. The present invention reduces the high recombination ratio of the P-type floating emitter region structure 20, and can appropriately increase the ratio of the N-type doping area of ​​the battery when the current is equal, thereby further improving the battery passivation performance and the conversion efficiency.

[0055] Furthermore, a suede layer 31 parallel to the P-type floating emitter region structure 20 is further disposed on the front surface of the N-type substrate 10 , and the suede layer 31 and the P-type floating emitter region structure 20 are alternately arranged.

[0056] The velvet layer 31 is prepared by placing the battery in a velvet-making machine and chemically etching the front surface of the N-type substrate 10 to have a concave-convex surface to reduce light reflection.

[0057] Furthermore, the P-type floating emitter region structure 20 occupies 10%-50% of the front surface area of ​​the N-type substrate 10. The loss of the open circuit voltage of the battery due to the introduction of the boron element is reduced. Due to the transmission effect of the P-type floating emitter region structure 20 on holes, the proportion of the N-type doping layer 42 can be increased by about 10%-20%, thereby improving the passivation performance of the battery.

[0058] The junction depth of the P-type floating emitter region structure 20 is controlled at 2 μm-5 μm. This can prevent the junction depth from being too deep, which will lead to an increase in surface defects, increase the probability of carrier recombination on the surface, and affect the incidence and absorption of light. At the same time, it can also prevent the problem of insufficient electric field strength and reduced carrier collection efficiency caused by the junction depth being too shallow.

[0059] Further, a front passivation layer is provided on the front surface of the suede layer 31 and the P-type floating emitter region structure 20. Optionally, the front passivation layer includes a first front passivation layer and a second front passivation layer stacked sequentially from the inside to the outside. The first front sub-passivation layer and the second front sub-passivation layer are respectively a first aluminum oxide layer 32 and a first silicon nitride layer 33.

[0060] However, it should be noted that the front passivation layer includes but is not limited to one or more combinations of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, indium tin oxide, and titanium oxide, and its function is to provide free hydrogen to chemically passivate the dangling bonds on the surface of the N-type substrate 10.

[0061] The thickness of the first aluminum oxide layer 32 is 5nm-15nm, and the thickness of the first silicon nitride layer 33 is 60nm-100nm. By setting the thickness of the front passivation layer, it is possible to prevent the front passivation layer from being too thick, which may lead to a decrease in optical performance and damage to electrical performance, and it is also possible to prevent the front passivation layer from being too thin, which may lead to poor passivation effect.

[0062] Furthermore, a first tunneling layer 41 and a second tunneling layer 51 are arranged in parallel on the back surface of the N-type substrate 10. An N-type doped layer 42 and a first back passivation layer are sequentially stacked on the back surface of the first tunneling layer 41 from the inside to the outside. A P-type doped layer 52 and a second back passivation layer are sequentially stacked on the back surface of the second tunneling layer 51 from the inside to the outside.

[0063] An isolation region 60 is provided adjacent to the N-type doping layer 42 and the P-type doping layer 52. The isolation region 60 is sequentially stacked with an isolation velvet layer and an isolation passivation layer 61 ( Figure 1 , Figure 2 Only the isolation passivation layer 61 is shown in the figure. The structure of the isolation passivation layer 61 is the same as that of the front passivation layer, and will not be described in detail.

[0064] Among them, the setting position of the P-type floating emitter region structure 20 corresponds to the isolation region 60. The width of the P-type floating emitter region structure 20 is greater than or equal to the width of the isolation region 60, that is, the projection of the P-type floating emitter region structure 20 on the isolation region 60 can completely cover the isolation region 60. The P-type floating emitter region structure 20 improves the transmission path of holes, thereby reducing the accumulation of holes in the isolation region 60, thereby promoting the flow of holes. Of course, those skilled in the art can set the width of the P-type floating emitter region structure 20 and the isolation region 60 according to actual needs, and the P-type floating emitter region structure 20 can also partially project to cover the isolation region 60.

[0065] The N-type doped layer 42 and the N-type substrate 10 form a tunnel junction through the first tunnel layer 41, and the P-type doped layer 52 and the N-type substrate 10 form a tunnel junction through the second tunnel layer 51. The tunnel layer can improve the interface properties of the rear surface of the N-type substrate 10, and effectively transfer the generated carriers through tunneling to promote photoelectric conversion. The tunnel layer is generally composed of insulating materials such as silicon oxide and silicon nitride, and its function is to allow only specific types of carriers to tunnel, for example, only allow electrons to tunnel and block holes, or only allow holes to tunnel and block electrons.

[0066] The N-type doping layer 42 is formed by performing N-type doping on the semiconductor, for example, by introducing pentavalent elements (such as phosphorus, arsenic, and antimony) under the surface of the semiconductor by diffusion or ion implantation to form the N-type doping layer 42. The P-type doping layer 52 is formed by performing P-type doping on the back of the semiconductor, for example, by using diffusion or ion implantation to infiltrate or implant trivalent elements (such as boron, indium, and gallium) into the semiconductor to form a p-type doping layer, so as to construct a pn junction.

[0067] Optionally, the first tunneling layer 41 has a thickness of 1 nm-2 nm, the N-type doping layer 42 has a thickness of 90 nm-180 nm, the second tunneling layer 51 has a thickness of 1 nm-2 nm, and the P-type doping layer 52 has a thickness of 200 nm-400 nm.

[0068] By designing the thickness of the N-type doping layer 42, it is possible to prevent the problem of the N-type doping layer 42 being too thick, which will increase the cost and affect the carrier transmission and optical performance. It is also possible to prevent the N-type doping layer 42 being too thin, which will lead to poor passivation effect and insufficient carrier collection.

[0069] By designing the thickness of the P-type doped layer 52, it is possible to prevent the P-type doped layer 52 from being too thick, which will lead to increased costs, increased carrier recombination, increased resistance during transmission, and affected optical performance. It is also possible to prevent the P-type doped layer 52 from being too thin, which will lead to poor passivation effect, insufficient field effect, and reduced stability.

[0070] By designing the thickness of the first tunneling layer 41 and the second tunneling layer 51, it is possible to prevent the tunneling layer from being too thick, resulting in increased costs and increased resistance that affects optical performance, and it is also possible to prevent the tunneling layer from being too thin, resulting in poor tunneling effects and reduced stability.

[0071] Optionally, the first back passivation layer includes a first sub-back passivation layer and a second sub-back passivation layer stacked from the inside to the outside. The first sub-back passivation layer and the second sub-back passivation layer are respectively a second aluminum oxide layer 43 and a second silicon nitride layer 44. The thickness of the second aluminum oxide layer 43 is 5nm-15nm, and the thickness of the second silicon nitride layer 44 is 60nm-100nm.

[0072] The second back passivation layer includes a third sub-back passivation layer and a fourth sub-back passivation layer stacked from the inside to the outside. The third sub-back passivation layer and the fourth sub-back passivation layer are respectively a third aluminum oxide layer 53 and a third silicon nitride layer 54. The thickness of the third aluminum oxide layer 53 is 5nm-15nm, and the thickness of the third silicon nitride layer 54 is 60nm-100nm.

[0073] However, it should be noted that the back passivation layer includes but is not limited to one or more combinations of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, indium tin oxide, and titanium oxide, and its function is to provide free hydrogen to chemically passivate the dangling bonds on the surface of the N-type substrate 10.

[0074] By designing the thickness of the first back passivation layer and the second back passivation layer, it is possible to prevent the back passivation layer from being too thick, which increases the cost and affects the optical and electrical properties, and it is also possible to prevent the back passivation layer from being too thin, which leads to poor passivation effect.

[0075] Furthermore, on the basis of adding N-type dopants and P-type dopants, the N-type doping layer 42 and the P-type doping layer 52 may also be doped with one or more elements such as carbon, nitrogen, oxygen, and fluorine.

[0076] The N-type substrate 10 , the N-type doping layer 42 and the P-type doping layer 52 include, but are not limited to, one or a combination of single crystal silicon, polycrystalline silicon, microcrystalline silicon, nanocrystalline silicon, and amorphous silicon.

[0077] Furthermore, the N-type doping layer 42 is connected to the first electrode 71 , and the P-type doping layer 52 is connected to the second electrode 72 .

[0078] The steps of preparing the above TBC photovoltaic cell include:

[0079] Step S11: performing double-sided polishing on the N-type substrate to remove the damaged layer;

[0080] Step S12: performing RCA (wet chemical cleaning) cleaning on the processed N-type substrate.

[0081] After the N-type substrate 10 is double-sided polished to remove damage, the polished N-type substrate 10 is cleaned by RCA.

[0082] Step S13: performing PECVD (plasma enhanced chemical vapor deposition) at a location on the back surface of the N-type substrate where P-type doping is required to deposit a second tunneling layer and a P-type doping layer;

[0083] Step S14: using a tubular annealing furnace at 930° C.-980° C. for crystallization for 15 min-35 min.

[0084] The second tunneling layer 51 and the P-type doping layer 52 are deposited on the back surface of the N-type substrate 10 by plasma enhanced chemical vapor deposition technology, and the P-type doping layer 52 is crystallized.

[0085] Step S15: laser opening the film at the position on the back of the battery where N-type doping is required, with the width of the opening film being 400 μm-600 μm and the length being 1000 μm;

[0086] Step S16: removing damage from the film-opening area by a wet method;

[0087] Step S17: performing PECVD on the battery to deposit a first tunneling layer and an N-type doping layer on the back side of the battery;

[0088] Step S18: placing the battery on an annealing machine for annealing at a temperature of 840°C-940°C and crystallization for 10min-30min.

[0089] After laser filming is performed at the position on the back of the battery where N-type doping is required, the damage is removed, and the first tunneling layer 41 and the N-type doping layer 42 are deposited on the back of the battery. Then, the battery is placed in an annealing station for annealing to crystallize the N-type doping layer 42. The N-type doping is performed on the entire back of the battery, which covers the P-type doping layer 52 and the isolation region 60.

[0090] Step S19: Laser-open the silicon dioxide film at the position of the non-N-type doping area on the back of the battery, and use a wet method to remove the P-type doping layer and the N-type doping layer on the isolation area.

[0091] Laser film opening is performed at the location of the non-N-type doping area, and then the P-type doping layer 52 on the back side of the battery and the N-type doping layer 42 on the isolation area 60 are removed by wet method.

[0092] Step S110: placing the battery in a velvet making machine, preparing a velvet layer on the front surface of the N-type substrate, and performing double-sided RCA cleaning;

[0093] Step S111: Use APCVD (atmospheric pressure chemical vapor deposition) to deposit a BSG film (a film composed of dopant boron incorporated into silicon dioxide) on the front of the battery and perform selective retention.

[0094] A texture layer 31 is formed after the front surface of the N-type substrate 10 is textured, and then a BSG film is deposited. A portion of the BSG film is retained and a portion is removed by laser cutting or wet washing to form an interval BSG film.

[0095] Step S112: placing the battery in a high-temperature tube device for doping to form a P-type floating emitter region structure;

[0096] Step S113: clean off the BSG film.

[0097] The battery is placed in a high-temperature tubular device for high-temperature doping, so that the boron element in the BSG film enters the N-type substrate 10 to form a P-type floating emitter region structure 20, and then the BSG film on the battery is cleaned off.

[0098] Step S114: Use a tubular ALD (atomic layer deposition) device to simultaneously deposit an aluminum oxide layer on the front and back sides of the battery; or, after cleaning, use a plate ALD device to sequentially deposit an aluminum oxide layer on the front and back sides.

[0099] A first aluminum oxide layer 32 is deposited on the front surface of the battery velvet layer 31 and the P-type floating emitter region structure 20 , and a second aluminum oxide layer 43 and a third aluminum oxide layer 53 are deposited on the back surface of the battery N-type doped layer 42 and the P-type doped layer 52 using a tubular ALD device.

[0100] Step S115: using PECVD to coat a silicon nitride layer on the front side of the battery and a silicon nitride layer on the back side.

[0101] The first silicon nitride layer 33 is plated on the front surface of the first aluminum oxide layer 32 , the second silicon nitride layer 44 is plated on the back surface of the second aluminum oxide layer 43 , and the third silicon nitride layer 54 is plated on the back surface of the third aluminum oxide layer 53 by PECVD.

[0102] Step S116: printing electrodes on the back of the battery by metal printing and sintering to form a first electrode and a second electrode.

[0103] Electrodes are printed on the back of the battery using a metal printing process and then sintered to form a first electrode 71 and a second electrode 72 .

[0104] In a second possible implementation:

[0105] Reference Figure 2 The back-contact photovoltaic cell includes a P-type substrate 11 , and a front surface of the P-type substrate 11 is provided with N-type floating emitter region structures 21 arranged at intervals.

[0106] Furthermore, a suede layer 31 parallel to the N-type floating emitter region structure 21 is further disposed on the front surface of the P-type substrate 11 , and the suede layer 31 and the N-type floating emitter region structure 21 are alternately arranged.

[0107] The N-type floating emitter region structure 21 occupies 10%-50% of the front surface area of ​​the P-type substrate 11. By arranging the N-type floating emitter region structures 21 at intervals, the loss of the open circuit voltage of the battery caused by the introduction of phosphorus elements is reduced.

[0108] The junction depth of the N-type floating emitter structure 21 is controlled to be 2 μm-5 μm. Further, a front passivation layer is provided on the front surface of the velvet layer 31 and the N-type floating emitter structure 21. Optionally, the front passivation layer includes a first front passivation layer and a second front passivation layer stacked sequentially from the inside to the outside. The first front sub-passivation layer and the second front sub-passivation layer are respectively a first aluminum oxide layer 32 and a first silicon nitride layer 33.

[0109] A first tunneling layer 41 and a second tunneling layer 51 are arranged in parallel on the back surface of the P-type substrate 11. An N-type doped layer 42 and a first back passivation layer are sequentially stacked on the back surface of the first tunneling layer 41 from the inside to the outside. A P-type doped layer 52 and a second back passivation layer are sequentially stacked on the back surface of the second tunneling layer 51 from the inside to the outside.

[0110] An isolation region 60 is disposed adjacent to the N-type doping layer 42 and the P-type doping layer 52. The N-type floating emitter region structure 21 is disposed at a position corresponding to the isolation region 60. The N-type floating emitter region structure 21 improves the transmission path of electrons.

[0111] Optionally, the first back passivation layer includes a first back passivation sub-layer and a second back passivation sub-layer stacked from inside to outside. The first back passivation sub-layer and the second back passivation sub-layer are a second aluminum oxide layer 43 and a second silicon nitride layer 44, respectively.

[0112] The second back passivation layer includes a third back passivation sub-layer and a fourth back passivation sub-layer stacked from the inside to the outside. The third back passivation sub-layer and the fourth back passivation sub-layer are a third aluminum oxide layer 53 and a third silicon nitride layer 54 respectively.

[0113] The specific structure and function of the first back passivation layer and the second back passivation layer are similar to those of the first possible implementation, so they are not described in detail. The back contact photovoltaic cell in the second implementation has the same principle as the back contact cell in the first implementation.

[0114] Specifically, the steps of preparing the TBC photovoltaic cell of the second embodiment include:

[0115] Step S21: performing double-sided polishing on the P-type substrate to remove the damaged layer;

[0116] Step S22: Clean the processed P-type substrate by RCA (wet chemical cleaning method).

[0117] After the P-type substrate 11 is double-sided polished to remove damage, the polished P-type substrate 11 is cleaned by RCA.

[0118] Step S23: performing PECVD (plasma enhanced chemical vapor deposition) at a location on the back surface of the P-type substrate where P-type doping is required to deposit a second tunneling layer and a P-type doping layer;

[0119] Step S24: using a tubular annealing furnace at 930° C.-980° C. for crystallization for 15 min-35 min.

[0120] The second tunneling layer 51 and the P-type doping layer 52 are deposited on the back surface of the P-type substrate 10 by plasma enhanced chemical vapor deposition technology, and the P-type doping layer 52 is crystallized.

[0121] Step S25: laser opening the film at the position on the back of the battery where N-type doping is required, with the width of the opening film being 400 μm-600 μm and the length being 1000 μm;

[0122] Step S26: removing damage from the film-opening area by a wet method;

[0123] Step S27: performing PECVD on the battery to deposit a first tunneling layer and an N-type doping layer on the back side of the battery;

[0124] Step S28: placing the battery on an annealing machine for annealing at a temperature of 840°C-940°C and crystallization for 10min-30min.

[0125] After laser filming is performed at the position on the back of the battery where N-type doping is required, the damage is removed, and the first tunneling layer 41 and the N-type doping layer 42 are deposited on the back of the battery. Then, the battery is placed in an annealing station for annealing to crystallize the N-type doping layer 42. The N-type doping is performed on the entire back of the battery, which covers the P-type doping layer 52 and the isolation region 60.

[0126] Step S29: Laser-open the silicon dioxide film at the position of the non-N-type doping area on the back of the battery, and use a wet method to remove the P-type doping layer and the N-type doping layer on the isolation area.

[0127] Laser film opening is performed at the location of the non-N-type doping area, and then the P-type doping layer 52 on the back side of the battery and the N-type doping layer 42 on the isolation area 60 are removed by wet method.

[0128] Step S210: placing the battery in a texturing machine, preparing a texturing layer on the front surface of the P-type substrate, and performing double-sided RCA cleaning;

[0129] Step S211: Use APCVD (atmospheric pressure chemical vapor deposition) to deposit a PSG film (a film composed of dopant phosphorus incorporated into silicon dioxide) on the front of the battery and perform selective retention.

[0130] A velvet layer 31 is formed after the front surface of the P-type substrate 11 is textured, and then a PSG film is deposited. A portion of the PSG film is retained and a portion is removed by laser cutting or wet washing to form an interval PSG film.

[0131] Step S212: placing the battery in a high-temperature tube device for doping to form an N-type floating emitter region structure;

[0132] Step S213: clean the PSG film.

[0133] The battery is placed in a high-temperature tubular device for high-temperature doping, so that the phosphorus element in the PSG film enters the P-type substrate 11 to form an N-type floating emitter region structure 21, and then the PSG film on the battery is cleaned off.

[0134] Step S214: Use a tubular ALD (atomic layer deposition) device to simultaneously deposit an aluminum oxide layer on the front and back sides of the battery; or, after cleaning, use a plate ALD device to sequentially deposit an aluminum oxide layer on the front and back sides.

[0135] A first aluminum oxide layer 32 is deposited on the front surface of the battery velvet layer 31 and the N-type floating emitter structure 21 , and a second aluminum oxide layer 43 and a third aluminum oxide layer 53 are deposited on the back surface of the battery N-type doped layer 42 and the P-type doped layer 52 using a tubular ALD device.

[0136] Step S215: using PECVD to coat a silicon nitride layer on the front side of the battery and a silicon nitride layer on the back side.

[0137] The first silicon nitride layer 33 is plated on the front surface of the first aluminum oxide layer 32 , the second silicon nitride layer 44 is plated on the back surface of the second aluminum oxide layer 43 , and the third silicon nitride layer 54 is plated on the back surface of the third aluminum oxide layer 53 by PECVD.

[0138] Step S216: Printing electrodes on the back of the battery using metal printing and sintering to form a first electrode and a second electrode.

[0139] Electrodes are printed on the back of the battery using a metal printing process and then sintered to form a first electrode 71 and a second electrode 72 .

[0140] As stated in the first paragraph of this section, the above implementation mode is only used to illustrate the principles of the present invention and is not intended to limit the scope of protection of the present invention. Without departing from the principles of the present invention, those skilled in the art can adjust the above structure so that the present invention can be applied to more specific application scenarios.

[0141] In addition, the present invention also provides a solar cell module, which has the back-contact photovoltaic cell described in any of the above embodiments.

[0142] The present invention also provides a solar cell system, which has the back-contact photovoltaic cell described in any one of the above embodiments.

[0143] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A back contact photovoltaic cell, characterized in that: The back contact photovoltaic cell comprises a semiconductor substrate containing a first dopant, wherein a front surface of the semiconductor substrate is provided with a floating emitter region structure arranged at intervals, wherein the floating emitter region structure contains a second dopant, and the conductivity type of the second dopant is opposite to that of the first dopant.

2. The back contact photovoltaic cell according to claim 1, characterized in that: The semiconductor substrate is an N-type substrate, and the corresponding floating emitter region structure is a P-type floating emitter region structure; or, the semiconductor substrate is a P-type substrate, and the corresponding floating emitter region structure is an N-type floating emitter region structure.

3. The back contact photovoltaic cell according to claim 1, characterized in that: The back surface of the semiconductor substrate is provided with an N-type doping layer and a P-type doping layer separated by an isolation region. In the thickness direction of the semiconductor substrate, the arrangement position of the floating emitter region structure corresponds to the isolation region.

4. The back-contact photovoltaic cell according to any one of claims 1 to 3, characterized in that: The junction depth of the floating emitter structure is 2μm-5μm; and / or, a suede layer is further provided on the front surface of the semiconductor substrate, the suede layer and the floating emitter structure are arranged alternately, and a front passivation layer is provided on the front surfaces of the suede layer and the floating emitter structure.

5. The back-contact photovoltaic cell according to any one of claims 1 to 3, characterized in that: The area of ​​the floating emitter region structure occupies 10%-50% of the area of ​​the front surface of the semiconductor substrate.

6. The back contact photovoltaic cell according to claim 3, characterized in that: A first tunneling layer is disposed between the N-type doping layer and the N-type substrate, and a second tunneling layer is disposed between the P-type doping layer and the N-type substrate.

7. The back contact photovoltaic cell according to claim 3, characterized in that: A first back passivation layer is disposed on the back surface of the P-type doping layer, and a second back passivation layer is disposed on the back surface of the N-type doping layer.

8. A method for preparing a back-contact photovoltaic cell, characterized in that: The steps of the preparation method include: Depositing a thin film containing a second dopant on the front surface of the semiconductor substrate containing the first dopant; Selectively retaining the film to form a spaced film; The second dopant in the thin film is doped into the front surface of the semiconductor substrate to form a floating emitter structure arranged at intervals.

9. A solar cell module, characterized in that: The solar cell module is provided with the back-contact photovoltaic cell according to any one of claims 1 to 7.

10. A solar cell system, characterized in that: The solar cell system is provided with the back-contact photovoltaic cell according to any one of claims 1 to 7.

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