LED chip with electrostatic protection function and preparation method thereof

Abstract

The invention provides an LED chip with an electrostatic protection function and a preparation method thereof, and the method comprises the following steps: growing an epitaxial layer on a substrate, the epitaxial layer comprising an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked from bottom to top; etching a through hole in the epitaxial layer to expose the N-type semiconductor layer; preparing a dielectric layer, a reflecting layer, a wafer bonding barrier layer and a wafer bonding bonding layer, and carrying out eutectic bonding on the wafer bonding bonding layer and the wafer bonding bonding layer on the substrate; removing the substrate; performing Schottky electrode protection photoetching; preparing an edge removing layer, and photoetching the epitaxial layer to form a channel; preparing a passivation layer, and preparing a Schottky electrode; and patterning the passivation layer and the edge removing layer to prepare an N-surface electrode. According to the invention, the Schottky diode is arranged below the bonding pad of the LED chip, so that the anti-electrostatic discharge capability of the LED is improved on the premise that the optical power is not sacrificed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an LED chip with an electrostatic protection function and a preparation method thereof. Background Art

[0002] LED is the abbreviation of Light-Emitting Diode, and its Chinese name is light-emitting diode. Its light-emitting principle is that holes in P-type semiconductors and electrons in N-type semiconductors undergo radiation recombination under the action of electric fields and become photons. LED chips have many advantages such as low power consumption, pure color, long life, small size, fast response time, energy saving and environmental protection, and are widely used in lighting, visible light communication, light-emitting display and other scenarios.

[0003] In order to prevent the LED from being damaged by electrostatic discharge, a common solution is to connect a Zener diode in reverse parallel with the LED at the package end. When reverse electrostatic discharge occurs, the pulse current generated by the electrostatic discharge will flow through the Zener diode to prevent the LED from being damaged by static electricity.

[0004] However, this solution has the following problems: 1. Before the packaging is completed, the LED chip is very likely to fail due to static electricity; 2. It is difficult to install the Zener diode during the packaging process and the packaging process cost is high; 3. Because the Zener diode is placed close to the LED chip in the package, the luminous efficiency of the LED package will be reduced due to the light absorbed by the Zener diode, thereby reducing the yield of the LED package. Summary of the invention

[0005] The purpose of the present application is to provide a method for preparing an LED chip with an electrostatic protection function, which can solve the problem of LED being damaged by electrostatic discharge.

[0006] In order to solve the above technical problems, this application is implemented as follows: On the one hand, the present application provides a method for preparing an LED chip with an electrostatic protection function, comprising the following steps: S1: growing an epitaxial layer on a substrate, wherein the epitaxial layer includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer stacked in sequence from bottom to top; S2: etching a through hole in the epitaxial layer to expose the N-type semiconductor layer; S3: preparing a dielectric layer, wherein the dielectric layer covers the side wall of the through hole; S4: preparing a reflective layer on the surface of the P-type semiconductor layer; S5: preparing a wafer bonding barrier layer and a wafer bonding adhesive layer on the surface of the epitaxial layer, the wafer bonding barrier layer fills the through hole and forms an ohmic contact with the N-type semiconductor layer through the through hole, and the wafer bonding adhesive layer fills the through hole; S6: eutectic bonding the wafer bonding adhesive layer to the wafer bonding adhesive layer on the substrate; S7: removing the substrate to expose one side of the N-type semiconductor layer; S8: protecting the N-type semiconductor layer in the Schottky electrode region, and then etching and roughening the N-type semiconductor layer in other unprotected regions; S9: preparing a trimming layer on the surface of the exposed N-type semiconductor layer, and photolithography the epitaxial layer and the trimming layer to form a channel; S10: preparing a passivation layer, and preparing a Schottky electrode on the surface of the N-type semiconductor layer and at a position corresponding to the through hole; S11: Patterning passivation layer and edge removal layer; S12: Prepare N-side electrode.

[0007] Optionally, the N-type semiconductor layer grown in step S1 consists of a low-doped N-type semiconductor layer close to the substrate and a high-doped N-type semiconductor layer far from the substrate.

[0008] Optionally, the wafer bonding barrier layer, the N-type semiconductor layer in ohmic contact with the wafer bonding barrier layer, and the Schottky electrode form a Schottky diode; the wafer bonding barrier layer is the cathode of the Schottky diode, and the Schottky electrode is the anode of the Schottky diode.

[0009] Optionally, the N-side electrode prepared in step S12 includes a pad and a finger electrode, the pad of the N-side electrode is located on the surface of the Schottky electrode, and the pad of the N-side electrode is larger than the Schottky electrode.

[0010] Optionally, the position of the through hole prepared in step S2 corresponds to the pad of the N-side electrode; the shape of the through hole is consistent with the shape of the pad of the N-side electrode.

[0011] Optionally, the through hole is cylindrical; the dielectric layer covers the side wall of the through hole to form an annular cylinder, and the pad size of the N-side electrode is smaller than the large circle size of the annular cylinder formed by the dielectric layer; the dielectric layer also includes a finger-shaped area, the finger-shaped area corresponds to the position of the finger-shaped electrode of the N-side electrode, and the width of the finger-shaped electrode of the N-side electrode is smaller than the width of the finger-shaped area of ​​the dielectric layer.

[0012] Optionally, the channel in step S9 includes a cutting path and a channel around the Schottky diode, and the channel around the Schottky diode separates the Schottky diode from the epitaxial layer of the light emitting region of the LED chip.

[0013] Optionally, when the passivation layer and the trimming layer are patterned in step S11, the pattern includes finger-shaped areas, the passivation layer and the trimming layer are left in the middle area of ​​the fingers, and the size of the retained passivation layer and the trimming layer is smaller than the finger electrodes of the N-side electrode.

[0014] In a second aspect, the present application provides an LED chip with electrostatic protection function prepared by the above preparation method.

[0015] Optionally, the LED chip with electrostatic protection function includes: substrate; An epitaxial layer, the epitaxial layer includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in a direction away from the substrate; the epitaxial layer has a through channel, and the channel separates the epitaxial layer into a Schottky region and a light-emitting region; the N-type semiconductor layer is composed of a highly doped N-type semiconductor layer close to the active layer and a low-doped N-type semiconductor layer away from the active layer; a through hole is provided on one side of the epitaxial layer close to the substrate and at a position corresponding to the channel, and the through hole exposes the highly doped N-type semiconductor layer in the Schottky region; An N-side electrode is disposed on a side of the epitaxial layer away from the substrate and forms an ohmic contact with the highly doped N-type semiconductor layer; The Schottky electrode is disposed between the pad of the N-side electrode and the N-type semiconductor layer in the Schottky region; the Schottky electrode forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky region; Edge removal layer and passivation layer, covering the channel and chip surface; A reflective layer, disposed on one side of the P-type semiconductor layer in the light emitting region; A wafer bonding barrier layer is provided on a side of the epitaxial layer close to the substrate; the wafer bonding barrier layer forms an ohmic contact with the highly doped N-type semiconductor layer in the Schottky region through a through hole; The dielectric layer is disposed between the wafer bonding barrier layer and the P-type semiconductor layer, isolating the wafer bonding barrier layer from the P-type semiconductor layer, the active layer and the reflective layer. At the cutting path of the LED chip, the dielectric layer is disposed between the wafer bonding barrier layer and the passivation layer. Wafer bonding adhesive layer, wafer bonding barrier layer and substrate; The back metal layer is arranged on the other side of the substrate.

[0016] Beneficial effects of the present invention: (1) The method for preparing an LED chip with an electrostatic protection function in the present invention comprises preparing a wafer bonding barrier layer and a Schottky electrode at corresponding positions on both sides of an N-type semiconductor layer in an LED chip. The wafer bonding barrier layer forms an ohmic contact with the N-type semiconductor layer, and the Schottky electrode forms a Schottky contact with the N-type semiconductor layer. That is, a Schottky diode is prepared in the LED chip, and the Schottky diode is reversely connected in parallel with the LED chip, thereby improving the anti-electrostatic discharge capability of the LED. The problem that the chip is not resistant to electrostatic discharge can be solved during the LED chip manufacturing process.

[0017] (2) The Schottky diode is placed under the pad of the N-side electrode of the LED chip, without occupying additional light-emitting area, thus achieving electrostatic protection of the LED chip without sacrificing light power.

[0018] (3) A passivation layer and a trimming layer that are smaller than the finger electrodes are left under the finger electrodes of the N-side electrodes of the LED chip, which can improve the current expansion of the LED chip. Under high current, the current distribution of the LED chip is more uniform. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. 1 is a top view schematically showing the process of completing step S2 in an embodiment of the present invention.

[0020] Figure 2 It is a cross-sectional schematic diagram of completing step S2 in an embodiment of the present invention.

[0021] Figure 3 FIG. 1 is a top view schematically showing the process of completing step S3 in an embodiment of the present invention.

[0022] Figure 4 It is a cross-sectional schematic diagram of completing step S3 in an embodiment of the present invention.

[0023] Figure 5 This is a top view schematic diagram of completing step S4 in the embodiment of the present invention.

[0024] Figure 6 It is a cross-sectional schematic diagram of completing step S4 in an embodiment of the present invention.

[0025] Figure 7 It is a cross-sectional schematic diagram of completing step S5 in an embodiment of the present invention.

[0026] Figure 8 FIG. 1 is a top view schematically showing the process of completing step S9 in an embodiment of the present invention.

[0027] Fig. 9 It is a cross-sectional schematic diagram of completing step S9 in an embodiment of the present invention.

[0028] Fig.10 In the embodiment of the present invention Figure 8 A magnified schematic diagram of point B in the middle.

[0029] Fig.11 It is a cross-sectional schematic diagram of completing step S10 in an embodiment of the present invention.

[0030] Fig.12 FIG. 1 is a top view schematically showing the process of completing step S11 in an embodiment of the present invention.

[0031] Fig.13 This is a comparison diagram of light distribution between the LED chip prepared according to the embodiment of the present invention and a common LED.

[0032] Fig.14 FIG. 1 is a top view schematically showing the process of completing step S12 in an embodiment of the present invention.

[0033] Fig.15 It is a cross-sectional schematic diagram of completing step S12 in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0035] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0036] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0037] In the present invention, the directions or positional relationships indicated by terms such as "upper", "lower", "horizontal", "middle", etc. are based on the directions or positional relationships shown in the accompanying drawings. They are relational words determined only for the convenience of describing the structural relationships of the various parts or elements of the present invention. They do not specifically refer to any part or element in the present invention and cannot be understood as limitations on the present invention.

[0038] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0039] In the first aspect, the embodiments of the present application provide an LED chip with electrostatic protection function and a preparation method thereof, by setting a Schottky diode under the pad of the N-side electrode of the LED chip, the anti-electrostatic discharge capability of the LED chip is achieved without occupying the light-emitting area.

[0040] The specific process steps for preparing LED chips with electrostatic protection function are as follows: Step S1: growing an epitaxial layer on a substrate 14, the epitaxial layer comprising, from bottom to top, an N-type semiconductor layer 9, an active layer 8 and a P-type semiconductor layer 7 stacked in sequence. The N-type semiconductor layer 9 is composed of a low-doped N-type semiconductor layer close to the substrate 14 and a high-doped N-type semiconductor layer far from the substrate (not shown in the figure).

[0041] Step S2: etching a through hole in the epitaxial layer to expose the highly doped N-type semiconductor layer.

[0042] In some embodiments of the present application, the epitaxial layer undergoes the first step of photolithography. After the photolithography is completed, the position of the preset Schottky diode on the surface of the epitaxial layer is not protected by photoresist, and other positions are protected by photoresist. Then, the inductively coupled plasma (ICP) etching technology is used to etch the position of the epitaxial layer that is not protected by photoresist, etch through holes, and expose the highly doped N-type semiconductor layer. The N-type semiconductor layer 9 below the through hole is the N-type semiconductor layer of the Schottky diode. The shape of the etched through hole is cylindrical, or forms a runway shape (that is, a combination of a semicircle spliced ​​at each end of a long rectangle), a rounded square column, etc. The schematic diagram of the top view after etching is completed is shown in FIG. Figure 1 As shown, the cross-sectional diagram is as follows Figure 2 shown.

[0043] Step S3: preparing a dielectric layer 5, wherein the dielectric layer 5 covers the sidewalls of the through hole.

[0044] In some embodiments of the present application, the photoresist in step S2 is removed, and a layer of dielectric material is deposited on the surface of the P-type semiconductor layer 7 using plasma enhanced chemical vapor deposition (PECVD) technology. Then, the second step of photolithography is performed. After the epitaxial layer is photolithographically processed, a photolithographic pattern is left, and then the dielectric material is etched. The remaining dielectric material forms a dielectric layer 5, and the dielectric layer 5 covers the sidewalls of the through hole and part of the bottom of the through hole. The top view after the dielectric layer 5 is prepared is shown in FIG. Figure 3 As shown, the cross-sectional diagram is as follows Figure 4 As shown, Figure 4 yes Figure 3 Schematic diagram of the cross section along AA.

[0045] In some embodiments of the present application, the shape formed by the dielectric layer 5 filling the side wall and partial area of ​​the bottom of the through hole is consistent with the shape of the through hole, which is an annular cylinder, or an annular racetrack shape, an annular rounded square column, etc.

[0046] In some embodiments of the present application, a dielectric layer 5 is also left in the die cutting street.

[0047] In some embodiments of the present application, the dielectric layer 5 is also provided with a finger structure. Whether the dielectric layer 5 is designed with a finger structure and the size of the finger structure shall be determined according to the chip size. For small-size products, such as 10 mil, a finger structure is not required.

[0048] In some embodiments of the present application, the dielectric material is an insulating material, such as aluminum oxide, silicon nitride, or silicon oxide.

[0049] It should be noted that the dielectric layer 5 at the through hole is used to isolate the P-type semiconductor layer 7, the active layer 8 and the wafer bonding barrier layer 4, and ensure that the highly doped N-type semiconductor layer of the Schottky diode is in contact with the wafer bonding barrier layer 4, and the wafer bonding barrier layer 4 serves as the cathode electrode of the Schottky diode. A dielectric layer 5 is left on the surface of the P-type semiconductor layer 7, which is used as a high resistance layer to improve the light extraction efficiency, and a dielectric layer 5 is left on the die cutting path, which is used for P-face passivation.

[0050] Step S4: preparing a reflective layer 6 on the surface of the P-type semiconductor layer 7 .

[0051] In some embodiments of the present application, after the epitaxial layer surface is activated, a metal reflective material is evaporated on the surface of the epitaxial layer by vacuum evaporation, magnetron sputtering or other techniques, and then a third step of photolithography is performed. After the epitaxial layer is photolithographically processed, a wet etching method is used to remove the metal reflective material at the position corresponding to the Schottky diode in the cut path and the middle area, and finally the photoresist is removed to form a reflective layer 6, which is used to improve the light extraction efficiency. The top view schematic diagram after preparing the reflective layer 6 is shown in FIG. Figure 5 As shown, the cross-sectional diagram is as follows Figure 6 shown.

[0052] In some embodiments of the present application, the reflective layer 6 is also the P-surface electrode of the vertical structure LED chip.

[0053] In some embodiments of the present application, the metal reflective material is a metal with a reflectivity greater than 90%, such as Ag, Al, etc.

[0054] In some embodiments of the present application, after the metal reflective material is evaporated and alloyed, a metal protective material, such as Ti, may be further evaporated on the surface of the metal reflective material, and then photolithography may be performed.

[0055] It should be noted that when the metal reflective material corresponding to the Schottky diode in the middle region is photolithographically formed, the photolithographic radius should be larger than the radius of the small circle of the dielectric layer to ensure that there is no reflective layer 6 in the hole above the N-type semiconductor layer of the Schottky diode. The photolithographic radius should also be smaller than the radius of the large circle of the dielectric layer to ensure that the optical power is not affected.

[0056] Step S5: preparing a wafer bonding barrier layer 4 and a wafer bonding adhesive layer 3, wherein the wafer bonding barrier layer 4 fills the through hole and forms an ohmic contact with the highly doped N-type semiconductor layer through the through hole, and the wafer bonding adhesive layer 3 fills the through hole.

[0057] In some embodiments of the present application, a wafer bonding barrier layer 4 is prepared on the surface of the epitaxial layer by vacuum evaporation or magnetron sputtering technology. The wafer bonding barrier layer 4 forms an ohmic contact with the highly doped N-type semiconductor layer through the through hole. Then, a wafer bonding adhesive layer 3 is evaporated on the surface of the wafer bonding barrier layer 4. The wafer bonding adhesive layer 3 fills the through hole to form a flat surface. The cross-sectional schematic diagram of the preparation is shown in FIG. Figure 7 shown.

[0058] In some embodiments of the present application, the material of the wafer bonding barrier layer 4 is Cr / Pt / Ti or Cr / Pt / TiW. The wafer bonding barrier layer 4 has two functions: one is to prevent the low melting point metal in the eutectic bonding from diffusing to the reflective layer to form black spots, and the other is to serve as the cathode electrode of the Schottky diode.

[0059] In some embodiments of the present application, the material of the wafer bonding adhesive layer 3 is a binary alloy, one of which is a low melting point metal and the other is a high melting point metal, including but not limited to CuIn, AuIn, AuSn, NiSn. In the eutectic process, the low melting point metal is in liquid state, filling the through hole and finally forming a flat bonding interface.

[0060] Step S6: eutectic bonding the wafer bonding adhesive layer 3 to the wafer bonding adhesive layer on the substrate.

[0061] In some embodiments of the present application, the substrate 2 with the wafer bonding adhesive layer evaporated on the front side is eutectic bonded with the wafer bonding adhesive layer 3 .

[0062] In some embodiments of the present application, a back metal layer 1 is also evaporated on the back side of the substrate 2 for conducting electricity on the back side of the vertically structured LED.

[0063] Step S7: removing the substrate 14 to expose one side of the N-type semiconductor layer 9 .

[0064] In some embodiments of the present application, after bonding is completed, the chip is flipped over and the substrate is removed, so that the low-doped N-type semiconductor layer is on the top.

[0065] Step S8: Protect the N-type semiconductor layer in the Schottky electrode area, and then etch and roughen the N-type semiconductor layer in other unprotected areas.

[0066] In some embodiments of the present application, a protective layer is first deposited using PECVD technology, and then the fourth step of photolithography is performed. After the photolithography is completed, the protective layer at the preset Schottky electrode position has a photoresist, and the protective layer in other areas is not protected by the photoresist and is etched with BOE. Etching is then performed using ICP etching technology to remove the low-doped N-type semiconductor layer in the unprotected area, and the light extraction efficiency of the chip is improved by roughening the high-doped N-type semiconductor layer. At this time, the low-doped N-type semiconductor layer in the unprotected area is completely removed, and the high-doped N-type semiconductor layer is roughened. The N-type semiconductor layer 9 in the preset Schottky electrode area is not etched and roughened, and the surface of the N-type semiconductor layer 9 in this area is a low-doped N-type semiconductor layer. After completion, a degumming solution is required to remove the photoresist and then the protective layer is corroded with BOE.

[0067] In some embodiments of the present application, the protective layer is made of insulating material, and the insulating material includes aluminum oxide, silicon nitride, and silicon oxide.

[0068] Step S9: preparing a trimming layer 10 on the surface of the exposed N-type semiconductor layer 9, and photolithography the epitaxial layer and the trimming layer 10 to form a channel.

[0069] In some embodiments of the present application, the above-mentioned chip is cleaned, and then the PECVD technology is used to deposit the trimming layer 10 on the surface of the N-type semiconductor layer 9, and then the fifth step of photolithography is performed. The photoresist protects the light-emitting area and the Schottky diode area, and the unprotected area is corroded. The trimming layer 10, the N-type semiconductor layer 9, the active layer 8, and the P-type semiconductor layer 7 of the cut path are corroded to form an independent LED die. In addition, the trimming layer 10, the N-type semiconductor layer 9, the active layer 8, and the P-type semiconductor layer 7 around the Schottky diode are also corroded to form a channel. The purpose is to separate the Schottky diode from the light-emitting area of ​​the LED chip. After the epitaxial layer is etched, the photoresist is removed, and the top view schematic diagram after preparation is shown as follows. Figure 8 As shown, the cross-sectional diagram is as follows Fig. 9 As shown, Fig.10 yes Figure 8 A partial enlarged view of point B in the middle.

[0070] In some embodiments of the present application, the edge removal layer is made of insulating material, and the insulating material includes aluminum oxide, silicon nitride, and silicon oxide.

[0071] It should be noted that the radius of the small circle of the edge removal lithography is larger than the radius of the small circle of the dielectric layer, and the radius of the large circle of the edge removal lithography is larger than the lithography radius of the epitaxial layer in step S2 and smaller than the large circle radius of the dielectric layer, the purpose is to completely remove the epitaxial layer around the cathode electrode of the Schottky diode and ensure that the wafer bonding barrier layer 4 in the through hole will not be corroded. The width of the edge removal lithography cutting road needs to be narrower than the cutting road of the reflective layer lithography to ensure that the reflective layer 6 of the light-emitting area is not corroded.

[0072] Step S10: preparing a passivation layer 11, and preparing a Schottky electrode 12 on the surface of the N-type semiconductor layer 9 and at a position corresponding to the through hole.

[0073] In some embodiments of the present application, a passivation layer 11 is prepared on the edge removal layer 10, and the passivation layer 11 covers the entire surface of the edge removal layer 10, the bottom and sidewalls of the trench, and the bottom and sidewalls of the cutting path. On the one hand, the passivation layer 11 protects the epitaxial structure of the cutting path to prevent leakage, and on the other hand, isolates the epitaxial structure of the LED from the Schottky diode. After the passivation layer 11 is prepared, the sixth step of photolithography is performed. After the photolithography is completed, the passivation layer 11 and the edge removal layer 10 at the preset Schottky electrode position are etched away. Then, the Schottky metal is evaporated on the entire surface of the chip, and the Schottky metal at other positions is peeled off after evaporation. The remaining Schottky metal is the Schottky electrode 12. The Schottky electrode 12 forms a Schottky contact with the low-doped N-type semiconductor layer. The cross-sectional schematic diagram after preparation is shown as follows. Fig.11 shown.

[0074] In some embodiments of the present application, the passivation layer 11 is prepared in two steps, firstly using the atomic layer deposition method to deposit a layer of dense passivation layer material, and then using the PECVD technology to deposit a layer of passivation layer material. The material of the passivation layer 11 is also an insulating material, including aluminum oxide, silicon nitride and silicon oxide.

[0075] In some embodiments of the present application, the Schottky electrode 12 is circular or square with rounded corners, racetrack-shaped, etc. The Schottky electrode 12 is to be disposed below the pad of the N-side electrode 13, and can be located in the middle of the chip or at other locations of the chip. The size of the Schottky electrode must be smaller than the size of the small circle of the edge removal lithography.

[0076] In some embodiments of the present application, the Schottky metal is Ni / Au or Pt / Au. Both Ni and Pt have good adhesion to semiconductor materials and a high metal work function. Depositing a layer of gold Au on Ni or Pt can prevent metal oxidation and increase conductivity.

[0077] Step S11: patterning the passivation layer 11 and the edge removal layer 10 .

[0078] In some embodiments of the present application, the seventh step of photolithography is performed. After the photolithography is completed, part of the passivation layer 11 and part of the edge removal layer 10 at the finger electrode region of the preset N-side electrode are etched away to expose the highly doped N-type semiconductor layer, so that the highly doped N-type semiconductor layer forms an ohmic contact with the subsequently prepared N-side electrode 13. The top view schematic diagram after etching the passivation layer 11 and the edge removal layer 10 is shown in FIG. Fig.12 shown.

[0079] Step S12: preparing the N-side electrode 13 .

[0080] After removing the photoresist in the seventh step of photolithography, the eighth step of photolithography is performed. After the photolithography is completed, the N-side electrode metal is evaporated first, and then the N-side electrode 13 is peeled off to complete the chip preparation. The structure of the prepared LED chip with electrostatic protection function is as follows Fig.14 , 15 As shown, Fig.15 yes Fig.14 Schematic cross-section at CC.

[0081] It should be noted that part of the passivation layer 11 and part of the edge removal layer 10 are left in the middle area of ​​the finger electrode of the N-side electrode 13 to improve the current expansion. Under the same current, compared with the tube core of the same size without retaining the passivation layer, the tube core of this solution has a more uniform light distribution, such as Fig.13 As shown, 13a is a light distribution diagram of an LED chip without retaining a passivation layer, and 13b is a light distribution diagram of an LED chip with retaining a portion of a passivation layer, and the lighting current of both is 100mA.

[0082] In some embodiments of the present application, for small-sized LEDs, such as 10 mil LEDs, the N-side electrode has no finger-shaped area, and it is necessary to etch part of the passivation layer 11 and part of the edge removal layer 10 in the pad area of ​​the N-side electrode so that the N-side electrode 13 can contact the N-type semiconductor layer 9 to form an ohmic contact.

[0083] In some embodiments of the present application, the material of the N-side electrode metal includes but is not limited to Cr / Pt / Au, Ti / Al / Ti / Pt / Au, Cr / Al / Cr / Pt / Au.

[0084] In some embodiments of the present application, the pad of the N-side electrode 13 is circular, square with rounded corners, racetrack-shaped, etc.

[0085] It should be noted that the chip with a thickness ranging from 6 mil to 80 mil can use the design method of the present application to improve the anti-electrostatic discharge capability, and the pad radius is designed to be 25 μm to 70 μm.

[0086] In a second aspect, an embodiment of the present application provides an LED chip with electrostatic protection function prepared by the above-mentioned preparation method.

[0087] In some embodiments of the present application, the LED chip with electrostatic protection function includes: substrate 2; An epitaxial layer, the epitaxial layer includes a P-type semiconductor layer 7, an active layer 8 and an N-type semiconductor layer 9 arranged in a direction away from the substrate; the epitaxial layer has a through channel, and the channel separates the epitaxial layer into a Schottky region and a light-emitting region; the N-type semiconductor layer 9 is composed of a highly doped N-type semiconductor layer close to the active layer and a low-doped N-type semiconductor layer away from the active layer; a through hole is provided on the side of the epitaxial layer close to the substrate 2 and at a position corresponding to the channel, and the through hole exposes the highly doped N-type semiconductor layer in the Schottky region; The N-side electrode 13 is disposed on the side of the epitaxial layer away from the substrate and forms an ohmic contact with the highly doped N-type semiconductor layer; The Schottky electrode 12 is disposed between the pad of the N-side electrode 13 and the N-type semiconductor layer 9 in the Schottky region; the Schottky electrode 12 forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky region; The edge removal layer 10 and the passivation layer 11 cover the channel and the chip surface; A reflective layer 6, provided on one side of the P-type semiconductor layer 7 in the light emitting region; The wafer bonding barrier layer 4 is arranged on the side of the epitaxial layer close to the substrate; the wafer bonding barrier layer 4 forms an ohmic contact with the highly doped N-type semiconductor layer in the Schottky region through the through hole; The dielectric layer 5 is disposed between the wafer bonding barrier layer 4 and the P-type semiconductor layer 7, isolating the wafer bonding barrier layer 4 from the P-type semiconductor layer 7, the active layer 8 and the reflective layer 6. At the cutting path of the LED chip, the dielectric layer 5 is disposed between the wafer bonding barrier layer 4 and the passivation layer 11; Wafer bonding adhesive layer 3, bonding wafer bonding barrier layer 4 and substrate 2; The back metal layer 1 is disposed on the other side of the substrate 2 . Example 1

[0088] This embodiment takes an LED chip with a size of 700 μm×700 μm as an example. Figure 1-15 As shown, the specific preparation process is as follows: Step S1: growing an N-type semiconductor layer 9 , an active layer 8 and a P-type semiconductor layer 7 in sequence on a substrate 14 .

[0089] Specifically, the substrate 14 is a silicon substrate, and the N-type semiconductor layer 9 , the active layer 8 and the P-type semiconductor layer 7 are GaN materials.

[0090] Step S2: Clean the substrate on which the epitaxial layer is grown first, and then perform the first step of photolithography, which is GaN etching photolithography. GaN etching photolithography includes six small steps: baking adhesive, coating positive photoresist, pre-baking, exposure, development and hardening. After the photolithography is completed, the position of the preset Schottky diode on the surface of the P-type semiconductor layer 7 is not protected by photoresist, and other positions are protected by photoresist. Then, ICP etching technology is used to start etching from the P-type semiconductor layer 7, and all P-type semiconductor layers 7 and active layers 8 are etched away. The etching depth is about 7000Å, and a through hole is etched to expose the highly doped N-type semiconductor layer. The N-type semiconductor layer 9 below the through hole is the N-type semiconductor layer of the Schottky diode. The shape of the etched through hole is cylindrical, with a radius of 31μm. The schematic diagram of the top view after etching is completed and the glue is removed is shown as follows Figure 1 As shown, the cross-sectional diagram is as follows Figure 2 shown.

[0091] Step S3: preparing a dielectric layer 5, wherein the dielectric layer 5 covers the sidewalls of the through hole.

[0092] Specifically, first use deionized water and alcohol ion ultrasonic cleaning, and then use PECVD technology to deposit a layer of silicon oxide on the surface of the P-type semiconductor layer 7. Then the second step of photolithography is carried out, which is dielectric layer photolithography, and also includes six small steps of baking adhesive, coating positive photoresist, pre-baking, exposure, development and hardening. After photolithography, the photolithography pattern is left, and then BOE is used to etch silicon oxide, and the remaining silicon oxide forms a dielectric layer 5. The dielectric layer 5 forms an annular cylinder in the side wall of the through hole and part of the bottom of the through hole, with a finger structure, and the tube core cutting path also leaves a dielectric layer.

[0093] In this embodiment, the dielectric layer 5 forms a circular cylinder with a large circle radius of 40 μm and a small circle radius of 23 μm on the side wall and part of the bottom of the through hole. The width of the finger-like structure of the dielectric layer 5 in the longitudinal direction is 18 μm, and the width in the lateral direction is 22 μm. The top view of the dielectric layer 5 after preparation is shown in FIG. Figure 3 As shown, the cross-sectional diagram is as follows Figure 4 As shown, Figure 4 yes Figure 3 Schematic diagram of the cross section along AA.

[0094] Step S4: After Mg is activated on the surface of the epitaxial layer (Mg-H bonds are broken by annealing method, Mg is activated to increase hole concentration, reduce voltage and improve light extraction efficiency), Ag is evaporated on the surface of the epitaxial layer by vacuum evaporation and other technologies, and then the third step of photolithography is performed. This photolithography is reflective layer photolithography, including 5 small steps of coating positive photoresist, pre-baking, exposure, development and hardening. The circular hole radius of the reflective layer photolithography is 35μm. After the epitaxial layer is photolithographically processed, the Ag at the corresponding position of the Schottky diode in the cutting path and the middle area is removed by wet etching, and finally the photoresist is removed to form a reflective layer 6. The top view schematic diagram after preparing the reflective layer 6 is shown as follows Figure 5 As shown, the cross-sectional diagram is as follows Figure 6 shown.

[0095] Step S5: After cleaning, a wafer bonding barrier layer 4 is prepared on the surface of the epitaxial layer using vacuum evaporation technology. The material of the wafer bonding barrier layer 4 is Cr / Pt / Ti. The wafer bonding barrier layer 4 forms an ohmic contact with the highly doped N-type semiconductor layer through the through hole. Then, a wafer bonding adhesive layer 3 is evaporated on the surface of the wafer bonding barrier layer 4. The material of the wafer bonding adhesive layer 3 is CuIn. During the eutectic process, In is in liquid state and fills the through hole to finally form a flat bonding interface. The cross-sectional schematic diagram of the preparation is shown as follows: Figure 7 shown.

[0096] Step S6: eutectic bonding is performed between the substrate 2 with the wafer bonding adhesive layer evaporated on the front side and the wafer bonding adhesive layer 3 , and the back side metal layer 1 is evaporated on the back side of the substrate 2 .

[0097] Step S7: After bonding is completed, the chip is turned over, and the silicon substrate is thinned first to a thickness of 215 μm to 245 μm, and the remaining silicon substrate is removed by wet etching. At this point, the low-doped N-type semiconductor layer is on the top.

[0098] Step S8: first use PECVD technology to deposit a protective layer of silicon oxide, and then perform the fourth step of photolithography, which is Schottky electrode protection photolithography. Schottky electrode photolithography includes 6 small steps of baking adhesive, coating positive photoresist, pre-baking, exposure, development and hardening. After completing Schottky electrode protection photolithography, the protective layer of the unprotected area is corroded. Then ICP etching technology is used to etch the low-doped N-type semiconductor layer in the unprotected area, and the high-doped N-type semiconductor layer is roughened to improve the light extraction efficiency of the chip. At this time, the low-doped N-type semiconductor layer in the unprotected area is completely removed, and the high-doped N-type semiconductor layer is roughened. The N-type semiconductor layer 9 in the preset Schottky electrode area is not etched and roughened, and the surface of the N-type semiconductor layer 9 in this area is a low-doped N-type semiconductor layer. After completing roughening, the photoresist is first removed with a degumming solution, and then the protective layer is corroded with a BOE solution.

[0099] In this embodiment, the Schottky electrode protection area is located in the middle of the chip and is circular. The radius of the circular hole in the Schottky electrode protection area is 20 μm.

[0100] Step S9: Grow a de-edging layer 10 on the surface of the N-type semiconductor layer, the material of which is silicon oxide, and then perform the fifth step of photolithography. This photolithography is de-edging photolithography, which includes six small steps: baking adhesive, coating positive photoresist, pre-baking, exposure, development, and hardening. The photoresist protects the light-emitting area and the Schottky diode area. The unprotected area is first etched with a BOE solution to etch the de-edging layer 10, and then a hot phosphoric acid solution is used to etch the semiconductor layer. The hot phosphoric acid solution corrodes the semiconductor layer of the cut path and the semiconductor layer around the Schottky diode to form a trench. After etching the semiconductor layer, the photoresist is removed with a de-edging solution. The top view schematic diagram after preparation is shown as follows. Figure 8 As shown, the cross-sectional diagram is as follows Fig. 9 As shown, Fig.10 yes Figure 8 A partial enlarged view of point B in the middle.

[0101] In this embodiment, the radius of the large circle of the edge-cutting photolithography is 35 μm, and the radius of the small circle is 27 μm. The width of the cutting road set by the edge-cutting photolithography is 20 μm, and the width of the cutting road set by the reflective layer photolithography is 32 μm.

[0102] Step S10: First, a layer of dense aluminum oxide is deposited on the surface of the edge removal layer 10 by atomic layer deposition method, and then a layer of silicon oxide is grown on the surface of the aluminum oxide by PECVD technology. Aluminum oxide and silicon oxide form a passivation layer 11. The passivation layer 11 covers the entire surface of the edge removal layer 10, the cutting path and cutting path sidewalls of the independent LED core, and the channel and channel sidewalls around the Schottky diode. After the passivation layer 11 is prepared, the sixth step of photolithography is performed. This photolithography is Schottky electrode photolithography. Schottky electrode photolithography includes six small steps of coating negative photoresist, pre-baking, exposure, post-baking, development and hardening. After completing the Schottky electrode photolithography, the passivation layer 11 and the edge removal layer 10 at the preset Schottky electrode position are etched away by BOE solution. Then, vacuum electron beam evaporation technology is used to evaporate Ni / Au on the entire surface of the chip. After evaporation, the Schottky metal in other parts is peeled off. The remaining Schottky metal is the Schottky electrode 12. The cross-sectional schematic diagram is shown in FIG. Fig.11 shown.

[0103] In this embodiment, the Schottky electrode 12 is located in the middle of the chip and is circular. The radius of the Schottky electrode 12 is 12 μm.

[0104] Step S11: After the passivation layer 11 is prepared, the seventh step of photolithography is performed. This photolithography is depassivation photolithography. The depassivation photolithography includes six small steps: baking adhesive, coating positive photoresist, pre-baking, developing, exposing and hardening. After the photolithography is completed, the BOE solution is used to etch away part of the passivation layer 11 and part of the edge removal layer 10 in the finger electrode area of ​​the preset N-side electrode to expose the highly doped N-type semiconductor layer, so that the highly doped N-type semiconductor layer 9 forms an ohmic contact with the subsequently prepared N-side electrode 13, leaving part of the passivation layer 11 and part of the edge removal layer 10 in the middle area of ​​the finger electrode of the N-side electrode 13. After the etching is completed, the photoresist needs to be removed with a degumming solution. The top view schematic diagram after etching the passivation layer 11 and the edge removal layer 10 is shown as follows Fig.12 shown.

[0105] In this embodiment, in the vertical direction of the depassivation lithography, the finger structure is set to have a width of 16 μm, a passivation layer is left in the middle area of ​​the finger structure, and the width is set to 5 μm; in the horizontal direction, the finger structure is set to have a width of 20 μm, a passivation layer is left in the middle area of ​​the finger structure, and the width is set to 8 μm.

[0106] Step S12: Perform the eighth step of photolithography, which is N-electrode photolithography. N-electrode photolithography includes six small steps: coating negative photoresist, pre-baking, developing, post-baking, exposing and hardening. After the photolithography is completed, the N-side electrode metal is evaporated on the chip by vacuum evaporation. After evaporation, the N-side electrode 13 is made by stripping. The N-side electrode 13 covers the Schottky electrode 12, the finger-shaped highly doped N-type semiconductor layer 9 and the passivation layer 11 in the middle of the finger-shaped area, and the chip is prepared. The structure of the prepared LED chip with electrostatic protection function is as follows: Fig.14 , 15 As shown, Fig.15 yes Fig.14 Schematic cross-section at CC.

[0107] In this embodiment, the pad of the N-side electrode 13 is circular with a radius of 35 μm. The finger electrode width of the N-side electrode 13 in the longitudinal direction is 8 μm, and the finger electrode width of the N-side electrode 13 in the transverse direction is 12 μm.

[0108] In this embodiment, the N-side electrode metal is Cr / Pt / Au.

[0109] In this embodiment, an LED chip with electrostatic protection function is prepared, and the structure is as follows Fig.15As shown, it includes: a substrate 2; an epitaxial layer, the epitaxial layer includes a P-type semiconductor layer 7, an active layer 8 and an N-type semiconductor layer 9 arranged in a direction away from the substrate 2; the N-type semiconductor layer is composed of a high-doped N-type semiconductor layer close to the active layer and a low-doped N-type semiconductor layer away from the active layer; the epitaxial layer has a through channel, and the channel separates the epitaxial layer into a Schottky region and a light-emitting region; a through hole is provided on the side of the epitaxial layer close to the substrate 2 and at a position corresponding to the channel, and the through hole exposes the high-doped N-type semiconductor layer in the Schottky region; an N-side electrode 13 is provided on the side of the epitaxial layer away from the substrate, and forms an ohmic contact with the high-doped N-type semiconductor layer; a Schottky electrode 12 is provided between the pad of the N-side electrode 13 and the N-type semiconductor layer 9 in the Schottky region; the Schottky electrode 1 2 forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky area; a trimming layer 10 and a passivation layer 11 cover the channel and the chip surface; a reflective layer 6 is arranged on one side of the P-type semiconductor layer 7 in the light-emitting area; a wafer bonding barrier layer 4 is arranged on the side of the epitaxial layer close to the substrate 2; the wafer bonding barrier layer 4 forms an ohmic contact with the high-doped N-type semiconductor layer in the Schottky area through the through hole; a dielectric layer 5 is arranged between the wafer bonding barrier layer 4 and the P-type semiconductor layer 7, isolating the wafer bonding barrier layer 4 from the P-type semiconductor layer 7, the active layer 8 and the reflective layer 6, and is arranged between the wafer bonding barrier layer 4 and the passivation layer 11 at the cutting path; a wafer bonding adhesive layer 3 adheres the wafer bonding barrier layer 4 and the substrate 2; a back metal layer 1 is arranged on the other side of the substrate 2.

[0110] The wafer bonding barrier layer 4, the N-type semiconductor layer 9 in ohmic contact with the wafer bonding barrier layer 4, and the Schottky electrode 12 form a Schottky diode; the wafer bonding barrier layer 4 is the cathode of the Schottky diode, and the Schottky electrode 12 is the anode of the Schottky diode. The Schottky diode and the LED chip form a reverse parallel connection to improve the anti-static discharge capability of the LED chip. The Schottky diode is placed under the pad of the N-side electrode 13 of the LED chip, and does not occupy the light-emitting area separately, so as to realize the electrostatic protection of the LED chip without sacrificing the light power.

[0111] In addition, a passivation layer 11 and a trimming layer 10 with a smaller size than the finger electrodes are left under the finger electrodes of the N-side electrode 13, which can improve the current expansion of the LED chip. Under high current, the current distribution of the LED chip is more uniform.

[0112] In the description of this specification, the description of "some embodiments" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0113] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing an LED chip with an electrostatic protection function, characterized in that: The following steps are involved: S1: growing an epitaxial layer on a substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer stacked in sequence from bottom to top; S2: etching a through hole in the epitaxial layer to expose the N-type semiconductor layer; S3: preparing a dielectric layer, wherein the dielectric layer covers the sidewall of the through hole; S4: preparing a reflective layer on the surface of the P-type semiconductor layer; S5: preparing a wafer bonding barrier layer and a wafer bonding adhesive layer on the surface of the epitaxial layer, wherein the wafer bonding barrier layer fills the through hole and forms an ohmic contact with the N-type semiconductor layer through the through hole, and the wafer bonding adhesive layer fills the through hole; S6: eutectic bonding the wafer bonding adhesive layer to the wafer bonding adhesive layer on the substrate; S7: removing the substrate to expose one side of the N-type semiconductor layer; S8: protecting the N-type semiconductor layer in the Schottky electrode area, and etching and roughening the N-type semiconductor layer in other unprotected areas; S9: preparing a trimming layer on the surface of the exposed N-type semiconductor layer, and photolithography the epitaxial layer and the trimming layer to form a channel; S10: preparing a passivation layer, and preparing a Schottky electrode on the surface of the N-type semiconductor layer and at a position corresponding to the through hole; S11: Patterning passivation layer and edge removal layer; S12: Prepare N electrode.

2. The method for preparing an LED chip according to claim 1, wherein: The N-type semiconductor layer grown in step S1 consists of a low-doped N-type semiconductor layer close to the substrate and a high-doped N-type semiconductor layer far from the substrate.

3. The method for preparing an LED chip according to claim 1, wherein: The wafer bonding barrier layer, the N-type semiconductor layer in ohmic contact with the wafer bonding barrier layer, and the Schottky electrode form a Schottky diode; the wafer bonding barrier layer is the cathode of the Schottky diode, and the Schottky electrode is the anode of the Schottky diode.

4. The method for preparing an LED chip according to claim 1, wherein: The N-side electrode prepared in step S12 includes a pad and a finger electrode. The pad of the N-side electrode is located on the surface of the Schottky electrode, and the pad size of the N-side electrode is larger than that of the Schottky electrode.

5. The method for preparing an LED chip according to claim 4, wherein: The position of the through hole prepared in step S2 corresponds to the pad of the N-side electrode; the shape of the through hole is consistent with the shape of the pad of the N-side electrode.

6. The method for preparing an LED chip according to claim 5, wherein: The through hole is cylindrical; the dielectric layer covers the side wall of the through hole to form an annular cylinder, and the pad size of the N-side electrode is smaller than the large circle size of the annular cylinder formed by the dielectric layer; the dielectric layer also includes a finger-shaped area, and the finger-shaped area corresponds to the position of the finger-shaped electrode of the N-side electrode, and the width of the finger-shaped electrode of the N-side electrode is smaller than the width of the finger-shaped area of ​​the dielectric layer.

7. The method for preparing an LED chip according to claim 3, wherein: The trench in step S9 includes the cutting road and the trench around the Schottky diode. The trench around the Schottky diode separates the Schottky diode from the epitaxial layer of the light emitting region of the LED chip.

8. The method for preparing an LED chip according to claim 4, wherein: When the passivation layer and the edge removal layer are patterned in step S11, the pattern includes a finger region, and the passivation layer and the edge removal layer are left in the middle region of the finger. The size of the retained passivation layer and the edge removal layer is smaller than the finger electrode of the N-side electrode.

9. An LED chip with electrostatic protection function, characterized in that: The method is prepared according to any one of claims 1 to 8.

10. The LED chip with electrostatic protection function according to claim 9, characterized in that: The LED chip comprises: substrate; An epitaxial layer, the epitaxial layer comprising a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in a direction away from the substrate; the N-type semiconductor layer is composed of a highly doped N-type semiconductor layer close to the active layer and a low doped N-type semiconductor layer away from the active layer; the epitaxial layer has a through channel, the channel separates the epitaxial layer into a Schottky region and a light emitting region; a through hole is provided at a position corresponding to the channel on one side of the epitaxial layer close to the substrate, the through hole exposes the highly doped N-type semiconductor layer in the Schottky region; An N-side electrode is disposed on a side of the epitaxial layer away from the substrate and forms an ohmic contact with the highly doped N-type semiconductor layer; The Schottky electrode is disposed between the pad of the N-side electrode and the N-type semiconductor layer in the Schottky region; the Schottky electrode forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky region; Edge removal layer and passivation layer, covering the channel and chip surface; A reflective layer, disposed on one side of the P-type semiconductor layer in the light emitting region; A wafer bonding barrier layer is provided on a side of the epitaxial layer close to the substrate; the wafer bonding barrier layer forms an ohmic contact with the highly doped N-type semiconductor layer in the Schottky region through the through hole; The dielectric layer is disposed between the wafer bonding barrier layer and the P-type semiconductor layer, isolating the wafer bonding barrier layer from the P-type semiconductor layer, the active layer and the reflective layer; at the cutting path of the LED chip, the dielectric layer is disposed between the wafer bonding barrier layer and the passivation layer; Wafer bonding adhesive layer, wafer bonding barrier layer and substrate; The back metal layer is arranged on the other side of the substrate.

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