Display device

Abstract

The present disclosure relates to a display device including: a display panel including a display area and a non-display area; and a driving chip disposed in the non-display area. The display panel includes an anti-cracking pattern disposed such that at least a portion of the anti-cracking pattern overlaps an edge of one short side of the driving chip. As a result, moisture penetration and metal corrosion are prevented, so that reliability of the display device can be improved, and deformation of the display panel can be minimized.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device capable of improving reliability. Background Art

[0002] Display devices that display images or videos on TVs, monitors, smart phones, tablet PCs, laptop computers, etc. are used in various types and forms.

[0003] The display device includes a plurality of light emitting devices or liquid crystals, and a display panel including a transistor for controlling the operation of each light emitting device or liquid crystal. The display device displays an image or video to be displayed through the plurality of light emitting devices or liquid crystals.

[0004] An organic light-emitting display device including a self-luminous device can be thinner than a display device with a built-in light source and does not require a separate light source. Therefore, a display device that can be bent or has various designs can be manufactured.

[0005] With the development of information society, the field of display devices that visually display electrical information signals is rapidly growing. In addition, research is being conducted on performance improvements of various display devices, such as being thinner, consuming less power, and achieving reliability. Summary of the invention

[0006] An object of an embodiment of the present disclosure is to provide a display device which improves reliability by preventing moisture penetration caused by lift-up of an insulating layer around a driving chip and by preventing corrosion defects of a pad or a wiring.

[0007] An object of an embodiment of the present disclosure is to provide a display device that prevents stress from being accumulated when a driving chip is mounted on a display panel and prevents cracks from occurring around the driving chip, thereby reducing deformation of the display panel.

[0008] An object of an embodiment of the present disclosure is to provide a display device that is capable of reducing energy utilization for producing a display device by utilizing the same process and by reducing or minimizing the occurrence of defects in the display device, and is capable of reducing the use of harmful production materials or regulated materials, so that the display device is conducive to recycling and leads to the realization of an environmentally friendly display device.

[0009] One embodiment is a display device, comprising: a display panel including a display area and a non-display area; and a driver chip disposed in the non-display area. The display panel includes a crack prevention pattern, the crack prevention pattern being arranged so that at least a portion of the crack prevention pattern overlaps an edge of a short side of the driver chip.

[0010] The crack prevention pattern may be disposed in the non-display region in a direction parallel to an edge of one short side of the driving chip.

[0011] The crack prevention pattern may be disposed on both short sides of the driving chip to be parallel to the short sides of the driving chip such that at least a portion of the crack prevention pattern overlaps edges of the two short sides of the driving chip.

[0012] At least a portion of the crack prevention pattern may be disposed to overlap an edge of the driving chip.

[0013] The crack prevention pattern may be disposed to overlap four points of the edge of the driving chip.

[0014] The display panel may include: a substrate; a plurality of insulating layers stacked on the substrate and disposed in the non-display area; a planarization layer disposed on the plurality of insulating layers and on the crack prevention pattern; and a first pad disposed to be spaced apart from the crack prevention pattern. The planarization layer may be disposed on the insulating layer exposed to a spacing space between the crack prevention pattern and the first pad and on one side of the first pad.

[0015] An edge of one short side of the driving chip may overlap the planarization layer and overlap the crack prevention pattern.

[0016] The display device may further include an anisotropic conductive film disposed between the driving chip and the first pad. The anisotropic conductive film may overlap at least a portion of the planarization layer and the crack prevention pattern at an edge of one short side of the driving chip.

[0017] The crack prevention pattern may be formed as an embossed pattern including a metal layer.

[0018] The display device may further include: a first pad disposed in the non-display area toward the display area; and a second pad disposed in a direction opposite to the display area while facing the first pad. The first pad and the second pad may overlap with two long sides of the driving chip, and the crack prevention pattern may be disposed to be spaced apart from the first pad and the second pad so as not to overlap with the first pad and the second pad.

[0019] The crack prevention pattern may be made of the same material as the first pad or the second pad.

[0020] At least a portion of the crack prevention pattern may not overlap with edges of both short sides of the driving chip, and a plurality of the crack prevention patterns may be disposed spaced apart from each other in such a manner as to overlap with four points of the edge of the driving chip.

[0021] The crack prevention pattern according to the embodiment of the present disclosure is arranged so that at least a portion of the crack prevention pattern overlaps with the edge of the short side of the driving chip, thereby preventing stress accumulation and stress generation due to pressure, etc. when the driving chip is installed. Therefore, the display panel can be prevented from being deformed due to stress or cracks can be prevented from occurring on the display panel due to interference with the driving chip.

[0022] According to the display device of the present embodiment, the crack prevention pattern of the embodiment of the present disclosure is arranged to overlap with the edge of the short side of the driving chip, thereby preventing cracks around the driving chip when the driving chip is bonded. As a result, moisture penetration due to cracks, lifting of the surrounding insulating layer due to moisture penetration, and cracks in the surrounding insulating layer due to lifting can be prevented from occurring.

[0023] Since the crack prevention pattern according to the embodiment of the present disclosure can prevent cracks from occurring in the insulating layer provided around the driving chip, the surrounding pads or wirings can be prevented from being corroded or broken due to the cracks in the insulating layer and moisture penetration. In addition, the crack prevention pattern according to the present disclosure can prevent cracks and moisture penetration, thereby reducing deformation of the display panel.

[0024] In the display device according to the present disclosure, the crack prevention pattern is arranged so that at least a portion of the crack prevention pattern overlaps with the edge of the driving chip, thereby blocking moisture penetration and preventing corrosion of metal arranged in the non-display area of ​​the display device. As a result, the reliability of the display device can be improved.

[0025] According to the display device of this embodiment, when a metal layer is provided as a crack prevention pattern, rigidity can be obtained so that when a driver chip is mounted, the crack prevention pattern can resist pressure such as pressure, thereby preventing cracks from being generated around the driver chip. Therefore, deformation of the display panel can be reduced with a more improved effect.

[0026] According to the display device of this embodiment, the crack prevention pattern is set using the same process, and the crack prevention pattern reduces or minimizes the occurrence of defects in the display device. Therefore, the energy utilization used to produce the display device can be reduced, and the use of dangerous production materials or conditioning materials can be reduced, making the display device favorable for recycling and an environmentally friendly display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a plan view of a display device according to an embodiment;

[0028] Figure 2 is a circuit diagram of a sub-pixel according to an embodiment;

[0029] Figure 3 yes Figure 1 an enlarged partial plan view of portion “A” of the embodiment;

[0030] Figure 4 is based on Figure 1 A partial plan view of a driving circuit region of an embodiment of the plan view;

[0031] Figure 5 is based on Figure 1 A partial plan view of a driving circuit region of another embodiment of the present invention in a plan view; and

[0032] Figure 6 Shown along Figure 4 An embodiment of a cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0034] The same reference numerals correspond to the same components. In addition, in the drawings, in order to effectively describe technical details, the thickness, proportion and size of the components may be exaggerated. Since the components shown in the drawings have a proportion different from their actual proportion for the convenience of description, these components are not limited to the proportions shown in the drawings.

[0035] In this specification, when referring to a component (or region, layer, part) being "on another component", "connected to another component" or "combined with another component", the terms "on another component", "connected to another component" or "combined with another component" mean that the component can be directly connected to another component / combined with another component, or mean that a third component can be set between them.

[0036] The term "and / or" includes all of one or more combinations that the relevant configurations can define.

[0037] Although terms such as first and second etc. can be used to describe various components, these components are not limited by the above terms. These terms are only used to distinguish one component from other components. For example, without departing from the scope of rights of each embodiment, a first component can be designated as a second component. Similarly, a second component can be designated as a first component. Expressions in the singular include expressions in the plural form unless otherwise clearly mentioned in the context.

[0038] Terms such as "below", "lower", "above", "upper" and the like are used to describe the relationship between the components shown in the drawings. These terms have related concepts and are described based on the directions shown in the drawings. As long as the terms "directly" or "immediately" are not used, one or more other components can be located between two components. For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like can be used to describe the correlation between one element or component and another element or component. Spatially relative terms can be understood to include different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, when the elements shown in the drawings are inverted, the elements described as "below another element" or "below another element" can be placed above the other element. Therefore, the exemplary term "below" can include an upward direction and a downward direction.

[0039] In this specification, it should be understood that the terms "include" or "comprising" and the like are intended to specify features, quantities, steps, operations, components, parts, or any combination thereof, and are not intended to previously exclude the possibility of the existence or addition of at least one other feature, quantity, step, operation, component, part, or any combination thereof.

[0040] The features of various embodiments of the present disclosure may be partially or completely connected or combined with each other, and these features may be connected and driven in various ways in technology. In addition, the embodiments may be implemented independently of each other, or implemented together in an associated relationship.

[0041] Hereinafter, a display device of the present disclosure will be described with reference to the accompanying drawings and embodiments. Figure 1 is a plan view of a display device according to an embodiment. Figure 2 is a circuit diagram of a sub-pixel according to an embodiment.

[0042] Reference Figure 1 and Figure 2 , the display device 100 according to an embodiment of the present disclosure includes: a display panel 110, which includes a display area AA and a non-display area NA; and a driving chip 107, which is disposed in the non-display area NA of the display panel 110. The driving chip 107 may be disposed in a driving circuit area 109 of the non-display area NA. The display panel 110 includes a crack prevention pattern 170, which is disposed to at least partially overlap the driving chip 107 in the driving circuit area 109.

[0043] The display area AA displays an image. A plurality of sub-pixels SP are disposed in the display area AA of the display panel 110, and images may be displayed using these sub-pixels SP. The area where the plurality of sub-pixels SP are disposed may be the display area AA, and an area other than the display area AA may be a non-display area NA.

[0044] Reference Figure 2 , at least one sub-pixel SP among the plurality of pixels includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

[0045] A first electrode (e.g., drain) of the switching transistor SW is electrically connected to the data line DL, and a second electrode (e.g., source) of the switching transistor SW is electrically connected to the first node N1. A gate of the switching transistor SW is electrically connected to the gate line GL. The switching transistor SW transmits a data signal provided through the data line DL to the first node N1 in response to a scan signal provided through the gate line GL.

[0046] The capacitor Cst is electrically connected to the first node N1 and is charged by a voltage applied to the first node N1.

[0047] A first electrode (e.g., drain) of the driving transistor DR is applied with a high potential driving voltage EVDD, and a second electrode (e.g., source) of the driving transistor DR is electrically connected to a first electrode (e.g., anode) of the organic light emitting diode OLED. The driving transistor DR can control the amount of driving current flowing through the organic light emitting diode OLED in response to a voltage applied to a gate of the driving transistor DR.

[0048] The semiconductor layer of the switching transistor SW and / or the driving transistor DR may include silicon such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si), or may include an oxide such as indium gallium zinc oxide (IGZO), etc. However, the present embodiment is not limited thereto.

[0049] The organic light emitting diode OLED outputs light corresponding to the driving current. The organic light emitting diode OLED may output light corresponding to any one of red, green, blue, and white.

[0050] The organic light emitting diode OLED may include an anode, a light emitting layer disposed on the anode, and a cathode providing a common voltage. The light emitting layer may be implemented to emit the same color light for each pixel, such as white light, or to emit different color light for each sub-pixel SP, such as red light, green light, or blue light.

[0051] The organic light emitting diode OLED may be a front emitting diode or a rear emitting diode.

[0052] The compensation circuit CC may be provided in the sub-pixel SP to compensate for the threshold voltage of the driving transistor DR. The compensation circuit CC may be composed of one or more transistors. The compensation circuit CC may include one or more transistors and capacitors and may be configured in various ways according to the compensation method. The pixel including the compensation circuit CC may have various structures, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0053] like Figure 1 As shown, the non-display area NA may be formed in an edge area surrounding the display area AA displaying an image. The non-display area NA includes a driving circuit area 109 for driving a plurality of sub-pixels SP, and at least one driving chip 107 may be disposed in the driving circuit area 109. The driving chip 107 may be in the form of a driving integrated circuit (D-IC). The driving chip 107 may be mounted in the non-display area NA of the display panel 110 using a chip on board (COP) method. The driving chip 107 may be used as a data driving circuit.

[0054] The driving circuit region 109 may further include a gate driving circuit (not shown) provided in the non-display area NA in the form of a gate on plate (GIP).

[0055] Figure 3 yes Figure 1 An enlarged partial plan view of portion "A". Figure 4 is based on Figure 1 A partial plan view of a driving circuit region of an embodiment of the plan view.

[0056] refer to Figure 3 and Figure 4 The display panel 110 may further include first and second pads PAD1 and PAD2 electrically connected to the driving chip 107 disposed in the non-display area NA, and may further include a plurality of wirings W1, W2, and L1 disposed in the non-display area NA and electrically connected to the pads PAD1 and PAD2.

[0057] The driving chip 107 may be disposed in the non-display area NA of the display panel 110 using a chip-on-board (COPF) method. The COP method is to use an anisotropic conductive film (ACF, see Figure 6 ) Attach the driver IC directly to the pads on the substrate.

[0058] The driving chip 107 receives a signal required to drive the display panel 110 from the outside, and provides or transmits the signal to the display panel 110. The driving chip 107 may be a source driver integrated circuit that provides data signals to the data lines DL of the display area AA. However, the driving chip 107 is not limited thereto.

[0059] The driving chip 107 is electrically connected to the display panel 110 through the second pad PAD2 and the first pad PAD1. The driving chip 107 receives a signal from the outside through the second wiring W2 and the second pad PAD2. The driving chip 107 can provide the signal received from the outside to the display area AA through the first pad PAD1, the first wiring W1 and the connection line L1.

[0060] The first pad PAD1 is disposed closer to the display area AA than the second pad PAD2.

[0061] The first pads PAD1 may be arranged in a plurality of rows. A plurality of first pads PAD1 arranged in a row are arranged to be spaced apart from each other. The first pads PAD1 are exemplarily shown as being arranged in three rows, but are not limited thereto, and may be arranged in two rows or less or four rows or more. The first pads PAD1 may have a short side and a long side. The short side of the first pads PAD1 may be perpendicular to the long side of the driving chip 107.

[0062] The first pads PAD1 are connected to the connection line L1 and the first wiring W1. The plurality of first pads PAD1 may be connected to the connection line L1 and the first wiring W1 one-to-one. The connection line L1 may be connected to the data line DL of the display area AA.

[0063] The first pad PAD1 may be disposed on the same layer as a layer on which one of the plurality of adjacent wirings, such as the first wiring W1, the third wiring W3, the connection line L1, and the fourth wiring W4, is disposed. The first pad PAD1 is made of the same material as one of the plurality of adjacent wirings, such as the first wiring W1, the third wiring W3, the connection line L1, and the fourth wiring W4.

[0064] The first pad PAD1 may be disposed on the same layer as the second wiring W2 provided with the second pad PAD2 electrically connected to the first pad. The first pad PAD1 may be made of the same material as the second wiring W2.

[0065] The first pad PAD1 is formed by an anisotropic conductive film 103 (see Figure 6 ) is connected to the driver chip 107. Here, the bump 105 (see Figure 6 ) and the first pad PAD1 are electrically connected. The first pad PAD1 may be connected to the bump 105 one-to-one. Therefore, the first pad PAD1 may receive a voltage and a signal applied to the driving chip 107 through the bump 105.

[0066] The second pads PAD2 may be arranged in a single row. A plurality of second pads PAD2 arranged in a row are arranged to be spaced apart from each other. The second pads PAD2 are exemplarily shown as being arranged in a row, but are not limited thereto, and may be arranged in two or more rows. The second pads PAD2 may have a short side and a long side. The short side of the second pads PAD2 may be perpendicular to the long side of the driving chip 107.

[0067] The second pads PAD2 are connected to the second wirings W2. A plurality of second pads PAD2 may be connected to the second wirings W2 one by one. Each second wiring W2 may be connected to an external circuit board (not shown).

[0068] The second pad PAD2 may be disposed on the same layer as a layer in which a second wiring W2 electrically connected to the second pad PAD2 is disposed. The second pad PAD2 may be made of the same material as the second wiring W2. The second pad PAD2 may be disposed on the same layer as one of a plurality of wirings (e.g., the first wiring W1, the third wiring W3, the connection line L1, and the fourth wiring W4) adjacent to the first pad PAD1 located on the opposite side of the second pad is disposed. The second pad PAD2 may be made of the same material as one of the first wiring W1, the third wiring W3, the connection line L1, and the fourth wiring W4.

[0069] The second pad PAD2 is formed by an anisotropic conductive film 103 (see Figure 6 ) is connected to the driver chip 107. Here, the bump 105 (see Figure 6 ) is electrically connected to the second pad PAD2. The second pad PAD2 can be connected to the bump 105 one-to-one. Therefore, the second pad PAD2 can provide external voltage and signal to the driving chip 107 through the bump 105.

[0070] The structures of the first pad PAD1 and the second pad PAD2 may be substantially the same.

[0071] The first wiring W1 may connect the first pad PAD1 and some signal lines (eg, the gate line GL). The first wiring W1 may be a gate control line.

[0072] The connection line L1 may connect the first pad PAD1 and some signal lines (eg, the data line DL).

[0073] The first wiring W1 and the connection line L1 may be disposed on the same layer. The first wiring W1 and the connection line L1 may be made of the same material.

[0074] The first wirings W1 and the connection lines L1 may be disposed in a direction intersecting the long sides of the driving chip 107 .

[0075] The second wiring W2 is disposed at one side of the display panel 110 and connects the second pad PAD2 and an external circuit board (not shown). For example, the external circuit board may be a flexible circuit board (FPC). The second wiring W2 may be disposed in a direction intersecting with the long side of the driving chip 107.

[0076] The second wiring W2 and the connection line L1 may be disposed on the same layer. The second wiring W2 and the connection line L1 may be made of the same material.

[0077] The display panel 110 may further include third and fourth wirings W3 and W4 disposed in the non-display area NA around the driving chip 107 .

[0078] The third wiring W3 may be spaced apart from the driving chip 107 without being electrically connected to the driving chip 107, and may be disposed in a direction parallel to a short side of the driving chip 107. The third wiring W3 may be a power wiring.

[0079] The third wiring W3 may be disposed on the same layer as the layer on which the first wiring W1 is disposed. The third wiring W3 and the first wiring W1 may be made of the same material. The third wiring W3 may be disposed on the same layer as the layer on which the connection line L1 is disposed. The third wiring W3 and the connection line L1 may be made of the same material.

[0080] The third wiring W3 may be disposed on the same layer as the layer on which the second wiring W2 is disposed. The third wiring W3 and the second wiring W2 may be made of the same material. The third wiring W3 may be disposed on the same layer as the layer on which the fourth wiring W4 is disposed. The third wiring W3 and the fourth wiring W4 may be made of the same material.

[0081] The fourth wiring W4 may be disposed in a direction intersecting a short side of the driving chip 107. The fourth wiring W4 may be a multiplexer driving line or a test line.

[0082] The fourth wiring W4 may be disposed on the same layer as the layer on which the first wiring W1 is disposed. The fourth wiring W4 and the first wiring W1 may be made of the same material. The fourth wiring W4 may be disposed on the same layer as the layer on which the connection line L1 is disposed. The fourth wiring W4 and the connection line L1 may be made of the same material.

[0083] The fourth wiring W4 may be disposed on the same layer as the layer on which the second wiring W2 is disposed. The fourth wiring W4 and the second wiring W2 may be made of the same material. The fourth wiring W4 may be disposed on the same layer as the layer on which the third wiring W3 is disposed. The fourth wiring W4 and the third wiring W3 may be made of the same material.

[0084] The fourth wiring W4 may be disposed to overlap with the crack prevention pattern 170 , and the crack prevention pattern 170 is disposed to at least partially overlap with the short side of the driving chip 107 .

[0085] The crack prevention pattern 170 may be disposed in the non-display area NA of the display panel 110 so that at least a portion of the crack prevention pattern 170 overlaps with an edge CE of one short side of the driving chip 107. Figure 4 shown.

[0086] The crack prevention pattern 170 may be disposed in the non-display area NA of the display panel 110 in a direction parallel to the edge CE of one short side of the driving chip 107. The crack prevention pattern 170 may be disposed on both short sides of the driving chip 107 to be parallel to the short sides of the driving chip 107 so that at least a portion of the crack prevention pattern 170 overlaps with the edge CE of both short sides of the driving chip 107.

[0087] The length of the crack prevention pattern 170 may be greater than the length of the edge CE of the short side of the driving chip 107. Specifically, at least a portion of the crack prevention pattern 170 may be disposed to overlap the edge of the driving chip 107. The crack prevention pattern 170 may be disposed to overlap four points of the edge of the driving chip 107.

[0088] The crack prevention pattern 170 is disposed to overlap four points of the edge of the driving chip 107 , so that the occurrence of interference caused by the driving chip 107 in the edge region of the driving chip, where interference from the driving chip 107 is relatively easy to occur, can be reduced.

[0089] The crack prevention pattern 170 may be disposed to be spaced apart from the first and second pads PAD1 and PAD2 so as not to overlap the first and second pads PAD1 and PAD2 .

[0090] Specifically, the crack prevention pattern 170 may be disposed to be spaced apart from the first pad PAD1 so as not to overlap with the first pad PAD1, which is disposed toward the display area AA in the non-display area NA and overlaps with one long side of the driving chip 107. The crack prevention pattern 170 may be disposed to be spaced apart from the second pad PAD2 so as not to overlap with the second pad PAD2, which is disposed in a direction opposite to the display area AA while facing the first pad PAD1 and overlapping with the other long side of the driving chip 107.

[0091] The crack prevention pattern 170 may be formed in an embossed pattern based on the top surface of the substrate 111 of the display panel 110 .

[0092] As described above, in the driver chip 107, the COP method attaches the source driver IC to the substrate 111. Therefore, an indentation test or the like is performed to check the connection state of the driver chip 107, and in order to prevent poor connection of the driver chip 107, a high voltage may be applied when the driver chip 107 is bonded to the substrate 111. Relatively few wirings are provided in the non-display area NA (such as the short side of the driver chip 107), so that when the driver chip is installed, stress caused by pressure or the like is easily accumulated. Therefore, the anti-crack pattern 170 according to the embodiment of the present disclosure is provided to overlap with the edge CE of the short side of the driver chip 107, which is prone to stress. Therefore, it is possible to prevent the display panel 110 from being deformed due to stress when the driver chip 107 is installed, or to prevent cracks from occurring in the display panel 110 due to interference with the driver chip 107.

[0093] The crack prevention pattern 170 of the embodiment of the present disclosure is disposed to overlap with the edge CE of the short side of the driving chip 107, thereby preventing cracks around the driving chip 107 when the driving chip 107 is bonded. As a result, moisture penetration due to cracks can be prevented, and surrounding insulating layers (e.g., Figure 6 The gate insulating layer 123 or the interlayer insulating layer 125 shown in FIG. 1 may be lifted, and cracks may occur in the surrounding insulating layer due to the lifting.

[0094] Since the crack prevention pattern 170 according to the embodiment of the present disclosure can prevent cracks from occurring in the insulating layer disposed around the driving chip 107, the surrounding pads PAD1 and PAD2 or the plurality of wirings W1, W2, W3, W4 and L1 can be prevented from being corroded or broken by moisture penetration due to cracks in the insulating layer.

[0095] The crack prevention pattern 170 according to an embodiment of the present disclosure may prevent cracks and moisture penetration, thereby reducing deformation of the display panel 110 .

[0096] The crack prevention pattern 170 may be formed as a pattern including a metal layer.

[0097] When a metal layer is provided as the crack prevention pattern 170, rigidity can be obtained so that when the driving chip 107 is mounted, the crack prevention pattern can resist pressure-like pressing, thereby preventing cracks from being generated around the driving chip 107. Therefore, deformation of the display panel 110 can be reduced.

[0098] The metal layer may be made of a material forming a source / drain or gate of a driving transistor or a switching transistor disposed in the display area constituting the display panel 110. The crack prevention pattern 170 may include the same material as a source / drain or gate of a switching transistor constituting the display area AA.

[0099] In this manner, when the crack prevention pattern 170 is provided using the same material and the same process as that of the electrode provided in the display area AA, energy utilization for producing a display device may be reduced by reducing process steps.

[0100] The crack prevention pattern 170 may be made of the same material as the first pad PAD1 disposed in the non-display area NA and electrically connected to the driving chip 107. The crack prevention pattern 170 may be disposed on the same layer as the layer on which the first pad PAD1 is disposed. The crack prevention pattern 170 may be made of the same material as the second pad PAD2 disposed in the non-display area NA and electrically connected to the driving chip 107. The crack prevention pattern 170 may be disposed on the same layer as the layer on which the second pad PAD2 is disposed.

[0101] In this way, when the anti-crack pattern 170 is set using the same material as the material of the first pad PAD1 or the second pad PAD2 set in the non-display area NA and the same process as the first pad PAD1 material or the second pad PAD2 material set in the non-display area NA, the energy utilization for manufacturing the display device can be reduced by reducing the process steps.

[0102] The crack prevention pattern 170 may be disposed on the same layer as a layer where one of the plurality of wirings W1, W2, W3, W4, and L1 disposed in the non-display area NA is disposed and may be made of the same material as one of the plurality of wirings W1, W2, W3, W4, and L1.

[0103] As described above, when the crack prevention pattern 170 is disposed on the display device in the same process by using an electrode material forming process, a pad forming process, or a wiring forming process, the manufacturing process for manufacturing the display device can be reduced. Therefore, greenhouse gases generated by the manufacturing process can be reduced, and thus environmental / social / governance (ESG) can be achieved.

[0104] like Figure 3 As shown, the crack prevention pattern 170 is disposed not to overlap one of the plurality of wirings W1 , W2 , W3 , W4 , and L1 disposed adjacent to each other in the non-display area NA.

[0105] The crack prevention pattern 170 may overlap one of the plurality of wirings W1, W2, W3, W4, and L1 disposed adjacent to each other in the non-display area NA. For example, when the crack prevention pattern 170 overlaps the fourth wiring W4 disposed to overlap one short side of the driving chip 107, the crack prevention pattern 170 and the fourth wiring W4 may be disposed in different layers. Here, the crack prevention pattern 170 may be made of a material different from that of the fourth wiring W4.

[0106] The crack prevention pattern 170 includes a metal layer, but is floating so that no voltage and signal are applied.

[0107] Figure 5 is based on Figure 1 A partial plan view of a driving circuit region of another embodiment of the plan view. Figures 1 to 4 Components having the same reference numerals as those described above may be denoted by reference numerals as those in the reference Figures 1 to 4 The embodiments described above can be applied or implemented in the same manner, or can be combined with reference to Figures 1 to 4 The description of the components with the same reference numerals will be omitted.

[0108] Reference Figure 5 The crack prevention pattern 270 may be disposed such that at least a portion thereof overlaps with the edges CE of both short sides of the driving chip 107 in the non-display area NA of the display panel 110 , and at least a portion thereof does not overlap.

[0109] The plurality of crack prevention patterns 270 may be disposed to be spaced apart from each other so as to overlap four points of the edge of the driving chip 107 .

[0110] The crack prevention pattern 270 may include first, second, third, and fourth crack prevention patterns 271, 272, 273, and 274. The first to fourth crack prevention patterns 271 to 274 may be disposed to overlap four points of the edge of the driving chip 107, respectively.

[0111] Specifically, the first crack prevention pattern 271 may be disposed in the non-display area NA of the display panel 110 in a direction parallel to the edge CE of one short side of the driving chip 107, so that at least a portion of the first crack prevention pattern 271 overlaps with the edge CE of one short side of the driving chip 107, and at least a portion of the first crack prevention pattern 271 does not overlap with the edge CE of one short side of the driving chip 107. The first crack prevention pattern 271 may be disposed so that at least a portion of the first crack prevention pattern 271 overlaps with one long side of the driving chip 107.

[0112] The first crack prevention pattern 271 may be disposed adjacent to the first pad PAD1 and spaced apart from the first pad PAD1 so as not to overlap with the first pad PAD1.

[0113] The length of the first crack prevention pattern 271 may be smaller than the length of the edge CE of the short side of the driving chip 107. The first crack prevention pattern 271 may be provided in an embossed pattern.

[0114] The second crack prevention pattern 272 may be disposed in the non-display area NA of the display panel 110 in a direction parallel to the edge CE of the other short side of the driving chip 107, so that at least a portion of the second crack prevention pattern 272 overlaps with the edge CE of the other short side of the driving chip 107, and at least a portion of the second crack prevention pattern 272 does not overlap with the edge CE of the other short side of the driving chip 107. The second crack prevention pattern 272 may be disposed to be spaced apart from the first crack prevention pattern 271 and overlap with the edge CE of the other short side of the driving chip 107. The second crack prevention pattern 272 may be disposed so that at least a portion of the second crack prevention pattern 272 overlaps with one long side of the driving chip 107.

[0115] The second crack prevention pattern 272 may be disposed adjacent to the first pad PAD1 and spaced apart from the first pad PAD1 so as not to overlap with the first pad PAD1.

[0116] The length of the second crack prevention pattern 272 may be smaller than the length of the edge CE of the short side of the driving chip 107. The second crack prevention pattern 272 may be provided in an embossed pattern.

[0117] The third crack prevention pattern 273 may be disposed in the non-display area NA of the display panel 110 in a direction parallel to the edge CE of the other short side of the driving chip 107, so that at least a portion of the third crack prevention pattern 273 overlaps with the edge CE of the other short side of the driving chip 107, and at least a portion of the third crack prevention pattern 273 does not overlap with the edge CE of the other short side of the driving chip 107. The third crack prevention pattern 273 may be disposed to be spaced apart from the second crack prevention pattern 272 and overlap with the edge CE of the other short side of the driving chip 107. The third crack prevention pattern 273 may be disposed so that at least a portion of the third crack prevention pattern 273 overlaps with the other long side of the driving chip 107.

[0118] The third crack prevention pattern 273 may be disposed adjacent to the second pad PAD2 and spaced apart from the second pad PAD2 so as not to overlap with the second pad PAD2.

[0119] The length of the third crack prevention pattern 273 may be smaller than the length of the edge CE of the short side of the driving chip 107. The third crack prevention pattern 273 may be provided in an embossed pattern.

[0120] The fourth crack prevention pattern 274 may be disposed in the non-display area NA of the display panel 110 in a direction parallel to the edge CE of one short side of the driving chip 107, so that at least a portion of the fourth crack prevention pattern 274 overlaps with the edge CE of one short side of the driving chip 107, and at least a portion of the fourth crack prevention pattern 274 does not overlap with the edge CE of one short side of the driving chip 107. The fourth crack prevention pattern 274 may be disposed so that at least a portion of the fourth crack prevention pattern 274 overlaps with one long side of the driving chip 107.

[0121] The fourth crack prevention pattern 274 may be disposed adjacent to the second pad PAD2 and spaced apart from the second pad PAD2 so as not to overlap with the second pad PAD2.

[0122] The length of the fourth crack prevention pattern 274 may be smaller than the length of the edge CE of the short side of the driving chip 107. The fourth crack prevention pattern 274 may be provided in an embossed pattern.

[0123] The crack prevention pattern 270 is disposed to overlap four points of the edge of the driving chip 107 , so that the occurrence of interference caused by the driving chip 107 in the edge region of the driving chip, where interference from the driving chip 107 is relatively easy to occur, can be reduced.

[0124] When the first and fourth crack prevention patterns 271 and 274 are disposed to be spaced apart from each other in such a manner as to overlap with an edge of one short side of the driving chip 107 , a step difference may be prevented from occurring due to an overlap with a wiring disposed adjacent to one short side of the driving chip 107 .

[0125] When the second and third crack prevention patterns 272 and 273 are disposed to be spaced apart from each other in such a manner as to overlap with an edge of one short side of the driving chip 107 , a step difference may be prevented from occurring due to an overlap with a wiring disposed adjacent to another short side of the driving chip 107 .

[0126] Relatively few wirings are arranged in the non-display area NA such as the short side of the driving chip 107, so that when the driving chip is mounted, stress due to pressure or the like is easily accumulated. Therefore, at least a portion of the crack prevention pattern 270 according to the embodiment of the present disclosure is arranged to overlap with the edge CE of the short side of the driving chip 107 where stress is easily generated and four points of the edge. Therefore, it is possible to prevent the display panel 110 from being deformed due to stress when the driving chip 107 is mounted, or to prevent cracks from occurring in the display panel 110 due to interference with the driving chip 107.

[0127] The crack prevention pattern 270 of the embodiment of the present disclosure is disposed to overlap with four points of the edge of the driving chip 107 and the edge CE of the short side, thereby preventing cracks around the driving chip 107 when the driving chip 107 is bonded. As a result, moisture penetration due to cracks, lifting of the surrounding insulating layer due to moisture penetration, and occurrence of cracks in the surrounding insulating layer due to lifting can be prevented.

[0128] Since the crack prevention pattern 270 according to an embodiment of the present disclosure can prevent cracks from occurring in the insulating layer disposed around the driving chip 107 , surrounding pads PAD1 and PAD2 or surrounding wirings can be prevented from being corroded or broken by moisture penetration due to cracks in the insulating layer.

[0129] The first to fourth crack prevention patterns 271 to 274 may be formed of a pattern including a metal layer.

[0130] When a metal layer is provided as the crack prevention pattern 270, rigidity can be obtained so that when the driving chip 107 is mounted, the crack prevention pattern can resist pressure such as pressure, thereby preventing cracks from being generated around the driving chip 107. Therefore, deformation of the display panel 110 can be reduced.

[0131] The metal layer constituting the crack prevention pattern 270 may include the same material as an electrode constituting a driving transistor or a switching transistor disposed in the display area AA of the display panel 110 .

[0132] The metal layer constituting the crack prevention pattern 270 may be disposed on the same layer as the layer in which the first pad PAD1 or the second pad PAD2 is disposed. The metal layer may include the same material as the first pad PAD1 or the second pad PAD2. The crack prevention pattern 270 may be disposed on the same layer as the layer in which one of the plurality of wirings disposed in the non-display area NA is disposed, and may be made of the same material as one of the plurality of wirings.

[0133] In this way, when the anti-crack pattern 270 is set using the same material as the material of the electrode set in the display area AA, the first pad PAD1 set in the non-display area NA, the second pad PAD2 and one of the adjacent wirings, and the same process as the process of the electrode set in the display area AA, the first pad PAD1 set in the non-display area NA, the second pad PAD2 and one of the adjacent wirings, the energy utilization for producing the display device can be reduced by reducing the process steps.

[0134] The features of various embodiments of the present disclosure may be partially or completely connected or combined with each other, and these features may be connected and driven in various ways in technology. In addition, the embodiments may be implemented independently of each other, or implemented together in an associated relationship.

[0135] In the following, reference will be made to Figure 6 An example of a stack structure of the above-mentioned crack prevention pattern 170 is described.

[0136] The display panel 110 includes a substrate 111. An insulating layer 120 may be disposed in a non-display area NA on the substrate 111. A crack prevention pattern 170 may be disposed on the insulating layer 120 such that at least a portion of the crack prevention pattern 170 overlaps an edge CE of one short side of the driving chip 107. A planarization layer 131 may be disposed on the insulating layer 120 in a manner of covering at least a portion of the crack prevention pattern 170.

[0137] A plurality of insulating layers 120 may be stacked on the substrate 111 and disposed in the non-display area NA. The insulating layer 120 may include a buffer layer 121, a gate insulating layer 123, and an interlayer insulating layer 125.

[0138] The substrate 111 is made of a flexible plastic material and may have a flexible property. The substrate 111 may be formed to include polyimide, and may include a flexible and thin glass material.

[0139] The substrate 111 may include a support substrate such as polyethylene terephthalate (PET), a polyimide film, and an adhesive film for adhering the PET and the polyimide film such as a pressure sensitive adhesive (PSA).

[0140] The substrate 111 may include a first substrate 113, a second substrate 115, and an intermediate layer 114 disposed between the first substrate 113 and the second substrate 115. The intermediate layer 114 may include an adhesive material. The intermediate layer 114 may include an insulating material such as silicon nitride or silicon oxide.

[0141] On the substrate 111, as Figure 1 As shown, a plurality of sub-pixels SP may be disposed in the display area AA, and the driving chip 107 may be disposed in the non-display area NA.

[0142] The buffer layer 121 is disposed on the substrate 111. The buffer layer 121 is disposed on the substrate 111 to protect the thin film transistor and the light emitting device disposed in the display area AA from moisture passing through the substrate 111. The buffer layer 121 is disposed to overlap the driving chip 107 in the non-display area AA and prevent moisture from penetrating from the edge of the substrate 111. The buffer layer 121 may be disposed to overlap the crack prevention pattern 170.

[0143] The buffer layer 121 may be composed of a plurality of inorganic layers alternately stacked. For example, the buffer layer 121 may include a plurality of layers formed by alternately stacking one or more inorganic layers selected from silicon oxide layers (SiOx), silicon nitride layers (SiNx), and silicon oxynitride layers (SiOxNy).

[0144] The gate insulating layer 123 is disposed on the buffer layer 121. Figure 1 and Figure 2 The gate insulating layer 123 is provided to extend to the non-display area NA, and can prevent a short circuit between electrodes constituting the thin film transistors provided in the non-display area NA. The gate insulating layer 123 can be provided to overlap with the driving chip 107 in the non-display area NA. The gate insulating layer 123 can be provided to overlap with the crack prevention pattern 170.

[0145] The gate insulating layer 123 may include an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multi-layer thereof.

[0146] The interlayer insulating layer 125 may be disposed on the gate insulating layer 123. The interlayer insulating layer 125 is disposed on Figure 1 and Figure 2 The interlayer insulating layer 125 may extend to the non-display area NA and electrically insulate the electrodes constituting the thin film transistors disposed above and below the non-display area NA. The interlayer insulating layer 125 may be disposed to overlap the driving chip 107 in the non-display area NA. The interlayer insulating layer 125 may be disposed to overlap the crack prevention pattern 170.

[0147] The interlayer insulating layer 125 may include an inorganic material. The inorganic material may include, for example, silicon nitride, silicon oxynitride, silicon oxide, etc. Alternatively, the interlayer insulating layer 125 may be provided to include a plurality of layers thereof.

[0148] The crack prevention pattern 170 is disposed on the plurality of insulating layers 120 (e.g., on the uppermost insulating layer among the plurality of insulating layers included in the insulating layer 120). The crack prevention pattern 170 may be disposed in an embossed pattern on the top surface of the insulating layer 120. A pad such as a first pad PAD1 may be disposed on the insulating layer 120 and spaced apart from the crack prevention pattern 170.

[0149] The crack prevention pattern 170 may include a metal layer.

[0150] When a metal layer is provided as the crack prevention pattern 170, rigidity can be obtained so that when the driving chip 107 is mounted, the crack prevention pattern can resist pressure such as pressure, thereby preventing cracks from being generated around the driving chip 107. Therefore, deformation of the display panel 110 can be more effectively reduced.

[0151] The crack prevention pattern 170 may be disposed on the same layer as the layer in which the first pad PAD1 is disposed. The crack prevention pattern 170 may include the same material as the first pad PAD1. When the crack prevention pattern 170 is disposed using the same material and the same process as the first pad PAD1 disposed in the non-display area NA, energy utilization for manufacturing a display device may be reduced by reducing process steps.

[0152] The planarization layer 131 is disposed on the crack prevention pattern 170. The planarization layer 131 may cover the embossed crack prevention pattern 170 to provide a flat surface. The planarization layer 131 may be disposed to extend to the side of the first pad PAD1 to cover the side of the first pad PAD1 and the insulating layer 120 exposed by the interval space between the crack prevention pattern 170 and the first pad PAD1.

[0153] The planarization layer 131 may be disposed to overlap with an edge CE of one short side of the driving chip 107. Here, the edge CE of one short side of the driving chip 107 may overlap with the planarization layer 131 and the crack prevention pattern 170.

[0154] The planarization layer 131 may include an organic material. The organic material may include at least one of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0155] In addition to the above-mentioned insulating layer 120 , various organic layers or inorganic layers may be further disposed between the substrate 111 and the planarization layer 131 .

[0156] The driving chip 107 may include bumps 105 corresponding to the first pads PAD1. The plurality of bumps 105 may be disposed to face pads disposed in the non-display area NA, such as the first pads PAD1. The bumps 105 may be disposed to be spaced apart from the crack prevention pattern 170.

[0157] The anisotropic conductive film 103 is provided between the driving chip 107 and the pads PAD1 and PAD2 .

[0158] The anisotropic conductive film 103 includes an adhesive part 101 and a plurality of conductive balls 102. The adhesive part 101 allows the driving chip 107 to be attached to the display panel 110, and the conductive balls 102 are irregularly distributed within the adhesive part 101 to electrically connect the driving chip 107 to the first pads PAD1.

[0159] The conductive balls 102 can be formed by using conductive particles themselves, by using polymer resin particles coated with a metal layer, or by using particles obtained by coating insulating resin on the surface of conductive particles or particles coated with a metal layer. For example, the metal layer can be made of a material such as nickel (Ni) or gold (Au).

[0160] The anisotropic conductive film 103 may be disposed to overlap an edge portion of the planarization layer 131, which overlaps an edge CE of the driving chip 107. The planarization layer 131 is disposed to overlap a side of the crack prevention pattern 170 and an edge of the driving chip 107, thereby preventing the crack prevention pattern 170 from being electrically connected to the conductive balls 102 of the anisotropic conductive film 103.

[0161] Since the driving chip 107 is electrically connected to the first pad PAD1 through the conductive ball 102, pressure is applied to install the driving chip 107, so that the conductive ball 102 is in contact with the bump 105 and the first pad PAD1. The crack prevention pattern 170 according to the embodiment of the present disclosure is provided so that at least a portion of the crack prevention pattern 170 overlaps with the edge of the short side of the driving chip 107, so that stress accumulation and stress generation due to pressure, etc. when installing the driving chip 107 can be prevented. Therefore, the display panel 110 can be prevented from being deformed due to stress, or cracks can be prevented from occurring in the display panel 110 due to interference with the driving chip 107.

[0162] The crack prevention pattern 170 of the embodiment of the present disclosure is disposed to overlap with the edge CE of the short side of the driving chip 107, thereby preventing cracks around the driving chip 107 when the driving chip 107 is bonded. As a result, moisture penetration due to cracks, lifting of the surrounding insulating layer 120 (e.g., the insulating layer 120 or one or more insulating layers 120) due to moisture penetration, and occurrence of cracks in the surrounding insulating layer 120 due to lifting can be prevented.

[0163] Since the crack prevention pattern 170 according to the embodiment of the present disclosure can prevent cracks from occurring in the insulating layer 120 disposed around the driving chip 107 , the first pad PAD1 and the like can be prevented from being corroded or broken by moisture penetration due to cracks in the insulating layer 120 .

[0164] The crack prevention pattern 170 according to the present disclosure may prevent cracks and moisture penetration, thereby reducing deformation of the display panel 110 .

[0165] In the display device 100 according to the present disclosure, the crack prevention pattern 170 is disposed so that at least a portion of the crack prevention pattern 170 overlaps the edge of the driving chip 107, thereby blocking moisture penetration and preventing corrosion of metal disposed in the non-display area NA of the display device 100. As a result, the reliability of the display device 100 can be improved.

[0166] According to the display device of this embodiment, the occurrence of defects in the display device 100 is reduced or minimized. Therefore, the energy utilization used to produce the display device can be reduced, and the use of hazardous production materials or conditioning materials can be reduced, making the display device advantageous for recycling, and leading to the realization of an environmentally friendly display device 100.

[0167] exist Figure 6 In the illustrated embodiment, the crack prevention pattern 170 is illustrated and described as being disposed on the same layer as the first pad PAD1 and being made of the same material as the first pad PAD1. However, according to an embodiment of the present disclosure, the crack prevention pattern 170 may be disposed on the same layer as one of the adjacent wirings (e.g., the first wiring W1, the second wiring W2, the third wiring W3, the fourth wiring W4, and the connection line L1) and be made of the same material.

[0168] Although the preferred embodiments of the present disclosure are described above, these are merely examples and do not limit the present disclosure. The present disclosure described above is not limited to the above embodiments and the accompanying drawings. The features, structures, effects, etc. provided in each embodiment may be combined or modified. Therefore, the contents related to combination and modification should be interpreted as being included in the scope of the present disclosure.

[0169] Reference numerals

[0170] 101: Adhesive material 102: Conductive ball

[0171] 103: Anisotropic conductive film 105: Bump

[0172] 107: driver chip 109: driver circuit area

[0173] 110: display panel 111: substrate

[0174] 113: first substrate 114: intermediate layer

[0175] 115: second substrate 120: insulating layer

[0176] 121: buffer layer 123: gate insulating layer

[0177] 125: interlayer insulating layer 131: planarization layer

[0178] 170: Anti-crack pattern

[0179] CROSS-REFERENCE TO RELATED APPLICATIONS

[0180] This application claims priority to Korean Patent Application No. 10-2023-0146456, filed on October 30, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area and a non-display area; as well as a driving chip, wherein the driving chip is arranged in the non-display area, The display panel includes a crack prevention pattern, and the crack prevention pattern is arranged such that at least a portion of the crack prevention pattern overlaps an edge of one short side of the driving chip.

2. The display device according to claim 1, wherein: The crack prevention pattern is disposed in the non-display area in a direction parallel to the edge of the one short side of the driving chip.

3. The display device according to claim 1, wherein: The crack prevention pattern is electrically floating.

4. The display device according to claim 1, wherein: The crack prevention pattern is disposed on two short sides of the driving chip to be parallel to the short sides of the driving chip, so that at least a portion of the crack prevention pattern overlaps with edges of the two short sides of the driving chip.

5. The display device according to claim 1, wherein: At least a portion of the crack prevention pattern is disposed to overlap an edge of the driving chip.

6. The display device according to claim 5, wherein: The crack prevention pattern is disposed to overlap four points of the edge of the driving chip.

7. The display device according to claim 1, wherein: The display panel comprises: substrate; a plurality of insulating layers, the plurality of insulating layers being stacked on the substrate and disposed in the non-display area; a planarization layer disposed on the plurality of insulating layers and on the crack prevention pattern; and a first pad disposed to be spaced apart from the crack prevention pattern, The planarization layer is disposed on the insulating layer exposed by the spacing space between the crack prevention pattern and the first pad and on one side of the first pad.

8. The display device according to claim 7, wherein: An edge of one short side of the driving chip overlaps with the planarization layer and overlaps with the crack prevention pattern.

9. The display device according to claim 7, further comprising an anisotropic conductive film disposed between the driving chip and the first pad, in, The anisotropic conductive film overlaps at least a portion of the planarization layer and the crack prevention pattern at an edge of one short side of the driving chip.

10. The display device according to claim 1, wherein: The crack prevention pattern is disposed to be spaced apart from the bumps of the driving chip.

11. The display device according to claim 1, wherein: The crack prevention pattern is formed as an embossed pattern including a metal layer.

12. The display device according to claim 1, wherein: The crack prevention pattern includes a material that is the same as a source electrode, a drain electrode, or a gate electrode constituting a switching transistor of the display area.

13. The display device according to claim 1, further comprising: A first pad, wherein the first pad is arranged in the non-display area toward the display area; as well as a second pad, the second pad being arranged in a direction opposite to the display area and facing the first pad, Wherein, the first pad and the second pad overlap with two long sides of the driving chip, and The crack prevention pattern is disposed to be spaced apart from the first pad and the second pad so as not to overlap with the first pad and the second pad.

14. The display device according to claim 13, wherein: The crack prevention pattern is made of the same material as that of the first pad or the second pad.

15. The display device according to claim 1, wherein: At least a portion of the crack prevention pattern does not overlap with edges of both short sides of the driving chip, and a plurality of the crack prevention patterns are disposed to be spaced apart from each other in such a manner as to overlap with four points of the edge of the driving chip.

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