Pixel driving circuit and display device

Abstract

The invention provides a pixel driving circuit and a display device, and belongs to the technical field of display. According to the pixel driving circuit disclosed by the invention, a gate driving sub-circuit is configured to output a gate driving signal with an adjustable duty ratio; the first light-emitting control sub-circuit is configured to respond to a light-emitting control signal, control the first voltage control sub-circuit to output a first light-emitting voltage through the data voltage signal, or control the second voltage control sub-circuit to output a second light-emitting voltage through the data voltage signal; the light-emitting time control sub-circuit is configured to output the received first light-emitting voltage or second light-emitting voltage under the control of the gate driving signal; and the second light-emitting control sub-circuit is configured to output the received first light-emitting voltage or the second light-emitting voltage to a light-emitting device to be driven under the control of the light-emitting control signal.

Description

Pixel driving circuit and display device

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a pixel driving circuit and a display device.

[0002] PAM is the main grayscale driving mode of existing display products. With the continuous development of a series of display technologies such as LCD, OLED, LED, QD, etc., the shortcomings of PAM driving, such as high power consumption, high heat generation, and inability to achieve low grayscale display, have become increasingly prominent. Therefore, PWM grayscale driving mode was introduced on the basis of PAM to improve such problems. After the introduction of PWM driving mode, the complexity of the driving circuit has been greatly increased, which is not conducive to the development of high-tech technologies such as high PPI and narrow borders. At the same time, the complex process will lead to a decrease in yield and further increase the cost. The existing PWM driving frequency is low and has a certain stimulation to the human eye. Further improvement is needed to achieve healthy display. At present, the PWM driving mode is full-screen driving, or a fixed duty cycle timing signal is introduced in the pixel driving circuit, and low grayscale display is achieved with PAM driving. The above two circuit design methods increase the complexity of the driving circuit, and at the same time do not improve the problems of high power consumption and high heat generation.

[0003]

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a pixel driving circuit and a display device.

[0005] The embodiment of the present disclosure provides a pixel driving circuit, which includes a gate driving subcircuit, a first light emitting control subcircuit, a first voltage control subcircuit, a second voltage control subcircuit, a light emitting time control subcircuit, and a second light emitting control subcircuit;

[0006] The gate drive subcircuit is configured to output a gate drive signal with an adjustable duty cycle;

[0007] The first light-emitting control subcircuit is configured to, in response to a light-emitting control signal, control the first voltage control subcircuit to output a first light-emitting voltage through a data voltage signal, or control the second voltage control subcircuit to output a second light-emitting voltage through the data voltage signal; the light-emitting time control subcircuit is configured to output the first light-emitting voltage or the second light-emitting voltage received under the control of the gate driving signal;

[0008] The second light-emitting control subcircuit is configured to output the received first light-emitting voltage or the second light-emitting voltage to the light-emitting device to be driven under the control of the light-emitting control signal; wherein,

[0009] The gate drive subcircuit comprises:

[0010] An input module, configured to control a signal output terminal to output a first power supply voltage or a second power supply voltage in response to an input control signal;

[0011] A reset module, configured to respond to a reset signal and reset a first node through the reset signal; the first node is a connection node between the output module and the duty cycle adjustment module;

[0012] a duty cycle adjustment module, configured to respond to the light emitting control signal and control the potential of the first node through a data voltage control signal;

[0013] The output module is configured to output the gate drive signal of the corresponding duty cycle through the signal output terminal in response to the potential of the first node; wherein the potential of the gate drive signal jumps between the first power supply voltage and the second power supply voltage.

[0014] Wherein, the input module includes a first transistor; the first electrode of the first transistor is connected to the second power supply voltage terminal, the second electrode is connected to the output module, and the control electrode is connected to the input signal control terminal.

[0015] Wherein, the reset module includes a second transistor; a first electrode of the second transistor is connected to the first node, and a second electrode is connected to its control electrode and a reset signal terminal.

[0016] Wherein, the output module comprises a third transistor, a first storage capacitor and a second storage capacitor; the switching characteristic of the third transistor is opposite to the switching characteristic of the second transistor;

[0017] The first electrode of the third transistor is connected to the first power supply voltage terminal, the second electrode is connected to the signal output terminal and the first end of the first storage capacitor, and the control electrode is connected to the first node; the second end of the first storage capacitor is connected to the second end of the second storage capacitor and the second power supply voltage terminal, and the first end of the second storage capacitor is connected to the first node.

[0018] Wherein, the duty cycle adjustment module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the fourth transistor and the seventh transistor have switching characteristics opposite to those of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as those of the second transistor;

[0019] The first electrode of the fourth transistor is connected to the first node, the second electrode is connected to the first electrode of the fifth transistor and the first electrode of the sixth transistor, and the control electrode is connected to the reset signal terminal; the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the second power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal terminal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal.

[0020] The duty cycle adjustment module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the seventh transistor has a switching characteristic opposite to that of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as the switching characteristics of the second transistor;

[0021] The first electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the first node, the second electrode is connected to the second electrode of the sixth transistor and the second power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal.

[0022] Wherein, the input module includes a first transistor; the first electrode of the first transistor is connected to the first power supply voltage terminal, the second electrode is connected to the output module, and the control electrode is connected to the input signal control terminal.

[0023] Wherein, the reset module includes a second transistor; a first electrode of the second transistor is connected to the first node, and a second electrode is connected to its control electrode and a reset signal terminal.

[0024] Wherein, the output module comprises a third transistor, a first storage capacitor and a second storage capacitor; the switching characteristic of the third transistor is opposite to the switching characteristic of the second transistor;

[0025] The first electrode of the third transistor is connected to the second power supply voltage terminal, the second electrode is connected to the signal output terminal and the first end of the first storage capacitor, and the control electrode is connected to the first node; the second end of the first storage capacitor is connected to the second end of the second storage capacitor and the second power supply voltage terminal, and the first end of the second storage capacitor is connected to the first node.

[0026] Wherein, the duty cycle adjustment module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the fourth transistor and the seventh transistor have switching characteristics opposite to those of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as those of the second transistor;

[0027] The first electrode of the fourth transistor is connected to the first node, the second electrode is connected to the first electrode of the fifth transistor and the first electrode of the sixth transistor, and the control electrode is connected to the reset signal terminal; the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the first power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal.

[0028] The duty cycle adjustment module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the seventh transistor has a switching characteristic opposite to that of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as the switching characteristics of the second transistor;

[0029] The first electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the first node, the second electrode is connected to the second electrode of the sixth transistor and the first power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal.

[0030] Wherein, the first light-emitting control subcircuit comprises an eleventh transistor and a fourth storage capacitor; the switching characteristics of the eleventh transistor are opposite to those of the second transistor;

[0031] The first electrode of the eleventh transistor is connected to the data signal terminal, the second electrode is connected to the first terminal of the fourth storage capacitor, the first voltage control subcircuit and the second voltage control subcircuit, and the control electrode is connected to the light-emitting control signal terminal; the second terminal of the fourth storage capacitor is connected to the first power supply voltage terminal.

[0032] Wherein, the first voltage control subcircuit includes a twelfth transistor, and the second voltage control subcircuit includes a thirteenth transistor; the twelfth transistor has the same switching characteristic as the eleventh transistor and is opposite to the switching characteristic of the thirteenth transistor;

[0033] The first electrode of the twelfth transistor is connected to the first voltage terminal, the second electrode is connected to the second electrode of the thirteenth transistor and the light-emitting time control subcircuit, the control electrode is connected to the control electrode of the thirteenth transistor and the second electrode of the eleventh transistor; the first electrode of the thirteenth transistor is connected to the second voltage terminal.

[0034] Wherein, the first light-emitting control subcircuit comprises an eleventh transistor, a fourteenth transistor, a fourth storage capacitor and a fifth storage capacitor; the switching characteristic of the eleventh transistor is opposite to that of the second transistor, and is the same as that of the fourteenth transistor;

[0035] The first electrode of the eleventh transistor is connected to the data signal terminal, the second electrode is connected to the first terminal of the fourth storage capacitor and the first voltage control subcircuit, and the control electrode is connected to the light emitting control signal terminal; the second terminal of the fourth storage capacitor is connected to the first power supply voltage terminal;

[0036] The first electrode of the fourteenth transistor is connected to the data signal terminal, the second electrode is connected to the first terminal of the fifth capacitor and the second voltage control subcircuit, and the control electrode is connected to the light emitting control signal terminal; the second terminal of the fifth storage capacitor is connected to the first power supply voltage terminal.

[0037] Wherein, the first voltage control subcircuit includes a twelfth transistor, and the second voltage control subcircuit includes a thirteenth transistor; the switching characteristics of the twelfth transistor are opposite to those of the thirteenth transistor;

[0038] The first electrode of the twelfth transistor is connected to the first voltage terminal, the second electrode is connected to the second electrode of the thirteenth transistor and the light-emitting time control subcircuit, the control electrode is connected to the control electrode of the thirteenth transistor and the second electrode of the eleventh transistor; the first electrode of the thirteenth transistor is connected to the second voltage terminal.

[0039] The thirteenth transistor has the same switching characteristic as the eleventh transistor.

[0040] Wherein, the light emission time control subcircuit comprises a ninth transistor, and the switching characteristic of the ninth transistor is the same as the switching characteristic of the second transistor;

[0041] The first electrode of the ninth transistor is connected to the first voltage control subcircuit and the second voltage control subcircuit, the second electrode is connected to the second light emitting control subcircuit, and the control electrode is connected to the signal output terminal.

[0042] Wherein, the second light emitting control subcircuit comprises a tenth transistor; the switching characteristic of the tenth transistor is the same as the switching characteristic of the second transistor;

[0043] The first electrode of the ninth transistor is connected to the light-emitting time control subcircuit, the second electrode is connected to the light-emitting device to be driven, and the control electrode is connected to the light-emitting control terminal.

[0044] Wherein, the light-emitting device to be driven includes any one of LED, OLED, Micro LED and Mini LED.

[0045] An embodiment of the present disclosure provides a display device, which includes any of the above-mentioned pixel driving circuits.

[0046] FIG. 1 is a schematic diagram of a first exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0047] FIG. 2 is a schematic diagram of a second exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0048] FIG. 3 is a schematic diagram of a third exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0049] FIG. 4 is a schematic diagram of a fourth exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0050] FIG. 5 is a schematic diagram of a fifth exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0051] FIG. 6 is a schematic diagram of a sixth exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0052] 7 and 8 are output simulation diagrams of the signal output terminal of the gate driving subcircuit under different data voltage control signals of the pixel driving circuits of the first to sixth examples of the embodiments of the present disclosure.

[0053] FIG. 9 is a schematic diagram of a seventh exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0054] FIG. 10 is a schematic diagram of an eighth exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0055] FIG. 11 is a schematic diagram of a ninth exemplary pixel driving circuit according to an embodiment of the present disclosure.

[0056] FIG. 12 is a schematic diagram of a tenth example of a pixel driving circuit according to an embodiment of the present disclosure.

[0057] FIG. 13 is a schematic diagram of an eleventh example of a pixel driving circuit according to an embodiment of the present disclosure.

[0058] FIG. 14 is a schematic diagram of a twelfth example of a pixel driving circuit according to an embodiment of the present disclosure.

[0059] 15 and 16 are output simulation diagrams of the signal output terminal of the gate driving subcircuit under different data control voltages of the pixel driving circuits of the seventh to twelfth examples of the embodiments of the present disclosure.

[0060] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0061] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] Before describing the embodiments of the present disclosure, it should be noted that the first power supply voltage in the embodiments of the present disclosure is greater than the second power supply voltage, for example: the first power supply voltage is 8V, and the second power supply voltage is -8V. In other words, the first power supply voltage is a high-level signal compared to the second power supply voltage, and the second power supply is a low-level signal compared to the first power supply. As for the first power supply voltage terminal and the second power supply voltage terminal mentioned in the following embodiments, the two are respectively for providing the first power supply voltage and the second power supply voltage. The input control signal and reset signal mentioned in the following embodiments are both high-frequency scanning signals.

[0063] In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, which includes a gate driving subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a first voltage control subcircuit, a second voltage control subcircuit and a light-emitting time control subcircuit. Among them, the gate driving subcircuit is configured to output a gate driving signal with an adjustable duty cycle. The first light-emitting control subcircuit is configured to respond to the light-emitting control signal, control the first voltage control subcircuit to output the first light-emitting voltage through a data voltage signal, or control the second voltage control subcircuit to output the second light-emitting voltage through a data voltage signal. The light-emitting time control subcircuit is configured to output the first light-emitting voltage or the second light-emitting voltage it receives. The second light-emitting control subcircuit is configured to output the received first light-emitting voltage or the second light-emitting voltage to the light-emitting device to be driven under the control of the light-emitting control signal. It should be noted that the first light-emitting voltage and the second light-emitting voltage correspond to different grayscale segments displayed by the light-emitting device, the first light-emitting voltage corresponds to a low grayscale segment, and the second light-emitting voltage corresponds to a high grayscale segment.

[0064] In an embodiment of the present disclosure, the gate drive subcircuit may specifically include an input module, a reset module, a duty cycle adjustment module and an output module. Among them, the connection node between the output module and the connection node between the duty cycle adjustment module is a first node. The input module is configured to respond to the input control signal, and the control signal output terminal outputs the first power supply voltage or the second power supply voltage. The reset module is configured to respond to the reset signal and reset the first node through the reset signal. The duty cycle adjustment module is configured to respond to the light emitting control signal and control the potential of the first node through the data voltage control signal. The output module is configured to respond to the potential of the first node and output the gate drive signal of the corresponding duty cycle through the signal output terminal; wherein the potential of the gate drive signal jumps between the first power supply voltage and the second power supply voltage.

[0065] The duty cycle adjustment module in the gate driving subcircuit of the pixel driving circuit in the embodiment of the present disclosure can control the potential of the first node through the data voltage control signal under the control of the light-emitting control signal, thereby controlling the duration of the output module outputting the effective level, that is, adjusting the duty cycle of the gate signal output by the output module. At the same time, the first light-emitting control module in the pixel driving circuit controls the first voltage control subcircuit to output the first light-emitting voltage, or controls the second light-emitting control subcircuit to output the second light-emitting voltage according to the data voltage signal, and controls the second light-emitting control subcircuit to work through the light-emitting control signal, so as to output the first light-emitting voltage or the second light-emitting voltage to the light-emitting device to be driven, so as to realize the display of the corresponding grayscale. The pixel driving circuit of the embodiment of the present disclosure is described below in combination with specific examples.

[0066] First example: FIG. 1 is a schematic diagram of a pixel driving circuit of the first example of an embodiment of the present disclosure; as shown in FIG. 1 , in this example, the input module 11 in the pixel driving subcircuit includes a first transistor M1; the reset module 12 includes a second transistor M2; the output module 13 includes a third transistor M3, a first storage capacitor C1 and a second storage capacitor C2; the duty cycle adjustment module 14 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a third storage capacitor C3. Among them, the switching characteristics of the first transistor M1, the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are the same. The switching characteristics of the second transistor M2 are opposite to those of the first transistor M1, and are the same as those of the fifth transistor M5, the sixth transistor M6 and the eighth transistor M8. In this example, the first transistor M1, the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are all P-type transistors, and the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the eighth transistor M8 are all N-type transistors.

[0067] Specifically, the first electrode of the first transistor M1 is connected to the second power supply voltage terminal, the second electrode of the first transistor M1 is connected to the second electrode of the third transistor M3, the first end of the first storage capacitor C1 and the signal output terminal OUTPUT, and the control electrode of the first transistor M1 inputs the signal control terminal HF_Input. The first electrode of the second transistor M2 is connected to the first node Q, and the second electrode of the second transistor M2 is connected to its control electrode and the reset signal terminal HF_Reset. The first electrode of the third transistor M3 is connected to the first power supply voltage terminal, the second electrode of the third transistor M3 is connected to the signal output terminal OUTPUT and the first end of the first storage capacitor C1, and the control electrode of the third transistor M3 is connected to the first node Q. The second end of the first storage capacitor C1 is connected to the second end of the second storage capacitor C2 and the second power supply voltage terminal, and the first end of the second storage capacitor C2 is connected to the first node Q. The first electrode of the fourth transistor M4 is connected to the first node Q, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5 and the first electrode of the sixth transistor M6, and the control electrode of the fourth transistor M4 is connected to the reset signal terminal HF_Reset. The second electrode of the fifth transistor M5 is connected to the second electrode of the sixth transistor M6 and the second power supply voltage terminal, and the control electrode of the fifth transistor M5 is connected to the second electrode of the eighth transistor M8. The control electrode of the sixth transistor M6 is connected to the signal output terminal OUTPUT. The first electrode of the seventh transistor M7 is connected to the data voltage control signal terminal Data, the second electrode of the seventh transistor M7 is connected to the first end of the third storage capacitor C3 and the first electrode of the eighth transistor M8 (that is, the second node R), and the control electrode of the seventh transistor M7 is connected to the light-emitting control signal terminal EOA. The control electrode of the eighth transistor M8 is connected to the light-emitting control signal terminal EOA. The second end of the third storage capacitor C3 is connected to the first power supply voltage terminal.

[0068] Among them, only the first power supply voltage is 8V, and the second power supply voltage is -8V; in the timing of the first light-emitting voltage, the high-level signal is 12V, the low-level signal is -12V, the period H=1000μs, and the duty cycle is low-level signal / high-level signal=5μs / 995μs; in the timing of the second light-emitting voltage, the high-level signal is 12V, the low-level signal is -12V, the period H=1000μs, and the duty cycle is high-level signal / low-level signal=5μs / 995μs; in the timing of the reset signal, the high-level signal is 20V, the low level signal is -12V, the period H=1000μs, and the duty cycle is low level signal / high level signal=995μs / 5μs; the data voltage control signal Datastep=[-6.65V, -6.92V], the first capacitor and the third storage capacitor C3 are both 50fF, and the second capacitor=500fF. Taking the gate drive subcircuit 1 of the pixel drive circuit in the first example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0069] The following describes a method for generating a gate driving signal of the gate driving subcircuit 1 of the pixel driving circuit. The method may specifically include the following stages:

[0070] Phase 1: the reset signal written into the reset signal terminal HF_Reset is a high-level signal, the second transistor M2 is turned on, the fourth transistor M4 is turned off, the potential of the first node Q is reset to 20V, and the third transistor M3 is turned off.

[0071] The second stage: the reset signal written into the reset signal terminal HF_Reset is a low-level signal, the second transistor M2 is turned off, the fourth transistor M4 is turned on, the input control signal written into the input signal control terminal HF_Input is a low-level signal, the first transistor M1 is turned on, the second power supply voltage is written into the first storage capacitor C1, the signal output terminal OUTPUT outputs a low-level signal, and at the same time, the sixth transistor M6 is turned off. The light-emitting control signal terminal EOA writes a low-level signal, the seventh transistor M7 is turned on, the data voltage control signal is written into the second node R and the third storage capacitor C3, the light-emitting control signal terminal EOA writes a high-level signal, the eighth transistor M8 is turned on, and the saturation current Id of the fifth transistor M5 is controlled by the potential of the second node R, and the discharge speed of the first node Q is controlled.

[0072] The third stage: after time t, when the voltage discharged to the first node Q minus the first power supply voltage (that is, the gate-source voltage Vgs of the third transistor M3) is less than the threshold voltage Vth of the third transistor M3, that is, VQ-VDD<Vth, the first power supply voltage written into the first power supply voltage terminal is written into the first storage capacitor C1, and the signal output terminal OUTPUT outputs a high level signal. At this time, the sixth transistor M6 is turned on, and the voltage of the first node Q is quickly discharged to the second power supply voltage.

[0073] Phase 4: The reset signal written into the reset signal terminal HF_Reset is a high level signal, the second transistor M2 is turned on, the fourth transistor M4 is turned off, the potential of the first node Q is reset to 20V, the third transistor M3 is turned off, the first storage capacitor C1 maintains a high level, and the signal output terminal OUTPUT continues to output a high level signal.

[0074] The next cycle begins to repeat stages 2 to 4.

[0075] It can be seen that the data voltage control signal is written into the control electrode of the fifth transistor M5, and the discharge speed of the first node Q is controlled by controlling the saturation current Id of the fifth transistor M5. The time t required for the first node Q to discharge to VQ-VDD<Vth is the duration of the low-level signal in the clock cycle of the input clock signal. By adjusting the voltage of the data voltage control signal, the output gate drive signal with different duty ratios can be obtained.

[0076] Next, continue to refer to FIG. 1. In this example, the light-emission duration control subcircuit 3 in the pixel driving circuit includes a ninth transistor M9, the second light-emission control subcircuit 4 includes a tenth transistor M10, the first light-emission control subcircuit 2 includes an eleventh transistor M11 and a fourth storage capacitor C4, the first light-emission voltage control subcircuit 5 includes a twelfth transistor M12, and the second light-emission voltage control subcircuit 6 includes a thirteenth transistor M13. Among them, the switching characteristics of the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are the same, and are the same as the switching characteristics of the second switching transistor, that is, an N-type transistor is used. The switching characteristics of the eleventh transistor M11 and the thirteenth transistor M13 are the same, and are different from the switching characteristics of the ninth transistor M9, that is, a P-type transistor is used.

[0077] Specifically, the first electrode of the ninth transistor M9 is connected to the second electrode of the twelfth transistor M12 and the second electrode of the thirteenth transistor M13, the second electrode of the ninth transistor M9 is connected to the first electrode of the tenth transistor M10, and the control electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The second electrode of the tenth transistor M10 is connected to the first electrode of the light-emitting device D to be driven, and the control electrode of the tenth transistor M10 is connected to the light-emitting control signal terminal EOA. The first electrode of the eleventh transistor M11 is connected to the data voltage signal terminal Data C, the second electrode of the eleventh transistor M11 is connected to the first end of the fourth storage capacitor C4, and the control electrode of the eleventh transistor M11 is connected to the light-emitting control signal terminal EOA. The second end of the fourth storage capacitor C4 is connected to the first power supply voltage terminal. The first electrode of the twelfth transistor M12 is connected to the first light-emitting voltage terminal, and the control electrode of the twelfth transistor M12 is connected to the control electrode of the thirteenth transistor M13, the second electrode of the eleventh transistor M11 and the first end of the fourth storage capacitor C4. The first electrode of the thirteenth transistor M13 is connected to the second light-emitting voltage terminal.

[0078] In the following, the driving method of the pixel driving circuit of the embodiment of the present disclosure is described in combination with the generation of the gate driving signal of the gate driving subcircuit 1 of the pixel driving circuit. The driving method of the pixel driving circuit may specifically include the following stages:

[0079] Data voltage writing stage: a low level signal is written to the light emitting control signal terminal EOA, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the data control voltage is written to the second node R, and stored in the third storage capacitor C3.

[0080] Light-emitting stage: A high-level signal is written to the light-emitting control signal terminal EOA, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the saturation current Id of the fifth transistor M5 is controlled by the potential of the second node R, and the discharge speed of the first node Q is controlled, thereby controlling the duty cycle of the gate drive signal output by the signal output terminal OUTPUT. When the gate drive signal is high and the signal input to the light-emitting control signal terminal EOA is a high-level signal, the ninth transistor M9 and the tenth transistor M10 are turned on. When a low-level signal is written to the light-emitting control signal terminal EOA, the light emission stops. In the light-emitting stage, according to the grayscale to be displayed, the data voltage signal terminal Data C writes the corresponding data voltage signal to control one of the first light-emitting voltage and the second light-emitting voltage to be output to the light-emitting device D to be driven.

[0081] Specifically, the ratio formula of different grayscale brightness to 255 grayscale brightness is as follows:

[0082] N grayscale brightness = 255 grayscale brightness * (N / 255) gamma

[0083] When driven by a duty cycle gate drive signal, the N grayscale duty cycle is:

[0084] N grayscale duty cycle = 255 grayscale duty cycle * (N / 255) gamma

[0085] Assuming that the duty cycle of grayscale 255 is 100%, that is, the light-emitting device D is always working in the 1H display period, the duty cycles of other grayscales can be calculated by the above formula, for example, the duty cycle of grayscale 1 = 0.0005%, the duty cycle of grayscale 23 = 0.5%. It can be seen that the duty cycle of grayscale 1, that is, the brightness, is 1 / 1000 of that of grayscale 23.

[0086] When the high grayscale segment is displayed, the data voltage signal terminal Data C writes a low level signal, the thirteenth transistor M13 is turned on, and the second light-emitting voltage (high voltage) signal is written to the light-emitting device D to be driven, with a maximum brightness of 255 grayscales. The display of different grayscales in the high grayscale segment is achieved by adjusting the duty cycle of the gate drive signal output by the signal output terminal OUTPUT. However, the minimum duty cycle that the gate drive subcircuit 1 can achieve is 0.1% (11 grayscales), and 1 to 10 grayscales (low grayscale segment) cannot be achieved.

[0087] When displaying grayscale 1 to 10 (low grayscale segment), the data voltage signal terminal Data C is written with high voltage, the twelfth transistor M12 is turned on, and the first light-emitting voltage (low voltage) signal is written to the light-emitting device D to be driven, and the maximum brightness is 23 grayscales (that is, when the duty cycle of the signal output by the signal output terminal OUTPUT is 100%). At this time, when the duty cycle of the gate drive signal output by the signal output terminal OUTPUT is adjusted to 0.1%, the brightness is 1 / 1000 of 23 grayscales, and 1 grayscale display can be achieved. Similarly, 2 to 22 grayscale display can be achieved.

[0088] Second example: FIG2 is a schematic diagram of a pixel driving circuit of the second example of the embodiment of the present disclosure; as shown in FIG2 , the pixel driving circuit in this example is substantially the same as the first example, and the only difference from the pixel driving circuit in the first example is that the first transistor M1 in the input module 11 of the pixel driving circuit adopts an N-type transistor. Affected by the parasitic capacitance of the first transistor M1, if the first transistor M1 adopts a P-type transistor, the signal outputted by the signal output terminal OUTPUT will be pulled up when the first transistor M1 is turned off, which will cause the risk of leakage of the sixth transistor M6. However, if the first transistor M1 adopts an N-type transistor, when the first transistor M1 is turned off, the output of the signal output terminal OUTPUT will be pulled down, thereby avoiding leakage of the sixth transistor M6.

[0089] The remaining structures in the second example are the same as those in the first example, and the driving method of the pixel driving circuit is also the same as that in the first example, so it will not be repeated here. However, it should be noted that in the first example, since the first transistor M1 is a P-type transistor, the timing signal input by the input signal control terminal HF_Input is HF_InputL, and in the second example, since the first transistor M1 is an N-type transistor, the timing signal input by the input signal control terminal HF_Input is HF_InputH, and the timing of HF_InputH is opposite to that of HF_InputL.

[0090] The third example: FIG3 is a schematic diagram of a pixel driving circuit of the third example of the embodiment of the present disclosure. As shown in FIG3, the pixel driving circuit in this example is substantially the same as the first example, and the difference from the pixel driving circuit in the first example is that the fourth transistor M4 is removed from the duty cycle adjustment module 14 of the pixel driving circuit, and only the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the third storage capacitor C3 are included. Although the pixel driving circuit in this example lacks the fourth transistor M4 compared to the pixel driving circuit in the first example, it does not affect the output of the signal output terminal OUTPUT. This kind of pixel driving circuit has a relatively small number of transistors, so it helps to display the panel with high resolution and high aperture ratio.

[0091] The remaining structures in the third example are the same as those in the first example, and the driving method of the pixel driving circuit is also the same as that in the first example, so they will not be repeated here.

[0092] The fourth example, FIG4 is a schematic diagram of a pixel driving circuit of the fourth example of the embodiment of the present disclosure; as shown in FIG4, the pixel driving circuit in this example is substantially the same as the third example, and the only difference from the pixel driving circuit in the third example is that the first transistor M1 in the input module 11 of the pixel driving circuit adopts an N-type transistor. Affected by the parasitic capacitance of the first transistor M1, if the first transistor M1 adopts a P-type transistor, the signal outputted by the signal output terminal OUTPUT will be pulled up when the first transistor M1 is turned off, which will cause the risk of leakage of the sixth transistor M6. However, the first transistor M1 adopts an N-type transistor, and when the first transistor M1 is turned off, the output of the signal output terminal OUTPUT will be pulled down, thereby avoiding leakage of the sixth transistor M6. However, it should be noted that in the third example, since the first transistor M1 is a P-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputL, and in the fourth example, since the first transistor M1 is an N-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputH, and the timing of HF_InputH is opposite to that of HF_InputL.

[0093] Fifth example: FIG5 is a schematic diagram of a pixel driving circuit of the fifth example of the embodiment of the present disclosure; as shown in FIG5 , the pixel driving circuit in this example is substantially the same as that in the first example, and the only difference from the pixel driving circuit in the first example is that the first light-emitting control subcircuit 2 is different. The first light-emitting control subcircuit 2 includes an eleventh transistor M11, a fourteenth transistor M14, a fourth storage capacitor C4, and a fifth storage capacitor; the eleventh transistor M11 has a switching characteristic opposite to that of the second transistor M2, and has the same switching characteristic as that of the fourteenth transistor M14, that is, the eleventh transistor M11 and the fourteenth transistor M14 are both P-type transistors.

[0094] Specifically, the first electrode of the eleventh transistor M11 is connected to the data signal terminal, the second electrode of the eleventh transistor M11 is connected to the first end of the fourth storage capacitor C4 and the control electrode of the twelfth transistor M12, and the control electrode of the eleventh transistor M11 is connected to the light-emitting control signal terminal EOA. The second end of the fourth storage capacitor C4 is connected to the first power supply voltage terminal. The first electrode of the fourteenth transistor M14 is connected to the data signal terminal, the second electrode of the fourteenth transistor M14 is connected to the first end of the fifth capacitor and the control electrode of the thirteenth transistor M13, and the control electrode of the fourteenth transistor M14 is connected to the light-emitting control signal terminal EOA. The second end of the fifth storage capacitor is connected to the first power supply voltage terminal.

[0095] It can be seen from this that the control electrode of the twelfth transistor M12 as the first light-emitting control subcircuit 2 is controlled by the output of the eleventh transistor M11, and the control electrode of the thirteenth transistor M13 as the second light-emitting control circuit is controlled by the output of the fourteenth transistor M14, and the first electrode of the twelfth transistor M12 is connected to the first light-emitting voltage terminal, and the first electrode of the thirteenth transistor M13 is connected to the second light-emitting voltage terminal, and the eleventh transistor M11 and the fourteenth transistor M14 both output the same data voltage signal when turned on, so the twelfth transistor M12 and the fourteenth transistor M14 can select transistors with the same switching characteristics, and in the light-emitting stage, the twelfth transistor M12 and the thirteenth transistor M13 have different light-emitting voltages written into their first electrodes, so only one transistor is turned on to control the light-emitting device D to be driven to emit light. That is to say, the twelfth transistor M12 and the thirteenth transistor M13 can both use P-type transistors or both use N-type transistors. Preferably, the twelfth transistor M12 and the thirteenth transistor M13 , and the eleventh transistor M11 and the fourteenth transistor M14 are transistors having the same switching characteristics, that is, P-type transistors, for ease of preparation.

[0096] The remaining structures in the pixel driving circuit of the fifth example are the same as those in the first example, so they are not described here in detail. Since the gate driving subcircuit 1 in the pixel driving circuit of the fifth example is the same as that in the first example, the method for generating the gate driving signal is also the same, so the method for generating the gate driving signal in this example is not described in detail.

[0097] In the following, the driving method of the pixel driving circuit of the embodiment of the present disclosure is described in combination with the generation of the gate driving signal of the gate driving subcircuit 1 of the pixel driving circuit in the first example above. The driving method of the pixel driving circuit may specifically include the following stages:

[0098] Data voltage writing stage: a low-level signal is written to the light-emitting control signal terminal EOA, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the data control voltage is written to the second node R and stored in the third storage capacitor C3, the eleventh transistor M11 and the fourteenth transistor M14 are turned on, and the data voltage signal is written to the control electrode of the twelfth transistor M12 and the fourth storage capacitor C4, and the control electrode of the thirteenth transistor M13 and the fifth storage capacitor respectively; the data voltage signal controls one of the first light-emitting voltage and the second light-emitting voltage to be written to the first electrode of the light-emitting device D to be driven. If the data voltage signal turns on the twelfth transistor M12, the first light-emitting voltage participates in the light emission, and the low grayscale segment display is realized; if the data voltage signal turns on the fourteenth transistor M14, the second light-emitting voltage participates in the light emission, and the high grayscale segment display is realized.

[0099] When the high grayscale segment is displayed, the data voltage signal terminal Data C writes a low level signal, the thirteenth transistor M13 is turned on, and the second light-emitting voltage (high voltage) signal is written to the light-emitting device D to be driven, with a maximum brightness of 255 grayscales. The display of different grayscales in the high grayscale segment is achieved by adjusting the duty cycle of the gate drive signal output by the signal output terminal OUTPUT. However, the minimum duty cycle that the gate drive subcircuit 1 can achieve is 0.1% (11 grayscales), and 1 to 10 grayscales (low grayscale segment) cannot be achieved.

[0100] When displaying grayscale 1 to 10 (low grayscale segment), the data voltage signal terminal Data C is written with high voltage, the twelfth transistor M12 is turned on, and the first light-emitting voltage (low voltage) signal is written to the light-emitting device D to be driven, and the maximum brightness is 23 grayscales (that is, when the duty cycle of the signal output by the signal output terminal OUTPUT is 100%). At this time, when the duty cycle of the gate drive signal output by the signal output terminal OUTPUT is adjusted to 0.1%, the brightness is 1 / 1000 of 23 grayscales, and 1 grayscale display can be achieved. Similarly, 2 to 22 grayscale display can be achieved.

[0101] 5 , by writing different data voltage control signals, the duty cycle of the gate driving signal outputted from the signal output terminal OUTPUT can be adjusted, and high and low grayscale segment display can be achieved by combining the first light-emitting voltage and the first light-emitting voltage signal.

[0102] Sixth example: FIG6 is a schematic diagram of a pixel driving circuit of the sixth example of an embodiment of the present disclosure; as shown in FIG6 , the pixel driving circuit in this example is substantially the same as the fifth example, and the only difference from the pixel driving circuit in the fifth example is that the first transistor M1 in the input module 11 of the pixel driving circuit adopts an N-type transistor. Affected by the parasitic capacitance of the first transistor M1, if the first transistor M1 adopts a P-type transistor, the signal outputted by the signal output terminal OUTPUT will be pulled up when the first transistor M1 is turned off, which will cause the risk of leakage of the sixth transistor M6. However, the first transistor M1 adopts an N-type transistor, and when the first transistor M1 is turned off, the output of the signal output terminal OUTPUT will be pulled down, thereby avoiding leakage of the sixth transistor M6. However, it should be noted that in the fifth example, since the first transistor M1 is a P-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputL, and in the sixth example, since the first transistor M1 is an N-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputH, and the timing of HF_InputH is opposite to that of HF_InputL.

[0103] The remaining structures in the sixth example are the same as those in the fifth example, and the driving method of the pixel driving circuit is also the same as that in the fifth example, so they will not be repeated here.

[0104] 7 and 8 are pixel driving circuits of the first to sixth examples of the embodiments of the present disclosure, which are output simulation diagrams of the signal output terminal OUTPUT of the gate driving sub-circuit 1 under different data control voltages; as shown in FIGS. 7 and 8 , by writing different data voltage control signals, the duty cycle of the gate driving signal output by the signal output terminal OUTPUT can be adjusted, and the display of high and low grayscale segments can be achieved in combination with the first light-emitting voltage and the second light-emitting voltage.

[0105] Seventh example: FIG. 9 is a schematic diagram of a pixel driving circuit of the seventh example of an embodiment of the present disclosure; as shown in FIG. 9 , in this example, the input module 11 in the pixel driving subcircuit includes a first transistor M1; the reset module 12 includes a second transistor M2; the output module 13 includes a third transistor M3, a first storage capacitor C1 and a second storage capacitor C2; the duty cycle adjustment module 14 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a third storage capacitor C3. Among them, the switching characteristics of the first transistor M1, the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are the same. The switching characteristics of the second transistor M2 are opposite to those of the first transistor M1, and are the same as those of the fifth transistor M5, the sixth transistor M6 and the eighth transistor M8. In this example, the first transistor M1, the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are all P-type transistors, and the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the eighth transistor M8 are all N-type transistors.

[0106] Specifically, the first electrode of the first transistor M1 is connected to the first power supply voltage terminal, the second electrode of the first transistor M1 is connected to the second electrode of the third transistor M3, the first end of the first storage capacitor C1 and the signal output terminal OUTPUT, and the control electrode of the first transistor M1 is connected to the signal control terminal HF_Input. The first electrode of the second transistor M2 is connected to the first node Q, and the second electrode of the second transistor M2 is connected to its control electrode and the reset signal terminal HF_Reset. The first electrode of the third transistor M3 is connected to the second power supply voltage terminal, the second electrode of the third transistor M3 is connected to the signal output terminal OUTPUT and the first end of the first storage capacitor C1, and the control electrode of the third transistor M3 is connected to the first node Q. The second end of the first storage capacitor C1 is connected to the second end of the second storage capacitor C2 and the first power supply voltage terminal, and the first end of the second storage capacitor C2 is connected to the first node Q. The first electrode of the fourth transistor M4 is connected to the first node Q, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5 and the first electrode of the sixth transistor M6, and the control electrode of the fourth transistor M4 is connected to the reset signal terminal HF_Reset. The second electrode of the fifth transistor M5 is connected to the second electrode of the sixth transistor M6 and the first power supply voltage terminal, and the control electrode of the fifth transistor M5 is connected to the second electrode of the eighth transistor M8. The control electrode of the sixth transistor M6 is connected to the signal output terminal OUTPUT. The first electrode of the seventh transistor M7 is connected to the data voltage control signal terminal Data, the second electrode of the seventh transistor M7 is connected to the first end of the third storage capacitor C3 and the first electrode of the eighth transistor M8 (that is, the second node R), and the control electrode of the seventh transistor M7 is connected to the light-emitting control signal terminal EOA. The control electrode of the eighth transistor M8 is connected to the light-emitting control signal terminal EOA. The second end of the third storage capacitor C3 is connected to the first power supply voltage terminal.

[0107] Among them, only the first power supply voltage is 8V, and the second power supply voltage is -8V; in the timing of the first light-emitting voltage, the high-level signal is 12V, the low-level signal is -12V, the period H=1000μs, and the duty cycle is high-level signal / low-level signal=5μs / 995μs; in the timing of the second light-emitting voltage, the high-level signal is 12V, the low-level signal is -12V, the period H=1000μs, and the duty cycle is low-level signal / high-level signal=5μs / 995μs; in the timing of the reset signal, the high-level signal is 20V, the low level signal is -12V, the period H=1000μs, the duty cycle is high level signal / low level signal=996μs / 4μs; the data voltage control signal Datastep=[5.6V, 5.85V], the first capacitor and the third storage capacitor C3 are both 50fF, the second capacitor=500fF. Taking the gate drive sub-circuit 1 of the pixel drive circuit in the seventh example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of products.

[0108] The following describes a method for generating a gate driving signal of the gate driving subcircuit 1 of the pixel driving circuit. The method may specifically include the following stages:

[0109] Phase 1: the reset signal written into the reset signal terminal HF_Reset is a low level signal, the second transistor M2 is turned on, the fourth transistor M4 is turned off, the potential of the first node Q is reset to -20V, and the third transistor M3 is turned off.

[0110] The second stage: the reset signal written into the reset signal terminal HF_Reset is a high-level signal, the second transistor M2 is turned off, the fourth transistor M4 is turned on, the input control signal written into the input signal control terminal HF_Input is a high-level signal, the first transistor M1 is turned on, the first power supply voltage is written into the first storage capacitor C1, and the signal output terminal OUTPUT outputs a high-level signal. At the same time, the sixth transistor M6 is turned off, and the first node Q is charged through the first power supply voltage. A low-level signal is written into the light-emitting control signal terminal EOA, the seventh transistor M7 is turned on, the data voltage control signal is written into the second node R and the third storage capacitor C3, the light-emitting control signal terminal EOA is written into a high-level signal, the eighth transistor M8 is turned on, and the saturation current Id of the fifth transistor M5 is controlled by the potential of the second node R, and the charging speed of the first node Q is controlled.

[0111] The third stage: after time t, when the voltage charged to the first node Q minus the second power supply voltage (that is, the gate-source voltage Vgs of the third transistor M3) is greater than the threshold voltage Vth of the third transistor M3, that is, VQ-VSS>Vth, the second power supply voltage written into the second power supply voltage terminal is written into the first storage capacitor C1, and the signal output terminal OUTPUT outputs a low level signal. At this time, the sixth transistor M6 is turned on, and the voltage of the first node Q is quickly charged to the first power supply voltage.

[0112] Phase 4: The reset signal written into the reset signal terminal HF_Reset is a low level signal, the second transistor M2 is turned on, the fourth transistor M4 is turned off, the potential of the first node Q is reset to -20V, the third transistor M3 is turned off, the first storage capacitor C1 maintains a low level, and the signal output terminal OUTPUT continues to output a low level signal.

[0113] The next cycle begins to repeat stages 2 to 4.

[0114] It can be seen that the data voltage control signal is written into the control electrode of the fifth transistor M5, and the charging speed of the first node Q is controlled by controlling the saturation current Id of the fifth transistor M5. The time t required for the first node Q to discharge to VQ-VSS>Vth is the duration of the high-level signal in the clock cycle of the input clock signal. By adjusting the voltage of the data voltage control signal, the output gate drive signal with different duty ratios can be obtained.

[0115] Next, continue to refer to FIG. 9. In this example, the light-emission duration control subcircuit 3 in the pixel driving circuit includes a ninth transistor M9, the second light-emission control subcircuit 4 includes a tenth transistor M10, the first light-emission control subcircuit 2 includes an eleventh transistor M11 and a fourth storage capacitor C4, the first light-emission voltage control subcircuit 5 includes a twelfth transistor M12, and the second light-emission voltage control subcircuit 6 includes a thirteenth transistor M13. Among them, the switching characteristics of the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 are the same, and are the same as the switching characteristics of the second switching transistor, that is, a P-type transistor is used. The switching characteristics of the eleventh transistor M11 and the twelfth transistor M12 are the same, and are different from the switching characteristics of the ninth transistor M9, that is, an N-type transistor is used.

[0116] Specifically, the first electrode of the ninth transistor M9 is connected to the second electrode of the twelfth transistor M12 and the second electrode of the thirteenth transistor M13, the second electrode of the ninth transistor M9 is connected to the first electrode of the tenth transistor M10, and the control electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The second electrode of the tenth transistor M10 is connected to the first electrode of the light-emitting device D to be driven, and the control electrode of the tenth transistor M10 is connected to the light-emitting control signal terminal EOA. The first electrode of the eleventh transistor M11 is connected to the data voltage signal terminal Data C, the second electrode of the eleventh transistor M11 is connected to the first end of the fourth storage capacitor C4, and the control electrode of the eleventh transistor M11 is connected to the light-emitting control signal terminal EOA. The second end of the fourth storage capacitor C4 is connected to the first power supply voltage terminal. The first electrode of the twelfth transistor M12 is connected to the first light-emitting voltage terminal, and the control electrode of the twelfth transistor M12 is connected to the control electrode of the thirteenth transistor M13, the second electrode of the eleventh transistor M11 and the first end of the fourth storage capacitor C4. The first electrode of the thirteenth transistor M13 is connected to the second light-emitting voltage terminal.

[0117] In the following, the driving method of the pixel driving circuit of the embodiment of the present disclosure is described in combination with the generation of the gate driving signal of the gate driving subcircuit 1 of the pixel driving circuit. The driving method of the pixel driving circuit may specifically include the following stages:

[0118] Data voltage writing stage: a high level signal is written to the light emitting control signal terminal EOA, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the data control voltage is written to the second node R, and stored in the third storage capacitor C3.

[0119] Light-emitting stage: A low-level signal is written to the light-emitting control signal terminal EOA, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the saturation current Id of the fifth transistor M5 is controlled by the potential of the second node R, and the charging speed of the first node Q is controlled, thereby controlling the duty cycle of the gate drive signal output by the signal output terminal OUTPUT. When the gate drive signal is low and the signal input to the light-emitting control signal terminal EOA is a low-level signal, the ninth transistor M9 and the tenth transistor M10 are turned on. When a high-level signal is written to the light-emitting control signal terminal EOA, the light emission stops. In the light-emitting stage, according to the grayscale to be displayed, the data voltage signal terminal Data C writes the corresponding data voltage signal to control one of the first light-emitting voltage and the second light-emitting voltage to be output to the light-emitting device D to be driven.

[0120] Specifically, the ratio formula of different grayscale brightness to 255 grayscale brightness is as follows:

[0121] N grayscale brightness = 255 grayscale brightness * (N / 255) gamma

[0122] When driven by a duty cycle gate drive signal, the N grayscale duty cycle is:

[0123] N grayscale duty cycle = 255 grayscale duty cycle * (N / 255) gamma

[0124] Assuming that the duty cycle of grayscale 255 is 100%, that is, the light-emitting device D is always working in the 1H display period, the duty cycles of other grayscales can be calculated by the above formula, for example, the duty cycle of grayscale 1 = 0.0005%, the duty cycle of grayscale 23 = 0.5%. It can be seen that the duty cycle of grayscale 1, that is, the brightness, is 1 / 1000 of that of grayscale 23.

[0125] When the high grayscale segment is displayed, the data voltage signal terminal Data C writes a low level signal, the thirteenth transistor M13 is turned on, and the second light-emitting voltage (high voltage) signal is written to the light-emitting device D to be driven, with a maximum brightness of 255 grayscales. The display of different grayscales in the high grayscale segment is achieved by adjusting the duty cycle of the gate drive signal output by the signal output terminal OUTPUT. However, the minimum duty cycle that the gate drive subcircuit 1 can achieve is 0.1% (11 grayscales), and 1 to 10 grayscales (low grayscale segment) cannot be achieved.

[0126] When displaying grayscale 1 to 10 (low grayscale segment), the data voltage signal terminal Data C is written with high voltage, the twelfth transistor M12 is turned on, and the first light-emitting voltage (low voltage) signal is written to the light-emitting device D to be driven, and the maximum brightness is 23 grayscales (that is, when the duty cycle of the signal output by the signal output terminal OUTPUT is 100%). At this time, when the duty cycle of the gate drive signal output by the signal output terminal OUTPUT is adjusted to 0.1%, the brightness is 1 / 1000 of 23 grayscales, and 1 grayscale display can be achieved. Similarly, 2 to 22 grayscale display can be achieved.

[0127] Eighth example: FIG. 10 is a schematic diagram of a pixel driving circuit of the eighth example of an embodiment of the present disclosure; as shown in FIG. 10 , the pixel driving circuit in this example is substantially the same as the seventh example, and the only difference from the pixel driving circuit in the seventh example is that the first transistor M1 in the input module 11 of the pixel driving circuit adopts a P-type transistor. Affected by the parasitic capacitance of the first transistor M1, if the first transistor M1 adopts an N-type transistor, the signal outputted by the signal output terminal OUTPUT will be pulled up when the first transistor M1 is turned off, which will cause the risk of leakage of the sixth transistor M6. However, the first transistor M1 adopts a P-type transistor, and when the first transistor M1 is turned off, the output of the signal output terminal OUTPUT will be pulled down, thereby avoiding leakage of the sixth transistor M6. However, it should be noted that in the first example, since the first transistor M1 is an N-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputH, while in the second example, since the first transistor M1 is a P-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputL, and the timing of HF_InputH is opposite to that of HF_InputL.

[0128] The remaining structures in the eighth example are the same as those in the seventh example, and the driving method of the pixel driving circuit is also the same as that in the seventh example, so they will not be repeated here.

[0129] Ninth example: FIG. 11 is a schematic diagram of a pixel driving circuit of the ninth example of an embodiment of the present disclosure; as shown in FIG. 11 , the pixel driving circuit in this example is substantially the same as the seventh example, and the only difference from the pixel driving circuit in the first example is that the fourth transistor M4 is removed from the duty cycle adjustment module 14 of the pixel driving circuit, and only the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the third storage capacitor C3 are included. Although the pixel driving circuit in this example lacks the fourth transistor M4 compared to the pixel driving circuit in the seventh example, it does not affect the output of the signal output terminal OUTPUT. This pixel driving circuit has a relatively small number of transistors, so it helps to display the panel with high resolution and high aperture ratio.

[0130] The remaining structures in the ninth example are the same as those in the seventh example, and the driving method of the pixel driving circuit is also the same as that in the seventh example, so they will not be repeated here.

[0131] The tenth example, FIG. 12 is a schematic diagram of a pixel driving circuit of the tenth example of an embodiment of the present disclosure; as shown in FIG. 12 , the pixel driving circuit in this example is substantially the same as the ninth example, and the only difference from the pixel driving circuit in the ninth example is that the first transistor M1 in the input module 11 of the pixel driving circuit adopts a P-type transistor. Affected by the parasitic capacitance of the first transistor M1, if the first transistor M1 adopts an N-type transistor, the signal outputted by the signal output terminal OUTPUT will be pulled up when the first transistor M1 is turned off, which will cause the risk of leakage of the sixth transistor M6. However, the first transistor M1 adopts a P-type transistor, and when the first transistor M1 is turned off, the output of the signal output terminal OUTPUT will be pulled down, thereby avoiding leakage of the sixth transistor M6. However, it should be noted that in the first example, since the first transistor M1 is an N-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputH, and in the second example, since the first transistor M1 is a P-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputL, and the timing of HF_InputH is opposite to that of HF_InputL.

[0132] Eleventh example: FIG. 13 is a schematic diagram of a pixel driving circuit of the eleventh example of the embodiment of the present disclosure; as shown in FIG. 13 , the pixel driving circuit in this example is substantially the same as the seventh example, and the only difference from the pixel driving circuit in the first example is that the first light-emitting control subcircuit 2 is different. The first light-emitting control subcircuit 2 includes an eleventh transistor M11, a fourteenth transistor M14, a fourth storage capacitor C4, and a fifth storage capacitor; the eleventh transistor M11 has a switching characteristic opposite to that of the second transistor M2, and has the same switching characteristic as that of the fourteenth transistor M14, that is, the eleventh transistor M11 and the fourteenth transistor M14 are both N-type transistors.

[0133] Specifically, the first electrode of the eleventh transistor M11 is connected to the data signal terminal, the second electrode of the eleventh transistor M11 is connected to the first end of the fourth storage capacitor C4 and the control electrode of the twelfth transistor M12, and the control electrode of the eleventh transistor M11 is connected to the light-emitting control signal terminal EOA. The second end of the fourth storage capacitor C4 is connected to the first power supply voltage terminal. The first electrode of the fourteenth transistor M14 is connected to the data signal terminal, the second electrode of the fourteenth transistor M14 is connected to the first end of the fifth capacitor and the control electrode of the thirteenth transistor M13, and the control electrode of the fourteenth transistor M14 is connected to the light-emitting control signal terminal EOA. The second end of the fifth storage capacitor is connected to the first power supply voltage terminal.

[0134] It can be seen from this that the control electrode of the twelfth transistor M12 as the first light-emitting control subcircuit 2 is controlled by the output of the eleventh transistor M11, and the control electrode of the thirteenth transistor M13 as the second light-emitting control circuit is controlled by the output of the fourteenth transistor M14, and the first electrode of the twelfth transistor M12 is connected to the first light-emitting voltage terminal, and the first electrode of the thirteenth transistor M13 is connected to the second light-emitting voltage terminal, and the eleventh transistor M11 and the fourteenth transistor M14 both output the same data voltage signal when turned on, so the twelfth transistor M12 and the fourteenth transistor M14 can select transistors with the same switching characteristics, and in the light-emitting stage, the twelfth transistor M12 and the thirteenth transistor M13 have different light-emitting voltages written into their first electrodes, so only one transistor is turned on to control the light-emitting device D to be driven to emit light. That is to say, the twelfth transistor M12 and the thirteenth transistor M13 can both use P-type transistors or both use N-type transistors. Preferably, the twelfth transistor M12 and the thirteenth transistor M13 , and the eleventh transistor M11 and the fourteenth transistor M14 are transistors having the same switching characteristics, that is, N-type transistors, for ease of preparation.

[0135] The remaining structures of the pixel driving circuit of the eleventh example are the same as those of the seventh example, so they are not described here in detail. Since the gate driving subcircuit 1 in the pixel driving circuit of the eleventh example is the same as that of the first example, the method for generating the gate driving signal is also the same, so the method for generating the gate driving signal in this example is not repeated in detail.

[0136] In the following, the driving method of the pixel driving circuit of the embodiment of the present disclosure is described in combination with the generation of the gate driving signal of the gate driving subcircuit 1 of the pixel driving circuit in the seventh example. The driving method of the pixel driving circuit may specifically include the following stages:

[0137] Data voltage writing stage: a high-level signal is written to the light-emitting control signal terminal EOA, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the data control voltage is written to the second node R and stored in the third storage capacitor C3, the eleventh transistor M11 and the fourteenth transistor M14 are turned on, and the data voltage signal is written to the control electrode of the twelfth transistor M12 and the fourth storage capacitor C4, and the control electrode of the thirteenth transistor M13 and the fifth storage capacitor respectively; the data voltage signal controls one of the first light-emitting voltage and the second light-emitting voltage to be written to the first electrode of the light-emitting device D to be driven. If the data voltage signal turns on the twelfth transistor M12, the first light-emitting voltage participates in the light emission, and the low grayscale segment display is realized; if the data voltage signal turns on the fourteenth transistor M14, the second light-emitting voltage participates in the light emission, and the high grayscale segment display is realized.

[0138] When the high grayscale segment is displayed, the data voltage signal terminal Data C writes a high level signal, the thirteenth transistor M13 is turned on, and the second light-emitting voltage (high voltage) signal is written to the light-emitting device D to be driven, with a maximum brightness of 255 grayscales. The display of different grayscales in the high grayscale segment is achieved by adjusting the duty cycle of the gate drive signal output by the signal output terminal OUTPUT. However, the minimum duty cycle that the gate drive subcircuit 1 can achieve is 0.1% (11 grayscales), and 1 to 10 grayscales (low grayscale segment) cannot be achieved.

[0139] When displaying grayscale 1 to 10 (low grayscale segment), the data voltage signal terminal Data C is written with high voltage, the twelfth transistor M12 is turned on, and the first light-emitting voltage (low voltage) signal is written to the light-emitting device D to be driven, and the maximum brightness is 23 grayscales (that is, when the duty cycle of the signal output by the signal output terminal OUTPUT is 100%). At this time, when the duty cycle of the gate drive signal output by the signal output terminal OUTPUT is adjusted to 0.1%, the brightness is 1 / 1000 of 23 grayscales, and 1 grayscale display can be achieved. Similarly, 2 to 22 grayscale display can be achieved.

[0140] 13 , by writing different data voltage control signals, the duty cycle of the gate driving signal outputted from the signal output terminal OUTPUT can be adjusted, and high and low grayscale segment display can be achieved by combining the first light-emitting voltage and the first light-emitting voltage signal.

[0141] Example 12: FIG. 14 is a schematic diagram of a pixel driving circuit of the twelfth example of an embodiment of the present disclosure; as shown in FIG. 14 , the pixel driving circuit in this example is substantially the same as the eleventh example, and the only difference from the pixel driving circuit in the eleventh example is that the first transistor M1 in the input module 11 of the pixel driving circuit adopts a P-type transistor. Affected by the parasitic capacitance of the first transistor M1, if the first transistor M1 adopts an N-type transistor, the signal outputted by the signal output terminal OUTPUT will be pulled up when the first transistor M1 is turned off, which will cause the risk of leakage of the sixth transistor M6. However, the first transistor M1 adopts a P-type transistor, and when the first transistor M1 is turned off, the output of the signal output terminal OUTPUT will be pulled down, thereby avoiding leakage of the sixth transistor M6. However, it should be noted that in the first example, since the first transistor M1 is an N-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputH, and in the second example, since the first transistor M1 is a P-type transistor, the timing signal input to the input signal control terminal HF_Input is HF_InputL, and the timing of HF_InputH is opposite to that of HF_InputL.

[0142] The remaining structures in the twelfth example are the same as those in the eleventh example, and the driving method of the pixel driving circuit is also the same as that in the eleventh example, so they will not be repeated here.

[0143] Figures 15 and 16 are pixel driving circuits of the seventh to twelfth examples of the embodiments of the present disclosure, which are output simulation diagrams of the signal output terminal OUTPUT of the gate driving sub-circuit 1 under different data control voltages; as shown in Figures 15 and 16, by writing different data voltage control signals, the duty cycle of the gate driving signal output by the signal output terminal OUTPUT can be adjusted, and the display of high and low grayscale segments can be achieved in combination with the first light-emitting voltage and the second light-emitting voltage.

[0144] The embodiment of the present disclosure provides a display device, which includes any one of the above-mentioned pixel driving circuits. Of course, the display device also includes a light-emitting device electrically connected to the pixel driving circuit. The light-emitting device can be an organic light emitting diode (OLED). Of course, the light-emitting device D can also be a miniature inorganic light-emitting diode, and further, it can be a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED).

[0145] The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiment of the present invention is not limited thereto.

[0146] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

A pixel driving circuit, comprising a gate driving subcircuit, a first light-emitting control subcircuit, a first voltage control subcircuit, a second voltage control subcircuit, a light-emitting time control subcircuit and a second light-emitting control subcircuit; the gate driving subcircuit is configured to output a gate driving signal with an adjustable duty cycle; the first light-emitting control subcircuit is configured to control the first voltage control subcircuit to output a first light-emitting voltage through a data voltage signal in response to the light-emitting control signal, or to control the second voltage control subcircuit to output a second light-emitting voltage through the data voltage signal; the light-emitting time control subcircuit is configured to output the first light-emitting voltage or the second light-emitting voltage received under the control of the gate driving signal; The second light-emitting control subcircuit is configured to output the received first light-emitting voltage or the second light-emitting voltage to the light-emitting device to be driven under the control of the light-emitting control signal; wherein, The gate drive subcircuit includes: an input module, configured to respond to an input control signal, and control a signal output terminal to output a first power supply voltage or a second power supply voltage; a reset module, configured to respond to a reset signal and reset a first node through the reset signal; the first node is a connection node between the output module and the duty cycle adjustment module; the duty cycle adjustment module is configured to respond to the light emitting control signal and control the potential of the first node through a data voltage control signal; the output module is configured to respond to the potential of the first node and output the gate drive signal of the corresponding duty cycle through a signal output terminal; wherein the potential of the gate drive signal jumps between the first power supply voltage and the second power supply voltage. The pixel driving circuit according to claim 1, wherein: The input module comprises a first transistor; a first electrode of the first transistor is connected to a second power supply voltage terminal, a second electrode is connected to the output module, and a control electrode is connected to an input signal control terminal. The pixel driving circuit according to claim 2, wherein: The reset module comprises a second transistor; a first electrode of the second transistor is connected to the first node, and a second electrode is connected to its control electrode and a reset signal terminal. The pixel driving subcircuit according to claim 3, wherein: The output module includes a third transistor, a first storage capacitor and a second storage capacitor; the switching characteristics of the third transistor are opposite to those of the second transistor; the first electrode of the third transistor is connected to the first power supply voltage terminal, the second electrode is connected to the signal output terminal and the first terminal of the first storage capacitor, and the control electrode is connected to the first node; The second end of the first storage capacitor is connected to the second end of the second storage capacitor and the second power supply voltage end, and the first end of the second storage capacitor is connected to the first node. The pixel driving circuit according to claim 3, wherein: The duty cycle adjustment module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the fourth transistor and the seventh transistor have switching characteristics opposite to those of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as those of the second transistor; the first electrode of the fourth transistor is connected to the first node, the second electrode is connected to the first electrode of the fifth transistor and the first electrode of the sixth transistor, and the control electrode is connected to the reset signal terminal; the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the second power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal terminal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal. The pixel driving circuit according to claim 3, wherein: The duty cycle adjustment module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the seventh transistor has a switching characteristic opposite to that of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as the switching characteristics of the second transistor; The first electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the first node, the second electrode is connected to the second electrode of the sixth transistor and the second power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal. The pixel driving circuit according to claim 1, wherein: The input module comprises a first transistor; a first electrode of the first transistor is connected to a first power supply voltage terminal, a second electrode is connected to the output module, and a control electrode is connected to an input signal control terminal. The pixel driving circuit according to claim 7, wherein: The reset module comprises a second transistor; a first electrode of the second transistor is connected to the first node, and a second electrode is connected to its control electrode and a reset signal terminal. The pixel driving circuit according to claim 8, wherein: The output module includes a third transistor, a first storage capacitor and a second storage capacitor; the switching characteristics of the third transistor are opposite to those of the second transistor; the first electrode of the third transistor is connected to the second power supply voltage terminal, the second electrode is connected to the signal output terminal and the first terminal of the first storage capacitor, and the control electrode is connected to the first node; The second end of the first storage capacitor is connected to the second end of the second storage capacitor and the second power supply voltage end, and the first end of the second storage capacitor is connected to the first node. The pixel driving circuit according to claim 8, wherein: The duty cycle adjustment module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the fourth transistor and the seventh transistor have switching characteristics opposite to those of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as those of the second transistor; the first electrode of the fourth transistor is connected to the first node, the second electrode is connected to the first electrode of the fifth transistor and the first electrode of the sixth transistor, and the control electrode is connected to the reset signal terminal; the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the first power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal. The pixel driving circuit according to claim 8, wherein: The duty cycle adjustment module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third storage capacitor; the seventh transistor has a switching characteristic opposite to that of the second transistor; the switching characteristics of the fifth transistor, the sixth transistor and the eighth transistor are the same as the switching characteristics of the second transistor; the first electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the first node, the second electrode is connected to the second electrode of the sixth transistor and the first power supply voltage terminal, and the control electrode is connected to the second electrode of the eighth transistor; the control electrode of the sixth transistor is connected to the signal output terminal; the first electrode of the seventh transistor is connected to the data voltage control signal, the second electrode is connected to the first end of the third storage capacitor and the first electrode of the eighth transistor, and the control electrode is connected to the light-emitting control signal terminal; the control electrode of the eighth transistor is connected to the light-emitting control signal terminal; the second end of the third storage capacitor is connected to the first power supply voltage terminal. The pixel driving circuit according to any one of claims 3-6 and 8-11, wherein: The first light-emitting control subcircuit includes an eleventh transistor and a fourth storage capacitor; the eleventh transistor has opposite switching characteristics to the second transistor; the first electrode of the eleventh transistor is connected to the data signal terminal, the second electrode is connected to the first end of the fourth storage capacitor, the first voltage control subcircuit and the second voltage control subcircuit, and the control electrode is connected to the light-emitting control signal terminal; the second end of the fourth storage capacitor is connected to the first power supply voltage terminal. The pixel driving circuit according to claim 12, wherein: The first voltage control subcircuit includes a twelfth transistor, and the second voltage control subcircuit includes a thirteenth transistor; the twelfth transistor has the same switching characteristics as the eleventh transistor, and opposite switching characteristics to the thirteenth transistor; the first electrode of the twelfth transistor is connected to the first voltage terminal, the second electrode is connected to the second electrode of the thirteenth transistor and the light-emitting time control subcircuit, and the control electrode is connected to the control electrode of the thirteenth transistor and the second electrode of the eleventh transistor; the first electrode of the thirteenth transistor is connected to the second voltage terminal. The pixel driving circuit according to any one of claims 3-6 and 8-11, wherein: The first light-emitting control subcircuit includes an eleventh transistor, a fourteenth transistor, a fourth storage capacitor and a fifth storage capacitor; the eleventh transistor has a switching characteristic opposite to that of the second transistor and the same as that of the fourteenth transistor; the first electrode of the eleventh transistor is connected to the data signal terminal, the second electrode is connected to the first end of the fourth storage capacitor and the first voltage control subcircuit, and the control electrode is connected to the light-emitting control signal terminal; the second end of the fourth storage capacitor is connected to the first power supply voltage terminal; the first electrode of the fourteenth transistor is connected to the data signal terminal, the second electrode is connected to the first end of the fifth capacitor and the second voltage control subcircuit, and the control electrode is connected to the light-emitting control signal terminal; The second terminal of the fifth storage capacitor is connected to the first power supply voltage terminal. The pixel driving circuit according to claim 14, wherein: The first voltage control subcircuit includes a twelfth transistor, and the second voltage control subcircuit includes a thirteenth transistor; the twelfth transistor has opposite switching characteristics to the thirteenth transistor; the first electrode of the twelfth transistor is connected to the first voltage terminal, the second electrode is connected to the second electrode of the thirteenth transistor and the light-emitting time control subcircuit, and the control electrode is connected to the control electrode of the thirteenth transistor and the second electrode of the eleventh transistor; the first electrode of the thirteenth transistor is connected to the second voltage terminal. The pixel driving circuit according to claim 15, wherein: The thirteenth transistor has the same switching characteristics as the eleventh transistor. The pixel driving circuit according to claim 12, wherein: The light-emitting time control subcircuit includes a ninth transistor, and the switching characteristics of the ninth transistor are the same as the switching characteristics of the second transistor; the first electrode of the ninth transistor is connected to the first voltage control subcircuit and the second voltage control subcircuit, the second electrode is connected to the second light-emitting control subcircuit, and the control electrode is connected to the signal output terminal. The pixel driving circuit according to claim 12, wherein: The second light-emitting control subcircuit includes a tenth transistor; the switching characteristics of the tenth transistor are the same as the switching characteristics of the second transistor; the first electrode of the ninth transistor is connected to the light-emitting time control subcircuit, the second electrode is connected to the light-emitting device to be driven, and the control electrode is connected to the light-emitting control terminal. The pixel driving circuit according to claim 1, wherein: The light-emitting device to be driven includes any one of LED, OLED, Micro LED, and Mini LED. A display device comprising the pixel driving circuit according to any one of claims 1 to 19.

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