Array substrate, driving method thereof, display panel and display device

Abstract

An array substrate, a driving method thereof, a display panel and a display device, the array substrate comprising: a plurality of pixel groups (C), each pixel group (C) comprising two sub-pixels arranged along a column direction (Y), each column of pixel groups (C) comprising a plurality of sub-pixels (A1, A2, A3) with a plurality of alternately arranged display colors, the display colors of the sub-pixels located in the same row being the same; each data line group (D) comprises a first data line (D1) and a second data line (D2) which extend in the column direction (Y), each column of pixel groups (C) corresponds to one data line group (D), and the first data line (D1) and the second data line (D2) in each data line group (D) are located on the two opposite sides of each column of pixel groups (C) in the row direction (X) respectively; the first data line (D1) in each data line group (D) is electrically connected with one sub-pixel in each pixel group (C) in the corresponding column, and the second data line (D2) in each data line group (D) is electrically connected with the other sub-pixel in each pixel group (C) in the corresponding column; and a plurality of rows of scanning lines (G1, G2 and G3), each row of scanning lines (G1, G2 and G3) and each row of pixel groups (C) are alternately arranged in the column direction (Y), and the scanning lines (G1, G2 and G3) are electrically connected with the sub-pixels in the corresponding rows.

Description

An array substrate, a driving method thereof, a display panel and a display device

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, a display panel and a display device.

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation and easy to carry. It has been rapidly developed in recent years and has gradually replaced the traditional cathode ray tube display (CRT) and has occupied a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc.

[0003] Summary of the invention

[0004] The present disclosure provides an array substrate, a driving method thereof, a display panel and a display device, and the specific solutions are as follows:

[0005] An array substrate provided in an embodiment of the present disclosure includes:

[0006] A plurality of pixel groups arranged in an array along row and column directions, each of the pixel groups comprising two sub-pixels arranged along the column direction, each column of the pixel groups comprising a plurality of sub-pixels alternately arranged with a plurality of display colors, and the display colors of the sub-pixels in the same row are the same;

[0007] a plurality of data line groups, each of the data line groups comprising a first data line and a second data line extending along the column direction, each column of the pixel groups corresponding to one of the data line groups, and the first data line and the second data line in each of the data line groups are respectively located at opposite sides of each column of the pixel groups in the row direction; wherein the first data line in each of the data line groups is respectively electrically connected to one of the sub-pixels in each of the pixel groups in the corresponding column, and the second data line in each of the data line groups is respectively electrically connected to another of the sub-pixels in each of the pixel groups in the corresponding column;

[0008] A plurality of rows of scan lines, each row of the scan lines and each row of the pixel groups are alternately arranged in the column direction, and the scan lines are electrically connected to the sub-pixels in the corresponding row.

[0009] In a possible implementation, in the array substrate provided in the embodiment of the present disclosure, each row of sub-pixels is electrically connected to the scan line most adjacent thereto.

[0010] In a possible implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, each sub-row sub-pixel in the pixel group located in the Nth row is electrically connected to the scan line most adjacent to it, and the pixel group located in the N+1th row includes a first sub-row sub-pixel and a second sub-row sub-pixel, the first sub-row sub-pixel is electrically connected to the scan line most adjacent to the second sub-row sub-pixel, and the second sub-row sub-pixel is electrically connected to the scan line most adjacent to the first sub-row sub-pixel; wherein N is a positive integer.

[0011] In a possible implementation, in the array substrate provided in the embodiment of the present disclosure, two sub-pixels located on both sides of the same scan line and in the most adjacent column are connected to the same data line.

[0012] In a possible implementation, in the array substrate provided in the embodiment of the present disclosure, each row of pixel groups is electrically connected to the scan lines in the same row, and different rows of pixel groups are electrically connected to different rows of scan lines.

[0013] In a possible implementation, in the array substrate provided by an embodiment of the present disclosure, each column of the pixel group includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence in the column direction, the display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red; wherein,

[0014] Each of the first sub-pixels in the pixel group located in the Mth column is electrically connected to the first data line and the second data line of the corresponding group alternately, and each of the first sub-pixels in the pixel group located in the M+1th column is electrically connected to the first data line of the corresponding group;

[0015] Each of the second sub-pixels in the pixel group located in the Mth column is electrically connected to the second data line of the corresponding group, and each of the second sub-pixels in the pixel group located in the M+1th column is alternately electrically connected to the second data line and the first data line of the corresponding group;

[0016] Each of the third sub-pixels in the pixel group located in the Mth column is electrically connected to the first data line of the corresponding group, and each of the third sub-pixels in the pixel group located in the M+1th column is electrically connected to the second data line of the corresponding group; wherein M is a positive integer.

[0017] In a possible implementation, the array substrate provided in the embodiment of the present disclosure further includes a plurality of rows of common electrode lines, each row of the common electrode lines being located between two rows of sub-pixels in a corresponding row of the pixel group.

[0018] In a possible implementation manner, in the array substrate provided in the embodiment of the present disclosure, the common electrode lines and the scan lines are alternately arranged along the column direction.

[0019] In a possible implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, a sub-pixel in one of any two adjacent pixel groups in the column direction has the same display color as a sub-pixel in the other group, and a sub-pixel in any two adjacent sub-pixels in the column direction has different display colors.

[0020] In a possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the sub-pixels in each column are divided into a plurality of pixel units arranged in sequence in the column direction, and each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence in the column direction; the display colors of the first sub-pixel, the second sub-pixel and the third sub-pixel are different.

[0021] In a possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red.

[0022] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the length of each sub-pixel along the row direction is greater than the length along the column direction.

[0023] In a possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the sub-pixel includes a pixel electrode and a thin film transistor, the gate of the transistor is electrically connected to the corresponding scanning line, the first electrode of the transistor is electrically connected to the corresponding data line, and the second electrode of the transistor is electrically connected to the corresponding pixel electrode.

[0024] Correspondingly, an embodiment of the present disclosure further provides a display panel, comprising: the above-mentioned array substrate provided in the embodiment of the present disclosure, and an opposing substrate arranged in a box with the array substrate.

[0025] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure.

[0026] Correspondingly, the embodiment of the present disclosure further provides a driving method of an array substrate, which is used to drive the above array substrate provided by the embodiment of the present disclosure, and the driving method includes:

[0027] Within one frame time, a scan voltage is loaded onto the scan line, and a data voltage is loaded onto the sub-pixels of the corresponding row through the data line group; wherein the voltage polarities loaded onto the first data line and the second data line in each of the data line groups are opposite, and the voltage polarities loaded onto the two columns of data lines between two adjacent columns of the pixel groups are the same.

[0028] In a possible implementation, in the driving method provided in the embodiment of the present disclosure, within one frame time, a scan voltage is applied to the scan lines row by row, or a scan voltage is applied to two adjacent rows of scan lines at the same time.

[0029] FIG1 is a schematic structural diagram of an array substrate provided in the related art;

[0030] FIG2 is a schematic structural diagram of another array substrate provided in the related art;

[0031] FIG3 is a schematic structural diagram of another array substrate provided in the related art;

[0032] FIG4 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0033] FIG5 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0034] FIG6 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0035] FIG7 is a timing diagram of the array substrate shown in FIG4 ;

[0036] FIG8 is a schematic diagram showing the effect of a green (G) sub-pixel being brighter in the array substrate shown in FIG4 ;

[0037] FIG9 is a schematic diagram showing the effect of brightening the red (R) sub-pixel and the green (G) sub-pixel in the array substrate shown in FIG5 ;

[0038] FIG10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0039] FIG. 11 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure.

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "Include" or "comprising" and other similar words used in the present disclosure mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0043] Currently, the commonly used pixel architectures include Single Gate (single gate, each row of pixel units is driven by a row of scan lines), Dual gate (double gate, each row of pixel units is driven by two rows of scan lines) and Triple Gate (three gates, each row of pixel units is driven by three rows of scan lines), as shown in Figures 1-3, Figure 1 is a single gate pixel architecture provided in the relevant technology, Figure 2 is a double gate pixel architecture provided in the relevant technology, and Figure 3 is a triple gate pixel architecture provided in the relevant technology, wherein G1, G2... are scan lines, D1, D2... are data lines, and each pixel unit includes a plurality of sub-pixels of different display colors (for example, R, G, B). Under the same display panel resolution, different pixel architectures require different numbers of data driver ICs (integrated circuits), which in turn affects the production cost of the display panel. Take the display panel with a resolution of 1920*1080 as an example, that is, it has 1920 columns of pixel units and 1080 rows of pixel units, and the number of sub-pixels in the row direction is 1920*3=5760. Take a single data driver IC driving 960 data lines as an example. Six data driver ICs are required under the Single gate pixel architecture, three data driver ICs are required under the Dual gate pixel architecture, and two data driver ICs are required under the Triple Gate pixel architecture. However, the reduction in the number of data driver ICs is at the expense of compressing the actual charging time of each pixel. Assuming that the actual charging time of each pixel under the Single gate pixel architecture is 1H, the actual charging time of each pixel under the Dual gate pixel architecture is 1 / 2H, and the actual charging time of each pixel under the Triple Gate pixel architecture is 1 / 3H. For ultra-large-size and high-resolution products, the Dual gate or Triple Gate pixel architecture design can reduce the cost of the data driver IC, but the picture quality cannot be guaranteed due to the short charging time of the pixel.

[0044] In order to solve the above technical problems, the present disclosure provides an array substrate, as shown in FIG. 4 to FIG. 6 , including:

[0045] A plurality of pixel groups C are arrayed along the row direction X and the column direction Y, each pixel group C includes two sub-pixels arranged along the column direction Y, each column of pixel group C includes a plurality of sub-pixels (A1, A2, A3) alternately arranged with a plurality of display colors, and the display colors of the sub-pixels in the same row are the same; for example, along the column direction Y, the pixel group C may include two sub-pixels A1 and A2, the pixel group C may include two sub-pixels A3 and A1, and the pixel group C may include two sub-pixels A2 and A3; along the row direction X, for example, the first row includes sub-pixels A1, the second row includes sub-pixels A2, the third row includes sub-pixels A3, and then A1, A2, and A3 are arranged in a group in a circular manner;

[0046] A plurality of data line groups D, each data line group D comprising a first data line D1 and a second data line D2 extending along a column direction Y, each column of pixel groups C corresponding to one data line group D, and the first data line D1 and the second data line D2 in each data line group D are respectively located at opposite sides of each column of pixel groups C in a row direction X; wherein the first data line D1 in each data line group D is respectively electrically connected to one sub-pixel in each pixel group C in a corresponding column, and the second data line D2 in each data line group D is respectively electrically connected to another sub-pixel in each pixel group C in a corresponding column;

[0047] A plurality of rows of scan lines (G1, G2, G3, ...), each row of scan lines (G1, G2, G3, ...) and each row of pixel groups C are alternately arranged in the column direction Y, and the scan lines (G1, G2, G3, ...) are electrically connected to the sub-pixels of the corresponding row.

[0048] The array substrate provided by the embodiment of the present disclosure is designed to have a whole row of sub-pixels of the same color in the row direction, and to have sub-pixels of different colors arranged in a group in the column direction in a circular manner, and to have a row of scan lines arranged every two rows of sub-pixels in the column direction, and to have two data lines arranged between every two adjacent columns of sub-pixels in the row direction. Compared with the Single Gate pixel architecture in the related art, the pixel architecture of the present disclosure has a number of scan lines of 1.5 times that of the Single Gate, a number of data driver ICs of 2 / 3 times that of the Single Gate, and a charging time of 2 / 3 times that of the Single Gate. Therefore, compared with the Single Gate, the pixel architecture of the present disclosure can save 1 / 3 of the number of data driver ICs at the same resolution. Compared with the Dual Gate pixel architecture in the related art, the pixel architecture of the present disclosure has a number of scan lines of 3 / 4 times that of the Dual Gate, a number of data driver ICs of 4 / 3 times that of the Dual gate, and a charging time of 4 / 3 times that of the Dual gate. Therefore, compared with the Dual Gate, the pixel architecture of the present disclosure can increase the charging time of each row of pixels by 1 / 3. Therefore, the array substrate provided in the embodiment of the present disclosure can be used for some ultra-large high-resolution display panels, which can not only reduce the cost of data driver ICs, but also ensure the charging time of pixels, thereby ensuring the picture quality.

[0049] Optionally, the array substrate provided by the embodiment of the present disclosure may be applied to liquid crystal display products, but is certainly not limited thereto.

[0050] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 4 to 6, a sub-pixel in one of any two adjacent pixel groups C in the column direction Y has the same display color as a sub-pixel in the other group. For example, taking the first column of pixel groups C as an example, the sub-pixel A1 in the first pixel group C and the sub-pixel A1 in the second pixel group C have the same display color, the sub-pixel A3 in the second pixel group C and the sub-pixel A3 in the third pixel group C have the same display color, and the sub-pixel A2 in the third pixel group C and the sub-pixel A2 in the fourth pixel group C have the same display color; the display colors of any two adjacent sub-pixels in the column direction Y are different.

[0051] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 4 to 6, each column of sub-pixels is divided into a plurality of pixel units P arranged in sequence in the column direction Y, and each pixel unit P includes a first sub-pixel A1, a second sub-pixel A2 and a third sub-pixel A3 arranged in sequence in the column direction Y, that is, each column of pixel groups includes a first sub-pixel A1, a second sub-pixel A2 and a third sub-pixel A3 arranged in sequence in the column direction Y; wherein the display colors of the first sub-pixel A1, the second sub-pixel A2 and the third sub-pixel A3 are different. Optionally, the display color of the first sub-pixel A1 is blue (B), the display color of the second sub-pixel A2 is green (G), and the display color of the third sub-pixel A3 is red (R), that is, the arrangement order of the sub-pixels in the column direction is BGRBGRBGR..., but not limited to this; for example, the display color of the first sub-pixel A1 can also be red (R), the display color of the second sub-pixel A2 is green (G), and the display color of the third sub-pixel A3 is blue (B), that is, the arrangement order of the sub-pixels in the column direction is RGBRGBRGB..., and the display colors of the first sub-pixel A1, the second sub-pixel A2 and the third sub-pixel A3 can be set according to actual needs.

[0052] In specific implementation, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG. 4 to FIG. 6 , the length of each sub-pixel along the row direction X is greater than the length along the column direction Y. The sub-pixel arrangement method of the present disclosure is that the row direction X is a whole line of sub-pixels of the same color, and the BGRBGR is arranged in a cyclic manner in the column direction Y, so that compared with Single Gate, 1 / 3 of the number of data driver ICs can be saved at the same resolution, and compared with Dual Gate, the charging time of each row of pixels can be increased by 1 / 3 at the same resolution.

[0053] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 4-6, the sub-pixel may include a pixel electrode 10 and a thin film transistor T, the gate of the transistor T is electrically connected to the corresponding scan line, the first electrode of the transistor T is electrically connected to the corresponding data line, and the second electrode of the transistor T is electrically connected to the corresponding pixel electrode 10.

[0054] Optionally, the gate of the transistor T is integrally arranged with the scan line, the first electrode of the transistor T is integrally arranged with the data line, and the second electrode of the transistor T is partially in contact and electrically connected with the pixel electrode.

[0055] Optionally, the transistor T may be a P-type transistor or an N-type transistor, and the transistor T may be a bottom-gate transistor, a top-gate transistor, or a double-gate transistor, etc., which is not limited here. In the present disclosure, the first electrode of the transistor T may be a source electrode, and the second electrode may be a drain electrode, or the first electrode of the transistor T may be a drain electrode, and the second electrode may be a source electrode, which is not limited here. The transistor T also includes an active layer, and the material of the active layer may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc. Optionally, a gate insulating layer (GI) may be provided between the layer where the gate of the transistor T is located and the active layer, and the material of the gate insulating layer may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0056] Optionally, the material of the pixel electrode includes transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0057] Optionally, the material of the scanning line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., and the scanning line may be a single-layer structure or a stacked-layer structure, for example, the scanning line is a single-layer structure composed of a molybdenum metal layer.

[0058] Optionally, the material of the data line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. The data line may be a single-layer structure or a stacked structure, for example, the data line is a stacked structure consisting of titanium metal layer / aluminum metal layer / titanium metal layer.

[0059] In specific implementation, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG4 , each row of sub-pixels is electrically connected to the scan line that is most adjacent thereto. In the column direction Y, a scan line is arranged for every two rows of sub-pixels, for example, the first row of scan line G1 is electrically connected to the first row of sub-pixels, the second row of scan line G2 is electrically connected to the second row of sub-pixels and the third row of sub-pixels, the third row of scan line G3 is electrically connected to the fourth row of sub-pixels and the fifth row of sub-pixels, and so on; two adjacent data lines are arranged between every two adjacent columns of sub-pixels in the row direction X, such as D2 and D1 between the first column of pixel group C and the second column of pixel group C, D2 drives the even-numbered rows of sub-pixels on its left side, and D1 drives the odd-numbered rows of sub-pixels on its right side; of course, D2 can also drive the odd-numbered rows of sub-pixels on its left side, and D1 can drive the even-numbered rows of sub-pixels on its right side. The polarity arrangement of each data line along the row direction X can be "-++--++-" or "+--++--+", and a data line does not switch polarity within a frame, that is, the voltage polarities loaded on the first data line D1 and the second data line D2 in each data line group D are opposite, and the voltage polarities loaded on the two columns of data lines (D1 and D2) between two adjacent columns of pixel groups C are the same. The pixel architecture design shown in FIG. 4 provided by the embodiment of the present disclosure can save 1 / 3 of the number of data driver ICs compared to Single Gate at the same resolution, and can increase the charging time of each row of pixels by 1 / 3 compared to Dual Gate at the same resolution.

[0060] Based on the array substrate shown in FIG4, during the image quality test, for example, during the red-green (RG) mixed color image quality test, all green (G) sub-pixels are pre-charged, resulting in a long charging time, and red (R) sub-pixels are not pre-charged, resulting in a short charging time. In this way, the green (G) sub-pixels are brighter and the red (R) sub-pixels are darker, which is prone to color deviation. For example, the high level of each row of scan lines will last for 4 hours. Of course, the high level of each row of scan lines can also last for 2 hours / 3 hours / 5 hours / 6 hours / 7 hours / 8 hours, etc. This disclosure takes 4 hours as an example. Combined with the timing diagram shown in FIG7, the last 1 hour of the high level of the scan signal G1 / G2 / G3 / G4... is the actual data charging time of the sub-pixel, and the previous 3 hours are all pre-charging time. Taking the third row of red (R) sub-pixels and the fifth row of green (G) sub-pixels as examples, since the sub-pixels in the same column and the same data line are electrically connected, when the red (R) sub-pixels are charged, the green (G) sub-pixels are pre-charged. Therefore, the green (G) sub-pixels are brighter and the red (R) sub-pixels are darker, as shown in Figure 8, which is a schematic diagram of the effect of the green (G) sub-pixels being brighter.

[0061] For example, to solve the problem of color deviation when the array substrate shown in FIG. 4 is tested for a red-green (RG) mixed color screen, the embodiment of the present disclosure provides another array substrate, as shown in FIG. 5, each row of pixel groups C is electrically connected to the same row of scan lines, and different rows of pixel groups C are electrically connected to different rows of scan lines. For example, the two rows of sub-pixels in the first row of pixel group C are electrically connected to the second row of scan lines G2, the two rows of sub-pixels in the second row of pixel group C are electrically connected to the third row of scan lines G3, and the two rows of sub-pixels in the third row of pixel group C are electrically connected to the fourth row of scan lines G4...; of course, it can also be that the two rows of sub-pixels in the first row of pixel group C are electrically connected to the first row of scan lines G1, the two rows of sub-pixels in the second row of pixel group C are electrically connected to the second row of scan lines G2, and the two rows of sub-pixels in the third row of pixel group C are electrically connected to the third row of scan lines G3...

[0062] In a specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG5 , each first sub-pixel A1 in the pixel group C located in the Mth column is alternately electrically connected to the first data line D1 and the second data line D2 of the corresponding group, and each first sub-pixel A1 in the pixel group C located in the M+1th column is electrically connected to the first data line D1 of the corresponding group; wherein M is a positive integer; for example, each first sub-pixel A1 in the pixel group C located in the first column is alternately electrically connected to the first data line D1 and the second data line D2 of the corresponding group, and each first sub-pixel A1 in the pixel group C located in the second column is electrically connected to the first data line D1 of the corresponding group; each first sub-pixel A1 in the pixel group C located in the third column is alternately electrically connected to the first data line D1 and the second data line D2 of the corresponding group, and each first sub-pixel A1 in the pixel group C located in the fourth column is electrically connected to the first data line D1 of the corresponding group; and so on;

[0063] Each second sub-pixel A2 in the pixel group C located in the Mth column is electrically connected to the second data line D2 of the corresponding group, and each second sub-pixel A2 in the pixel group C located in the M+1th column is electrically connected to the second data line D2 and the first data line D1 of the corresponding group alternately; wherein M is a positive integer; for example, each second sub-pixel A2 in the pixel group C located in the first column is electrically connected to the second data line D2 of the corresponding group, and each second sub-pixel A2 in the pixel group C located in the second column is electrically connected to the second data line D2 and the first data line D1 of the corresponding group alternately; each second sub-pixel A2 in the pixel group C located in the third column is electrically connected to the second data line D2 of the corresponding group, and each second sub-pixel A2 in the pixel group C located in the fourth column is electrically connected to the second data line D2 and the first data line D1 of the corresponding group alternately; and so on;

[0064] Each third sub-pixel A3 in the pixel group C located in the Mth column is electrically connected to the first data line D1 of the corresponding group, and each third sub-pixel A3 in the pixel group C located in the M+1th column is electrically connected to the second data line D2 of the corresponding group; wherein M is a positive integer; for example, each third sub-pixel A3 in the pixel group C located in the first column is electrically connected to the first data line D1 of the corresponding group, and each third sub-pixel A3 in the pixel group C located in the second column is electrically connected to the second data line D2 of the corresponding group; each third sub-pixel A3 in the pixel group C located in the third column is electrically connected to the first data line D1 of the corresponding group, and each third sub-pixel A3 in the pixel group C located in the fourth column is electrically connected to the second data line D2 of the corresponding group; and so on.

[0065] In the pixel architecture design shown in FIG5 provided by the embodiment of the present disclosure, during the red-green (RG) color mixing picture quality test, when charging the red (R) sub-pixel in the previous row, the red (R) sub-pixel or green (G) sub-pixel in the following row is pre-charged, or when charging the green (G) sub-pixel in the previous row, the green (G) sub-pixel or red (R) sub-pixel in the following row is pre-charged, so that half of the green (G) sub-pixels are brighter and 3 / 4 of the red (R) sub-pixels are brighter, as shown in FIG9, which is a schematic diagram of the effect of brighter red (R) sub-pixels and green (G) sub-pixels. Thereby, the red-green (RG) color mixing can be made more uniform, and the color deviation problem of the picture can be improved.

[0066] In a specific implementation, in order to further improve the charging time of each row of pixels of the array substrate provided by the embodiment of the present disclosure, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG6 , each sub-row sub-pixel in the pixel group C located in the Nth row is electrically connected to the scan line most adjacent thereto, and the pixel group C located in the N+1th row includes a first sub-row (C1) sub-pixel and a second sub-row (C2) sub-pixel, the first sub-row (C1) sub-pixel is electrically connected to the scan line most adjacent to the second sub-row (C2) sub-pixel, and the second sub-row (C2) sub-pixel is electrically connected to the scan line most adjacent to the first sub-row (C1) sub-pixel; wherein N is a positive integer; for example, the first sub-row sub-pixel in the first row pixel group C is electrically connected to the first row scan line G1 most adjacent thereto, the second sub-row sub-pixel in the first row pixel group C is electrically connected to the second row scan line G2 most adjacent thereto; the first sub-row (C1) sub-pixel in the second row pixel group C is electrically connected to the third row scan line G3 most adjacent to the second sub-row (C2) sub-pixel, and the second sub-row (C2) sub-pixel in the second row pixel group C is electrically connected to the third row scan line G4 most adjacent to the second sub-row (C5) sub-pixel. The second sub-row (C2) sub-pixels are electrically connected to the second row scan line G2 that is most adjacent to the first sub-row (C1) sub-pixels; the first sub-row sub-pixels in the third row pixel group C are electrically connected to the third row scan line G3 that is most adjacent to it, and the second sub-row sub-pixels in the third row pixel group C are electrically connected to the fourth row scan line G4 that is most adjacent to it; the first sub-row (C1) sub-pixels in the fourth row pixel group C are electrically connected to the fifth row scan line G5 that is most adjacent to the second sub-row (C2) sub-pixels, and the second sub-row (C2) sub-pixels in the fourth row pixel group C are electrically connected to the fourth row scan line G4 that is most adjacent to the first sub-row (C1) sub-pixels….

[0067] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in FIG6 , two sub-pixels (G and R) located on both sides of the same scan line (for example, G2) and in the same column (for example, the first column) that are most adjacent are connected to the same data line D2, two sub-pixels (B and G) located on both sides of the same scan line (for example, G3) and in the same column (for example, the second column) that are most adjacent are connected to the same data line D1, and two sub-pixels (R and B) located on both sides of the same scan line (for example, G4) and in the same column (for example, the third column) that are most adjacent are connected to the same data line D2….

[0068] As shown in FIG6 , for example, two adjacent data lines D2 and D1 between the first column pixel group C and the second column pixel group C, D2 drives the pixels on its left side, and the driving order is one row of green sub-pixels, then two rows of red sub-pixels, then two rows of blue sub-pixels, and then one row of green sub-pixels, and repeats; D1 drives the pixels on its right side, and the driving order is two rows of blue sub-pixels, two rows of green sub-pixels, and two rows of red sub-pixels, and repeats. The polarity of the data line is arranged as "-++--++-", or "+--++--+", and a data line does not switch polarity within a frame. Since each adjacent two sub-pixels connected to each column data line of the pixel architecture shown in FIG6 are of the same color, for example, the sub-pixel color connected to the first column data line D1 is BBGGRR..., and the sub-pixel color connected to the second column data line D2 is GGRRBB..., the pixel architecture shown in FIG6 can support the gates of each two rows of sub-pixels to be opened at the same time, and the pixel charging time is doubled, thereby improving the charging rate of each row of pixels. Taking the first column data line D1 as an example, when G1 and G2 are turned on at the same time, D1 charges two blue sub-pixels and does not cause image abnormality.

[0069] As shown in the following Table 1, Table 1 is a comparison result of the number of scan lines, the number of data lines, the number of data driver ICs, and the charging time of each row of pixels corresponding to the pixel architecture provided by the embodiment of the present disclosure and several common pixel architectures in the related art, taking the resolution of the display panel as 1920*1080 as an example.

[0070] Table 1

[0071] As can be seen from Table 1, the pixel architecture design of the array substrate provided in the embodiment of the present disclosure, compared with the Single Gate and Dual Gate in the related art, the number of scan lines in the present disclosure is between Single Gate and Dual Gate, the number of data lines is between Single Gate and Dual Gate, the number of data driver ICs is between Single Gate and Dual Gate, and the charging time of each row of pixels is between the charging time of each row of pixels. Therefore, the pixel architecture design of the array substrate provided in the embodiment of the present disclosure can reduce the cost of the data driver IC and ensure the charging time of the pixels, thereby ensuring the picture quality.

[0072] In specific implementation, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG. 4 to FIG. 6 , multiple rows of common electrode lines Com are also included, and each row of common electrode lines Com is located between two rows of sub-pixels in the corresponding row of pixel groups C. For example, the first row of common electrode lines Com is located between two rows of sub-pixels in the first row of pixel groups C, the second row of common electrode lines Com is located between two rows of sub-pixels in the second row of pixel groups C, the third row of common electrode lines Com is located between two rows of sub-pixels in the third row of pixel groups C... Specifically, the common electrode lines Com and the scan lines (G1, G2, G3...) are alternately arranged along the column direction Y, so that multiple common electrode lines Com are arranged in the entire array substrate, which can ensure the uniformity of the common signal to improve the display uniformity.

[0073] It should be noted that other essential components in the array substrate should be understood by those skilled in the art and will not be described in detail herein and should not be regarded as limitations to the present disclosure.

[0074] Based on the same inventive concept, an embodiment of the present disclosure further provides a driving method of an array substrate, which is used to drive the above array substrate provided by an embodiment of the present disclosure. The driving method includes:

[0075] Within one frame time, a scan voltage is loaded onto the scan line, and a data voltage is loaded onto the corresponding row of sub-pixels through the data line group; wherein the voltage polarities loaded onto the first data line and the second data line in each data line group are opposite, and the voltage polarities loaded onto the two columns of data lines between two adjacent columns of pixel groups are the same.

[0076] The specific driving distance can refer to the related description of the aforementioned array substrate, which will not be elaborated here.

[0077] In a specific implementation, in the above-mentioned driving method provided in the embodiment of the present disclosure, as shown in Figures 4 and 5, within one frame time, the scanning voltage is loaded to the scanning lines row by row; as shown in Figure 6, the scanning voltage is loaded to two adjacent rows of scanning lines at the same time to increase the charging rate of each row of pixels.

[0078] In specific implementation, the array substrate provided in the embodiment of the present disclosure may further include other functional film layers well known to those skilled in the art, which are not listed one by one here.

[0079] Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, as shown in FIG10, comprising: the array substrate 001 provided in the embodiment of the present disclosure, and an opposing substrate 002 arranged in a box with the array substrate 001. The principle of solving the problem by the display panel is similar to that of the aforementioned array substrate, so the implementation of the display panel can refer to the implementation of the aforementioned array substrate, and the repeated parts will not be repeated here.

[0080] In a specific implementation, the display panel provided in the embodiment of the present disclosure, as shown in FIG. 10 , further includes: a liquid crystal layer 003 located between the array substrate 001 and the counter substrate 002 , and a backlight module 004 located on the light incident side of the array substrate 001 .

[0081] Specifically, the opposite substrate includes: a blue color filter arranged corresponding to the first sub-pixel, a green color filter arranged corresponding to the second sub-pixel, and a red color filter arranged corresponding to the third sub-pixel.

[0082] In some embodiments, in the above-mentioned display panel provided in the embodiments of the present disclosure, the backlight module 004 can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., which are stacked, and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, etc., which are stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening that is arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0083] Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.

[0084] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including the display panel provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0085] In a specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a liquid crystal display device, which also includes other necessary components and components, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements based on the specific use requirements of the display device, which will not be elaborated here and should not be regarded as a limitation to the present disclosure.

[0086] In specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a full-screen display device, or may also be a flexible display device, etc., which is not limited here.

[0087] In specific implementation, the display device provided in the embodiment of the present disclosure may be a full-screen mobile phone as shown in FIG11. Of course, the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0088] The embodiments of the present disclosure provide an array substrate, a driving method thereof, a display panel, and a display device. The array substrate provided by the embodiments of the present disclosure is designed to have a whole row of sub-pixels of the same color in the row direction, and to design sub-pixels of different colors in the column direction to be arranged in a group in a circular manner in sequence, and to set a row of scan lines for every two rows of sub-pixels in the column direction, and to set two data lines between every two adjacent columns of sub-pixels in the row direction. Compared with the Single Gate pixel architecture in the related art, the pixel architecture of the present disclosure has a number of scan lines of 1.5 times that of the Single Gate, a number of data driver ICs of 2 / 3 times that of the Single Gate, and a charging time of 2 / 3 times that of the Single Gate. Therefore, compared with the Single Gate, the pixel architecture of the present disclosure can save 1 / 3 of the number of data driver ICs at the same resolution; compared with the Dual Gate pixel architecture in the related art, the pixel architecture of the present disclosure has a number of scan lines of 3 / 4 times that of the Dual Gate, a number of data driver ICs of 4 / 3 times that of the Dual Gate, and a charging time of 4 / 3 times that of the Dual Gate. Therefore, compared with the Dual Gate pixel architecture in the related art, the pixel architecture of the present disclosure has a number of scan lines of 3 / 4 times that of the Dual Gate, a number of data driver ICs of 4 / 3 times that of the Dual gate, and a charging time of 4 / 3 times that of the Dual gate. Gate can increase the charging time of each row of pixels by 1 / 3 at the same resolution. Therefore, the array substrate provided by the embodiment of the present disclosure can be used for some ultra-large and high-resolution display panels, which can not only reduce the cost of data driver ICs, but also ensure the charging time of pixels, thereby ensuring the picture quality.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0090] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

An array substrate, wherein: include: A plurality of pixel groups arranged in an array along row and column directions, each of the pixel groups comprising two sub-pixels arranged along the column direction, each column of the pixel groups comprising a plurality of sub-pixels alternately arranged with a plurality of display colors, and the display colors of the sub-pixels located in the same row are the same; a plurality of data line groups, each of the data line groups comprising a first data line and a second data line extending along the column direction, each column of the pixel groups corresponding to one data line group, and the first data line and the second data line in each data line group are respectively located on opposite sides of the pixel groups in each column in the row direction; wherein the first data line in each data line group is electrically connected to one of the sub-pixels in each of the pixel groups in the corresponding column, and the second data line in each data line group is electrically connected to another sub-pixel in each of the pixel groups in the corresponding column; and a plurality of rows of scan lines, each row of the scan lines and each row of the pixel groups are alternately arranged in the column direction, and the scan lines are electrically connected to the sub-pixels in the corresponding row. The array substrate according to claim 1, wherein: Each row of sub-pixels is electrically connected to the scan line most adjacent to it. The array substrate according to claim 1, wherein: Each sub-row sub-pixel in the pixel group located in the Nth row is electrically connected to the scan line most adjacent to it, and the pixel group located in the N+1th row includes a first sub-row sub-pixel and a second sub-row sub-pixel, the first sub-row sub-pixel is electrically connected to the scan line most adjacent to the second sub-row sub-pixel, and the second sub-row sub-pixel is electrically connected to the scan line most adjacent to the first sub-row sub-pixel; wherein N is a positive integer. The array substrate according to claim 3, wherein: Two sub-pixels located at two sides of the same scan line and in the most adjacent column are connected to the same data line. The array substrate according to claim 1, wherein: The pixel groups in each row are electrically connected to the scan lines in the same row, and the pixel groups in different rows are electrically connected to the scan lines in different rows. The array substrate according to claim 5, wherein: Each column of the pixel group includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence in the column direction, the display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red; wherein, each of the first sub-pixels in the pixel group located in the Mth column is alternately electrically connected to the first data line and the second data line of the corresponding group, and each of the first sub-pixels in the pixel group located in the M+1th column is electrically connected to the first data line of the corresponding group; each of the second sub-pixels in the pixel group located in the Mth column is electrically connected to the second data line of the corresponding group, and each of the second sub-pixels in the pixel group located in the M+1th column is alternately electrically connected to the second data line and the first data line of the corresponding group; each of the third sub-pixels in the pixel group located in the Mth column is electrically connected to the first data line of the corresponding group, and each of the third sub-pixels in the pixel group located in the M+1th column is electrically connected to the second data line of the corresponding group; wherein M is a positive integer. The array substrate according to any one of claims 1 to 6, wherein: It also includes a plurality of rows of common electrode lines, each row of the common electrode lines is located between two rows of sub-pixels in the corresponding row of the pixel group. The array substrate according to claim 7, wherein: The common electrode lines and the scan lines are alternately arranged along the column direction. The array substrate according to any one of claims 1 to 4, wherein: A sub-pixel in one of any two adjacent pixel groups in the column direction has the same display color as a sub-pixel in the other group, and a sub-pixel in any two adjacent sub-pixels in the column direction has different display colors. The array substrate according to claim 9, wherein: The sub-pixels in each column are divided into a plurality of pixel units arranged sequentially in the column direction, and each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged sequentially in the column direction; the display colors of the first sub-pixel, the second sub-pixel and the third sub-pixel are different. The array substrate according to claim 10, wherein: The display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red. The array substrate according to any one of claims 1 to 11, wherein: The length of each sub-pixel along the row direction is greater than the length along the column direction. The array substrate according to any one of claims 1 to 12, wherein: The sub-pixel includes a pixel electrode and a thin film transistor, a gate of the transistor is electrically connected to the corresponding scan line, a first electrode of the transistor is electrically connected to the corresponding data line, and a second electrode of the transistor is electrically connected to the corresponding pixel electrode. A display panel, wherein include: An array substrate as claimed in any one of claims 1 to 13, and a counter substrate arranged in a box with the array substrate. A display device, wherein Comprising the display panel as claimed in claim 14. A method for driving an array substrate, for driving the array substrate according to any one of claims 1 to 13, wherein: The driving method includes: within one frame time, loading a scanning voltage onto the scanning line, and loading a data voltage onto the sub-pixels of the corresponding row through the data line group; wherein the voltage polarities loaded onto the first data line and the second data line in each of the data line groups are opposite, and the voltage polarities loaded onto the two columns of data lines between two adjacent columns of the pixel groups are the same. The driving method according to claim 16, wherein: In one frame time, a scan voltage is applied to the scan lines row by row, or a scan voltage is applied to two adjacent rows of scan lines at the same time.

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