Apparatus and method for single pass access of ECC information, metadata information, or combination thereof

Abstract

Devices, systems, and methods for single pass access of ECC information, metadata information, or a combination thereof. The memory array includes a plurality of column planes and additional column planes. The memory device may be provided in an x4 single pass mode of operation. In this mode, the memory may store data in a selected one of the column planes, and metadata may be stored in the additional column planes. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in an unselected one of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 383,871, filed on November 15, 2022. The entire contents of this application are incorporated herein by reference for all purposes. Background Art

[0003] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information may be stored as physical signals (such as charge on a capacitive element) on individual memory cells of the memory. During an access operation, an access command may be received along with address information specifying which memory cells should be accessed.

[0004] There is a growing interest in enabling memories to store information associated with a stripe in an array. For example, error correction information and / or metadata may be stored in the array along with its associated data. There is a need to ensure that this information can be accessed along with the specified data and does not unduly impact the performance of the device. Summary of the invention

[0005] In at least one aspect, the present disclosure is directed to an apparatus comprising: a first data column plane comprising a first bit line and a second bit line; a second data column plane comprising a third bit line and a fourth bit line; and an additional column plane comprising a fifth bit line and a sixth bit line. The apparatus further comprises: a column decoder that activates the first bit line, the fourth bit line, and the fifth bit line as part of an access operation; and an error correction code (ECC) circuit that accesses data bits along the first bit line, metadata bits along the fifth bit line, and parity bits along the fourth bit line as part of the access operation.

[0006] The column decoder may activate the second bit line, the third bit line, and the fifth bit line as part of a second access operation, and the ECC circuit may access data along the third bit line, access parity bits along the second bit line, and access metadata along the sixth bit line as part of the second access operation. The column decoder may selectively activate the bit lines based on a received column address, and the column address may include a column plane select bit that specifies whether the data is stored in the first data column plane or the second data column plane.

[0007] The apparatus may include an input / output circuit that receives the data and the metadata from the ECC circuit when the access operation is a read operation and provides the data and the metadata to the ECC circuit when the access operation is a write operation. The ECC circuit may locate and correct errors in the data and the metadata based on the data metadata and the parity when the access operation is a read operation.

[0008] The parity bits stored along the second bit line may be associated with data bits stored along the third bit line, and the data bits along the first bit line may be associated with the parity bits stored along the fourth bit line. In response to a column address received as part of the access operation, the column decoder may provide a column select signal having a first value to the first data column plane, a second column select signal having a second value to the second data column plane, and a third column select signal having the first value to the additional column plane.

[0009] In at least one aspect, the present disclosure is directed to an apparatus comprising a memory bank and a column decoder. The memory bank comprises a first plurality of column planes, a second plurality of column planes, and an additional column plane. The column decoder selects the first or the second plurality of column planes based on a column address received as part of an access operation, wherein as part of the access operation, data bits are accessed in a selected one of the first or the second plurality of column planes, parity bits are accessed in an unselected one of the first or the second plurality of column planes, and metadata bits are accessed in the additional column plane.

[0010] The apparatus may include an error correction code (ECC) circuit that locates and corrects errors in the data bits and the metadata bits based on the parity bits when the access operation is a read operation. The ECC circuit may perform single error correction double error detection (SECDED). The column address may include a column plane selection bit and the first plurality of column planes or the second plurality of column planes may be selected based on the column plane selection bit. A plurality of bits may be accessed from the additional column plane and the column decoder may select a first half or a second half of the plurality of bits as the metadata bits.

[0011] The apparatus may include a first plurality of local input / output (LIO) lines coupled to the first plurality of column planes and a second plurality of LIO lines coupled to the second plurality of column planes. The column decoder may activate all of the first plurality or the second plurality of LIO lines coupled to the selected ones of the first or second plurality of column planes and less than all of the first plurality or the second plurality of LIO lines coupled to the unselected ones of the first or second plurality of column planes as part of the access operation. The apparatus may be a memory device operating in x4 mode.

[0012] In at least one aspect, the present disclosure may relate to a method comprising: receiving a column address as part of an access operation; selecting a first portion of a plurality of column planes based on the column address; accessing data bits from columns in the first portion of the plurality of column planes as part of the access operation; accessing parity bits from columns in column planes not in the first portion as part of the access operation; and accessing metadata bits from additional column planes as part of the access operation.

[0013] The method may also include locating errors, correcting errors, or a combination thereof in the data bits and the metadata bits with an error correction code (ECC) circuit based on the parity bits. The method may include performing single error correction double error detection (SECDED) with the ECC circuit. The method may include accessing a set of bits from the additional column plane and selecting half of the set of bits as the metadata bits based on the column address.

[0014] The method may include selecting a first half of the plurality of column planes as the first portion and selecting a column plane in a second half of the plurality of column planes as the column plane not in the first portion. The method may include: receiving a second column address as part of a second access operation; selecting the second half of the plurality of column planes based on the second column address; accessing second data bits from the second half as part of the second access operation; accessing parity bits from columns in the first half as part of the second access operation; and accessing metadata bits from the additional column planes as part of the second access operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0017] Figure 3 is a block diagram showing an example of a read operation of a memory according to some example embodiments of the present disclosure.

[0018] Figure 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure.

[0019] Figure 5 is a flow chart of a method according to some embodiments of the present disclosure.

[0020] Figure 6 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure.

[0021] Figure 7 is a flow chart of a method according to some embodiments of the present disclosure.

[0022] Figure 8 is a flow chart of a method according to some embodiments of the present disclosure.

[0023] Fig. 9 is a flow chart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] The following description of certain embodiments is merely exemplary and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and that show by way of illustration specific embodiments in which the described system and method may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for clarity, the detailed description of certain features will not be discussed when it is obvious to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be considered as intended to be limiting, and the scope of the present disclosure is defined solely by the appended claims.

[0025] A memory array may typically include a number of memory cells arranged at the intersection of word lines (rows) and bit lines / digit lines (columns). Columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns within each of the active column planes to provide data. When an access command is received, the memory may pre-fetch a codeword (e.g., a number of data bits) and one or more associated bits from the memory and replace the pre-fetched data with new data (e.g., as part of a write operation) or provide the pre-fetched data from the memory device (e.g., as part of a read operation). Some memory modes may involve providing less than all of the pre-fetched data from the memory device. For example, in a conventional memory device, in certain modes, half of the pre-fetched data may be provided from the device, and the remainder may be ignored.

[0026] The memory device may store additional information associated with each codeword. For example, the additional information may include parity bits used as part of an error correction scheme, metadata including information about the data codeword (or part of information about a larger set of data including the codeword), or a combination thereof. However, the maximum number of bits that can be retrieved as part of a single access pass may be limited by the architecture of the memory, and this number may typically be based on the maximum number of data bits in a codeword plus some number of additional bits (e.g., 128 data bits + 8 additional bits).

[0027] As used herein, the term "data" may represent any information bit that the controller wishes to store and / or retrieve from the memory. The term "metadata" may represent any information bit about the data that the controller writes to the memory and / or receives from the memory. For example, metadata may be information generated by the controller about the data, about how or where the data storage is stored in the memory, about how many errors are detected in the data, etc. Data and metadata together represent information written to the memory by the controller and then also read from the memory by the controller, where the data and metadata differ in content and generation because the metadata is based on information about the data. The term "parity" may represent any bit generated by the error correction circuit of the memory based on data, metadata, or a combination thereof. Parity may generally be retained in the memory. In some embodiments, the amount of data and / or metadata retrieved as part of a single access operation may represent a group of bits as a fragment of a larger piece of information. For example, metadata bits (e.g., 4 bits) retrieved as part of a single access operation may not have any meaning by themselves, but may have meaning when combined with several groups of metadata bits retrieved as part of other access operations (e.g., for other memory arrays and / or the same array at different times).

[0028] Some memories may include a set of data column planes and additional column planes for storing additional information. However, various applications may desire to include a larger number of additional information bits than can be retrieved from the additional column planes (e.g., including parity bits and metadata, including more parity bits, etc.). Some memory devices may use a 'two-pass' architecture, where at least some of the additional bits are first retrieved, stored, and then a second access pass retrieves the codeword data bits. However, this incurs a penalty in latency for any given access operation. It is desirable to extend the one-pass or single-pass storage of the additional information so that the codeword and additional bits are retrieved as part of a single access pass to the memory array.

[0029] The present disclosure relates to apparatus, systems and methods for single-pass access of ECC information, metadata information, or a combination thereof, and associated codewords. Some memory devices may operate in a mode in which not all data bits that may be pre-fetched are provided from the device. For example, a memory device may pre-fetch 128 data bits as part of a codeword in x8 or x16 mode, whereas in x4 memory mode, a 64-bit codeword is provided at the data terminal of the device. The data bits of the codeword in the x4 memory mode are stored in some but not all data column planes (e.g., half of the column planes). The selection of which half of the data column planes may be based on the column address. Additional bits associated with the data (e.g., parity bits and / or metadata bits) may be stored in additional column planes and may also be stored in data column planes that are not selected by the column address as part of the current access.

[0030] According to some embodiments of the present disclosure, an example memory device may include a set of data column planes and additional column planes. The memory may be set in a mode in which metadata is stored with its associated data. When an access operation is performed, a column select signal having a first value is provided to columns in a first portion of the data column plane and the additional column plane and a column select signal having a second value is provided to one or more columns not in the first portion of the data column plane. The memory may store data in the first portion of the data column plane, metadata in the additional column plane, and error correction parity bits in access columns not in the first portion of the data column plane. In this way, the data, metadata, and ECC information of a codeword may be pre-fetched together as part of a single access pass without pre-fetching additional data bits.

[0031] In some embodiments, a mode register may be used to switch between behaviors of a memory device. For example, if metadata is enabled, the memory may have a first x4 mode of operation (e.g., a two-pass x4 mode) in which, as part of an access operation, the memory may store data bits from a first portion of a data column plane and a second portion of a data column plane and pre-fetch ECC parity information from an additional column plane. In this two-pass x4 mode of operation, the ECC circuit of the memory may correct errors in the pre-fetched data bits based on the pre-fetched parity bits, and then provide half of the corrected data bits (e.g., the corrected bits from the first portion) from the memory. In a second mode of operation (e.g., a one-pass x4 mode of operation), as part of an access operation, the memory pre-fetches data bits from the first portion of the data column plane and ECC parity bits from column planes in the second portion of the data column plane, and pre-fetches metadata bits from the additional column plane. The ECC circuit corrects errors in the data and metadata bits based on the parity bits, and provides the corrected data and metadata from the device. Therefore, the ECC may pre-fetch and process fewer bits in the second mode than in the first mode. The memory may also have a metadata disabled mode, which may be similar in operation to the two-pass mode, except that only a single pass is performed since no metadata is stored or accessed.

[0032] Figure 1 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The device may be operated by a controller 150 (eg, a processor).

[0033] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1In the embodiment of the present invention, the memory array 118 is shown as including 8 memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. As explained in more detail herein, each memory bank may be further divided into two or more sub-memory banks. Although embodiments in which each memory bank includes two sub-memory banks are generally described herein, other embodiments may include more sub-memory banks per memory bank.

[0034] Each memory subbank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by the row decoder 108 and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In some embodiments, row decoder 108 includes a respective row decoder for each bank and column decoder 110 includes a respective column decoder for each bank. In some embodiments, components such as row and column decoders and refresh control circuit 116 that are repeated on a per-bank basis may also include components that are repeated on a per-sub-bank basis. For example, refresh control circuit 116 may exist for each sub-bank.

[0035] The bit lines BL are coupled to corresponding sense amplifiers (SAMPs). Read data from the bit lines BL are amplified by the sense amplifiers SAMPs and transmitted to the ECC circuit 120 through the local data lines (LIOs), the transfer gates (TGs), and the global data lines (GIOs). Conversely, write data output from the ECC circuit 120 are transmitted to the sense amplifiers SAMPs through the complementary main data lines GIOs, the transfer gates TGs, and the complementary local data lines LIOs and written into the memory cells MCs coupled to the bit lines BL.

[0036] The semiconductor device 100 may employ a plurality of external terminals such as pads, including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ coupled to a data bus to provide data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0037] The clock terminal is supplied with external clocks CK and / CK provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 for the operation timing of the circuit included in the input / output circuit 122, such as provided to the data receiver for the reception timing of write data. The input / output circuit 122 may include a number of interface connections, each of which may be coupled to one of the DQ pads (e.g., a pad that may serve as an external connection to the device 100).

[0038] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The decoded row address XADD may be used to determine which row should be turned on, which may cause data along the bit lines to be read out along the bit lines. The column decoder 110 may provide a column select signal CS, which may be used to determine which sense amplifiers provide data to the LIO. The address decoder 104 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and the column address YADD.

[0039] The C / A terminal may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0040] The command may be provided as an internal command signal via the command / address input circuit 102 to the command decoder 106. The command decoder 106 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing an operation. For example, the command decoder 106 may provide a signal indicating whether data is to be read, written, etc.

[0041] The device 100 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are supplied in time with the read command, read data is read from the memory cell corresponding to the row address and column address in the memory array 118. The read command is received by the command decoder 106, which provides an internal command so that the read data from the memory array 118 is provided to the ECC circuit 120. The ECC circuit 120 receives data bits, metadata bits, and parity bits from the array and detects and / or corrects errors in the data and metadata bits. Correct read data is provided along the data bus and output to the outside from the data terminal DQ via the input / output circuit 122.

[0042] The device 100 may receive an access command as a write command. When the write command is received and the bank address, row address, and column address are supplied in time with the write command, the write data supplied to the data terminal DQ is provided along the data bus and written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the write data is received by the data receiver in the input / output circuit 122 together with the metadata. The write data and metadata are supplied to the ECC circuit 120 via the input / output circuit 122. The ECC circuit generates a parity bit based on the received data and metadata, and the data, metadata, and parity are provided by the ECC circuit 120 to the memory array 118 to be written into the memory cell MC.

[0043] The device 100 includes refresh control circuits 116 each associated with a bank of the memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated bank. The refresh control circuit 116 provides a refresh address RXADD (and one or more refresh signals, Figure 1 1. The row decoder 108 performs a refresh operation on one or more word lines associated with RXADD. The refresh control circuit 116 can perform multiple types of refresh operations, which can determine how to generate the address RXADD and other details, such as how many word lines are associated with the address RXADD.

[0044] The ECC circuit 120 can detect and / or correct errors in access data. As part of a write operation, the ECC circuit 120 can receive bits from the IO circuit 122 and generate parity bits based on these received bits. The received bits and parity bits are written to the memory array 118. During an example read operation, the ECC circuit 120 receives a set of bits and their associated parity bits from the array 118 and uses them to locate and / or correct errors. For example, in a single error correction (SEC) scheme, up to one error bit can be located and detected. In a single error correction double error detection (SECDED) scheme, up to one error bit can be corrected, but two errors can be detected (although the bits causing those errors are not individually located and therefore cannot be corrected). The ECC circuit 120 can correct the information and then provide the corrected information (and / or a signal indicating the detected error) to the IO circuit 122. The parity bits may not typically be provided to the IO circuit 122.

[0045] Mode register 130 may include various settings and may be used to enable a metadata mode of memory 100. When metadata is enabled, device 100 may store metadata associated with the data. For example, as part of a write operation, controller 150 may provide data and its associated metadata, and as part of a read operation, may receive data and its associated metadata. In some embodiments, ECC circuit 120 may include metadata bits as part of the error correction process and in some embodiments, may exclude metadata bits. In some embodiments, whether metadata is included in the ECC process may be a setting of the memory (e.g., in mode register 130). The metadata may include information about the associated data.

[0046] The memory 100 may operate in various modes based on the number of DQ pads used. The mode may determine how many DQ pads the controller 150 expects to send / receive data along and the format and / or number of bits that the controller 150 expects as part of a single access command. For example, a memory may have 16 physical DQ pads. In x16 mode, all 16 DQ pads are used. In x8 mode, 8 DQ pads are used, and in x4 mode, 4 DQ pads are used. The mode may also determine the burst length at each DQ terminal as part of the DQ operation. The burst length represents the number of serial bits at each DQ terminal during an access operation.

[0047] For example, in x8 mode, the memory may send or receive 128 data bits along 8 DQ terminals, each of which has a burst length of 16. In an example x4 mode, a burst length of 16 may also be used, and thus 64 bits may be sent or received as part of an access operation. The present disclosure will generally be described with respect to an example embodiment, where a codeword of 64 data bits is accessed along with 4 metadata bits as part of the x4 mode, and the ECC circuit 120 uses 8 ECC parity bits. Other example embodiments may use different numbers of data, metadata, and parity.

[0048] Device 100 includes a mode register 130, which can be used to control various optional modes of the memory. For example, mode register 130 may include a setting that determines whether metadata is used. If metadata is enabled, mode register 130 may set a first x4 operating mode (e.g., a two-pass x4 operating mode) or a second x4 operating mode (e.g., a one-pass x4 operating mode). Controller 150 may perform a mode register write (MRW) operation to set a value in mode register 130, or may perform a mode register read (MRR) operation to check what the value in mode register 130 is. Mode register 130 includes several registers, each of which may store one or more bits corresponding to a setting or piece of information about the memory.

[0049] The controller 150 may provide the command and the row and column addresses as part of the access operation. In the two-pass x4 operating mode, in response to the access operation from the controller 150, the column decoder may perform a first access pass on the memory array to retrieve a first portion of information that may then be stored, and then perform a second access pass on the memory array to retrieve the remainder of the information combined with the stored information. For example, during a read operation, the controller 150 may provide an address and a single read command, but in response thereto, the memory 100 may retrieve 4 metadata bits as part of the first pass, and then retrieve the remaining 64 data bits and 8 parity bits as part of the second pass. In the single-pass x4 operating mode, in response to the address and read command, the memory may retrieve the data, metadata, and parity as part of a single access pass to the memory array.

[0050] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal.

[0051] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are provided to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 is not propagated to other circuit blocks.

[0052] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 200 may represent Figure 1 A portion of the memory device 100. Figure 2 The view of FIG. 1 shows a portion of memory arrays 210 to 214 and 220 to 224 (which may be memory banks (eg, Figure 1 118) and selected circuits used in the data path, such as ECC circuit 232 (e.g. Figure 1 120) and IO circuit 234 (e.g. Figure 1 122). For clarity, Figure 2 The view omits certain circuits and signals.

[0053] The memory device 200 is organized into several column planes 210 to 214. Each of the column planes represents a portion of a memory bank. Each column plane 210 to 214 includes several memory cells at the intersection of a word line WL and a bit line. The bit lines can be grouped together into groups, which are activated by the value of the CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column selection group, however, there may be multiple columns accessed by the value of CS. For example, each line may represent 8 bit lines, all of which are accessed together by the value of CS. As used herein, the 'value' of CS may refer to a decoded signal provided to a bit line group. Therefore, a first value may represent a first value of a multi-bit CS signal or be valid after decoding a signal line associated with the value. A word line may extend across multiple of the column planes 210 to 214.

[0054] The memory 200 includes a set of data column planes 210 and an additional column plane 212. The additional column plane 212 may be used to store additional information, such as error correction parity bits or metadata bits.

[0055] In some embodiments, the memory 200 may also include an optional global column redundancy (GCR) column plane 214. In some embodiments, the GCR plane 214 may have fewer memory cells (e.g., fewer column select groups) than the data column plane 210. The GCR CP 214 includes a number of redundant columns that may be used as part of a repair operation. If the value of the CS signal is identified as including a defective memory cell in one of the data column planes 210, the memory may be remapped such that the data that would have been stored in that column plane due to that value of CS is instead stored in the GCR CP 214.

[0056] For example, in some embodiments, the memory 210 may include 16 data column planes 210(0) to 210(15). Each of these data column planes 210 includes 64 groups of bit lines activated by the value of the column select signal, and each group of bit lines includes 8 bit lines. Therefore, when the word line is turned on in response to the row address and the column select signal is provided to each of the 16 column planes, 8 bits are accessed from each of the 16 column planes, for a total of 128 bits. The column select signal is also provided to the additional column plane 212, but the column select signal may be a different value than the value provided to the data column plane 210 for the additional 8 bits. If a repair has been performed, the GCR CP 214 may also be accessed and the value on the GCR LIO may be used while ignoring the LIO of the column plane it replaced. Therefore, the maximum number of bits that can be retrieved as part of an access pass is 128 bits from the data column plane 210 (8 bits replaced by the GCR CP 214 if a repair already exists) and 8 additional bits from the extra CP 212.

[0057] The memory may operate in a x4 mode with fewer than the maximum number of bits provided to an external device. The column address may indicate which of the column planes 210 are used to store data accessed in the x4 mode. For example, the CP select bits of the column address (e.g., bit 10 C10 of the column address) may select data from an even column plane or an odd column plane or from the first half of the column plane or the second half of the column plane. Other schemes may be used in other example embodiments.

[0058] Not present Figure 2 The mode register shown in Figure 1 130) may be used to enable metadata on the device. If metadata is enabled, the mode register may have settings that set the memory device in a first x4 operating mode (two-pass mode) or a second x4 operating mode (one-pass mode). In both operating modes, the overall information received / sent to the external device is the same. For example, a controller (e.g., Figure 1150) can expect 64 data bits and 4 metadata bits for each access to the memory 200 in either mode, however, the operating mode can determine how the memory array is accessed, how many access passes are used to get the data (e.g., how fast the data is accessed), the power consumption of the access operation, the size of the pre-fetch information, the behavior of the ECC circuit 232, and what information is stored in what column plane. In a first x4 operating mode, two access passes are used to retrieve data (e.g., metadata from a first pass and data and ECC bits from a second pass), while in a second x4 operating mode, a single pass is used to retrieve the information.

[0059] In an example read command in the first x4 mode of operation, the column, row, and bank addresses are received from the controller. The row decoder (e.g. Figure 1 108) opens a selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a first access pass, a column select signal is provided to one of the column planes 210, which is selected by the CP select bit (e.g., C10) of the column address. A set of metadata (e.g., 128 metadata bits) (some of which are associated with the current access operation) is retrieved from the column plane 210, while parity bits (associated with the set of metadata) are retrieved from the additional column plane 212. The ECC circuit 232 can check and correct errors based on the 128 metadata bits + 8 associated parity bits. The metadata bits (e.g., 4 metadata bits) within the set that are associated with the current access operation (e.g., as indicated by the column address) are stored in a buffer (not shown) as part of the IO circuit 234. As part of a second access pass, column select signals are provided to all data column planes 210 and additional column select signals are provided to additional column planes. The column select signal and the additional column select signal have the same value as each other and do not necessarily have the same value as the column select signal provided as part of the first access pass. As part of the second access pass, the data bits are retrieved from the data column plane 210 and the parity bits are retrieved from the additional column plane 212. The ECC circuit 232 uses the retrieved data and parity bits to locate and / or correct errors in the data. Then, half of the retrieved (corrected) data bits are concatenated with the previously retrieved metadata in the IO circuit 234, and the IO circuit provides the data and metadata from the device at the DQ pad.

[0060] The example write command in the first x4 operation mode may generally be similar. The controller provides the data bits and metadata bits along with the command and address. The metadata is stored in a buffer of the IO circuit 234. Data is pre-fetched from the array and half of the data is replaced with the new write data. The ECC circuit 232 then generates new parity based on the update data group and writes the data to the data column plane 210. In a similar manner, in the second access pass, the metadata group is retrieved so that the metadata can be added to it and the ECC circuit 232 can generate new parity associated with the update metadata group. The update metadata group and parity are then written to the array. In the second access pass, the parity is simultaneously written to the additional column plane 212.

[0061] There may be a delay tCCD_L_WR that is part of the design specification of the memory. The time tCCD_L_WR represents the minimum amount of time that must elapse before a bank in the same bank group can be accessed again. The time tCCD_L_WR represents the long column-to-column (or command) delay period for writes, which may be a specification of the memory. During a write operation, the two-pass operation mode may incur a delay of 2×tCCD_L_WR because each access pass requires a delay of tCCD_L_WR before the bank can be accessed again. One tCCD_L_WR is incurred by adding an extra pass to overwrite the metadata, and another tCCD_L_WR is incurred because in order to generate the parity bits (which are based on all prefetched data in this mode), half of the prefetched data bits that were not written must still be prefetched (e.g., read) so that they can be added to the write bits received from the controller.

[0062] The second x4 operating mode may be a 'one pass' mode where fewer data bits are pre-fetched and the location of metadata and parity is changed compared to the first x4 operating mode. Rather than pre-fetching additional data bits that are not part of the access operation as in the first x4 operating mode, in the second x4 operating mode only the access data bits are pre-fetched.

[0063] In an example read command in the second x4 mode of operation, the column, row, and bank addresses are received from the controller. The row decoder (e.g. Figure 1108) turns on a selected word line based on a row address. A column decoder generates a column select signal based on the column address. As part of a single access pass, a column select value having a first value is provided to a first portion of the column plane and a column select signal having a second value is provided to at least one column plane that is not in the first portion. At the same time, a column select signal (which may or may not have the same value of the first or second column select signal) is provided to an additional column plane 212. Which columns are in the first portion may be based on a CP select bit (e.g., C10) of the column address. The data column planes of the first portion provide data bits, the data column planes not in the first portion provide ECC parity bits, and the additional column plane 212 provides metadata bits. During the second x4 operating mode, since only a portion of the column plane 210 is accessed, only the number of data bits (as well as metadata and ECC bits) provided to / from the device is accessed. The ECC circuit 232 receives the data and metadata as well as the parity bits, and locates and / or corrects any errors in the data and metadata. The (corrected) data and (corrected) metadata are provided to IO circuitry 234, which provides the data and metadata to the DQ terminals.

[0064] In an example write command in the second x4 operating mode, the column, row, and bank addresses are received from the controller along with the data and metadata. The data and metadata are provided to the ECC circuit through the IO circuit, which generates parity bits based on the data and metadata and then writes the data, metadata, and parity to the column plane accessed in a manner similar to that described for the read operation. In some embodiments, the number of bits retrieved when accessing a column may be greater than the specified number of metadata bits. In such embodiments, during a write operation, metadata may be pre-fetched (e.g., read) and then some of the bits are overwritten by the new metadata. This may incur a tCCD_L_WR penalty. However, since only a single additional tCCD_L_WR penalty is incurred (compared to two for the two-pass 4x operating mode), the single-pass mode may have reduced latency.

[0065] In the first (two-pass) x4 operation mode, each of the data column planes 210 stores a mix of data and metadata, with ECC parity bits stored in the extra column plane 212. In the second (one-pass) x4 operation mode, each of the data column planes 210 stores a mix of data and ECC parity bits, and metadata is stored in the extra column plane 212. In the single-pass mode, the ECC circuit 232 locates and corrects errors in both the data and the metadata (e.g., because the parity is based on both the data and the metadata). In the two-pass mode, the ECC circuit 232 locates and corrects errors in the metadata during the first pass. During the second pass, the ECC circuit 232 will only correct the data because the metadata is not used for parity in the second pass. In other words, in the one-pass mode, the parity bits are based on both the data and the metadata, while in the two-pass mode, there are separate parity bits for the data and the metadata.

[0066] Additionally, accesses in a one-pass x4 mode of operation may draw less power than accesses in a two-pass x4 mode of operation. In the two-pass mode of operation, all column planes are activated and data read from their sense amplifiers 220 are driven along the LIO to the ECC circuit 232 and the sense amplifiers 222 and LIO associated with the additional column planes 212 (and to the sense amplifiers 224 and LIO of the GCR 214 if a repair has been present). However, in a one-pass x4 mode of operation, only a selected portion (e.g., half) of the data column planes 210 are activated and thus not all data LIOs are driven by the respective sense amplifiers 220. Similarly, various switches, signal lines, etc. may not be used in every access in a one-pass x4 mode of operation. Thus, less power is drawn in the x4 mode of operation.

[0067] Figure 3 is a block diagram showing an example of a read operation of a memory according to some example embodiments of the present disclosure. Figure 3 A view of a memory array 300 is shown showing a representation of what portions of the memory array are set aside for different types of information. Figure 3 The blocks shown in represent portions of a memory array, but do not necessarily represent the spatial layout of where information is stored in the memory array. In some embodiments, the memory array 300 may be a second x4 operating mode described herein. Figure 1 The memory array 118 and / or Figure 2 Implementation of column planes 210 to 214.

[0068] Description of Example Embodiments Figure 3, where there are 16 data column planes (each of which provides 8 bits when activated by a column select signal) and an additional column plane (which also provides 8 bits when activated by its corresponding column select value). The example memory operates in x4 mode, where 64 data bits and 4 metadata bits are controlled by a controller (e.g. Figure 1 150) access. The CP select bit C10 of the column address is used to determine which column planes provide data. The bits of the column address can further specify which bits are provided (for example, which of the metadata bits are retrieved).

[0069] During an example read operation in which C10 is in a low logic state (e.g., C10=0), 8 column planes are accessed in the first portion 301 of the memory array 300, each of which provides 8 bits for a total of 64 data bits. A second column select is also provided to the column planes in the second portion 302. A second column select signal is provided to a single column plane and retrieves a total of 8 ECC parity bits. A column select signal is also provided to an additional column plane 308, which provides 8 metadata bits. However, four of these bits may not be relevant to the current read data, so they may not be provided from the device. The ECC circuit 310 (e.g., Figure 2 232) receives 64 data bits and 4 metadata bits and 8 parity bits and provides 64 data bits and 4 metadata bits. Which of the 8 retrieval bits from the extra column plane are provided as the 4 metadata bits can be based on C10 or another column address bit, such as CA9. This address will represent the data selected from the even or odd sense amplifier stripe.

[0070] In another example read operation, when C10 has an opposite value (eg, C10=1), 64 data bits may be accessed from the second portion 302 , 8 parity bits may be accessed from the first portion 301 , and metadata bits may be accessed from the additional column plane 308 .

[0071] In the example write operation, since 8 metadata bits are accessed, but only 4 are actually specified by the access operation, an additional 4 metadata bits may be protected. For example, the memory 300 may employ a read-modify-write (or RMW) strategy, where all 8 metadata bits are pre-fetched, and then four of these bits are changed (as needed) based on the newly written metadata, and then all 8 bits are written back. This may protect the additional 4 bits (so they are not accidentally changed by a direct write operation, since no data is written to these cells), at the expense of additional latency (e.g., tCCD_L_WR required for RMW).

[0072] The blocks in the first portion 301 and the second portion 302 represent portions of these column planes that may be set aside for different storage and do not necessarily represent the physical arrangement of where information is stored in the portions of the column planes or the spatial relationship of the column planes in each portion to each other. For example, the first portion may represent the even column planes while the second portion represents the odd column planes, and the columns set aside for storing ECC bits may be distributed among all data column planes. Figure 3 In the example of , since 8 ECC bits are required for every 64 data bits, each portion 301 and 302 may have 87.5% of its total memory space used for data and 12.5% ​​used for ECC and metadata bits. In other words, from the perspective of the controller, only 87.5% of the memory array may be addressed because the remainder is reserved for metadata, which is expected to arrive with the data. In the two-pass x4 operating mode, more of the memory array may be available because the metadata is stored in the data array and there are 4 metadata bits for every 64 data bits. Therefore, in the two-pass x4 operating mode, 93.75% of the array may be reserved for data and 6.25% for metadata. When metadata is disabled, 100% of the array space is available for data. The controller may address different addressable portions of the memory array based on generated column addresses associated with different ranges of CS values.

[0073] Table 1 is a summary of different operations in two different x4 modes with metadata according to some embodiments of the present disclosure.

[0074] Two times x4 One time x4 Metadata Deactivation Prefetch 8p+128md / 128d+8p 64d+4md+8p 128d+8p Data CP Data + Metadata Data + Parity data Additional CP Parity Metadata Parity % arrays available for data 93.75％ 87.5％ 100％ ECC SEC SECDED SEC MD ECC? yes yes no Latency 2x tCCD_L_WR 1x tCCD_L_WR 1x tCCD_L_WR electricity 17CS+1 CS 9CS 17CS

[0075] Table 1. Comparison of two-pass and one-pass x4 operation modes

[0076] In Table 1, the symbols d, p, and md are used to represent data bits, parity bits, and metadata bits, respectively. For example, the first row uses the symbols 8p+128md / 128d+8p to represent that in two-pass mode, 128 bits (4 of which are metadata bits) and 8 parity bits are acquired in the first pass, and then 128 data bits and 8 parity bits are acquired in the second pass, while the symbols 64d+4md+8p are used to represent pre-fetching 64 data bits, 4 metadata bits, and 8 parity bits as part of a single access pass. The mode register may also have a setting to disable metadata. When metadata is not used, the device may operate in a manner similar to the 'two-pass' mode, except that only a single pass is required to pre-fetch 128 data bits and 8 parity bits.

[0077] In the two-pass x4 mode of operation (and in the metadata disabled mode), 128 metadata bits (4 of which are associated with data access) and 8 parity bits associated with these 128 metadata bits are used by the ECC circuit 232 in the first pass, while 128 data bits and 8 parity bits are used by the ECC circuit 232 in the second pass. In the one-pass x4 mode of operation, 64 data bits, 4 metadata bits, and 8 parity bits are used by the ECC circuit 232. In the two-pass x4 mode, the ECC circuit 232 can implement the SEC scheme separately for both the 128 metadata bits and the 128 data bits, while in the one-pass x4 mode, the SECDED scheme can be used together on both the data and the metadata. In other words, in the two-pass mode, each set of parity checks can correspond to either data or metadata, while in the one-pass mode, the parity checks correspond to both data and metadata together. Since a higher number of parity checks are used relative to other bits in the one-pass mode, more protection can be provided. Additionally, in one-pass mode, metadata may also be checked by the ECC circuit, whereas in two-pass mode, metadata may not be protected by the ECC circuit of the second pass.

[0078] In two-pass x4 operation mode, there may be an additional latency of 2×tCCD_L_WR because two access passes (of metadata and prefetch data) need to go through the RMW cycle. In one-pass x4 operation mode, only a single additional tCCD_L_WR is incurred. Metadata disabled mode may also only incur an additional tCCD_L_WR because the amount of prefetched data is greater than the amount to be written, so RMW is used to prefetch the entire set of data and then overwrite selected bits.

[0079] The one-pass x4 mode of operation may draw less power than the two-pass x4 mode of operation (or metadata disabled mode). In the one-pass mode, the CS signal may be provided only to a selected half of the column planes (based on C10). Thus, only half of the column planes need to activate their switches, drive voltages along the LIO lines, etc. This may reduce the power draw of a single access operation. For example, in the two-pass mode, 17 different CS signals (16 data column planes and 1 additional column plane) and their associated LIO / GIO, etc. are activated, while in the one-pass mode, 9 different CS signals and their associated LIO / GIO, etc. are activated (17 column planes of data and ECC are activated when metadata is disabled).

[0080] Figure 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. In some embodiments, the memory bank 400 may include Figure 1 Memory 100, Figure 2 200 and / or Figure 3300. Memory bank 400 shows a simplified schematic diagram of the layout of a memory bank and example signals that may be used to activate various columns in the column plane as part of a second x4 operating mode (eg, a one-pass x4 operating mode).

[0081] Similar to Figure 3 , with respect to which example embodiments are described Figure 4 , where there are 16 data column planes, each of which includes 64 groups of bit lines (e.g., 64 values ​​of the CS signal), each of which provides 8 data bits when activated by a corresponding CS signal. It should be understood that this is one example implementation of the present disclosure, and other arrangements (e.g., more or fewer CS groups per CP, more or fewer CPs per bank, etc.) may be used in other example embodiments.

[0082] Memory bank 400 is shown organized into 16 column planes 412 through 448 (e.g. Figure 2 210 and / or Figure 3 301 to 302), each of the 16 column planes is associated with a DQ pad 410 to 440. Thus, the first DQ pad 410 is associated with column planes 412 to 418, the second DQ pad 420 is associated with column planes 422 to 428, the third DQ pad 430 is associated with column planes 432 to 438, and the fourth DQ pad is associated with column planes 442 to 448. Figure 4 In the example x4 mode of FIG. 4 , each of the four DQ pads 410, 420, 430, and 440 handles 16 data bits as part of an access operation, for a total of 64 data bits. In addition to the four DQ pads 410, 420, 430, and 440, the memory bank 400 may also be associated with a metadata terminal 450 that may be used to send / receive metadata as part of an access operation. The metadata terminal is associated with an additional column plane 452 (e.g., Figure 1 212 and / or Figure 3 308). Figure 4 In a simplified diagram of FIG. 4 , a single word line WL is shown, along with a global row decoder 402 that drives the word line. Similarly, only selected ones of the bit lines are shown, each of which represents a group of bit lines activated by a common CS signal in the CP. When activated, the bit line is coupled to a corresponding LIO line.

[0083] The memory bank 400 is organized with cells of the memory array between two sense amplifier regions 404. The sense amplifier regions 404 may be elongated in the same direction as the word lines WL. Column planes 412 to 448 are separated by sub-word line (SWL) drivers 406. Each column plane is adjacent to another column plane and the SWL driver 406. For example, the column plane 412 is adjacent to the SWL driver 406 on one side and adjacent to the column plane 414 on the other side. The column plane 414 is adjacent to the column plane 412 on a first side and adjacent to the second SWL driver 406 on the opposite side. Another column plane 416 is on the opposite side of the SWL driver 406, and so on.

[0084] Thus, each data terminal is associated with 4 column planes, 2 pairs of column planes adjacent to each other and separated from another pair by the SWL driver. Each pair is associated with a different value of the column plane select bit C10. For example, the first DQ pad 410 is associated with column planes 412 and 414 (both column planes are activated by C10 at a high logic level) and with column planes 416 and 418 (both column planes are activated by C10 at a low logic level). Thus, column planes 412, 414, 422, 424, 432, 434, 442, and 444 all contain data accessed when C10=1 and column planes 416, 418, 426, 428, 436, 438, 446, and 448 all contain data accessed when C10=0. Regardless of which group of column planes is selected by C10, one or more column planes of the other group can be used to store ECC parity bits.

[0085] Figure 4 An example access operation in a second x4 mode of operation (e.g., a one-pass x4 mode) is shown. The memory device receives a column address that includes C10=0 and has a value decoded to the first column select signal CS0. Therefore, CS0 is provided by the column decoder to column planes 416, 418, 426, 428, 436, 438, 446, and 448, and the bit lines associated with CS0 in each of these column planes each provide 8 data bits. The column decoder also provides CS0 to an additional column plane 452, and accesses 8 metadata bits (4 of which can be selected based on the value of C10). In addition, the column decoder also generates an additional CS signal and provides it to one of the column planes not selected by the value of C10. In this example embodiment, the value CS56 is provided to column plane 444. Therefore, column plane 444 provides 8 ECC parity bits. In this way, from a single access pass, 64 data bits (8 each from column planes 416, 418, 426, 428, 436, 438, 446, and 448), 4 metadata bits (half of which are retrieved from extra column plane 452), and 8 parity bits (from column plane 444) are accessed. Arrows are used to show which CS signals and which column planes are accessed as part of a single access pass.

[0086] In other words, the column decoder (e.g. Figure 1 110) may activate the digit lines and couple them to the LIOs of column planes 416, 418, 426, 428, 436, 438, 446, and 448. This may represent all LIOs available for the column planes activated by C10=0 (e.g., 8 LIOs per column plane). However, in the column plane group associated with C10=1, the column decoder may activate not all LIOs because only CS56 in column plane 444 is coupled to the LIO. The remaining LIOs associated with the column planes activated by C10=1 are not used in this access operation.

[0087] Although Figure 4 , but a similar access may occur as part of a second access operation, where a column address is received that includes C10=1 but the same decoded value of CS. In the example, the column decoder provides CS0 to column planes 412, 414, 422, 424, 432, 434, 442, and 444 and additional column plane 450, while the CS56 value is provided to column plane 448. It should be noted that the same 8 bits may be provided from additional column plane 452, but the value of C10 controls which portion of the 8 bits are provided as the 4 metadata bits.

[0088] Based on the operating mode of the memory, the controller may have different ranges of addressable values. In this example, the controller may generate column addresses associated with CS values ​​in the range of CS0 to CS55. However, CS55 to CS63 may represent 'unaddressable' space because the controller cannot directly access these columns (which are left for parity checking).

[0089] Figure 5 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 500 may be implemented by one or more of the devices or systems described herein. For example, method 500 may be implemented by Figure 1 Memory 100, Figure 2 200 Figure 3 300 and / or Figure 4 400 implementation.

[0090] Method 500 may generally begin at block 510, which describes receiving a column address as part of an access operation. Method 500 may also include receiving a row and bank address and an access command as part of the access operation. For example, the address and command may be received along a C / A terminal of a memory, such as Figure 1 C / A terminal.

[0091] Block 510 may generally be followed by block 520, which describes selecting a first portion of the plurality of column planes based on the column address. Method 500 may include selecting a first half of the column planes as the first portion or selecting a second half of the column planes as the first portion. The column address may include a column plane select bit (e.g., C10) that specifies which column planes are or are not in the first portion. For example, method 500 may include selecting the first half when the column plane select bit is in a first state and selecting the second half when the column plane select bit is in a second state. Method 500 may include selecting the first half when the column plane select bit is in a first state and selecting the second half when the column plane select bit is in a second state. Figure 1 110) generates a column selection signal associated with an access operation.

[0092] Block 520 may generally be followed by blocks 530 through 550, which may occur sequentially (as shown or in any order) or may occur nearly simultaneously with one another. Block 530 describes accessing data bits from a column in a first portion of a plurality of column planes as part of an access operation. Block 540 describes accessing parity bits from a column in a column plane not in the first portion as part of an access operation. Block 550 describes accessing metadata bits from an additional column plane as part of an access operation.

[0093] For example, method 500 may include generating a first column select signal with a column decoder and providing it to a first portion of column planes, generating a second column select signal and providing it to a column plane annotation in the first portion, and generating a third column select signal to an additional column plane. The first column select signal and the third column select signal may have the same value. The second column select signal may have a different value than the first column select signal. In an example embodiment, method 500 may include accessing 64 data bits from a column in the first portion, accessing 4 metadata bits from an additional column plane, and accessing 8 parity bits from a column plane not in the first portion.

[0094] In some embodiments, method 500 may include using an ECC circuit (eg, Figure 1 120 Figure 2 232 and / or Figure 3 310) locates errors, corrects errors, or a combination thereof based on parity bits. For example, as part of a read operation, data, parity, and metadata may all be provided to an ECC circuit. In some embodiments, method 500 may include performing SECDED error correction with an ECC circuit.

[0095] The first portion may represent a first half of the column planes, and the column planes not in the first portion may be a single column plane in a second half of the column planes. In some embodiments, method 500 may include: receiving a second column address as part of a second access operation; selecting a second half of the plurality of column planes based on the second column address; accessing second data bits from the second half as part of the second access operation; accessing parity bits from columns in the first half as part of the second access operation; and accessing metadata bits from additional column planes as part of the second access operation.

[0096] Figure 6 600 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure. Timing diagram 600 may represent how a controller may write a value to a mode register (e.g. Figure 1 130) to set the memory mode instance.

[0097] Timing diagram 600 shows a clock signal CK_t / CK_c (eg Figure 1 The chip select signal is used to indicate that the controller is addressing this specific memory device (such as a chip). Figure 6 In FIG. 1 , a higher level is used to indicate that the chip select signal is valid, but in some embodiments, the chip select signal may be active low. Also shown are signals along the command / address bus CA and the command CMD.

[0098] Timing diagram 600 shows three MRW operations occurring sequentially at time points Ta0R, Tb1R, and Tc1R. Each MRW operation includes providing an address within the mode register and data written to this register along the CA (shown in a box labeled "valid" to indicate that the value MR address and data are being provided). Two sequential MRW commands labeled MRW-1 and MRW-2 are used to indicate that the information along the CA bus is part of a MRW operation.

[0099] Figure 7 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 700 may be a method of operating a memory device. For example, when Figure 1 The controller 150 of the controller operates the memory (eg Figure 1 100 Figure 2 200 Figure 3 300 and / or Figure 4 400), method 700 may be implemented by the controller.

[0100] Method 700 includes block 710, which describes writing a mode register value to set the memory in a first x4 operating mode or a second x4 operating mode. For example, the controller may perform a similar operation to that described with respect to Figure 6The MRW operation described in FIG. MRW operations may write values ​​to one or more registers that control which x4 operating mode the memory is in.

[0101] Block 710 may be followed by block 720, which describes writing the data and metadata to the memory array. For example, method 700 may include providing an address and a write command along a CA bus and providing data along a DQ terminal and providing metadata along a metadata terminal. For example, a controller may provide 64 data bits and 4 metadata bits in 4 16-bit bursts (e.g., in 4-bit bursts).

[0102] Block 720 may generally be followed by block 730, which describes addressing a first percentage of the memory array in a first x4 operating mode or addressing a second percentage of the memory array in a second x4 operating mode. The mode may determine how much percentage of the array is used for data and how much percentage is reserved for additional information. Figure 3 As described, when the memory is in the second (one-pass) operating mode, more data arrays may be reserved for metadata than when the memory is in the first (two-pass) operating mode. For example, method 700 may include storing a greater total amount of data in the memory in the first mode than in the second mode.

[0103] The method 700 may include generating column addresses associated with addressable regions of the memory array. Thus, when the memory is in a first operating mode, the controller may generate column addresses associated with a first range of CS values ​​(e.g., CS0 to CS59) and in a second operating mode, generate column addresses associated with a second range of CS values ​​(e.g., CS0 to CS54).

[0104] In some embodiments, method 700 may include writing an MR value to set the memory in a mode in which metadata is disabled and writing data (but not metadata) to the memory array. In this mode, the controller may address a third percentage in the metadata disabled mode. The third percentage may be 100% of the memory array. For example, when the memory is in the third mode, the controller may generate a column address associated with a third range of CS values ​​(e.g., CS0 to CS63).

[0105] Figure 8 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 800 may be a method of operating a memory device. For example, when Figure 1 The controller 150 of the controller operates the memory (eg Figure 1 100 Figure 2 200 Figure 3 300 and / or Figure 4 400), method 800 may be implemented by the controller.

[0106] Method 800 includes block 810, which describes writing a mode register value to set the memory in a first x4 operating mode or a second x4 operating mode. For example, the controller may perform a similar operation to that described with respect to Figure 6 The MRW operation described in FIG. MRW operations may write values ​​to one or more registers that control which x4 operating mode the memory is in.

[0107] Block 810 may be followed by block 820, which describes writing the data and metadata to the memory array. For example, method 800 may include providing an address and a write command along a CA bus and providing data along a DQ terminal and providing metadata along a metadata terminal. For example, a controller may provide 64 data bits and 4 metadata bits in 4 16-bit bursts (e.g., in 4-bit bursts).

[0108] Block 820 may be followed by block 830, which describes writing the data and metadata to the memory array with a first latency in the first x4 operating mode or with a second latency in the second x4 operating mode. The first latency may be greater than the second latency. For example, the first latency may include two additional tCCD_L_WR periods, while the second latency may include one additional tCCD_L_WR period.

[0109] Fig. 9 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 900 may be a method of operating a memory device. For example, when Figure 1 The controller 150 of the controller operates the memory (eg Figure 1 100 Figure 2 200 Figure 3 300 and / or Figure 4 400), method 900 may be implemented by the controller.

[0110] Method 900 includes block 910, which describes writing a mode register value to set the memory in a one-pass x4 operating mode. For example, the controller may perform a similar operation to that described with respect to Figure 6 The MRW operation described in FIG. MRW operations may write values ​​to one or more registers that control which x4 operating mode the memory is in.

[0111] Block 910 may be followed by block 920, which describes reading the data and metadata to the memory array. For example, method 900 may include providing an address and a read command along a CA bus. Method 900 may include receiving data and metadata along a DQ terminal and one or more metadata terminals of the memory. For example, the controller may receive 64 data bits and 4 metadata bits in 4 16-bit bursts (e.g., in 4-bit bursts).

[0112] Block 920 may generally be followed by block 930, which depicts receiving a signal from the memory indicating double-bit error detection in the data and metadata. For example, in a one-pass x4 operating mode, the memory may perform SECDED on both the data and metadata. If a single-bit error is detected, it may be corrected. If a double-bit error is detected, the memory may provide a signal indicating the double-bit error.

[0113] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes or separated and / or performed in separate devices or device portions according to the present systems, devices, and methods.

[0114] Finally, the above discussion is intended to be illustrative only of the inventive system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the inventive system has been described in particular detail with reference to exemplary embodiments, it should also be understood that a person of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the inventive system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: A first data row plane including a first bit line and a second bit line; A second data row plane including a third bit line and a fourth bit line; an additional column plane including a fifth bit line and a sixth bit line; a column decoder configured to activate the first bit line, the fourth bit line, and the fifth bit line as part of an access operation; and An error correction code (ECC) circuit is configured to access data bits along the first bit line, metadata bits along the fifth bit line, and parity bits along the fourth bit line as part of the access operation.

2. The apparatus of claim 1 , wherein the column decoder is configured to activate the second bit line, the third bit line, and the fifth bit line as part of a second access operation, wherein the ECC circuit is configured to access data along the third bit line, access parity bits along the second bit line, and access metadata along the sixth bit line as part of the second access operation.

3. The apparatus of claim 1 , wherein the column decoder is configured to selectively activate the bit lines based on a received column address, and wherein the column address includes a column plane select bit that specifies whether the data is stored in the first data column plane or the second data column plane.

4. The apparatus of claim 1 , further comprising an input / output circuit configured to receive the data and the metadata from the ECC circuit when the access operation is a read operation and configured to provide the data and the metadata to the ECC circuit when the access operation is a write operation.

5. The apparatus of claim 1, wherein the ECC circuit is configured to locate and correct errors in the data and the metadata based on the data metadata and the parity when the access operation is a read operation.

6. The apparatus of claim 1, wherein parity bits stored along the second bit line are associated with data in data bits stored along the third bit line, and wherein the data bits along the first bit line are associated with the parity bits stored along the fourth bit line.

7. The apparatus of claim 1 , wherein in response to a column address received as part of the access operation, the column decoder is configured to provide a column select signal having a first value to the first data column plane, a second column select signal having a second value to the second data column plane, and a third column select signal having the first value to the additional column plane.

8. A device comprising: A storage body, comprising: a first plurality of column planes; a second plurality of column planes; and Additional row planes; and a column decoder configured to select the first or the second plurality of column planes based on a column address received as part of an access operation, wherein data bits are accessed in the selected one of the first or the second plurality of column planes, parity bits are accessed in an unselected one of the first or the second plurality of column planes, and metadata bits are accessed in the additional column plane as part of the access operation.

9. The apparatus of claim 8, further comprising an error correction code (ECC) circuit configured to locate and correct errors in the data bits and the metadata bits based on the parity bits when the access operation is a read operation.

10. The apparatus of claim 9, wherein the ECC circuit is configured to perform single error correction double error detection (SECDED).

11. The apparatus of claim 8, wherein the column address includes a column plane select bit, and wherein the first plurality of column planes or the second plurality of column planes are selected based on the column plane select bit.

12. The apparatus of claim 11, wherein a plurality of bits are accessed from the additional column plane, and wherein the column decoder selects a first half or a second half of the plurality of bits as the metadata bits.

13. The apparatus of claim 8, further comprising: a first plurality of local input / output (LIO) lines coupled to the first plurality of column planes; and a second plurality of LIO lines coupled to the second plurality of column planes, wherein the column decoder is configured to activate all of the first plurality or the second plurality of LIO lines coupled to the selected ones of the first or the second plurality of column planes and less than all of the first plurality or the second plurality of LIO lines coupled to the unselected ones of the first or the second plurality of column planes as part of the access operation.

14. The apparatus of claim 8, wherein the apparatus is a memory device operating in x4 mode.

15. A method comprising: receiving a column address as part of an access operation; selecting a first portion of a plurality of column planes based on the column address; accessing data bits from columns in the first portion of the plurality of column planes as part of the access operation; accessing parity bits from columns in a column plane not in the first portion as part of the access operation; and Metadata bits are accessed from the extra column planes as part of the access operation.

16. The method of claim 15, further comprising locating errors, correcting errors, or a combination thereof in the data bits and the metadata bits with an error correction code (ECC) circuit based on the parity bits.

17. The method of claim 16, further comprising performing single error correction double error detection (SECDED) with the ECC circuit.

18. The method of claim 15, further comprising accessing a set of bits from the additional column plane and selecting half of the set of bits as the metadata bits based on the column address.

19. The method of claim 15, further comprising: selecting a first half of the plurality of column planes as the first portion; and A column plane is selected in the second half of the plurality of column planes as the column plane not in the first portion.

20. The method of claim 19, further comprising: receiving a second column address as part of a second access operation; selecting the second half of the plurality of column planes based on the second column address; accessing a second data bit from the second half as part of the second access operation; accessing parity bits from columns in the first half as part of the second access operation; and Metadata bits are accessed from the additional column plane as part of the second access operation.

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