System and method for oscillator calibrator for inverter for electric vehicle

Abstract

A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, where the inverter includes: an electrical isolator separating a high voltage region from a low voltage region; a low voltage phase controller in the low voltage region, the low voltage phase controller configured to receive a clock reference signal; and a high voltage phase controller in the high voltage region, the high voltage phase controller configured to align a clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 18 / 063,332 filed on December 8, 2022, which claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, and U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure generally relate to systems and methods for an oscillator calibrator for an inverter for an electric vehicle, and more particularly to systems and methods for an oscillator calibrator for a power switching element of an inverter for an electric vehicle. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for, for example, converting high voltage direct current (HVDC) to alternating current (AC) to drive the motor. In inverters, differences in oscillator frequency can lead to inverter inefficiencies.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: an electrical isolator that separates a high voltage region from a low voltage region; a low voltage phase controller that is in the low voltage region and is configured to receive a clock reference signal; and a high voltage phase controller that is in the high voltage region and is configured to align the clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller.

[0007] In some aspects, the techniques described herein relate to a system in which a low voltage phase controller includes a clock reference sampler configured to align a clock reference signal of the low voltage phase controller with a clock reference signal of an inverter controller.

[0008] In some aspects, the technology described herein relates to a system wherein a low voltage phase controller includes a clock reference sampler configured to align a clock reference signal of the low voltage phase controller with a clock reference signal of an inverter controller when the clock reference signal of the inverter controller is available, and to align the clock reference signal of the low voltage phase controller with a clock reference signal of another low voltage phase controller when the clock reference signal of the inverter controller is not available.

[0009] In some aspects, the technology described herein relates to a system wherein the inverter further includes a use-point phase controller, the use-point phase controller being in a high voltage region, the use-point phase controller being configured to align a clock reference signal of the use-point phase controller with a clock reference signal of a high voltage phase controller.

[0010] In some aspects, the technology described herein relates to a system in which a low voltage phase controller includes a clock reference sampler configured to align a clock reference signal of the low voltage phase controller with a master clock reference signal by counting a number of system clock pulses in one or more cycles of the master clock reference signal and comparing the counted number to an expected value.

[0011] In some aspects, the technology described herein relates to a system in which a low voltage phase controller includes a clock calibrator configured to increase or decrease a period of an internal oscillator of the low voltage phase controller to align a counted number with an expected value.

[0012] In some aspects, the technology described herein relates to a system wherein a high voltage phase controller includes a clock reference sampler configured to align a clock reference signal of the high voltage phase controller with a clock reference signal of a low voltage phase controller by counting a number of system clock pulses in one or more cycles of the clock reference signal of the low voltage phase controller and comparing the counted number with an expected value.

[0013] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to an inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0014] In some aspects, the technology described herein relates to a system comprising: a power module, the power module being for an inverter for an electric vehicle, the power module comprising: a power switching element, the power switching element comprising a drain terminal, a source terminal, and a gate terminal; a gate driver, the gate driver being configured to provide a signal to the gate terminal to control the operation of the power switching element; and a use-point phase controller, the use-point phase controller being configured to align a clock reference signal of the use-point phase controller with a clock reference signal of a high voltage phase controller, and to control the gate driver based on the clock reference signal of the use-point phase controller.

[0015] In some aspects, the technology described herein relates to a system in which a use-point phase controller is configured to align a clock reference signal of the use-point phase controller with a clock reference signal of a high-voltage phase controller by counting the number of system clock pulses in one or more cycles of the clock reference signal of the high-voltage phase controller and comparing the counted number to an expected value.

[0016] In some aspects, the technology described herein relates to a system wherein a point-of-use phase controller is further configured to increase or decrease a period of an internal oscillator of the point-of-use phase controller to align a counted number with an expected value.

[0017] In some aspects, the technology described herein relates to a system wherein a use point phase controller is further configured to iteratively perform alignment of an oscillator of the use point phase controller with a clock reference signal of a high voltage phase controller such that continuous counting of the number of system clock pulses aligns the oscillator of the use point phase controller with the clock reference signal of the high voltage phase controller.

[0018] In some aspects, the technology described herein relates to a system in which a point-of-use controller is configured to align a clock reference signal of a point-of-use phase controller with a clock reference signal of a high-voltage phase controller using a command bus for initial alignment after initialization of the point-of-use controller and using a message bus for subsequent alignments after the initial alignment.

[0019] In some aspects, the techniques described herein relate to a system in which a clock reference signal of a high voltage phase controller has a frequency from about 100 Hz to about 10 kHz.

[0020] In some aspects, the technology described herein relates to a system comprising: a first controller configured to: receive a clock reference signal of a master controller; align an oscillator of the first controller with the clock reference signal of the master controller; and provide a reference signal to a second controller based on the clock reference signal of the aligned oscillator of the first controller.

[0021] In some aspects, the technology described herein relates to a system wherein a first controller is further configured to count a number of system clock pulses in one or more cycles of a clock reference signal of a master controller and compare the counted number to an expected value to align an oscillator of the first controller with the clock reference signal of the master controller.

[0022] In some aspects, the technology described herein relates to a system wherein the first controller is further configured to increase or decrease a period of an oscillator of the first controller to align the counted number with an expected value to align the oscillator of the first controller with a clock reference signal of a master controller.

[0023] In some aspects, the technology described herein relates to a system wherein a first controller is further configured to iteratively perform alignment of an oscillator of the first controller with a clock reference signal of a master controller such that consecutive counting of a number of system clock pulses aligns the oscillator of the first controller with the clock reference signal of the master controller.

[0024] In some aspects, the technology described herein relates to a system in which a first controller is configured to provide a reference signal to a second controller when an oscillator of the first controller is aligned with a clock reference signal of a master controller.

[0025] In some aspects, the technology described herein relates to a system in which a reference signal to a second controller is a defined number of clock pulses of an oscillator of a first controller for a defined period of time.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 An exemplary system infrastructure for an inverter with a controller including oscillator calibration is depicted in accordance with one or more embodiments. DETAILED DESCRIPTION

[0035] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0036] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0037] Various embodiments of the present disclosure generally relate to systems and methods for an oscillator calibrator for an inverter for an electric vehicle, and more particularly to systems and methods for an oscillator calibrator for a power switching element of an inverter for an electric vehicle.

[0038] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three half-H-bridge switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the half-H-bridge switches. The half-H-bridge switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the half-H-bridge switch by passing through the isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the half-H switching element via the gate driver output.

[0039] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0040] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0041] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0042] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0043] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0044] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point of use ICs have not yet been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0045] The gate driver circuit may include various oscillators for providing clock reference signals used in various operations in the inverter. Oscillator frequency variations between multiple controllers connected by a common communication bus can be a major source of uncertainty in the exchange of information between the controllers. For example, a first controller without onboard non-volatile memory may have a large variation in oscillator frequency relative to a second controller. This difference in oscillator frequency may result in reduced communication reliability or complex communication protocols in order to overcome the potential uncertainty in communication caused by the difference.

[0046] One or more embodiments may trim the oscillator frequency of a high voltage controller to the oscillator frequency of a low voltage controller to a high accuracy. One or more embodiments may trim the oscillator frequency of a point-of-use controller. One or more embodiments may include an isolated gate driver having a low voltage (LV) PWM signal domain and a high voltage (HV) phase domain. One or more embodiments may include a transceiver that allows communication between the LV and HV domains. One or more embodiments may include a clock reference sampler for sampling the LV domain and aligning the LV domain with an external quartz clock reference, and may have an error of less than one percent. One or more embodiments may include a clock calibrator for aligning the HV domain clock with the LV domain clock so that all timing is synchronized. One or more embodiments may synchronize all voltage domains of a phase switching device to an absolute clock reference with an error of less than one percent.

[0047] One or more embodiments may perform an initial trim operation using a handshaking process during controller initialization to ensure both controllers are ready to perform the trim operation. One or more embodiments may determine whether a trim operation should be performed and may perform this determination continuously and independently on any controller having an oscillator.

[0048] The initial trimming operation may use a waveform transmitted by the low voltage controller to the high voltage controller over a command bus through an electrically isolated interface between the high voltage controller and the low voltage controller. The waveform may have a predetermined period, and the high voltage controller may use a successive approximation algorithm to manipulate the trimming input of the oscillator of the high voltage controller to obtain the correct oscillator frequency.

[0049] After the initial trim operation has been performed, subsequent trim operations may be performed over the electrically isolated interface using messages transmitted using a standard communication protocol using a message bus rather than a command bus. Subsequent trim operations must not interfere with command bus communications between the high voltage controller and the low voltage controller that may be occurring during the subsequent trim operation.

[0050] One or more embodiments may eliminate the need to store oscillator trim values ​​for controllers in non-volatile memory. One or more embodiments may correct any drift in oscillator frequency due to temperature effects and component drift or aging by performing trim operations at controller initialization and periodically during operation. One or more embodiments may eliminate the need for dedicated pins and external components for improving oscillator frequency matching between controllers. By eliminating the need for onboard non-volatile memory for controllers, one or more embodiments may save costs due to reduced component count, testing, and process complexity. One or more embodiments may provide more robust and faster communication between controllers due to simplified communication protocols. One or more embodiments may use an external oscillator reference to improve low voltage controller oscillators. One or more embodiments may improve timing measurements performed by peripheral controllers (such as high voltage controllers and point of use controllers), for example, by trimming the oscillator of the peripheral controller to match the oscillator of the low voltage controller. One or more embodiments may provide close matching of clock frequencies between controllers and save costs due to performing oscillator trimming locally in the controller.

[0051] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0052] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 3 14). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor in the pair carries an inverted data signal from the other capacitor in the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0053] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0054] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0055] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0056] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0057] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0058] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0059] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0060] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0061] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0062] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0063] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0064] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0065] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0066] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0067] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0068] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0069] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0070] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0071] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0072] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0073] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0074] Figure 6 An exemplary system infrastructure for an inverter with a controller including oscillator calibration is depicted in accordance with one or more embodiments. Figure 6An inverter 600 may be included, which includes a PWM controller 602, an upper gate driver 604, a lower gate driver 606, an upper phase switch 608, and a lower phase switch 609. The upper phase switch 608 and the lower phase switch 609 may provide a switchable connection between a battery 611 and a phase connector 610, which may be connected to the motor 190, for example, to drive the motor 190. The PWM controller 602 may generate a master clock reference signal and may provide the master clock reference signal as a PWM signal 603 to the upper gate driver 604, and may provide the master clock reference signal as a PWM signal 605 to the lower gate driver 606.

[0075] The upper gate driver 604 may include a low voltage region 612 and a high voltage region 614 separated by an electrical isolator 616. The low voltage region 612 may receive a PWM signal 603 from the PWM controller 602 and pass the PWM signal across the electrical isolator 616 to the high voltage region 614, which may then drive the upper phase switch 608. Here, the upper gate driver 604 may drive the upper phase switch 608, and the lower gate driver 606 may drive the lower phase switch 609.

[0076] Inverter 600 may be a specific implementation of inverter 110. PWM controller 602 may be a specific implementation of inverter controller 300. Upper gate driver 604 may be a specific implementation of: low voltage upper phase controller 120; and one or more of high voltage upper phase controller 130 or point of use upper phase controller 142. Lower gate driver 606 may be a specific implementation of: low voltage lower phase controller 125; and one or more of high voltage lower phase controller 135 or point of use lower phase controller 146. Upper phase switching element 608 may be a specific implementation of upper phase switching element 144. Lower phase switching element 609 may be a specific implementation of lower phase switching element 148. Low voltage region 612 may be a specific implementation of low voltage upper phase controller 120. High voltage region 614 may be a specific implementation of one or more of high voltage upper phase controller 130 or point of use upper phase controller 142. Electrical isolator 616 may be a specific implementation of electrical isolator 150.

[0077] The high voltage region 614 may include a phase switch on-time detector 618 that can measure and store the actual on-time of the upper phase switch 608 and send the information to the low voltage region 612 of the upper gate driver 604, for example, in the form of an encoded message. For example, the phase switch on-time detector 618 can detect the number of pulses of the system clock that occur when the upper phase switch 608 is detected to be turned on. The phase switch on-time detector 618 can measure the actual on-time of the upper phase switch 608 using, for example, the gate-to-source voltage of the upper phase switch 608. The phase switch on-time detector 618 can measure the actual on-time of the upper phase switch 608 using, for example, the absolute value of the current through the upper phase switch 608. The phase switch on-time detector 618 can measure the actual on-time of the upper phase switch 608 using, for example, the absolute value of the drain-to-source voltage of the upper phase switch 608 (such as when the voltage is above a threshold).

[0078] For the gate-to-source voltage, the gate-to-source waveform can be divided into three charge phases: (i) Qgs1 phase - the switching charge required to reach the threshold voltage, (ii) Qgd phase - the switching charge required to switch the drain-to-source voltage, and (iii) Qgs2 phase - the switching charge required to reach full enhancement. The phase switch element on-time detector 618 can detect each of these three phases by monitoring the gate-to-source voltage and gate-to-source current of the upper phase switch element 608. If the upper phase switch element 608 that is turning off has reached the Qgs1 / Qgd boundary before the lower phase switch element 609 that is turning on has started the Qgs1 phase, then direct conduction can be avoided. For example, the phase switch element on-time detector 618 can start the on-time counter at the beginning of the Qgs1 on-phase and keep the counter running when the upper phase switch element 608 is fully turned on until the end of the Qgs2 phase. The counter then continues to run after the upper phase switch 608 is commanded off and stops counting when the upper phase switch 608 reaches the Qgd to Qgs1 boundary as a result of the upper phase switch 608 being commanded off. This defines the "on time" as the time during which there is any possibility that the upper phase switch 608 can conduct current and ensure that the on times of the opposing upper phase switches 608 and lower phase switches 609 do not overlap.

[0079] The low voltage region 612 may include an on-time comparator 628 configured to receive information from the phase switch on-time detector 618, such as in an encoded message providing a feedback signal, and compare the received feedback signal with the PWM signal 603 as a feedback comparison. The low voltage region 612 may include a PWM on-time trimmer 622 that may use the feedback comparison from the on-time comparator 628 to generate a programmable delay of the rising or falling edge of the PWM signal 603. The programmable delay may be generated so that the commanded duty cycle at the upper phase switch 608 is the same as the incoming PWM duty cycle from the PWM controller 602 as defined by the PWM signal 603.

[0080] The low voltage region 612 may further include a PWM delay trimmer 620 that can trim the incoming signal so that the absolute delay of the PWM edge is the same for the parallel gate drivers including the upper gate driver 604. For example, a PWM signal 603 may be sent to two upper phase gate drivers so that the two upper phases receive the PWM signal 603 in parallel. The two upper phase gate drivers may have different propagation delays and other circuit characteristics from each other. Therefore, without correction, although the PWM signal 603 input to the circuit is the same, the different circuit delays cause different output phase switching element switching times from each other. The PWM delay trimmer 620 provides a trimming operation to delay the PWM signal 603 by a separate amount for each phase gate driver so that the two upper phase gate drivers have the same output phase switching element switching time based on the PWM signal 603 even though they have different circuit characteristics.

[0081] The low voltage region 612 may further include a clock reference sampler 624 that samples an external clock reference to align the low voltage domain clock with an external precision reference. For example, the clock reference sampler 624 may be configured to align the clock reference signal of the upper gate driver 604 with the clock reference signal of the PWM controller 602. Both the low voltage region 612 and the high voltage region 614 may include a corresponding clock calibrator 626 for aligning the clock or oscillator of the low voltage region 612 and the high voltage region 614. The corresponding clock calibrator 626 may each include an oscillator, or the oscillator may be separated from the corresponding clock calibrator 626. For example, the function of the clock calibrator 626 may be included in the communication manager 405. For example, the clock reference sampler 624 may count the number of system clock pulses in one or more cycles of the incoming reference clock signal and compare the number with the expected value. For example, the reference clock frequency may be a value from about 100 Hz to about 10 kHz. The clock calibrator 626 in the low voltage region 612 can increase or decrease the period of the internal oscillator in the low voltage region 612 to align the system clock count to the expected value. This process can occur in a single operation, or it can be iterative so that consecutive reference clock samples align the LV internal oscillator with the reference clock. The clock alignment can be run periodically over time to make adjustments to account for drift that may occur, for example, due to aging of the circuit or changes in temperature.

[0082] When the clock calibrator 626 in the low voltage region 612 is adjusted so that the low and high voltage clocks are aligned, the clock calibrator 626 in the low voltage region 612 can send updates to the clock calibrator 626 in the high voltage region 614. The clock calibrator 626 in the high voltage region 614 can operate in a similar manner to the clock calibrator 626 in the low voltage region 612, and can receive a reference signal, compare the reference signal with an internal expected value and make adjustments accordingly. The clock calibrator 626 in the low voltage region 612 can send a data stream to the clock calibrator 626 in the high voltage region 614, and the data stream can be a limited number of LV system clock pulses. For example, the limited number can be a limited number of LV system clock pulses that last for about 1mS. The clock calibrator 626 in the high voltage region 614 can count the number of system clock pulses during the message time, compare the number with the reference value, and adjust the internal oscillator in the high voltage region 614 based on the comparison. This process may occur in a single operation, or may be iterative, so that continuous LV clock samples align the HV internal oscillator with the LV internal oscillator. The reference clock signal may be a signal from the PWM controller 602, or may be generated by one of the upper gate driver 604 or the lower gate driver 606 for use by the other gate driver. For example, when the clock signal from the PWM controller 602 is available, the upper gate driver 604 may synchronize the internal clock to the PWM controller 602, and the lower gate driver 606 may synchronize the internal clock to the upper gate driver 604. When the clock signal from the PWM controller 602 is not available, the lower gate driver 606 may continue to synchronize the internal clock to the upper gate driver 604. The clock signal from the PWM controller 602 may be unavailable due to a fault on the clock signal (e.g., such as a short-circuited high signal or an open-circuited low signal) or a fault of the PWM controller 602 itself. For example, the clock reference sampler 624 may set a "no clock" fault after a threshold time has passed without a change in the clock signal from the PWM controller 602.

[0083] For example, if oscillator calibration is not provided, oscillator frequency variations between the PWM controller 602, the low voltage region 612, the high voltage region 614, and the point of use controller for the upper phase switch 608 may be a major source of uncertainty in the exchange of information between the controllers. The high voltage region 614 of the upper gate driver 604 may not include local non-volatile memory, which may cause large variations in oscillator frequency relative to the low voltage region 612 of the upper gate driver 604 if oscillator calibration is not provided. This difference in oscillator frequency may result in reduced communication reliability or complex communication protocols to overcome the potential uncertainty.

[0084] One or more embodiments may include a clock calibrator 626 that trims the oscillator frequency of the high voltage region 614 of the upper gate driver 604 to the oscillator frequency of the low voltage region 612 of the upper gate driver 604 to a high degree of accuracy. For example, the clock calibrator 626 may also be used to trim the oscillator frequency of a point of use controller (e.g., such as the point of use upper phase A controller 142A) for the upper phase switch 608.

[0085] An initial trimming operation may be performed using a handshake process during initialization of the upper gate driver 604 to ensure that the clock calibrator 626 in the low voltage region 612 and the clock calibrator 626 in the high voltage region 614 are ready to perform trimming operations when needed. Both the clock calibrator 626 in the low voltage region 612 and the clock calibrator 626 in the high voltage region 614 may continuously and independently determine whether a trimming operation should be performed. For example, there may be several mechanisms that can trigger recalibration after the initial calibration is performed at power-up. These mechanisms may include one or more of the following: periodic timeouts, commands from the PWM controller 602, changes in die temperature, integrity check communication failure between the clock calibrator 626 in the low voltage region 612 and the clock calibrator 626 in the high voltage region 614, or a reset and subsequent reinitialization of one or more of the upper gate driver 604 or the lower gate driver 606.

[0086] For an initial trim operation, the clock calibrator 626 in the low voltage region 612 may transmit a waveform on the command bus of the galvanic isolator 616 to the clock calibrator 626 in the high voltage region 614. The waveform may have a predetermined frequency, and the clock calibrator 626 in the high voltage region 614 may implement a successive approximation algorithm to manipulate the oscillator circuit trim input to calibrate the correct oscillator frequency.

[0087] After the initial trimming operation has been performed, subsequent trimming operations may be performed using the message bus of only the electrical isolator 616 using messages transmitted using the communication protocol. For example, the subsequent trimming operation may include a two-message sequence. First, a message may be sent with a header that alerts the high voltage region 614 that a trimming operation is required so that the high voltage region 614 may perform any housekeeping that needs to be performed prior to the trimming operation. Next, the trimming message itself may be sent. The header of the message may indicate the trimming operation, and the message payload may be used by the clock calibrator 626 in the high voltage region 614 to perform the trimming operation. Similar to the initial trimming operation, the message payload may be a waveform with a known period and duration. The message may include three fields: (1) a header field including address and identification information, (2) a payload field whose length is determined by the header field, and (3) a cyclic redundancy check (CRC) field for message integrity checking. Using the message bus of the electrical isolator 616 for subsequent trimming operations may ensure that the oscillator calibration does not interfere with command bus communications that may be occurring during the subsequent trimming operation.

[0088] The low voltage domain clock calibration between the clock calibrator 626 in the low voltage region 612 and the clock calibrator 626 in the high voltage region 614 may include various operations. For example, the clock calibrator 626 in the low voltage region 612 may receive an oscillator trim request via the message bus of the electrical isolator 616. The oscillator trim request received from the clock calibrator 626 in the high voltage region 614 via the message bus of the electrical isolator 616 may be formulated so that the trim request will always win the contention for the message bus and will initiate the oscillator trim process. The clock calibrator 626 in the low voltage region 612 may send an oscillator trim confirmation via the message bus. The oscillator trim request and confirmation may have the same format (width, etc.) and may be formulated so that they always win the contention for the normal priority message bus communication, but may lose the contention for the oscillator trim request from the clock calibrator 626 in the high voltage region 614.

[0089] The clock calibrator 626 in the low voltage region 612 may send an oscillator trim waveform via the command bus. The clock calibrator 626 in the low voltage region 612 may receive an oscillator trim confirmation via the message bus. When the oscillator trim confirmation is not received after a threshold time, the clock calibrator 626 in the low voltage region 612 may resend the oscillator trim waveform via the command bus. When the oscillator trim confirmation is received, the clock calibrator 626 in the low voltage region 612 may enter mission mode operation.

[0090] In mission mode operation, the clock calibrator 626 in the low voltage region 612 may wait for an oscillator trim request and determine whether the clock calibration should be updated. When the clock calibration should be updated, the clock calibrator 626 in the low voltage region 612 may send a clock calibration message via the message bus. The mission mode trim request may be sent via a series of normal priority message bus messages. The header of the first message may notify the clock calibrator 626 in the high voltage region 614 that an oscillator trim message will be sent, followed by subsequent messages, where the header notifies the clock calibrator 626 in the high voltage region 614 that an oscillator trim operation is being performed. The payload of the message may include a plurality of bits that will be used by the clock calibrator 626 in the high voltage region 614 to count clock cycles to determine the oscillator trim value required to synchronize the frequency of the clock calibrator 626 in the high voltage region 614 relative to the clock calibrator 626 in the low voltage region 612.

[0091] In a reset operation, the clock calibrator 626 in the low voltage region 612 may complete the startup configuration and wait for an oscillator trim request. When the post-configuration timeout has elapsed, the clock calibrator 626 in the low voltage region 612 may send an oscillator trim request via the message bus. If the oscillator trim request is not received within a threshold time, the clock calibrator 626 in the low voltage region 612 may resend the oscillator trim request via the message bus. If the oscillator trim request is received, the clock calibrator 626 in the low voltage region 612 may send an oscillator trim confirmation via the message bus and continue the trim operation. As described above, there may be a timeout for some of the operations in the trimming process to ensure that the clock calibrator 626 in the low voltage region 612 does not get stuck. For example, after the device initialization / configuration is completed, if the oscillator trim request is not received within a threshold amount of time, the clock calibrator 626 in the low voltage region 612 may initiate an oscillator trim request.

[0092] The high voltage domain clock calibration between the clock calibrator 626 in the low voltage region 612 and the clock calibrator 626 in the high voltage region 614 may include various operations. For example, in a reset operation, the clock calibrator 626 in the high voltage region 614 may complete the startup configuration and send an oscillator trim request via the message bus. If the oscillator trim request is not received within the threshold time, the clock calibrator 626 in the high voltage region 614 may resend the oscillator trim request via the message bus. If the oscillator trim request is received, the clock calibrator 626 in the low voltage region 612 may trim the oscillator based on the oscillator trim waveform received via the command bus, and send a confirmation on the message bus to confirm the ongoing oscillator trim operation. The clock calibrator 626 in the low voltage region 612 may enter a task mode operation and wait for an oscillator trim message. When an oscillator trim message is received via the message bus, the clock calibrator 626 in the low voltage region 612 may trim the oscillator based on the oscillator trim waveform received via the message bus.

[0093] One or more embodiments may eliminate the need to store oscillator trim values ​​for the high voltage region 614 of the upper gate driver 604 in non-volatile memory of the high voltage region 614 of the upper gate driver 604. In addition, any drift in oscillator frequency due to temperature effects and component drift or aging can be effectively corrected by performing trim operations at device initialization and periodically during operation of the upper gate driver 604. One or more embodiments may eliminate the need for dedicated pins and external components for improving oscillator frequency matching between controllers. By eliminating the need for on-board non-volatile memory for the high voltage region 614 of the upper gate driver 604, one or more embodiments may exhibit cost savings due to associated circuit area savings, test savings, and reduced process complexity. One or more embodiments may be useful for such a system that requires relatively close matching of timing or frequency measurements but does not have robust control of on-board oscillator frequencies between controllers.

[0094] One or more embodiments may include a clock calibrator 626 of the low voltage region 612 that determines an oscillator frequency difference between an oscillator of the low voltage region 612 of the upper gate driver 604 and an oscillator of the high voltage region 614 of the upper gate driver 604 and provides correction to the clock calibrator 626 of the high voltage region 614 via a message bus of the electrical isolator 616.

[0095] One or more embodiments may provide more robust and faster communication between controllers than some solutions by avoiding the need to over-specify the timing of the communication protocol. In addition, as the oscillator of the low voltage region 612 is improved due to an external reference (e.g., such as a clock reference sampler 624 from the PWM controller 602), the timing measurements performed by the peripheral controllers may be improved due to trimming the peripheral oscillator of the high voltage region 614 of the upper gate driver 604 and the point-of-use controller for the upper phase switch 608 to match the low voltage region 612 oscillator. One or more embodiments may allow close matching of clock frequencies between controllers while reducing the cost of the high voltage region 614 of the upper gate driver 604 due to the in-situ performance of the oscillator trimming.

[0096] Due to the clock alignment, the feedback signal from the phase switch on-time detector 618 can be used by the on-time comparator 628 without the error that would occur due to the difference between the clocks in the low voltage region 612 and the high voltage region 614. The clock alignment can further allow the PWM delay trimmer 620 to add delay to the PWM signal 603 on the basis of the individual phase gate drivers so that all phase switches have the same total delay from the PWM input to the phase voltage output. The tester at the end of the manufacturing line can measure the time delay between the state change in the PWM signal and the state change in the phase voltage. Due to the inherent characteristics of the inverter 600, this time delay cannot be reduced. However, for individual components, the time delay can be increased. The PWM delay trimmer 620 can be set for each individual phase gate driver based on the longest delay of any individual phase gate driver so that the final trimmed delay from the PWM edge to the phase edge is the same for all phase gate drivers in the inverter 600. In this way, the transition time between the upper and lower devices is standardized to reduce the possibility of shoot-through. This PWM hold-off trimming can be performed at final end-of-line testing, and clock alignment can ensure that the hold-off trimming remains effective for the life of the inverter 600. Figure 6 As shown, the lower gate driver 606 may include all of the components and functions described herein for the upper gate driver 604 and, therefore, does not include detailed labeling in the figures or description herein.

[0097] The PWM on-time trimming algorithm may require an on-time pulse to be sent to the input of the PWM on-time trimmer 622, such as from the PWM controller 602 in test mode or by the upper gate driver 604 itself. For example, the on-time pulse may be at least 5 μS. When the on-time pulse enters the PWM on-time trimmer 622, the on-time comparator 628 may count the number of system clock pulses in the on-time pulse. The on-time pulse may pass through the PWM on-time trimmer 622 and the PWM delay trimmer 620 without change, and the phase switch on-time detector 618 may count the number of clock pulses for the on-time pulse using one of the above methods. The phase switch on-time detector 618 may send a clock count to the on-time comparator 628, which compares the on-time comparator 628 count with the count received from the phase switch on-time detector 618. The on-time comparator 628 may adjust the setting in the PWM on-time trimmer 622 to match the two clock counts. This process may be repeated, and the expected result may be that the on-time comparator 628 will observe that the phase switch on-time detector 618 has reported the correct value. PWM delay trimming may require the tester to observe a change (increase or decrease) in the PWM signal 603 and observe a change (increase or decrease) in the voltage at the phase connector 610. The delay between these two events may be the total propagation delay of the command signal. The tester may adjust the setting in the PWM delay trimmer 620 to trim the delay to the same value on a part-by-part basis. For example, the delay trim value may be from about 100nS to about 500nS.

[0098] Some methods may include a PWM command signal path from a PWM controller to a half-H switching element, but does not include feedback from the high voltage side to the low voltage side for the purpose of fault feedback. The upper gate driver 604 of the inverter 600 may include adding a phase switching element on-time detector 618 in the high voltage region 614. The upper gate driver 604 may include a path for sending the on-time data of the upper phase switching element 608 from the high voltage region 614 to the on-time comparator 628 in the low voltage region 612. The path may pass through the electrical isolator 616 of the upper gate driver 604. The upper gate driver 604 may include a PWM on-time trimmer 622, which may use the on-time data to de-skew the PWM signal path from the PWM signal 603 to the upper phase switching element 608. The upper gate driver 604 may include a PWM delay trimmer 620 for adjusting the absolute delay of the PWM edges of the PWM signal 603 so that all PWM signal paths within a given design are the same regardless of circuit characteristics. The upper gate driver 604 may include a clock reference sampler 624 that trims the low voltage domain clock to an external precision reference. The upper gate driver 604 may include a low voltage region 612 clock calibrator 626 that communicates with the high voltage region 614 clock calibrator 626 so that both the low voltage and high voltage clocks are aligned to the external reference to ensure that the PWM on-time trimmer 622 and PWM delay trimmer 620 set points are stable over time and accurately set for the individual parallel gate drivers.

[0099] The corresponding PWM on-time trimmer 622 and PWM hold-off trimmer 620 can use a common timing reference for all low-voltage and high-voltage regions of all gate drivers to maintain timing alignment between all inverter gate drivers on a common phase or between adjacent phases. The corresponding phase switch on-time detector 618 in all gate drivers can allow the PWM on-time trimmer 622 to maintain the expected PWM duty cycle at the point of use for the corresponding phase switch.

[0100] One or more embodiments may trim the oscillator frequency of a high voltage controller to the oscillator frequency of a low voltage controller to a high accuracy. One or more embodiments may trim the oscillator frequency of a point-of-use controller. One or more embodiments may include an isolated gate driver having a low voltage (LV) PWM signal domain and a high voltage (HV) phase domain. One or more embodiments may include a transceiver that allows communication between the LV and HV domains. One or more embodiments may include a clock reference sampler for sampling the LV domain and aligning the LV domain with an external quartz clock reference, and may have an error of less than one percent. One or more embodiments may include a clock calibrator for aligning the HV domain clock with the LV domain clock so that all timing is synchronized. One or more embodiments may synchronize all voltage domains of a phase switching device to an absolute clock reference with an error of less than one percent.

[0101] One or more embodiments may eliminate the need to store oscillator trim values ​​for controllers in non-volatile memory. One or more embodiments may correct any drift in oscillator frequency due to temperature effects and component drift or aging by performing trim operations at controller initialization and periodically during operation. One or more embodiments may eliminate the need for dedicated pins and external components for improving oscillator frequency matching between controllers. By eliminating the need for onboard non-volatile memory for controllers, one or more embodiments may save costs due to reduced component count, testing, and process complexity. One or more embodiments may provide more robust and faster communication between controllers due to simplified communication protocols. One or more embodiments may use an external oscillator reference to improve low voltage controller oscillators. One or more embodiments may improve timing measurements performed by peripheral controllers (such as high voltage controllers and point of use controllers), for example, by trimming the oscillator of the peripheral controller to match the oscillator of the low voltage controller. One or more embodiments may provide close matching of clock frequencies between controllers and save costs due to performing oscillator trimming locally in the controller.

[0102] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: an electrical isolator that separates a high voltage region from a low voltage region; a low voltage phase controller, the low voltage phase controller being in the low voltage region, the low voltage phase controller being configured to receive a clock reference signal; and A high voltage phase controller is provided in the high voltage region, the high voltage phase controller being configured to align a clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller. 2 . The system of claim 1 , wherein the low voltage phase controller comprises a clock reference sampler configured to align the clock reference signal of the low voltage phase controller with a clock reference signal of an inverter controller.

3. The system of claim 1 , wherein the low voltage phase controller comprises a clock reference sampler configured to align the clock reference signal of the low voltage phase controller with the clock reference signal of the inverter controller when the clock reference signal of the inverter controller is available, and to align the clock reference signal of the low voltage phase controller with the clock reference signal of another low voltage phase controller when the clock reference signal of the inverter controller is not available.

4. The system according to claim 1, wherein the inverter further includes a use-point phase controller, wherein the use-point phase controller is in the high voltage region, and the use-point phase controller is configured to align a clock reference signal of the use-point phase controller with the clock reference signal of the high voltage phase controller.

5. The system of claim 1 , wherein the low voltage phase controller comprises a clock reference sampler configured to align the clock reference signal of the low voltage phase controller with the master clock reference signal by counting a number of system clock pulses in one or more cycles of the master clock reference signal and comparing the counted number with an expected value. 6 . The system of claim 5 , wherein the low voltage phase controller comprises a clock calibrator configured to increase or decrease a period of an internal oscillator of the low voltage phase controller to align the counted number with the expected value.

7. The system of claim 1 , wherein the high voltage phase controller comprises a clock reference sampler configured to align the clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller by counting a number of system clock pulses in one or more cycles of the clock reference signal of the low voltage phase controller and comparing the counted number with an expected value.

8. The system of claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

9. A system comprising: A power module, the power module is for an inverter for an electric vehicle, the power module comprising: a power switch, the power switch comprising a drain terminal, a source terminal and a gate terminal; a gate driver configured to provide a signal to the gate terminal to control the operation of the power switch; and A use point phase controller is configured to align a clock reference signal of the use point phase controller with a clock reference signal of a high voltage phase controller and control the gate driver based on the clock reference signal of the use point phase controller.

10. The system of claim 9, wherein the use point phase controller is configured to align the clock reference signal of the use point phase controller with the clock reference signal of the high voltage phase controller by counting the number of system clock pulses in one or more cycles of the clock reference signal of the high voltage phase controller and comparing the counted number with an expected value.

11. The system of claim 10, wherein the point-of-use phase controller is further configured to increase or decrease a period of an internal oscillator of the point-of-use phase controller to align the counted number with the expected value.

12. The system of claim 11, wherein the use-point phase controller is further configured to iteratively perform the alignment of the oscillator of the use-point phase controller with the clock reference signal of the high voltage phase controller such that continuous counting of the number of system clock pulses aligns the oscillator of the use-point phase controller with the clock reference signal of the high voltage phase controller.

13. The system of claim 9, wherein the point-of-use controller is configured to align the clock reference signal of the point-of-use phase controller with the clock reference signal of the high voltage phase controller using a command bus for initial alignment after initialization of the point-of-use controller and using a message bus for subsequent alignment after the initial alignment.

14. The system of claim 9, wherein the clock reference signal of the high voltage phase controller has a frequency from about 100 Hz to about 10 kHz.

15. A system comprising: A first controller, wherein the first controller is configured to: Receive a clock reference signal from a main controller; aligning an oscillator of the first controller with the clock reference signal of the master controller; as well as A reference signal is provided to a second controller based on a clock reference signal of the aligned oscillator of the first controller.

16. The system of claim 15, wherein the first controller is further configured to count the number of system clock pulses in one or more cycles of the clock reference signal of the master controller and compare the counted number with an expected value to align the oscillator of the first controller with the clock reference signal of the master controller.

17. The system of claim 16, wherein the first controller is further configured to increase or decrease a period of the oscillator of the first controller to align the counted number with the expected value to align the oscillator of the first controller with the clock reference signal of the master controller.

18. The system of claim 17, wherein the first controller is further configured to iteratively perform the alignment of the oscillator of the first controller with the clock reference signal of the master controller such that consecutive counting of the number of system clock pulses aligns the oscillator of the first controller with the clock reference signal of the master controller.

19. The system of claim 15, wherein the first controller is configured to provide the reference signal to the second controller when the oscillator of the first controller is aligned with the clock reference signal of the master controller.

20. The system of claim 19, wherein the reference signal to the second controller is a defined number of clock pulses of the oscillator of the first controller for a defined period of time.

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