Switch structure and preparation method thereof, and radio frequency chip

Abstract

The invention provides a switch structure and a preparation method thereof, and a radio frequency chip. The switch structure comprises a glass substrate; at least one switch sub-circuit located on the glass substrate, wherein the switch sub-circuit comprises at least one switch unit; the switch unit comprises transistors, resistors and power supply equipment, grid electrodes of the transistors are electrically connected with the resistors, the resistors are electrically connected with the power supply equipment, a first pole of at least one transistor is electrically connected with the input conductive pad, and a second pole of at least one transistor is electrically connected with the output conductive pad; the silicon material layer is bonded with the glass substrate, the silicon material layer comprises a conductive region, a part of the conductive region is configured to be electrically connected with the grid electrode of the transistor and the resistor, and the ion doping concentration of the conductive region is greater than or equal to 1 * 1018 cm <-3 >. The switch structure is good in performance and low in cost.

Description

Switch structure and preparation method thereof, and radio frequency chip

[0001] The present application relates to the field of switch technology, and in particular to a switch structure and a preparation method thereof, and a radio frequency chip.

[0002] The RF switch can connect any one or more of the multiple RF signals through control logic to achieve switching of different model paths, including switching between reception and transmission, switching between different frequency bands, etc., so as to achieve the purpose of sharing antennas and saving terminal product costs.

[0003] At present, the commonly used RF switch technology is RF SOI (Radio Frequency Silicon On Insulator). RF switch products using SOG (Silicon On Glass) technology are rarely seen.

[0004] Summary of the invention

[0005] The embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a switch structure, including:

[0007] Glass substrate;

[0008] At least one switch subcircuit located on the glass substrate, the switch subcircuit comprising at least one switch unit; the switch unit comprising a transistor and a resistor, the gate of the transistor being electrically connected to the resistor, the resistor being electrically connected to a power supply device, a first electrode of at least one of the transistors being electrically connected to an input conductive pad, and a second electrode of at least one of the transistors being electrically connected to an output conductive pad;

[0009] A silicon material layer located on the glass substrate and bonded to the glass substrate, the silicon material layer comprising a conductive region, a portion of the conductive region being configured to electrically connect the gate of the transistor and the resistor, wherein the ion doping concentration of the conductive region is greater than or equal to 1×10 18 cm -3 .

[0010] In at least one embodiment of the present application, at least one of the first electrode of the transistor, the second electrode of the transistor, and the gate of the transistor includes an interdigital structure.

[0011] In at least one embodiment of the present application, the first electrode of the transistor, the second electrode of the transistor and the gate of the transistor all include the interdigitated structure, and the gate of the transistor partially overlaps with the orthographic projection of one of the first electrode of the transistor and the second electrode of the transistor on the glass substrate.

[0012] In at least one embodiment of the present application, the first electrode of the transistor and the second electrode of the transistor both include the interdigitated structure, and the gate of the transistor includes a serpentine structure;

[0013] The orthographic projection of the gate of the transistor on the glass substrate is located between the orthographic projection of the first pole of the transistor on the glass substrate and the orthographic projection of the second pole of the transistor on the glass substrate, and the orthographic projection of the gate of the transistor and the first pole of the transistor and the second pole of the transistor on the glass substrate do not overlap with each other.

[0014] In at least one embodiment of the present application, a channel width-to-length ratio of the transistor is greater than or equal to 5000.

[0015] In at least one embodiment of the present application, the silicon material layer includes a single crystal silicon sublayer.

[0016] In at least one embodiment of the present application, the silicon material layer includes a single crystal silicon sublayer and an amorphous silicon sublayer sequentially disposed on the glass substrate; the thickness of the amorphous silicon sublayer is less than the thickness of the single crystal silicon sublayer.

[0017] In at least one embodiment of the present application, the switch subcircuit includes one input conductive pad and one output conductive pad.

[0018] In at least one embodiment of the present application, the switch subcircuit includes a first switch unit, the first switch unit includes a first transistor and a first resistor, and the power supply device includes a first power supply device;

[0019] The first electrode of the first transistor is electrically connected to the input conductive pad, the second electrode of the first transistor is electrically connected to the output conductive pad, the gate of the first transistor is electrically connected to the first end of the first resistor, and the first power supply device is electrically connected to the ground terminal and the second end of the first resistor, respectively.

[0020] In at least one embodiment of the present application, the switch subcircuit includes a second switch unit and a third switch unit; the second switch unit includes a second transistor and a second resistor, and the third switch unit includes a third transistor and a third resistor; the power supply device includes a second power supply device and a third power supply device;

[0021] The first electrode of the second transistor and the first electrode of the third transistor are both electrically connected to the input conductive pad, the second electrode of the second transistor is electrically connected to the output conductive pad, the gate of the second transistor is electrically connected to the first end of the second resistor, and the second power supply device is electrically connected to the ground terminal and the second end of the second resistor respectively;

[0022] The gate of the third transistor is electrically connected to the first end of the third resistor, the third power supply device is electrically connected to the ground terminal and the second end of the third resistor respectively, and the second electrode of the third transistor is electrically connected to the ground terminal.

[0023] In at least one embodiment of the present application, the switch subcircuit includes a fourth switch unit, a fifth switch unit, a sixth switch unit, and a seventh switch unit;

[0024] The fourth switch unit includes a fourth transistor and a fourth resistor, the fifth switch unit includes a fifth transistor and a fifth resistor; the sixth switch unit includes a sixth transistor and a sixth resistor, the seventh switch unit includes a seventh transistor and a seventh resistor; the power supply device includes a fifth power supply device and a sixth power supply device;

[0025] The fourth switch unit and the sixth switch unit share the sixth power supply device, and the fifth switch unit and the seventh switch unit share the fifth power supply device.

[0026] In at least one embodiment of the present application, the switch subcircuit includes one input conductive pad and two output conductive pads.

[0027] In at least one embodiment of the present application, the switch subcircuit includes two input conductive pads and one output conductive pad.

[0028] In at least one embodiment of the present application, the first electrodes of the fourth transistor and the fifth transistor are both electrically connected to the first output conductive pad, the second electrode of the fourth transistor is electrically connected to the ground terminal, the second electrode of the fifth transistor is electrically connected to the input conductive pad, the gate of the fourth transistor is electrically connected to the first end of the fourth resistor, and the gate of the fifth transistor is electrically connected to the first end of the fifth resistor;

[0029] The first electrodes of the sixth transistor and the seventh transistor are both electrically connected to the second output conductive pad, the second electrode of the sixth transistor is electrically connected to the input conductive pad, the second electrode of the seventh transistor is electrically connected to the ground terminal, the gate of the sixth transistor is electrically connected to the first end of the sixth resistor, and the gate of the seventh transistor is electrically connected to the first end of the seventh resistor.

[0030] In at least one embodiment of the present application, the second end of the fourth resistor and the second end of the sixth resistor are both electrically connected to the sixth power supply device, and the second end of the fifth resistor and the second end of the seventh resistor are both electrically connected to the fifth power supply device.

[0031] In at least one embodiment of the present application, the switch structure includes a plurality of switch sub-circuits arranged in an array on the glass substrate.

[0032] In at least one embodiment of the present application, the transistor includes a plurality of sub-transistors arranged in series, and the gate of each of the sub-transistors is connected to one of the resistors; and the first pole of the sub-transistor and the second pole of the transistor both include a forked finger structure, and the gate of the transistor includes a serpentine structure.

[0033] In at least one embodiment of the present application, the switch structure includes:

[0034] The silicon material layer includes a first semiconductor pattern and a second semiconductor pattern;

[0035] a gate insulating layer, wherein the gate insulating layer covers the silicon material layer;

[0036] A gate layer, the gate layer is located on a side of the gate insulating layer away from the glass substrate, and includes a gate of the transistor;

[0037] an interlayer dielectric layer, wherein the interlayer dielectric layer covers the gate layer;

[0038] A source-drain conductive layer, the source-drain conductive layer is located on a side of the interlayer dielectric layer away from the glass substrate, and includes a first electrode and a second electrode of the transistor;

[0039] The first semiconductor pattern and the second semiconductor pattern both include a semiconductor region and the conductive regions located on both sides of the semiconductor region; a first electrode of the transistor is electrically connected to one of the conductive regions in the first semiconductor pattern, and a second electrode of the transistor is electrically connected to another of the conductive regions in the first semiconductor pattern; the semiconductor region in the first semiconductor pattern serves as a channel region of the transistor, and the semiconductor region in the second semiconductor pattern serves as the resistor.

[0040] In at least one embodiment of the present application, the source-drain conductive layer further includes a first routing line, a second routing line, and a third routing line, and the first routing line is electrically connected to one of the second routing line and the third routing line;

[0041] The first routing line is electrically connected to a gate of the transistor, the second routing line is electrically connected to one of the conductive regions in the second semiconductor pattern, and the third routing line is electrically connected to another of the conductive regions in the second semiconductor pattern.

[0042] In at least one embodiment of the present application, for at least one of the transistors, the first electrode of the transistor includes an interdigitated structure;

[0043] The first electrode of the transistor includes a first connecting portion and N-2 first extending portions arranged in the same row, the extending direction of the first connecting portion intersects with the extending direction of the first extending portions, and the arrangement direction of the first extending portions is the same as the extending direction of the first connecting portion; the first connecting portion is located on the same side of each of the first extending portions and connects each of the first extending portions together; N is a positive integer and is greater than or equal to 4;

[0044] The orthographic projections of the first extension portions on the glass substrate at least partially overlap with the orthographic projections of the first semiconductor pattern on the glass substrate.

[0045] In at least one embodiment of the present application, for at least one transistor, the second electrode of the transistor includes an interdigitated structure;

[0046] The second electrode of the transistor includes a second connecting portion and N-3 second extending portions arranged in the same row, the extending direction of the second connecting portion is the same as the extending direction of the first connecting portion, and the arrangement direction of the second extending portions is the same as the arrangement direction of the first extending portions; the second connecting portion is located on the same side of each of the second extending portions and connects each of the second extending portions together;

[0047] The orthographic projections of the second extension portions on the glass substrate at least partially overlap with the orthographic projections of the first semiconductor pattern on the glass substrate.

[0048] In at least one embodiment of the present application, for at least one transistor, a gate of the transistor includes an interdigitated structure;

[0049] The gate of the transistor includes a third connection portion and N third extension portions arranged in the same row, the extension directions of the third connection portion and the third extension portions intersect, the third connection portion is located on the same side of each of the third extension portions, and connects each of the third extension portions together; the orthographic projection of each of the third extension portions on the glass substrate overlaps at least partially with the orthographic projection of the first semiconductor pattern on the glass substrate; the third connection portion overlaps partially with the orthographic projections of all the second extension portions on the glass substrate;

[0050] Wherein, along the extending direction of the third connecting portion, the orthographic projections of the first extending portion, the third extending portion and the second extending portion on the glass substrate are alternately arranged in sequence.

[0051] In at least one embodiment of the present application, for at least one transistor, a gate of the transistor includes a serpentine structure;

[0052] The gate of the transistor has a first bending portion and a second bending portion that are alternately arranged, and the gate of the transistor also has a first opening portion and a second opening portion that are alternately arranged, so that the gate of the transistor has the serpentine structure, the outer contour of the first opening portion is arranged on the first bending portion, the outer contour of the second opening portion is arranged on the second bending portion, and the opening directions of the first opening portion and the second opening portion are opposite;

[0053] The outer contour of the first opening and the outer contour of the second opening both include a combination of a plurality of straight line segments, a combination of a straight line segment and an arc, or an arc.

[0054] In at least one embodiment of the present application, the outer contour of the side of the first bending portion where the first opening portion is not provided and the outer contour of the side of the second bending portion where the second opening portion is not provided both include a combination of multiple straight line segments, a combination of straight line segments and arcs, or arcs.

[0055] In at least one embodiment of the present application, the source-drain conductive layer further includes a coplanar waveguide, the input conductive pad, the output conductive pad and at least one power supply conductive pad, the number of the power supply conductive pad and the power supply device is the same and the two are electrically connected in a one-to-one correspondence, the coplanar waveguide includes a first part and a second part, and there is a gap between the first part and the second part of the coplanar waveguide; the input conductive pad and the output conductive pad are located in the gap;

[0056] The orthographic projections of the transistor, the resistor, the input conductive pad, the output conductive pad and the power supply conductive pad on the glass substrate do not overlap with the orthographic projections of the coplanar waveguide on the glass substrate; the coplanar waveguide is electrically connected to the ground terminal.

[0057] In at least one embodiment of the present application, when the switch subcircuit includes a first switch unit, the first portion of the coplanar waveguide includes a first hollow region, and the second portion of the coplanar waveguide includes a second hollow region;

[0058] A partial area of ​​the first semiconductor pattern of the first transistor and a partial area of ​​the first pole of the first transistor extend to the first hollow area; a partial area of ​​the first semiconductor pattern, a partial area of ​​the first pole of the first transistor, the first resistor, the power supply conductive pad, the first routing, the second routing and the third routing are all located in the second hollow area.

[0059] In at least one embodiment of the present application, when the switch subcircuit includes a second switch unit and a third switch unit, the first portion of the coplanar waveguide includes a third hollow area, the second portion of the coplanar waveguide includes a fourth hollow area and a fifth hollow area, and the fourth hollow area is connected to the fifth hollow area;

[0060] A partial area of ​​the first semiconductor pattern of the second transistor and a partial area of ​​the first electrode of the second transistor extend to the third hollow area; the third transistor, the third resistor, and the power supply conductive pad electrically connected to the third power supply device are all located in the fourth hollow area; the second resistor and the power supply conductive pad electrically connected to the second power supply device are all located in the fifth hollow area.

[0061] In at least one embodiment of the present application, when the switch subcircuit includes a fourth switch unit, a fifth switch unit, a sixth switch unit, and a seventh switch unit, the first portion of the coplanar waveguide includes a sixth hollow area and a seventh hollow area, the second portion of the coplanar waveguide includes an eighth hollow area and a ninth hollow area, the sixth hollow area is connected to the seventh hollow area, and the eighth hollow area is connected to the ninth hollow area;

[0062] A main body portion of the fifth transistor and a main body portion of the sixth transistor are located in the gap;

[0063] The fourth transistor and the fourth resistor are located in the eighth hollow area; a partial area of ​​the first semiconductor pattern of the fifth transistor, a partial area of ​​the first pole of the fifth transistor, the fifth resistor, and the power supply conductive pad electrically connected to the fifth power supply device are located in the sixth hollow area; a partial area of ​​the first semiconductor pattern of the sixth transistor and a partial area of ​​the first pole of the sixth transistor are located in the seventh hollow area; a partial area of ​​the first semiconductor pattern of the sixth transistor, a partial area of ​​the first pole of the sixth transistor, the sixth resistor, and the power supply conductive pad electrically connected to the sixth power supply device are located in the ninth hollow area; the main body of the seventh transistor and the seventh resistor are located in the seventh hollow area.

[0064] In a second aspect, an embodiment of the present application provides a radio frequency chip, comprising a switch structure as described in any one of the first aspects.

[0065] In a third aspect, an embodiment of the present application provides a method for preparing a switch structure, which is applied to prepare the switch structure as described in any one of the first aspects, and the method comprises:

[0066] providing a glass substrate;

[0067] bonding a single crystal silicon thin film on the glass substrate;

[0068] Performing patterning on the single crystal silicon thin film to obtain a first semiconductor pattern and a second semiconductor pattern;

[0069] Ion implantation is performed on a local area of ​​the first semiconductor pattern and a local area of ​​the second semiconductor pattern respectively, and the first semiconductor pattern and the second semiconductor pattern are annealed at a preset temperature so that the first semiconductor pattern and the second semiconductor pattern respectively include a conductive area; the ion implantation dose range of the conductive area is 3×10 15 cm -3 ~9×10 15 cm -3 The ion doping concentration of the conductive region is greater than or equal to 1×10 18 cm -3 , the preset temperature is less than 650°C.

[0070] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below.

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments or descriptions of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0072] FIG1 is a line graph showing the change in resistivity of a single crystal silicon film bonded to a glass substrate as the ion implantation dose changes, provided in an embodiment of the present application;

[0073] FIG2 is a line graph showing the change in impurity concentration of a single crystal silicon film bonded to a glass substrate as the ion implantation dose changes, provided in an embodiment of the present application;

[0074] FIG3 , FIG11 and FIG12 are schematic diagrams of circuit structures of three switch sub-circuits provided in embodiments of the present application;

[0075] FIG4 is a schematic diagram of a planar structure of the circuit structure shown in FIG3 ;

[0076] 5, 6 and 7 are schematic diagrams of planar structures of three transistors provided in embodiments of the present application;

[0077] 8 and 10 are schematic diagrams of planar structures of gates of two transistors provided in embodiments of the present application;

[0078] FIG9 is a schematic cross-sectional view of a switch structure provided in an embodiment of the present application;

[0079] FIG13 is a schematic diagram of a planar structure of the circuit structure shown in FIG11;

[0080] FIG14 is a schematic diagram of a planar structure of two sub-transistors arranged in parallel;

[0081] FIG15 is a schematic diagram of a planar structure of the circuit structure shown in FIG12;

[0082] FIG16 is another schematic diagram of a planar structure of the circuit structure shown in FIG3 ;

[0083] 17A-17L are schematic diagrams of intermediate structures during the preparation process of the switch structure provided in an embodiment of the present application.

[0084] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0085] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0086] In the embodiments of the present application, the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0087] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to indicate that a specific feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0088] In the embodiments of the present application, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly and specifically defined.

[0089] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present application include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances related to the measurement of specific quantities (e.g., the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0090] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0091] The "same layer" in the embodiments of the present application refers to the relationship between multiple film layers formed by the same material after the same step (e.g., a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. The polygons in this specification are not strictly defined, and can be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and there may be some small deformations caused by tolerances.

[0092] RF switches can connect any one or more of the multiple RF signals through control logic to achieve the switching of different model paths, including the switching between reception and transmission, and the switching between different frequency bands, so as to achieve the purpose of sharing antennas and saving terminal product costs. At present, the commonly used RF switch technology is RF SOI (Radio Frequency Silicon On Insulator). RF switch products using SOG (Silicon On Glass) technology are rarely seen.

[0093] Based on this, the present application proposes a switch structure of SOG technology, which can realize low-cost preparation of the switch structure, and SOG has better insulation performance than SOI, which can reduce the leakage of RF signals. In addition, in order to realize the impurity activation of single crystal silicon after ion implantation, since the heat resistance temperature of high-temperature glass is about 650°C, the existing high-temperature annealing process of 1000°C cannot be realized. Therefore, the present application also proposes a low-temperature process to realize the doping and impurity activation of single crystal silicon, so as to complete the production of the switch structure based on SOG technology.

[0094] The embodiments of the present application provide a switch structure and a preparation method thereof, and a radio frequency chip, wherein the switch structure includes a glass substrate; at least one switch subcircuit located on the glass substrate, the switch subcircuit includes at least one switch unit; the switch unit includes a transistor, a resistor, and a power supply device, the gate of the transistor is electrically connected to the resistor, the resistor is electrically connected to the power supply device, the first electrode of at least one transistor is electrically connected to an input conductive pad, and the second electrode of at least one transistor is electrically connected to an output conductive pad; a silicon material layer located on the glass substrate and bonded to the glass substrate, the silicon material layer includes a conductive region, a portion of the conductive region is configured to electrically connect the gate of the transistor and the resistor, wherein the ion doping concentration of the conductive region is greater than or equal to 1×10 18 cm -3 The switch structure provided by the embodiment of the present application is provided by directly setting a silicon material layer on a glass substrate, and the ion doping concentration in a local area of ​​the silicon material layer is greater than or equal to 1×10 18 cm -3 ; In this way, in the actual preparation process, after the silicon material layer is annealed by a low-temperature process, the impurities can be activated and the local area of ​​the silicon material layer can be conductive; in addition, by directly bonding the silicon material layer to the glass substrate, compared with the switch structure of SOI technology, the leakage of RF signals can be greatly reduced, thereby improving the signal transmission stability of the switch structure.

[0095] The switch structure and its preparation method, and the radio frequency chip provided in the embodiments of the present application will be specifically introduced and explained below in conjunction with the accompanying drawings.

[0096] An embodiment of the present application provides a switch structure, as shown in FIG. 3 , FIG. 11 , FIG. 12 and FIG. 9 , the switch structure includes:

[0097] A glass substrate 100;

[0098] at least one switch subcircuit located on the glass substrate 100 (FIG. 3, FIG. 11 and FIG. 12 respectively show three switch subcircuits), the switch subcircuit comprising at least one switch unit (e.g., the first switch unit DY1 shown in FIG. 3, the second switch unit DY2 and the third switch unit DY3 shown in FIG. 11, the fourth switch unit DY4, the fifth switch unit DY5, the sixth switch unit DY6 and the seventh switch unit DY7 shown in FIG. 12);

[0099] Taking the switch subcircuit shown in FIG3 as an example, the switch unit includes a transistor (such as MOS1), a resistor (such as R1) and a power supply device (not drawn), the gate Gate of the transistor is electrically connected to the resistor (such as R1), the resistor (such as R1) is electrically connected to the power supply device, the first electrode of at least one transistor is electrically connected to the input conductive pad In (In pad), and the second electrode of at least one transistor is electrically connected to the output conductive pad Out (Out pad);

[0100] As shown in FIG9 , the switch structure further includes a silicon material layer 1 located on the glass substrate 100 and bonded to the glass substrate 100. The silicon material layer 1 includes a conductive region, such as a region marked A2. Part of the conductive region is configured to electrically connect the gate of the transistor and the resistor. The ion doping concentration of the conductive region is greater than or equal to 1×10 18 cm -3 .

[0101] Exemplarily, the switch structure may include a radio frequency switch.

[0102] Among them, the glass substrate 100 has a better resistivity than other plastic or resin insulating substrates, so when it is used in a radio frequency switch, it can reduce the leakage of radio frequency signals and improve the transmission stability of signals.

[0103] There is no limitation on the number of switch sub-circuits provided on the glass substrate 100 .

[0104] In some examples, a switch subcircuit may be disposed on the glass substrate 100 .

[0105] In some examples, a plurality of switch sub-circuits may be disposed on the glass substrate 100 , where a plurality refers to two or more.

[0106] For example, a plurality of switch sub-circuits arranged in an array may be disposed on the glass substrate 100 .

[0107] Among them, each switch subcircuit includes at least one switch unit. For the same switch structure, each switch subcircuit includes the same number of switch units. Among them, the number of switch units included in a switch subcircuit is related to the design of the switch subcircuit and is not limited here.

[0108] In the embodiment of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. One of the "first electrode" and the "second electrode" of the above transistor is the source, and the other is the drain.

[0109] Exemplarily, the transistor is a MOS tube which is a metal oxide semiconductor field effect transistor.

[0110] Exemplarily, the power supply device (eg, a battery) may be built into the switch subcircuit, or the power supply device may be an external power supply.

[0111] There is no limitation on the type of the power supply device mentioned above.

[0112] In some examples, the power supply device may be a direct current (DC) power supply device.

[0113] In some examples, the power supply device may be an alternating current (AC) power supply device.

[0114] It should be noted that in the relevant circuit diagrams provided in the embodiments of the present application, the power supply device is marked and drawn as a direct current power supply (Direct Current) as an example. In addition, in the planar structure diagram of the switch structure provided in the embodiments of the present application, the power supply device is not drawn, and only the conductive pad (or conductive terminal) electrically connected to the power supply device is drawn, such as the structure marked as DC pad in FIG.

[0115] In an exemplary embodiment, the glass substrate 100 and the silicon material layer 1 are bonded together using a bonding process.

[0116] For example, since glass is mainly composed of silicon dioxide (SiO2, i.e. quartz, the main component of sand), and the melting point of pure silica is 2000°C, sodium carbonate (Na2CO3, i.e. soda) and potassium carbonate (Potash, K2CO3, potash) are generally added when making glass, so that the melting point of silica will drop to about 1000°C.

[0117] In the actual bonding process, by applying a negative voltage to the glass substrate 100 and a positive voltage to the silicon material layer 1, under the preset temperature and pressure, the atoms near the interface between the glass substrate 100 and the silicon material layer 1 migrate to each other and move to each other's film layer, thereby achieving the bonding of the glass substrate 100 and the silicon material layer 1. Among them, the voltage difference between the voltage applied to the glass substrate 100 and the silicon material layer 1 is approximately 200V, and the preset temperature is 200℃~400℃. Among them, the specific details of the bonding can refer to the bonding process introduction in the relevant technology, which will not be repeated here.

[0118] In an exemplary embodiment, the main component of the silicon material layer 1 may be single crystal silicon.

[0119] Exemplarily, when the main component of the silicon material layer 1 is single crystal silicon, before the ion implantation process and the annealing process, the initial resistivity of the silicon material layer 1 is 10±2Ω·cm.

[0120] In the embodiment of the present application, the silicon material layer 1 includes a conductive region, wherein the impurities may be activated by a low-temperature annealing process after ion doping, thereby achieving conductiveness of a local region of the silicon material layer 1 .

[0121] In conventional SOI processes, in order to achieve complete activation of single crystal silicon after ion implantation, the annealing temperature often reaches 1000°C. However, since the heat resistance temperature of high-temperature glass is approximately 650°C, conventional annealing temperatures cannot be used, so a low-temperature annealing process must be found.

[0122] FIG1 provides a line graph of the resistivity and impurity concentration of a silicon material layer 1 with an initial resistivity of 10Ω·cm and a main component of single crystal silicon after different doses of phosphorus ions are implanted and annealed at 600°C for 1h. It can be seen from FIG1 that when the implantation dose of phosphorus ions is 3×10 15 cm -2 When the resistivity is less than 0.001Ω·cm, it can be seen from Figure 2 that the phosphorus ion impurity concentration is greater than 1×10 18 cm -3 , which can achieve heavy doping of silicon and meet the ohmic contact requirements between metal and semiconductor.

[0123] For example, in practical applications, the concentration of phosphorus ion impurities can be set to be greater than 1×10 20 cm -3 .

[0124] Ohmic contact means that there is a pure resistance between metal and semiconductor at the contact point, and the smaller the resistance, the better, so that when the device is in operation, most of the voltage drop is in the active area rather than on the contact surface. Therefore, its IV characteristic is a linear relationship, the larger the slope, the smaller the contact resistance, and the size of the contact resistance directly affects the performance indicators of the device.

[0125] In the embodiment of the present application, the ion implantation dose range of the silicon material layer 1 with an initial resistivity of 10Ω·cm and a main component of single crystal silicon is 3×10 15 cm -3 ~9×10 15 cm -3 .

[0126] It should be noted that the conductorization process is related to the solid phase epitaxial growth process. + ) The ion implantation dose is greater than or equal to 6×10 14 cm -2When the single crystal silicon film layer is annealed, the surface of the single crystal silicon film layer becomes amorphous silicon. The single crystal silicon under the amorphous silicon can be used as a seed crystal for the amorphous silicon to crystallize again. During the annealing process, the amorphous silicon on the surface crystallizes again and grows into single crystal silicon. <100> In the direction of the crystal plane, the rate of recrystallization growth is 10nm / min at a temperature of 550°C and 50nm / min at a temperature of 600°C. In this process, the doping atoms are combined with the main atoms into the lattice position, so that the doping atoms are activated at a relatively low temperature.

[0127] Among them, solid phase epitaxy refers to the process of epitaxial recrystallization of the amorphous layer on a semiconductor single crystal at a temperature lower than the melting point or eutectic point of the material.

[0128] The switch structure provided by the embodiment of the present application is formed by directly disposing a silicon material layer 1 on the glass substrate 100, and the ion doping concentration in the local area of ​​the silicon material layer 1 is greater than or equal to 1×10 18 cm -3 ; In this way, in the actual preparation process, after annealing the silicon material layer 1 using a low-temperature process, the impurities can be activated and the local area of ​​the silicon material layer 1 can be conductorized; in addition, by directly bonding the silicon material layer 1 to the glass substrate 100, compared with the switch structure of SOI technology, the leakage of RF signals can be greatly reduced, thereby improving the signal transmission stability of the switch structure.

[0129] In at least one embodiment of the present application, at least one of the first electrode of the transistor, the second electrode of the transistor, and the gate of the transistor includes an interdigital structure.

[0130] Exemplarily, the first electrode of the transistor includes an interdigital structure;

[0131] Exemplarily, the second electrode of the transistor includes an interdigitated structure;

[0132] Exemplarily, the gate of the transistor includes an interdigital structure;

[0133] Exemplarily, the first electrode, the second electrode and the gate of the transistor all include an interdigitated structure.

[0134] The number of interdigits in the interdigital structure is not limited here, and can be determined based on the planar size of the interdigits and the performance requirements of the transistor.

[0135] In at least one embodiment of the present application, as shown in Figure 5, the first electrode of the transistor (for example, the source S), the second electrode of the transistor (for example, the drain D) and the gate Gate of the transistor all include a forked finger structure, and the gate Gate of the transistor partially overlaps with the positive projection of the first electrode of the transistor and one of the second electrode of the transistor on the glass substrate 100.

[0136] Exemplarily, the first electrode of the transistor is the source S, and the second electrode is the drain D; or, the first electrode of the transistor is the drain D, and the second electrode is the source S.

[0137] Exemplarily, since the first electrode of the transistor (e.g., source S), the second electrode of the transistor (e.g., drain D), and the gate Gate of the transistor all include a forked-finger structure, inevitably, as shown in the area marked by the dotted circle in FIG. 5 , the gate Gate of the transistor overlaps with the orthographic projection of one of the first electrode of the transistor and the second electrode of the transistor on the glass substrate 100, wherein the smaller the area of ​​the overlapping region, the smaller the parasitic capacitance between the gate Gate of the transistor and the source (or drain), the better the electrical properties of the transistor, and the more stable the control of the signal.

[0138] In some examples, as shown in FIG5 , the width of the fingers in the area marked by the dotted circle can be set smaller than the width of the fingers in the area outside the dotted circle, thereby reducing the overlapping area between the gate Gate and the source (or drain) of the transistor, improving the electrical properties of the transistor, and improving the stability of the transistor.

[0139] Exemplarily, the width of the gate Gate of the transistor located in the area marked by the dotted circle may be set to be smaller than the width in the area outside the dotted circle.

[0140] Exemplarily, the width of the drain D of the transistor located in the area marked by the dotted circle may be set to be smaller than the width in the area outside the dotted circle.

[0141] In at least one embodiment of the present application, as shown in FIG. 6 or FIG. 7 , the first electrode (eg, source electrode S) of the transistor and the second electrode (eg, drain electrode D) of the transistor both include an interdigitated structure, and the gate Gate of the transistor includes a serpentine structure;

[0142] The orthographic projection of the gate Gate of the transistor on the glass substrate 100 is located between the orthographic projection of the first electrode (for example, the source S) of the transistor on the glass substrate 100 and the orthographic projection of the second electrode (for example, the drain D) of the transistor on the glass substrate 100, and the gate Gate of the transistor does not overlap with the orthographic projections of the first electrode (for example, the source S) of the transistor and the second electrode (for example, the drain D) of the transistor on the glass substrate 1.

[0143] In an embodiment of the present application, as shown in FIG. 6 or 7, by setting the gate Gate of the transistor to include a serpentine structure, the switching ratio of the transistor can be increased. In addition, the gate Gate of the transistor and the positive projections of the first electrode (for example, the source S) and the second electrode (for example, the drain D) of the transistor on the glass substrate 1 do not overlap with each other, which can reduce the parasitic capacitance between the gate Gate and the source S (or the drain D), thereby improving the performance of the switching device.

[0144] The on-off ratio refers to the ratio between the on state and the off state of a switch in a circuit. In circuit design, the on-off ratio is a very important parameter that directly affects the performance and stability of the circuit. In a circuit, the on-off ratio is usually used to describe the ratio between the on time and the off time of a switch tube.

[0145] In at least one embodiment of the present application, a channel width-to-length ratio of the transistor is greater than or equal to 5000.

[0146] In practical applications, the on-resistance of a single transistor can be calculated by the following formula:

[0147] Where μ is the carrier mobility, C ox It is the capacitance between the gate of the transistor and the conductive area in the silicon material layer 1. Its size is related to the thickness of the gate insulating layer. V GS is the gate-source voltage, V th is the threshold voltage of the transistor, W is the channel width of the transistor, and L is the channel length of the transistor.

[0148] Since the transistor (MOS tube) needs a smaller on-resistance R when it is turned on on Therefore, a larger channel width-to-length ratio is required. By setting W / L>5000 and setting the channel width range of the transistor (MOS tube) used in the switch structure to 0.1mm~10mm, the normal use of the switch structure can be achieved.

[0149] It should be noted that, for the transistor shown in FIG. 5 or FIG. 6 , compared with a transistor of a conventional design, its channel width W can be significantly increased.

[0150] Where, ΔW = (n-1)·S gate ;

[0151] As shown in Figures 5 and 6, n is the fork index of the gate Gate, Sgate is the distance h between the two forks of the gate; taking the structure shown in Figure 5 as an example, n is 6; taking the structure shown in Figure 6 as an example, n is 6; wherein, for the gate of the serpentine structure as shown in Figure 6, its fork index n refers to the number of line segments extending in the horizontal direction in the serpentine gate Gate.

[0152] In addition, for the gate of the serpentine structure as shown in FIG6 , since there is no overlap between the gate Gate and the source S (or the drain D), the magnitude of the parasitic capacitance of the transistor that can be reduced is as follows:

[0153] Among them, ε ILDis the dielectric constant of the interlayer dielectric layer (the insulating layer between the gate Gate and the source S), W SD is the width of the source and drain electrodes, W gate is the width of the gate electrode, d ILD is the thickness of the interlayer dielectric layer.

[0154] It should be noted that the conductorization process mentioned above is related to the solid phase epitaxial growth process. + ) The ion implantation dose is greater than or equal to 6×10 14 cm -2 During the annealing process, the surface of the single crystal silicon film layer becomes amorphous silicon. The single crystal silicon under the amorphous silicon can serve as a seed crystal for the amorphous silicon to crystallize again. During the annealing process, the amorphous silicon on the surface crystallizes again and grows into single crystal silicon.

[0155] In at least one embodiment of the present application, the surface of the single crystal silicon film layer becomes amorphous silicon, and the amorphous silicon can be completely crystallized again, so that the silicon material layer 1 includes a single crystal silicon sublayer.

[0156] In at least one embodiment of the present application, the surface of the single crystal silicon film layer becomes amorphous silicon, and the amorphous silicon can crystallize again, but there is still a small amount of amorphous silicon on the surface. At this time, the silicon material layer 1 includes a single crystal silicon sublayer and an amorphous silicon sublayer arranged in sequence on the glass substrate 100; the thickness of the amorphous silicon sublayer is less than the thickness of the single crystal silicon sublayer.

[0157] The specific structure of the switch subcircuit is introduced and explained below.

[0158] In at least one embodiment of the present application, as shown in combination with FIG. 3 and FIG. 4 , the switch sub-circuit includes an input conductive pad In pad and an output conductive pad Out pad.

[0159] Among them, an input conductive pad In pad corresponds to an input port, and an output conductive pad Out pad corresponds to an output port.

[0160] In at least one embodiment of the present application, as shown in FIG3 , the switch subcircuit includes a first switch unit DY1 , the first switch unit DY1 includes a first transistor MOS1 , a first resistor R1 , and the power supply device includes a first power supply device DC1 ;

[0161] A first electrode (e.g., source electrode S) of the first transistor MOS1 is electrically connected to an input conductive pad In pad, a second electrode (e.g., drain electrode D) of the first transistor MOS1 is electrically connected to an output conductive pad Out pad, a gate Gate of the first transistor MOS1 is electrically connected to a first end of a first resistor R1, and a first power supply device DC1 is electrically connected to a ground terminal GND and a second end of the first resistor R1, respectively.

[0162] Wherein, FIG3 shows a switch structure of a single-pole single-throw structure. When the first transistor MOS1 is turned on, the switch subcircuit is equivalent to a resistor with an extremely low resistance value. At this time, the RF signal can be transmitted through the switch subcircuit; when the first transistor MOS1 is turned off, the switch subcircuit is equivalent to a capacitor, thereby preventing the passage of the RF signal and realizing the cutoff of the switch structure. Wherein, the gate Gate of the first transistor MOS1 is connected to the first resistor R1, which can effectively prevent the breakdown between the gate Gate and the drain D or the gate Gate and the source S caused by the excessive peak-to-peak value of the RF signal on the source and drain.

[0163] The resistance value of the first resistor R1 ranges from 10 kΩ to 100 kΩ. For example, the resistance value of the first resistor R1 is 20 kΩ, 30 kΩ, 40 kΩ, 50 kΩ, 60 kΩ, 70 kΩ, 80 kΩ, or 90 kΩ.

[0164] In at least one embodiment of the present application, as shown in FIG11 , the switch subcircuit includes a second switch unit DY2 and a third switch unit DY3; the second switch unit DY2 includes a second transistor MOS2 and a second resistor R2, the third switch unit DY3 includes a third transistor MOS3 and a third resistor R3, and the power supply device includes a second power supply device DC2 and a third power supply device DC3;

[0165] The first electrode (e.g., source electrode S) of the second transistor MOS2 and the first electrode (e.g., source electrode S) of the third transistor MOS3 are both electrically connected to the input conductive pad In pad, the second electrode (e.g., drain electrode D) of the second transistor MOS2 is electrically connected to the output conductive pad Out pad, the gate Gate of the second transistor MOS2 is electrically connected to the first end of the second resistor R2, and the second power supply device DC2 is electrically connected to the ground terminal GND and the second end of the second resistor R2 respectively;

[0166] The gate Gate of the third transistor MOS is electrically connected to the first end of the third resistor R3, the third power supply device DC3 is electrically connected to the ground terminal GND and the second end of the third resistor R3 respectively, and the second electrode (for example, the drain D) of the third transistor MOS3 is electrically connected to the ground terminal GND.

[0167] Exemplarily, the resistance range of the second resistor R2 and the third resistor R3 are both 10 kΩ to 100 kΩ.

[0168] Here, it is not limited whether the structures, sizes and electrical parameters of the second transistor MOS2 and the third transistor MOS3 are the same;

[0169] Exemplarily, when the second transistor MOS2 and the third transistor MOS3 have the same structure, size and electrical parameters, the second resistor R2 and the third resistor R3 have the same resistance value, and the second power supply device DC2 and the third power supply device DC3 provide the same power supply voltage.

[0170] Based on the switch structure of the single-pole single-throw structure shown in Figure 3, a series branch can be added to improve the isolation of the switch structure. The isolation is the attenuation between the input port and the output port of the circuit, which is an indicator to measure the effectiveness of the switch cutoff.

[0171] Among them, Figure 11 provides a circuit structure of a switch structure of a single-pole single-throw series-parallel structure; wherein the second switch unit DY2 is a series branch, and the third switch unit DY3 is a parallel branch, and each branch includes a resistor electrically connected to the gate of the transistor. When a positive voltage is applied to the gate Gate of the second transistor MOS2 in the series branch, a negative voltage is applied to the gate Gate of the third transistor MOS3 in the parallel branch, the series branch is turned on, and the parallel branch is disconnected. At this time, the RF signal is output through the series branch, and the switch is in an open state; when a negative voltage is applied to the gate Gate of the second transistor MOS2 in the series branch, a positive voltage is applied to the gate Gate of the third transistor MOS3 in the parallel branch, the series branch is disconnected, and the parallel branch is turned on. At this time, the RF signal flows into the ground terminal GND through the parallel branch, and the switch is in a closed state. Relative to the switch structure mentioned in Figure 3, the switch structure shown in Figure 11 adds a grounded parallel branch when the switch is closed, thereby improving the isolation of the switch structure.

[0172] In at least one embodiment of the present application, as shown in FIG12 , the switch subcircuit includes a fourth switch unit DY4 , a fifth switch unit DY5 , a sixth switch unit DY6 , and a seventh switch unit DY7 ;

[0173] The fourth switch unit DY4 includes a fourth transistor MOS4 and a fourth resistor R4, the fifth switch unit DY5 includes a fifth transistor MOS5 and a fifth resistor R5; the sixth switch unit DY6 includes a sixth transistor MOS6 and a sixth resistor R6, the seventh switch unit DY7 includes a seventh transistor MOS7 and a seventh resistor R7; the power supply device includes a fifth power supply device DC5 and a sixth power supply device DC6;

[0174] The fourth switch unit DY4 and the sixth switch unit DY6 share the sixth power supply device DC6 , and the fifth switch unit DY5 and the seventh switch unit DY7 share the fifth power supply device DC5 .

[0175] In at least one embodiment of the present application, as shown in FIG. 12 , the switch subcircuit includes an input conductive pad In pad and two output conductive pads Out pads, wherein one input conductive pad In pad corresponds to one input port, and two output conductive pads Out pads correspond to two output ports.

[0176] In at least one embodiment of the present application, the switch subcircuit includes two input conductive pads Inpad and one output conductive pad Out pad, the two input conductive pads In pad correspond to two input ports, and the one output conductive pad Out pad corresponds to one output port.

[0177] In at least one embodiment of the present application, as shown in FIG12 , the first electrodes (e.g., source electrodes S) of the fourth transistor MOS4 and the fifth transistor MOS5 are both electrically connected to the first output conductive pad Out pad (a conductive pad electrically connected to the output port on the left side in FIG12 ), the second electrode (e.g., drain electrode D) of the fourth transistor MOS4 is electrically connected to the ground terminal GND, the second electrode (e.g., drain electrode D) of the fifth transistor MOS5 is electrically connected to the input conductive pad In pad, the gate Gate of the fourth transistor MOS4 is electrically connected to the first end of the fourth resistor R4, and the gate Gate of the fifth transistor MOS5 is electrically connected to the first end of the fifth resistor R5;

[0178] The first electrodes (e.g., source electrodes S) of the sixth transistor MOS6 and the seventh transistor MOS7 are both electrically connected to the second output conductive pad Out pad (a conductive pad electrically connected to the output port on the right side of FIG. 12 ), the second electrode (e.g., drain electrode D) of the sixth transistor MOS6 is electrically connected to the input conductive pad In pad, the second electrode (e.g., drain electrode D) of the seventh transistor MOS7 is electrically connected to the ground terminal GND, the gate Gate of the sixth transistor MOS6 is electrically connected to the first end of the sixth resistor R6, and the gate Gate of the seventh transistor MOS7 is electrically connected to the first end of the seventh resistor R7.

[0179] In at least one embodiment of the present application, as shown in Figure 12, the second end of the fourth resistor R4 and the second end of the sixth resistor R6 are both electrically connected to the sixth power supply device DC6, and the second end of the fifth resistor R5 and the second end of the seventh resistor D7 are both electrically connected to the fifth power supply device DC5.

[0180] FIG12 provides a circuit structure of a single-pole double-throw switch structure, which may have two channels, namely channel L1 on the left side of the dotted line and channel L2 on the right side of the dotted line in FIG12 , wherein each channel includes a series branch and a parallel branch.

[0181] Among them, the series branch in the channel L1 is the fifth switch unit DY5, and the parallel branch is the fourth switch unit DY4; the series branch in the channel L2 is the sixth switch unit DY6, and the parallel branch is the seventh switch unit DY7. The fifth switch unit DY5 in the series branch in the channel L1 and the seventh switch unit DY7 in the parallel branch in the channel L2 share a DC power supply (i.e., the gate Gate of the fifth transistor MOS5 and the gate Gate of the seventh transistor MOS7 are connected to the same DC power supply), and the fourth switch unit DY4 in the parallel branch in the channel L1 and the sixth switch unit DY6 in the series branch in the channel L2 share a DC power supply (i.e., the gate Gate of the fourth transistor MOS4 and the gate Gate of the sixth transistor MOS6 are connected to the same DC power supply). When the same positive voltage is applied to the gate Gate of the fifth transistor MOS5 and the gate Gate of the seventh transistor MOS7, and the same negative voltage is applied to the gate Gate of the fourth transistor MOS4 and the gate Gate of the sixth transistor MOS6, channel L1 is turned on and channel L2 is turned off, and the RF signal leaked from the output port of channel L1 (such as the output port Out on the left side in Figure 12) to the input port of channel L2 is short-circuited to the ground terminal GND through the parallel branch in channel L2, which significantly improves the isolation between the ports.

[0182] In at least one embodiment of the present application, the switch structure includes a plurality of switch sub-circuits arranged in an array on a glass substrate 100, thereby enabling large-area integration of switch devices, expanding the application field of the switch structure, improving its application flexibility, and reducing the preparation cost of the switch structure.

[0183] In at least one embodiment of the present application, as shown in FIG14 , the transistor includes a plurality of sub-transistors arranged in series ( FIG14 is drawn with two sub-transistors arranged in series as an example), and as shown in FIG16 , the gate Gate of each sub-transistor is connected to a resistor R; and the first electrode of the sub-transistor (for example, the source electrode S) and the second electrode of the transistor (for example, the drain electrode D) both include a forked finger structure, and the gate Gate of the transistor includes a serpentine structure.

[0184] 16 is a schematic diagram of a planar structure in which the first transistor MOS1 in the switch sub-circuit shown in FIG3 includes four sub-transistors.

[0185] In practical applications, the operating voltage and breakdown voltage of a single MOS tube are relatively low and may not meet the index requirements. By connecting multiple low-voltage devices in series, the power handling capacity of the switch structure is improved to ensure that the switch structure can withstand sufficiently high-power signals. The more sub-transistors are set in series, the smaller the voltage actually applied to each MOS tube.

[0186] In at least one embodiment of the present application, as shown in FIG9 , the switch structure includes:

[0187] A silicon material layer 1, wherein the silicon material layer 1 includes a first semiconductor pattern 11 (AL) and a second semiconductor pattern 12;

[0188] A gate insulating layer 2, the gate insulating layer 2 covers the silicon material layer 1;

[0189] The gate layer 3 is located on a side of the gate insulating layer 2 away from the glass substrate 100 and includes a gate Gate of the transistor;

[0190] An interlayer dielectric layer 4, the interlayer dielectric layer 4 covers the gate layer 3;

[0191] A source-drain conductive layer 5, which is located on a side of the interlayer dielectric layer 4 away from the glass substrate 100, and includes a first electrode (eg, source electrode S) and a second electrode (eg, drain electrode D) of the transistor;

[0192] Among them, the first semiconductor pattern 11 (AL) and the second semiconductor pattern 12 both include a semiconductor region A1 and conductive regions A2 located on both sides of the semiconductor region A1, a first electrode (e.g., source S) of the transistor is electrically connected to one conductive region A2 in the first semiconductor pattern 11 (AL), and a second electrode (e.g., drain D) of the transistor is electrically connected to another conductive region A2 in the first semiconductor pattern 11 (AL); the semiconductor region A1 in the first semiconductor pattern 11 (AL) serves as a channel region of the transistor, and the semiconductor region A1 in the second semiconductor pattern 12 serves as a resistor.

[0193] Exemplarily, the main component of the silicon material layer 1 is single crystal silicon; in some examples, the silicon material layer 1 includes single crystal silicon at the bottom layer and amorphous silicon at the surface layer; in addition, the silicon material layer 1 also includes doping elements, such as phosphorus atoms or boron atoms.

[0194] In an exemplary embodiment, the single crystal silicon in the silicon material layer 1 is mainly P-type silicon. In this case, the doping element in the conductive region A2 in the first semiconductor pattern 11 (AL) is phosphorus atoms.

[0195] It should be noted that, in this specification, the transistor (MOS tube) is taken as an N-type MOS for example.

[0196] In an exemplary embodiment, the doping elements in the conductive region A2 in the second semiconductor pattern 12 may be phosphorus atoms or boron atoms.

[0197] In an exemplary embodiment, the material of the gate insulating layer 2 may be an inorganic material, for example, silicon nitride (SiNx), silicon oxide (SiO2), or silicon oxynitride (SiNxOy).

[0198] In an exemplary embodiment, the material of the gate layer 3 may be metal, for example, a combination of one or more of copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0199] In an exemplary embodiment, the material of the interlayer dielectric layer (ILD) may be an organic material, such as resin.

[0200] In an exemplary embodiment, the material of the interlayer dielectric layer (ILD) may be an inorganic material, for example, silicon nitride (SiNx), silicon oxide (SiO2), or silicon oxynitride (SiNxOy).

[0201] In at least one embodiment of the present application, the source-drain conductive layer 5 further includes a first wiring Z1, a second wiring Z2 and a third wiring Z3, and the first wiring Z1 is electrically connected to one of the second wiring Z2 and the third wiring Z3;

[0202] The first wiring Z1 is electrically connected to the gate Gate of the transistor, the second wiring Z2 is electrically connected to a conductive area A2 in the second semiconductor pattern 12 , and the third wiring Z3 is electrically connected to another conductive area A2 in the second semiconductor pattern 12 .

[0203] The second routing Z2 and a conductive area A2 in the second semiconductor pattern 12 are electrically connected to serve as the input end of the resistor; the third routing Z3 and another conductive area A2 in the second semiconductor pattern 12 are electrically connected to serve as the output end of the resistor; or, the second routing Z2 and a conductive area A2 in the second semiconductor pattern 12 are electrically connected to serve as the output end of the resistor; the third routing Z3 and another conductive area A2 in the second semiconductor pattern 12 are electrically connected to serve as the input end of the resistor, so that one end of the resistor is electrically connected to the gate Gate of the transistor, and the other end of the resistor is electrically connected to the power supply device.

[0204] In at least one embodiment of the present application, as shown in FIG. 5 or FIG. 6 , for at least one transistor, the first electrode (e.g., source S) of the transistor includes an interdigitated structure; the first electrode (e.g., source S) of the transistor includes a first connecting portion S2 and N-2 first extension portions S1 arranged in the same row, the extension direction of the first connecting portion S2 intersects with the extension direction of the first extension portion S1, and the arrangement direction of the first extension portion S1 is the same as the extension direction of the first connecting portion S2; the first connecting portion is located on the same side of each first extension portion and connects each first extension portion S1 together; N is a positive integer and is greater than or equal to 4;

[0205] The orthographic projections of the first extension portions S1 on the glass substrate 100 at least partially overlap with the orthographic projections of the first semiconductor patterns 11 (AL) (regions marked Si in FIG. 5 or 6 ) on the glass substrate.

[0206] Here, "at least partially overlapped" includes partial overlap and complete overlap. The meaning of the related descriptions in the following text is similar to that here and will not be repeated here.

[0207] In an exemplary embodiment, one of the conductive areas A2 in the first semiconductor pattern 11 (AL) may be electrically connected to at least one first extension S1 in the first electrode of the transistor through a via.

[0208] In some examples, in order to reduce the contact resistance, two vias can be provided to electrically connect one of the conductive regions A2 in the first semiconductor pattern 11 (AL) and the first extension portion S1 in the first pole (e.g., the source S) of the transistor, for example, one of the vias electrically connects one first extension portion S1, and the other via electrically connects the other first extension portion S1.

[0209] The shape of the plane figure of the first extension portion S1 is not limited here. For example, the shape of the plane figure of the first extension portion S1 may include two relatively parallel sides, so that the distance between any two points on two adjacent first extension portions S1 along the extension direction of the first connection portion S2 is equal. That is, the two sides on the two adjacent first extension portions S1 that are close to each other are arranged in parallel.

[0210] The length and width of the first extension portion S1 are not limited here, wherein the length refers to the dimension of the first extension portion S1 along its extension direction, and the width refers to the dimension of the first extension portion S1 along the extension direction of the first connection portion S2.

[0211] In an exemplary embodiment, the line widths (Width) of the first extension portion S1 and the first connection portion S2 may be set to be substantially equal.

[0212] In some embodiments, an orthographic projection of the first semiconductor pattern 11 (AL) on the glass substrate 100 and an orthographic projection of the first connection portion S2 on the glass substrate 100 may be arranged to partially overlap.

[0213] In an exemplary embodiment, the first electrodes (eg, sources S) of all transistors in the switch structure may include an interdigital structure.

[0214] In at least one embodiment of the present application, as shown in FIG. 5 or FIG. 6 , for at least one transistor, the second electrode (e.g., drain) of the transistor includes an interdigital structure; the second electrode (e.g., drain) of the transistor includes a second connection portion D2 and N-3 second extension portions D1 arranged in the same row, the extension direction of the second connection portion D2 is the same as the extension direction of the first connection portion S2, and the arrangement direction of the second extension portions D1 is the same as the arrangement direction of the first extension portions S1; the second connection portion D2 is located on the same side of each second extension portion D1 and connects each second extension portion D1 together;

[0215] The orthographic projections of the second extension portions D1 on the glass substrate 100 at least partially overlap with the orthographic projections of the first semiconductor pattern 11 (AL) (regions marked Si in FIG. 5 or 6 ) on the glass substrate 100 .

[0216] In some embodiments, the lengths and line widths of the first extension portion S1 and the second extension portion D1 may be substantially equal.

[0217] In an exemplary embodiment, one of the conductive areas A2 in the first semiconductor pattern 11 (AL) may be electrically connected to at least one second extension D1 in the second electrode of the transistor through a via.

[0218] In some examples, in order to reduce the contact resistance, two vias can be provided to electrically connect one of the conductive regions A2 in the first semiconductor pattern 11 (AL) and the second extension portion D1 in the second electrode (e.g., the drain D) of the transistor, for example, one of the vias electrically connects one second extension portion D1, and the other via electrically connects the other second extension portion D1.

[0219] In an exemplary embodiment, the line widths (Width) of the second extension portion D1 and the second connection portion D2 may be set to be substantially equal.

[0220] In some embodiments, an orthographic projection of the first semiconductor pattern 11 (AL) on the glass substrate 100 and an orthographic projection of the second connection portion D2 on the glass substrate 100 may be arranged to partially overlap.

[0221] In an exemplary embodiment, the second electrodes (eg, drain electrodes D) of all transistors in the switch structure may include an interdigital structure.

[0222] In at least one embodiment of the present application, as shown in FIG5 , for at least one transistor, a gate Gate of the transistor includes an interdigitated structure;

[0223] The gate Gate of the transistor includes a third connection portion G2 and N third extension portions G1 arranged in the same row. The extension directions of the third connection portion G2 and the third extension portion G1 intersect. The third connection portion G2 is located on the same side of each third extension portion G1 and connects each third extension portion G1 together. The orthographic projections of each third extension portion G1 on the glass substrate 100 overlap with the orthographic projections of the first semiconductor pattern 11 (AL) on the glass substrate 100. Taking the area marked by the dotted circle in FIG. 5 as an example, the orthographic projections of the third connection portion G2 and all the second extension portions D1 on the glass substrate 100 overlap.

[0224] Wherein, along the extending direction of the third connecting portion G2 , the orthographic projections of the first extending portion S1 , the third extending portion G1 , and the second extending portion D1 on the glass substrate 100 are alternately arranged in sequence.

[0225] In an exemplary embodiment, the length of the third extension portion G1 is less than the lengths of the first extension portion S1 and the second extension portion D1.

[0226] In an exemplary embodiment, in order to simplify the design and reduce the difficulty of the manufacturing process, the line widths of the first extension portion S1 , the third extension portion G1 , and the second extension portion D1 may be set to be substantially equal.

[0227] Among them, in the plane figure shown in Figure 5, any third extension portion G1 is located between the first extension portion S1 and the second extension portion D1. In order to improve the electrical properties of the transistor and ensure that the voltage of the gate Gate is the same as the magnitude of the lateral parasitic capacitance generated between the first electrode (for example, the source electrode S) and the second electrode (for example, the drain electrode D), it can be arranged in a plane parallel to the glass substrate 100. The distance between the third extension portion G1 and the adjacent first extension portion S1 is approximately equal to the distance between the third extension portion G1 and the adjacent second extension portion D1, that is, the third extension portion G1 is located in the middle between the first extension portion S1 and the second extension portion D1.

[0228] In addition, in some embodiments, as shown in Figure 5, a partial area of ​​the third connection portion G2 (for example, as shown in the area marked by the rectangular dotted box in Figure 5) is located between the first extension portion S1 and the second connection portion D2. For this partial area of ​​the third connection portion G2, along the extension direction of the first extension portion S1, the distance between this partial area of ​​the third connection portion G2 of the gate Gate and the first extension portion S1 and the distance between this partial area of ​​the third connection portion G2 and the second connection portion D2 can be set to be approximately equal.

[0229] In at least one embodiment of the present application, in order to reduce the parasitic capacitance between the gate Gate and the source S (or drain D) of the transistor, for at least one transistor, as shown in FIGS. 6 and 7 , the gate Gate of the transistor includes a serpentine structure;

[0230] Exemplarily, as shown in FIG8 or FIG10, the gate Gate of the transistor has a first bending portion W1 and a second bending portion W2 that are alternately arranged, and the gate Gate of the transistor also has a first opening portion K1 and a second opening portion K2 that are alternately arranged, so that the gate Gate of the transistor has a serpentine structure, the outer contour of the first opening portion K1 is arranged on the first bending portion W1, the outer contour of the second opening portion K2 is arranged on the second bending portion W2, and the opening directions of the first opening portion K1 and the second opening portion K2 are opposite;

[0231] Among them, the orthographic projection of the gate Gate of the transistor on the glass substrate 100 does not overlap with the orthographic projection of the first electrode (for example, the source S) of the transistor on the glass substrate 100, and the orthographic projection of the gate Gate of the transistor on the glass substrate 100 does not overlap with the orthographic projection of the second electrode (for example, the drain D) of the transistor on the glass substrate 100.

[0232] In addition, as shown in FIG. 8 or FIG. 10 , the outer contour of the first opening portion K1 and the outer contour of the second opening portion K2 both include a combination of a plurality of straight line segments, a combination of a straight line segment and an arc, or an arc.

[0233] Exemplarily, as shown in FIG. 8 , the outer contour of the first opening portion K1 and the outer contour of the second opening portion K2 both include a combination of multiple straight line segments. For example, the outer contour of the first opening portion K1 and the outer contour of the second opening portion K2 both include a right-angle structure.

[0234] Exemplarily, as shown in FIG. 10 , the outer contour of the first opening portion K1 and the outer contour of the second opening portion K2 both include a combination of straight line segments and arcs. For example, the outer contour of the first opening portion K1 and the outer contour of the second opening portion K2 both include rounded corner structures.

[0235] Exemplarily, the outer contour of the first opening portion K1 and the outer contour of the second opening portion K2 both include arcs. For example, the outer contour of the serpentine structure is entirely arcs.

[0236] In some examples, at least one of the interdigital structures of the first electrode (eg, source S) and the second electrode (eg, drain D) of the transistor may include a rounded structure.

[0237] In at least one embodiment of the present application, in combination with Figure 8 or 10, the outer contour of the side of the first bending portion W1 where the first opening portion K1 is not set and the outer contour of the side of the second bending portion W2 where the second opening portion K2 is not set both include a combination of multiple straight line segments, a combination of straight line segments and arcs, or arcs.

[0238] Exemplarily, as shown in Figure 8, the outer contour of the side of the first bending portion W1 where the first opening portion K1 is not set and the outer contour of the side of the second bending portion W2 where the second opening portion K2 is not set both include a combination of multiple straight line segments. For example, the outer contour of the side of the first bending portion W1 where the first opening portion K1 is not set and the outer contour of the side of the second bending portion W2 where the second opening portion K2 is not set both include right-angle structures.

[0239] Exemplarily, as shown in Figure 10, the outer contour of the side of the first bending portion W1 where the first opening portion K1 is not set and the outer contour of the side of the second bending portion W2 where the second opening portion K2 is not set both include a combination of straight line segments and arcs. For example, the outer contour of the side of the first bending portion W1 where the first opening portion K1 is not set and the outer contour of the side of the second bending portion W2 where the second opening portion K2 is not set both include rounded corner structures.

[0240] Exemplarily, the outer contour of the side of the first bending portion W1 where the first opening portion K1 is not provided and the outer contour of the side of the second bending portion W2 where the second opening portion K2 is not provided both include arcs. For example, the outer contour of the serpentine structure is entirely arcs.

[0241] In at least one embodiment of the present application, as shown in FIGS. 4 , 13 and 15 , the source-drain conductive layer SD further includes a coplanar waveguide CPW (including CPW-1 and CPW-2), an input conductive pad In pad, an output conductive pad Out pad and at least one power conductive pad DC pad, the number of the power conductive pad DC pad and the power supply device (not drawn) are the same and the two are electrically connected one-to-one, the coplanar waveguide includes a first part CPW-1 and a second part CPW-2, and a gap is provided between the first part CPW-1 and the second part CPW-2 of the coplanar waveguide; the input conductive pad In pad and the output conductive pad Out pad are located in the gap;

[0242] As shown in FIGS. 4 , 13 and 15 , the orthographic projections of all transistors, resistors, input conductive pads In pads, output conductive pads Out pads and power supply conductive pads DC pads on the glass substrate 100 do not overlap with the orthographic projections of the coplanar waveguide CPW (including CPW-1 and CPW-2) on the glass substrate 100; the coplanar waveguide CPW (including CPW-1 and CPW-2) is electrically connected to the ground terminal GND.

[0243] Among them, an input conductive pad In pad corresponds to an input port In, and an output conductive pad Out pad corresponds to an output port Out.

[0244] There is no limitation on the size and planar shape of the gap between the first part CPW-1 and the second part CPW-2 of the coplanar waveguide, which can be determined according to the design space.

[0245] In some examples, as shown in FIG. 4 , at least a portion of the transistor is also located in the gap between the first portion CPW- 1 and the second portion CPW- 2 of the coplanar waveguide.

[0246] In at least one embodiment of the present application, as shown in FIG. 4 , when the switch subcircuit includes a first switch unit DY1 , the first portion CPW- 1 of the coplanar waveguide includes a first hollow region LK1 , and the second portion CPW- 2 of the coplanar waveguide includes a second hollow region LK2 ;

[0247] Part of the first semiconductor pattern 11 (AL) of the first transistor MOS1 (the area where the pattern marked Si in FIG. 4 is located) and part of the first electrode (for example, the source S) of the first transistor MOS1 extend to the first hollow area LK1; part of the first semiconductor pattern 11 (AL) (the area where the pattern marked Si in FIG. 4 is located), part of the first electrode (for example, the source S) of the first transistor MOS1, the first resistor R1, the power supply conductive pad DC pad, the first routing Z1, the second routing Z2 and the third routing Z3 are all located in the second hollow area LK2.

[0248] In some examples, as shown in FIG. 4 , a portion of the second electrode (eg, the drain D) of the first transistor MOS1 extends to the first hollow region LK1 .

[0249] In some examples, as shown in FIG. 4 , a portion of the second electrode (eg, the drain D) of the first transistor MOS1 extends to the second hollow region LK2 .

[0250] The shapes and sizes of the plane figures of the first hollow area LK1 and the second hollow area LK2 are not limited here.

[0251] Exemplarily, as shown in FIG. 4 , the plane shape of the first hollow area LK1 is a rectangle.

[0252] Exemplarily, as shown in FIG. 4 , the plane shape of the second hollow area LK2 is a spliced ​​shape formed by two rectangles.

[0253] In at least one embodiment of the present application, when the switching sub-circuit includes a second switching unit DY2 and a third switching unit DY3, as shown in Figure 13, the first part CPW-1 of the coplanar waveguide includes a third hollow area LK3, and the second part CPW-2 of the coplanar waveguide includes a fourth hollow area LK4 and a fifth hollow area LK5, and the fourth hollow area LK4 and the fifth hollow area LK5 are connected; a partial area of ​​the first semiconductor pattern 11 (AL) of the second transistor MOS2 and a partial area of ​​the first pole (for example, the source S) of the second transistor MOS2 extend to the third hollow area LK3; the third transistor MOS3, the third resistor R3, and the power supply conductive pad DC pad electrically connected to the third power supply device DC3 are all located in the fourth hollow area LK4; the second resistor R2, and the power supply conductive pad DC pad electrically connected to the second power supply device DC2 are all located in the fifth hollow area LK5.

[0254] In an exemplary embodiment, as shown in FIG. 13 , a portion of the second electrode (eg, drain D) of the second transistor MOS2 and a portion of the gate Gate of the second transistor MOS2 extend to the third hollow region LK3 .

[0255] In an exemplary embodiment, as shown in FIG. 13 , the second transistor MOS2 extends from the third hollow region LK3 , to a gap between the first portion CPW- 1 of the coplanar waveguide and the second portion CPW- 2 of the coplanar waveguide, and further to the fifth hollow region LK5 .

[0256] In an exemplary embodiment, the coplanar waveguide is grounded. As shown in FIG. 13 , a second electrode (eg, drain D) of the third transistor MOS3 is electrically connected to the ground terminal GND through the second portion CPW- 2 of the coplanar waveguide.

[0257] In at least one embodiment of the present application, when the switch sub-circuit includes a fourth switch unit DY4, a fifth switch unit DY5, a sixth switch unit DY6 and a seventh switch unit DY7, as shown in FIG15, the first part CPW-1 of the coplanar waveguide includes a sixth hollow area LK6 and a seventh hollow area LK7, the second part CPW-2 of the coplanar waveguide includes an eighth hollow area LK8 and a ninth hollow area LK9, the sixth hollow area LK6 is connected to the seventh hollow area LK7, and the eighth hollow area LK8 is connected to the ninth hollow area LK9; the main part of the fifth transistor MOS5 and the main part of the sixth transistor MOS6 are located in the gap;

[0258] The fourth transistor MOS4 and the fourth resistor R4 are located in the eighth hollow area LK8;

[0259] Part of the first semiconductor pattern 11 (AL) of the fifth transistor MOS5, part of the first electrode (eg, source S) of the fifth transistor MOS5, the fifth resistor R5, and the power supply conductive pad DC pad electrically connected to the fifth power supply device DC5 are located in the sixth hollow area LK6;

[0260] A partial area of ​​the first semiconductor pattern 11 (AL) of the sixth transistor MOS6 and a partial area of ​​the first electrode (for example, the source electrode S) of the sixth transistor MOS6 are located in the seventh hollow area LK7; a partial area of ​​the first semiconductor pattern 11 (AL) of the sixth transistor MOS6, a partial area of ​​the first electrode (for example, the source electrode S) of the sixth transistor MOS6, a sixth resistor R6, and a power supply conductive pad DC pad electrically connected to the sixth power supply device DC6 are located in the ninth hollow area LK9;

[0261] The main part of the seventh transistor MOS7 and the seventh resistor R7 are located in the seventh hollow area LK7.

[0262] In an exemplary embodiment, as shown in Figure 15, a partial area of ​​the first semiconductor pattern 11 (AL) of the fifth transistor MOS5, a partial area of ​​the first electrode (for example, the source S) of the fifth transistor MOS5, and a partial area of ​​the second electrode (for example, the drain D) of the fifth transistor MOS5 are located in the sixth hollow area LK6; a partial area of ​​the first semiconductor pattern 11 (AL) of the fifth transistor MOS5, a partial area of ​​the first electrode (for example, the source S) of the fifth transistor MOS5, and a partial area of ​​the second electrode (for example, the drain D) of the fifth transistor MOS5 are located in the eighth hollow area LK8.

[0263] In an exemplary embodiment, as shown in Figure 15, a partial area of ​​the first semiconductor pattern 11 (AL) of the sixth transistor MOS6, a partial area of ​​the first electrode (for example, the source S) of the sixth transistor MOS6, and a partial area of ​​the second electrode (for example, the drain D) of the sixth transistor MOS6 are located in the seventh hollow area LK7; a partial area of ​​the first semiconductor pattern 11 (AL) of the sixth transistor MOS6, a partial area of ​​the first electrode (for example, the source S) of the sixth transistor MOS6, and a partial area of ​​the second electrode (for example, the drain D) of the sixth transistor MOS6 are located in the ninth hollow area LK9.

[0264] In an exemplary embodiment, the coplanar waveguide is grounded. As shown in FIG15 , the second electrode (e.g., the drain D) of the fourth transistor MOS4 is electrically connected to the ground terminal GND through the second portion CPW-2 of the coplanar waveguide, and the second electrode (e.g., the drain D) of the seventh transistor MOS7 is electrically connected to the first portion CPW-1 of the coplanar waveguide and the ground terminal GND.

[0265] The shape and size of the plane figure formed by the outer contours of the sixth hollow area LK6, the seventh hollow area LK7, the eighth hollow area LK8 and the ninth hollow area LK9 are not limited here, and are specifically determined according to the device arrangement design in the switch sub-circuit.

[0266] An embodiment of the present application provides a radio frequency chip, comprising the switch structure as described in any one of the foregoing.

[0267] The radio frequency chip provided in the embodiment of the present application is provided by directly setting a silicon material layer 1 on a glass substrate 100, and the ion doping concentration in a local area of ​​the silicon material layer 1 is greater than or equal to 1×10 18 cm -3 ; In this way, in the actual preparation process, after annealing the silicon material layer 1 using a low-temperature process, the impurities can be activated and the local area of ​​the silicon material layer 1 can be conductorized; in addition, by directly bonding the silicon material layer 1 to the glass substrate 100, compared with the switch structure of SOI technology, the leakage of RF signals can be greatly reduced, thereby improving the signal transmission stability of the switch structure.

[0268] An embodiment of the present application provides a method for preparing a switch structure, which is applied to prepare the switch structure described above, and the method includes:

[0269] S01, providing a glass substrate 100;

[0270] S02, as shown in FIG17A, bonding a single crystal silicon thin film 1' onto a glass substrate 100;

[0271] In the actual bonding process, by applying a negative voltage on the glass substrate 100 and a positive voltage on the silicon material layer 1 (single crystal silicon film 1'), under the preset temperature and pressure, the atoms near the interface between the glass substrate 100 and the silicon material layer 1 (single crystal silicon film 1') migrate to each other and move to each other's film layer, thereby achieving the bonding of the glass substrate 100 and the silicon material layer 1 (single crystal silicon film 1'). Among them, the voltage difference between the voltage applied to the glass substrate 100 and the silicon material layer 1 (single crystal silicon film 1') is approximately 200V, and the preset temperature is 200℃~400℃. Among them, the specific details of the bonding can refer to the bonding process introduction in the relevant technology, which will not be repeated here.

[0272] S03, as shown in FIG. 17B , patterning the single crystal silicon film 'to obtain a first semiconductor pattern 11 and a second semiconductor pattern 12;

[0273] S04, ion implantation is performed on a local area of ​​the first semiconductor pattern 11 and a local area of ​​the second semiconductor pattern 12, and the first semiconductor pattern 11 and the second semiconductor pattern 12 are annealed at a preset temperature, so that the first semiconductor pattern 11 and the second semiconductor pattern 12 respectively include a conductive area (for example, the area marked A2 shown in FIG. 9); the ion implantation dose range of the conductive area A1 is 3×10 15 cm -3 ~9×10 15 cm -3 , the ion doping concentration of the conductive region A2 is greater than or equal to 1×10 18 cm -3 , the preset temperature is less than 650℃.

[0274] Exemplarily, the preset temperature may be 550°C to 600°C; for example, the preset temperature may be 560°C, 570°C, 580°C, or 590°C.

[0275] The manufacturing method provided in the embodiment of the present application prepares a switch structure by directly providing a silicon material layer 1 on a glass substrate 100, and the ion doping concentration in a local area of ​​the silicon material layer 1 is greater than or equal to 1×10 18 cm -3 ; In this way, in the actual preparation process, after annealing the silicon material layer 1 using a low-temperature process, the impurities can be activated and the local area of ​​the silicon material layer 1 can be conductorized; in addition, by directly bonding the silicon material layer 1 to the glass substrate 100, compared with the switch structure of SOI technology, the leakage of RF signals can be greatly reduced, thereby improving the signal transmission stability of the switch structure.

[0276] The following is a detailed introduction and description of the method for preparing the switch structure in conjunction with FIG. 17A to FIG. 17L and FIG. 9 .

[0277] 1) Provide a SOG wafer (a substrate on which a single crystal silicon thin film 1' is bonded on a glass substrate 100) as shown in FIG. 17A, and perform pre-cleaning work. The top single crystal silicon is p-type silicon with a resistivity of 8 to 10 Ω·m;

[0278] 2) forming a photoresist film (PR), exposing and etching to obtain a mask formed by the photoresist, using the mask to etch the single crystal silicon film 1' (eg, ICP etching process), and obtaining the first semiconductor pattern 11 and the second semiconductor pattern 12 as shown in FIG. 17B after patterning;

[0279] 3) As shown in FIG. 17C , a gate insulating layer (GI) 2 is deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. The material of the gate insulating layer 2 may be silicon nitride, silicon oxide, or other dielectric materials;

[0280] 4) As shown in FIG. 17C , a conductive layer is formed by sputtering, and the conductive layer is a mask for boron ion implantation; (A photoresist PR as shown in FIG. 17C may be used to replace the conductive layer as a mask for subsequent processes)

[0281] 5) As shown in FIG. 17D , the photoresist PR is patterned to define an ion implantation region in the second semiconductor pattern 12 ;

[0282] 6) As shown in FIG. 17E , boron ion (B+) implantation is performed, and the implantation dose is greater than or equal to 3*e 15 cm -2 ;

[0283] 7) removing the photoresist PR used as the mask to obtain a structure as shown in FIG. 17F ;

[0284] 8) As shown in FIG. 17G , a gate film 3 ′ is formed by using a Sputter sputtering process;

[0285] 9) As shown in FIG. 17H , the gate film 3 ′ is patterned to define an implantation region in the first semiconductor pattern 11 .

[0286] 10) As shown in FIG. 17I , phosphorus ion (P+) implantation is performed, and the implantation dose is greater than or equal to 3*e 15 cm -2 After annealing at 600° C. for 1 h, p+ highly doped regions are formed in the two conductive regions A2 of the second semiconductor pattern 12 , and n+ highly doped regions are formed in the two conductive regions A2 of the first semiconductor pattern 11 .

[0287] 11) The gate film 3' shown in FIG. 17I is patterned for the second time to obtain the gate Gate of the transistor as shown in FIG. 17J.

[0288] 12) As shown in FIG. 17K , an inter-level dielectric layer 4 (ILD) is formed by a PECVD process. The material of the inter-level dielectric layer 4 may be silicon nitride, silicon oxide, or other dielectric materials.

[0289] 13) As shown in FIG. 17L , the interlayer dielectric layer 4 and the gate insulating layer 2 are patterned to define the region of the contact hole (also referred to as via Via).

[0290] 14) The source and drain conductive films are formed by using a Sputter sputtering process.

[0291] 15) Patterning the source-drain conductive film to obtain a source-drain conductive layer 5 as shown in FIG. 9 , wherein the source-drain conductive layer 5 includes the source and drain of the transistor, a coplanar waveguide CPW, and a plurality of first wirings Z1 , a plurality of second wirings Z2 , and a plurality of third wirings Z3 .

[0292] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A switch structure, wherein: include: Glass substrate; at least one switch subcircuit located on the glass substrate, the switch subcircuit comprising at least one switch unit; The switch unit includes a transistor and a resistor, a gate of the transistor is electrically connected to the resistor, the resistor is electrically connected to a power supply device, a first electrode of at least one of the transistors is electrically connected to an input conductive pad, and a second electrode of at least one of the transistors is electrically connected to an output conductive pad; A silicon material layer located on the glass substrate and bonded to the glass substrate, the silicon material layer comprising a conductive region, a portion of the conductive region being configured to electrically connect the gate of the transistor and the resistor, wherein the ion doping concentration of the conductive region is greater than or equal to 1×10 18 cm -3 . The switch structure according to claim 1, wherein: At least one of the first electrode of the transistor, the second electrode of the transistor, and the gate of the transistor includes an interdigitated structure. The switch structure according to claim 2, wherein: The first electrode of the transistor, the second electrode of the transistor and the gate of the transistor all include the interdigital structure, and the gate of the transistor partially overlaps with an orthographic projection of one of the first electrode of the transistor and the second electrode of the transistor on the glass substrate. The switch structure according to claim 2, wherein: The first electrode of the transistor and the second electrode of the transistor both include the interdigital structure, and the gate of the transistor includes a serpentine structure; the orthographic projection of the gate of the transistor on the glass substrate is located between the orthographic projection of the first electrode of the transistor on the glass substrate and the orthographic projection of the second electrode of the transistor on the glass substrate, and the gate of the transistor does not overlap with the orthographic projections of the first electrode of the transistor and the second electrode of the transistor on the glass substrate. The switch structure according to claim 3 or 4, wherein: The channel width-to-length ratio of the transistor is greater than or equal to 5000. The switch structure according to claim 2, wherein: The silicon material layer includes a single crystal silicon sublayer. The switch structure according to claim 2, wherein: The silicon material layer comprises a single crystal silicon sublayer and an amorphous silicon sublayer which are sequentially arranged on the glass substrate; the thickness of the amorphous silicon sublayer is smaller than the thickness of the single crystal silicon sublayer. The switch structure according to claim 5, wherein: The switch subcircuit includes an input conductive pad and an output conductive pad. The switch structure according to claim 8, wherein: The switch subcircuit includes a first switch unit, the first switch unit includes a first transistor and a first resistor, and the power supply device includes a first power supply device; the first electrode of the first transistor is electrically connected to the input conductive pad, the second electrode of the first transistor is electrically connected to the output conductive pad, the gate of the first transistor is electrically connected to the first end of the first resistor, and the first power supply device is electrically connected to the ground terminal and the second end of the first resistor, respectively. The switch structure according to claim 8, wherein: The switch subcircuit includes a second switch unit and a third switch unit; the second switch unit includes a second transistor and a second resistor, and the third switch unit includes a third transistor and a third resistor; the power supply device includes a second power supply device and a third power supply device; the first electrode of the second transistor and the first electrode of the third transistor are both electrically connected to the input conductive pad, the second electrode of the second transistor is electrically connected to the output conductive pad, the gate of the second transistor is electrically connected to the first end of the second resistor, and the second power supply device is electrically connected to the ground terminal and the second end of the second resistor respectively; the gate of the third transistor is electrically connected to the first end of the third resistor, the third power supply device is electrically connected to the ground terminal and the second end of the third resistor respectively, and the second electrode of the third transistor is electrically connected to the ground terminal. The switch structure according to claim 5, wherein: The switch subcircuit includes a fourth switch unit, a fifth switch unit, a sixth switch unit and a seventh switch unit; the fourth switch unit includes a fourth transistor and a fourth resistor, and the fifth switch unit includes a fifth transistor and a fifth resistor; The sixth switch unit includes a sixth transistor and a sixth resistor, and the seventh switch unit includes a seventh transistor and a seventh resistor; The power supply device includes a fifth power supply device and a sixth power supply device; wherein the fourth switch unit and the sixth switch unit share the sixth power supply device, and the fifth switch unit and the seventh switch unit share the fifth power supply device. The switch structure according to claim 11, wherein: The switch subcircuit includes one input conductive pad and two output conductive pads. The switch structure according to claim 11, wherein: The switch subcircuit includes two input conductive pads and one output conductive pad. The switch structure according to claim 12, wherein: The first electrodes of the fourth transistor and the fifth transistor are both electrically connected to the first output conductive pad, the second electrode of the fourth transistor is electrically connected to the ground terminal, the second electrode of the fifth transistor is electrically connected to the input conductive pad, the gate of the fourth transistor is electrically connected to the first end of the fourth resistor, and the gate of the fifth transistor is electrically connected to the first end of the fifth resistor; the first electrodes of the sixth transistor and the seventh transistor are both electrically connected to the second output conductive pad, the second electrode of the sixth transistor is electrically connected to the input conductive pad, the second electrode of the seventh transistor is electrically connected to the ground terminal, the gate of the sixth transistor is electrically connected to the first end of the sixth resistor, and the gate of the seventh transistor is electrically connected to the first end of the seventh resistor. The switch structure according to claim 14, wherein: The second end of the fourth resistor and the second end of the sixth resistor are both electrically connected to the sixth power supply device, and the second end of the fifth resistor and the second end of the seventh resistor are both electrically connected to the fifth power supply device. The switch structure according to any one of claims 1 to 15, wherein: The switch structure includes a plurality of switch sub-circuits arranged in an array on the glass substrate. The switch structure according to claim 1, wherein: The transistor comprises a plurality of sub-transistors arranged in series, and the gate of each sub-transistor is connected to one of the resistors; and the first pole of the sub-transistor and the second pole of the transistor both comprise an interdigitated structure, and the gate of the transistor comprises a serpentine structure. The switch structure according to any one of claims 9, 10 or 15, wherein: The switch structure comprises: the silicon material layer, the silicon material layer comprises a first semiconductor pattern and a second semiconductor pattern; a gate insulating layer, the gate insulating layer covers the silicon material layer; a gate layer, the gate layer is located on a side of the gate insulating layer away from the glass substrate, and comprises a gate of the transistor; an interlayer dielectric layer, the interlayer dielectric layer covers the gate layer; a source-drain conductive layer, the source-drain conductive layer is located on a side of the interlayer dielectric layer away from the glass substrate, and comprises a first electrode and a second electrode of the transistor; wherein the first semiconductor pattern and the second semiconductor pattern both comprise a semiconductor region and the conductive regions located on both sides of the semiconductor region, the first electrode of the transistor is electrically connected to one of the conductive regions in the first semiconductor pattern, and the second electrode of the transistor is electrically connected to another of the conductive regions in the first semiconductor pattern; the semiconductor region in the first semiconductor pattern serves as a channel region of the transistor, and the semiconductor region in the second semiconductor pattern serves as the resistor. The switch structure according to claim 18, wherein: The source-drain conductive layer further includes a first routing, a second routing and a third routing, wherein the first routing is electrically connected to one of the second routing and the third routing; the first routing is electrically connected to the gate of the transistor, the second routing is electrically connected to one of the conductive regions in the second semiconductor pattern, and the third routing is electrically connected to another of the conductive regions in the second semiconductor pattern. The switch structure according to claim 19, wherein: For at least one of the transistors, the first electrode of the transistor includes a forked finger structure; the first electrode of the transistor includes a first connecting portion and N-2 first extension portions arranged in the same row, the extension direction of the first connecting portion intersects with the extension direction of the first extension portion, and the arrangement direction of the first extension portion is the same as the extension direction of the first connecting portion; the first connecting portion is located on the same side of each of the first extension portions and connects each of the first extension portions together; N is a positive integer and is greater than or equal to 4; the orthographic projections of each of the first extension portions on the glass substrate at least partially overlap with the orthographic projections of the first semiconductor pattern on the glass substrate. The switch structure according to claim 20, wherein: For at least one transistor, the second electrode of the transistor includes a forked finger structure; the second electrode of the transistor includes a second connecting portion and N-3 second extension portions arranged in the same row, the extension direction of the second connecting portion is the same as the extension direction of the first connecting portion, and the arrangement direction of the second extension portions is the same as the arrangement direction of the first extension portions; the second connecting portion is located on the same side of each second extension portion and connects each second extension portion together; the orthographic projection of each second extension portion on the glass substrate at least partially overlaps with the orthographic projection of the first semiconductor pattern on the glass substrate. The switch structure according to claim 21, wherein: For at least one transistor, the gate of the transistor includes a forked finger structure; the gate of the transistor includes a third connection portion and N third extension portions arranged in the same row, the extension directions of the third connection portion and the third extension portions intersect, the third connection portion is located on the same side of each of the third extension portions, and connects each of the third extension portions together; the orthographic projections of each of the third extension portions on the glass substrate overlap at least partially with the orthographic projections of the first semiconductor pattern on the glass substrate; the third connection portion and the orthographic projections of all the second extension portions on the glass substrate partially overlap; wherein, along the extension direction of the third connection portion, the orthographic projections of the first extension portion, the third extension portion and the second extension portion on the glass substrate are alternately arranged in sequence. The switch structure according to claim 21, wherein: For at least one transistor, the gate of the transistor includes a serpentine structure; the gate of the transistor has a first bending portion and a second bending portion that are alternately arranged, and the gate of the transistor also has a first opening portion and a second opening portion that are alternately arranged, so that the gate of the transistor has the serpentine structure, the outer contour of the first opening portion is set on the first bending portion, the outer contour of the second opening portion is set on the second bending portion, and the opening directions of the first opening portion and the second opening portion are opposite; wherein the outer contour of the first opening portion and the outer contour of the second opening portion both include a combination of multiple straight line segments, a combination of straight line segments and arcs, or arcs. The switch structure according to claim 23, wherein: The outer contour of the side of the first bending portion where the first opening is not provided and the outer contour of the side of the second bending portion where the second opening is not provided both include a combination of multiple straight line segments, a combination of straight line segments and arcs, or arcs. The switch structure according to any one of claims 22 to 24, wherein: The source-drain conductive layer also includes a coplanar waveguide, the input conductive pad, the output conductive pad and at least one power supply conductive pad. The number of the power supply conductive pads and the power supply device is the same and the two are electrically connected one-to-one. The coplanar waveguide includes a first part and a second part. There is a gap between the first part and the second part of the coplanar waveguide; the input conductive pad and the output conductive pad are located in the gap; the orthographic projections of the transistor, the resistor, the input conductive pad, the output conductive pad and the power supply conductive pad on the glass substrate do not overlap with the orthographic projections of the coplanar waveguide on the glass substrate; the coplanar waveguide is electrically connected to the ground terminal. The switch structure according to claim 25, wherein: In the case where the switch subcircuit includes a first switch unit, the first portion of the coplanar waveguide includes a first hollow region, and the second portion of the coplanar waveguide includes a second hollow region; a partial region of the first semiconductor pattern of the first transistor and a partial region of the first electrode of the first transistor extend to the first hollow region; A partial area of ​​the first semiconductor pattern, a partial area of ​​the first electrode of the first transistor, the first resistor, the power supply conductive pad, the first routing line, the second routing line and the third routing line are all located in the second hollow area. The switch structure according to claim 25, wherein: In the case where the switching sub-circuit includes a second switching unit and a third switching unit, the first part of the coplanar waveguide includes a third hollow area, the second part of the coplanar waveguide includes a fourth hollow area and a fifth hollow area, and the fourth hollow area is connected to the fifth hollow area; a partial area of ​​the first semiconductor pattern of the second transistor and a partial area of ​​the first pole of the second transistor extend to the third hollow area; the third transistor, the third resistor, and the power supply conductive pad electrically connected to the third power supply device are all located in the fourth hollow area; the second resistor and the power supply conductive pad electrically connected to the second power supply device are all located in the fifth hollow area. The switch structure according to claim 25, wherein: In the case where the switch sub-circuit includes a fourth switch unit, a fifth switch unit, a sixth switch unit and a seventh switch unit, the first part of the coplanar waveguide includes a sixth hollow area and a seventh hollow area, the second part of the coplanar waveguide includes an eighth hollow area and a ninth hollow area, the sixth hollow area is connected to the seventh hollow area, and the eighth hollow area is connected to the ninth hollow area; the main body of the fifth transistor and the main body of the sixth transistor are located in the gap; the fourth transistor and the fourth resistor are located in the eighth hollow area; a partial area of ​​the first semiconductor pattern of the fifth transistor, a partial area of ​​the first electrode of the fifth transistor, the fifth resistor, and the power supply conductive pad electrically connected to the fifth power supply device are located in the sixth hollow area; A partial area of ​​the first semiconductor pattern of the sixth transistor and a partial area of ​​the first electrode of the sixth transistor are located in the seventh hollow area; a partial area of ​​the first semiconductor pattern of the sixth transistor, a partial area of ​​the first electrode of the sixth transistor, the sixth resistor, and the power supply conductive pad electrically connected to the sixth power supply device are located in the ninth hollow area; the main body of the seventh transistor and the seventh resistor are located in the seventh hollow area. A radio frequency chip, wherein: Comprising the switch structure as claimed in any one of claims 1-28. A method for preparing a switch structure, applied to preparing the switch structure according to any one of claims 1 to 28, the method comprising: providing a glass substrate; bonding a single crystal silicon thin film on the glass substrate; Performing patterning on the single crystal silicon thin film to obtain a first semiconductor pattern and a second semiconductor pattern; Ion implantation is performed on a local area of ​​the first semiconductor pattern and a local area of ​​the second semiconductor pattern respectively, and the first semiconductor pattern and the second semiconductor pattern are annealed at a preset temperature so that the first semiconductor pattern and the second semiconductor pattern respectively include a conductive area; the ion implantation dose range of the conductive area is 3×10 15 cm -3 ~9×10 15 cm -3 The ion doping concentration of the conductive region is greater than or equal to 1×10 18 cm -3 , the preset temperature is less than 650°C.

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