Chip defect detection method and device

Abstract

The invention relates to the technical field of industrial quality inspection, and provides a chip defect detection method and equipment, which are used for improving the accuracy and efficiency of LED chip defect detection. According to the method, local wafer images are respectively collected from different visual angles under a plurality of light sources, multi-light-source images corresponding to a single visual angle are spliced, and then two-stage defect detection is carried out based on the multi-light-source spliced images. And the detail information of the LED chip of the local wafer image is richer than that of the complete wafer image, so that the accuracy of defect detection can be improved, meanwhile, in the first stage of two-stage absent detection, the coarse detection and positioning of a single chip are realized by classifying the multi-light-source spliced image, and the defect detection accuracy is improved. In the second stage, defect detection is carried out on part of single chip images based on rough detection and positioning results in the first stage, and compared with defect detection carried out on single chip images of all LED chips, the detection efficiency is effectively improved.

Description

Background Art

[0002] The production process of LED chips is to first produce regularly arranged chips on the entire wafer, and then cut them into individual chips. During the production process, damaged or defective LED chips are inevitable due to the limitations of the production process. Therefore, the chip electrical and appearance defect detection is required before leaving the factory, so that chips that do not meet the quality standards can be detected and eliminated to improve product quality.

[0003] Generally, a single wafer is about 6-8 inches in size, and contains tens of thousands to hundreds of thousands of LED chips, up to millions. These chips are of the same size and are arranged in rows and columns on the wafer, such as Figure 1 As shown, the size of a single LED chip on the wafer is extremely small.

[0004] Initially, defect detection of industrial products mainly relied on manual visual inspection. However, since chips are tiny and large in number, they need to be seen under a microscope, which makes the human eye easily fatigued and inefficient. With the development of technology, automated defect detection has gradually begun to be applied. Classic defect detection algorithms are generally based on traditional image processing algorithms. With the development of computer vision (CV) and deep learning, target detection methods based on deep learning have also begun to be applied to industrial products, realizing the detection of multiple defect locations and types on a product.

[0005] When performing defect detection on the appearance of LED chips, the target detection algorithm based on deep learning generally uses the entire wafer image as input. However, since the defects are mainly targeted at the chip, and there are hundreds of thousands of chips on each wafer, and each chip may have multiple defects, the defects on each chip are too small relative to the wafer. Even if the deep learning model has a good detection effect on larger industrial products, when performing tiny LED chip defect recognition on the entire wafer image, the recognition accuracy is difficult to meet the 20ppm requirement. If each chip is individually tested for defects, the detection time of hundreds of thousands of chips is unacceptable for the production line. Therefore, in the field of LED chip quality inspection, deep learning models also face great challenges in terms of detection accuracy and detection speed. Summary of the invention

[0006] The embodiments of the present application provide a chip defect detection method and device for quickly and accurately identifying chip defects.

[0007] In a first aspect, an embodiment of the present application provides a chip defect detection method, comprising:

[0008] Acquire partial wafer images taken from multiple viewing angles under different light sources, wherein the partial wafer images taken from the multiple viewing angles constitute a complete wafer image, and each partial wafer image contains multiple LED chips;

[0009] For any single viewing angle among the multiple viewing angles, local wafer images under different light sources corresponding to the single viewing angle are stitched together to generate a multi-light source stitched image.

[0010] Classifying the multi-light source stitched image to output the position coordinates of each chip in a first category, and cropping a single chip image corresponding to the first category from the multi-light source stitched image according to the position coordinates of each chip in the first category; wherein the chips in the first category are some chips to be detected among the multiple LED chips contained in the local wafer image corresponding to the single viewing angle;

[0011] Defect detection is performed on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

[0012] The beneficial effects of the above technical solution are as follows: since different types of defect features may have different degrees of prominence under different light sources, partial wafer images are collected from different viewing angles under multiple light sources, and the multi-light source images corresponding to a single viewing angle are spliced, and then two-stage defect detection is performed based on the multi-light source spliced ​​image. On the one hand, the local wafer image has richer detail information of the LED chip than a complete wafer image, which helps to improve the accuracy of defect detection. On the other hand, in the two-stage absence detection, the first stage classifies the multi-light source spliced ​​image to output the position coordinates of a single chip under the first category, and cuts out a single chip image, thereby achieving rough inspection and positioning of a single chip. In the second stage, defect detection is performed on the cropped single chip image under the first category, which is relative to defect detection on the entire wafer image, effectively improving the accuracy of chip defect detection. Moreover, since the single chip under the first category is a partial chip to be detected among multiple LED chips, relative to defect detection of the single chip images of all LED chips under a single viewing angle, the detection accuracy is improved while also improving the detection efficiency.

[0013] Optionally, when classifying the multi-light source stitched image to output the position coordinates of each chip in the first category, the method further includes:

[0014] Outputting the position coordinates of each chip in the second category, wherein the chips in the second category are some chips that do not need to be defect-detected among a plurality of LED chips included in the local wafer image corresponding to the single viewing angle;

[0015] The step of cropping the multi-light source stitched image also includes:

[0016] According to the position coordinates of each chip in the second category, cropping a single chip image corresponding to the second category from the multi-light source stitched image;

[0017] After determining the defect type of the single chip under the first category, the method further includes:

[0018] Summarizing the single chip images corresponding to the first category and the second category in the single viewing angle to obtain a chip set in the single viewing angle; each single chip image in the chip set is associated with the position coordinates and target type of a single chip, the target type of the single chip in the first category is the defect type, and the target type of the single chip in the second category is the original type;

[0019] A complete wafer image with defects marked is drawn according to the chip sets corresponding to the multiple viewing angles.

[0020] The beneficial effect of the above technical solution is: when classifying a single-perspective multi-light source stitched image, in addition to outputting the position coordinates of a single chip under the first category, the position coordinates of a single chip under the second category that does not require defect detection are also output, wherein the single chip images under the first category and the second category cover multiple LED chips within the perspective, so that all chips on the wafer can be obtained based on multiple LED chips within multiple perspectives, and since the chip defect type under the first category and the original type of the chip under the second category are known, the complete wafer image marked with defects can be restored.

[0021] Optionally, drawing a complete wafer image marked with defects according to the chip sets corresponding to the multiple perspectives includes:

[0022] For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip;

[0023] Rectangles of the same size are drawn at multiple global positions to output a complete wafer image marked with defects, wherein each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

[0024] The beneficial effect of the above technical solution is: each chip is represented by a rectangle, and a complete wafer image is drawn according to the global position of each chip on the wafer. Since the target type of each chip has been determined, the rectangles corresponding to chips of different target types are displayed separately, which can more intuitively highlight the results of defect detection and provide a stronger visual effect.

[0025] Optionally, when classifying the multiple LED chips corresponding to the single viewing angle, the method further includes:

[0026] The multi-light source stitched image is replaced with a local wafer image taken with the single viewing angle under a single light source.

[0027] The beneficial effect of the above technical solution is that, since the rough inspection and positioning tasks of a single chip are relatively simple, classification can be performed based on the local wafer image of a single light source to improve the efficiency of rough inspection and positioning.

[0028] Optionally, the position coordinates are the center point coordinates of the chip, and a single chip image is cropped from the multi-light source stitched image, including:

[0029] Determine the size of a cutting frame of each chip according to the size of each chip and the intervals between adjacent chips in the horizontal and vertical directions; the size of the cutting frame is larger than the size of the single chip;

[0030] The center point coordinates of each chip are used as the center point coordinates of the corresponding cropping frame, and combined with the size of the corresponding cropping frame, a single chip image is cropped from the multi-light source stitched image.

[0031] The beneficial effect of the above technical solution is that, since some defects occur on the periphery of the chip, when cropping the multi-light source stitching image, in addition to considering the size of a single chip, the chip spacing is also considered to ensure that the size of the cropping frame is larger than the size of a single chip. In this way, when defect detection is performed based on a single chip image, defects around the chip can be detected, thereby improving the accuracy of defect detection.

[0032] Optionally, the performing defect detection on the single chip image corresponding to the first category to determine the defect type of the single chip under the first category includes:

[0033] For each single chip image in the first category, perform the following steps:

[0034] Inputting the single chip image into a trained defect detection model, and extracting chip features from the single chip image through a convolution operation;

[0035] Processing the chip features in different dimensions based on multiple stages of the defect detection model to output deep chip features; wherein each stage includes multiple convolution blocks, each convolution block includes the same number of convolution layers, and different convolution layers use different convolution kernels;

[0036] The defect type of the corresponding chip is identified according to the deep chip features.

[0037] The beneficial effects of the above technical solution are as follows: the defect detection model is divided into multiple stages, each stage contains multiple convolution blocks, each convolution block contains the same number of convolution layers, and different convolution layers use different convolution kernels. In this way, when using the defect detection model to perform defect detection on a single chip image, chip features of different dimensions can be obtained, thereby more comprehensively describing the defects in the chip and improving the accuracy of defect detection.

[0038] In a second aspect, an embodiment of the present application provides a chip defect detection device, including a processor, a memory, and a communication interface, wherein the communication interface, the memory, and the processor are connected via a bus;

[0039] The memory stores a computer program, and the processor performs the following operations according to the computer program:

[0040] Acquire partial wafer images taken from multiple viewing angles under different light sources through the communication interface, wherein the partial wafer images taken from the multiple viewing angles constitute a complete wafer image, and each partial wafer image contains multiple LED chips;

[0041] For any single viewing angle among the multiple viewing angles, local wafer images under different light sources corresponding to the single viewing angle are stitched together to generate a multi-light source stitched image.

[0042] Classifying the multi-light source stitched image to output the position coordinates of each chip in a first category, and cropping a single chip image corresponding to the first category from the multi-light source stitched image according to the position coordinates of each chip in the first category; wherein the chips in the first category are some chips to be detected among the multiple LED chips contained in the local wafer image corresponding to the single viewing angle;

[0043] Defect detection is performed on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

[0044] Optionally, the processor is further configured to:

[0045] Classifying the multi-light source stitched image to output the position coordinates of each chip in the second category, and cropping a single chip image corresponding to the second category from the multi-light source stitched image according to the position coordinates of each chip in the second category; wherein the chips in the second category are some chips that do not need to be defect-detected among the multiple LED chips included in the local wafer image corresponding to the single viewing angle;

[0046] Summarizing the single chip images corresponding to the first category and the second category in the single viewing angle to obtain a chip set in the single viewing angle; each single chip image in the chip set is associated with the position coordinates and target type of a single chip, the target type of the single chip in the first category is the defect type, and the target type of the single chip in the second category is the original type;

[0047] A complete wafer image with defects marked is drawn according to the chip sets corresponding to the multiple viewing angles.

[0048] Optionally, the device further includes a display screen, and the processor specifically performs:

[0049] For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip;

[0050] Rectangles of the same size are drawn at multiple global positions to output a complete wafer image marked with defects, and displayed on the display screen; wherein each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

[0051] Optionally, when classifying the multiple LED chips corresponding to the single viewing angle, the processor further executes:

[0052] The multi-light source stitched image is replaced with a local wafer image taken with the single viewing angle under a single light source.

[0053] Optionally, the position coordinates are the coordinates of the center point of the chip, and the processor cuts out a single chip image from the multi-light source stitched image by:

[0054] Determine the size of a cutting frame of each chip according to the size of each chip and the intervals between adjacent chips in the horizontal and vertical directions; the size of the cutting frame is larger than the size of the single chip;

[0055] The center point coordinates of each chip are used as the center point coordinates of the corresponding cropping frame, and combined with the size of the corresponding cropping frame, a single chip image is cropped from the multi-light source stitched image.

[0056] Optionally, the processor performs defect detection on the single chip image corresponding to the first category to determine the defect type of the single chip under the first category, and the specific operation is:

[0057] For each single chip image in the first category, perform the following steps:

[0058] Inputting the single chip image into a trained defect detection model, and extracting chip features from the single chip image through a convolution operation;

[0059] Processing the chip features in different dimensions based on multiple stages of the defect detection model to output deep chip features; wherein each stage includes multiple convolution blocks, each convolution block includes the same number of convolution layers, and different convolution layers use different convolution kernels;

[0060] The defect type of the corresponding chip is identified according to the deep chip features.

[0061] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed, the steps of any chip defect detection method provided in the first aspect can be implemented.

[0062] The technical effects brought about by any one of the implementation methods in the second aspect to the third aspect can refer to the technical effects brought about by the corresponding implementation method in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0064] Figure 1 A schematic diagram of a wafer provided in an embodiment of the present application;

[0065] Figure 2 The main process of LED chip appearance defect detection provided by the embodiment of the present application;

[0066] Figure 3 A complete architecture diagram of chip defect detection provided in an embodiment of the present application;

[0067] Figure 4 A flow chart of a chip defect detection method provided in an embodiment of the present application;

[0068] Figure 5 A schematic diagram of a process of capturing a partial wafer image provided in an embodiment of the present application;

[0069] Figure 6 A schematic diagram of the shooting result of a local wafer image provided in an embodiment of the present application;

[0070] Figure 7 A flow chart of a defect detection method for a single chip image provided in an embodiment of the present application;

[0071] Fig. 8AA flow chart of a method for restoring a complete wafer provided in an embodiment of the present application;

[0072] Figure 8B A schematic diagram of a wafer image after defect detection provided in an embodiment of the present application;

[0073] Fig. 9 An overall flow chart of cutting and splicing for chip defect detection provided in an embodiment of the present application;

[0074] Fig.10 A structural diagram of a chip defect detection device provided in an embodiment of the present application;

[0075] Fig.11 This is a structural diagram of the chip defect detection equipment provided in an embodiment of the present application. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the technical solution of the present application, rather than all of the embodiments. Based on the embodiments recorded in the application documents, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the technical solution of the present application.

[0077] Based on the exemplary embodiments shown in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. In addition, although the disclosure in this application is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete technical solution separately.

[0078] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0079] The terms "first", "second", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise indicated. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, for example, they can be implemented in an order other than those given in the diagrams or descriptions of the embodiments of this application.

[0080] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.

[0081] The term "module" as used in this application refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that is capable of performing the functions associated with that element.

[0082] The following is an overview of the design concept of the embodiments of the present application in conjunction with application scenarios.

[0083] The main process of LED chip appearance defect detection is as follows: Figure 2 As shown, after the entire wafer is fixed, different light sources are used to illuminate it, and an industrial camera is used to capture wafer images under different light sources. Then, based on the acquired wafer images under different light sources, defect detection of LED chips is performed, and finally the location and type of defective LED chips are output.

[0084] At present, the appearance defect detection of LED chips mainly adopts computer vision (CV) algorithm, which detects the main features of the chip and determines whether it is a defective chip through pre-established card control standards, thereby realizing automatic defect detection. With the development of deep learning technology, computer vision algorithms are increasingly using deep learning technology to achieve efficient feature extraction and recognition. However, due to the extremely small and large number of LED chips on the wafer, the detection accuracy and efficiency of the algorithm are low. The defect detection rate on the existing production line is about 300ppm, and the over-inspection rate (i.e., identifying normal chips as defective chips) is greater than 0.2%. In this way, manual re-inspection is required after the algorithm detection, and the full-automatic detection of the production line cannot be truly realized, resulting in a waste of manpower, reducing production efficiency, and affecting production capacity.

[0085] In view of this, the embodiments of the present application provide a chip defect detection method, device and electronic device for improving the detection performance of LED chips. For tiny LED chips on a wafer, considering the visibility of different defects under different light sources, local wafer images that can be spliced ​​into a complete wafer image are taken from multiple perspectives under different light sources, and the local wafer images of different light sources under the same perspective are spliced ​​into a multi-light source spliced ​​image, and then two-stage defect detection is realized based on the multi-light source spliced ​​image. Among them, the first stage is to classify the multi-light source spliced ​​image to output the position coordinates of a single chip under the first category, and crop a single chip image, so as to realize the rough inspection and positioning of a single chip, and the second stage is to perform defect detection on the cropped single chip image under the first category, which effectively improves the accuracy of chip defect detection compared to the defect detection of the entire wafer image, and because the single chip under the first category is a partial chip to be detected among multiple LED chips, compared to the single chip images of all LED chips under a single perspective, the detection accuracy is improved while the detection efficiency is also improved.

[0086] In addition, for the multi-light source stitching image, image cropping is also performed based on the position coordinates of a single chip in the second category that does not need to be detected. Since the chips in the first category and the second category constitute a chip set under the same viewing angle, the complete wafer image after defect detection can be restored based on the chip set under each viewing angle.

[0087] See also Figure 3 , which is a complete architecture diagram of chip defect detection provided in the embodiment of the present application, mainly includes five parts: multi-light source shooting, wafer image acquisition, two-stage chip defect detection, chip stitching and output display. Among them, the multi-light source shooting part takes the complete wafer as input, and shoots local wafer images under different light sources from multiple perspectives; the wafer image acquisition part reads the local wafer images shot under all light sources corresponding to a single perspective each time as the input of the two-stage chip defect detection part; in the two-stage chip defect detection part, the first stage mainly realizes the rough detection and positioning of the chip on the wafer based on the input image, and the second stage mainly cuts out a single chip image based on the output of the first stage, and accurately identifies defects for some valid chip images; the chip stitching part restores the chips after defect detection and the undetected chips at each perspective to a complete wafer image, and presents it by the output display part. The entire detection process is completely end-to-end, without the need for user operation, thereby realizing automatic defect detection of each chip on the wafer.

[0088] like Figure 4 As shown in the figure, it is a flow chart of the chip defect detection method, which mainly includes the following steps:

[0089] S401: Acquire local wafer images taken from multiple viewing angles under different light sources.

[0090] Since there are various types of defects in the appearance of chips, such as dirt, scratches, needle marks, off-cut, damage to various components, etc., and different types of defect characteristics may be different in degree of obviousness under different light sources, the complete wafer is used as input, and partial wafer images are taken from multiple perspectives under different light sources. Among them, the type and number of light sources can be determined according to the model of the wafer, usually 2-4 light sources.

[0091] In some embodiments, after determining the light source corresponding to the wafer, the camera is controlled to shoot different areas of the wafer in a set order (such as a Z-order). The shooting area covers the entire wafer, and each area generates a local wafer image under different light sources. Each wafer area shot corresponds to a field of view of the camera, that is, a viewing angle. There is an overlapping chip part between two adjacent viewing angles. In this way, the local wafer image under each viewing angle contains multiple LED chips on a wafer. The local wafer images shot under multiple viewing angles can form a complete wafer image, and there is an overlapping area in the local wafer images of adjacent viewing angles.

[0092] Take two light sources as an example. Figure 5 As shown, it is a schematic diagram of the process of shooting a local wafer image. After the camera shoots a local wafer image at a first perspective under a first light source, the position of the camera is kept unchanged, that is, the first perspective of the camera is kept unchanged, and the first light source is switched to the second light source. The camera shoots another local wafer image at the first perspective under the second light source. The wafer areas corresponding to these two local wafer images are the same. After completing the shooting of the two light sources at the first perspective, the position of the camera is moved so that the camera shoots the local wafer image under the first light source at the second perspective, wherein the edge areas of the local wafer image at the first perspective and the local wafer image at the second perspective overlap. As shown Figure 6 As shown, it is a local wafer image from multiple viewing angles under one light source.

[0093] In some embodiments, since wafers of different models have different sizes, the required shooting angles are also different, and the number of shooting angles is positively correlated with the size of the wafer, that is, the larger the size of the wafer, the more shooting angles there are.

[0094] In some embodiments, after shooting is completed, the local wafer image under each light source is temporarily stored in the memory separately in a lossless format (such as RAW format).

[0095] In some embodiments, since there are a large number of LED chips on the wafer and their sizes are small, a microscope camera with higher precision is used when photographing the wafer.

[0096] In some embodiments, the size of the chip overlap between adjacent viewing angles is greater than or equal to a complete chip.

[0097] When capturing images in the embodiment of the present application, local wafer images are collected from different perspectives under multiple light sources. Since different types of defect features may be more or less obvious under different light sources, the detailed information of the LED chip in the local wafer image is richer than that in a complete wafer image. Therefore, collecting local images of the wafer under different light sources helps to improve the accuracy of defect detection.

[0098] S402: For any single viewing angle among the multiple viewing angles, local wafer images under different light sources corresponding to the single viewing angle are stitched together to generate a multi-light source stitched image.

[0099] In some embodiments, for any single viewing angle among multiple viewing angles, local wafer images taken under all light sources corresponding to the viewing angle are read sequentially from the memory, and the local wafer images under different light sources are converted into single-channel images, and then the single-channel images of different light sources are spliced ​​by channel to obtain a multi-light source spliced ​​image.

[0100] For example, assuming that the width and height of a local wafer image are H*W, a single-channel image can be represented by a single-channel matrix, and the final multi-light source stitching image can be represented by a matrix of (H, W, L), where L is the number of light sources used.

[0101] S403: Classify the multi-light source stitched image to output the position coordinates of each chip in the first category, and cut out a single chip image from the multi-light source stitched image according to the position coordinates of each chip in the first category.

[0102] In some embodiments, for any single viewing angle among multiple viewing angles, the matrix of the multi-light source stitched image corresponding to the viewing angle is input into the target detection model based on deep learning for feature extraction, and classification is performed based on the extracted features to output the position coordinates of a single chip in the first category, and then the image of the single chip in the first category is cropped according to the position coordinates. The chips in the first category are some of the chips to be detected among the multiple LED chips contained in the local wafer image corresponding to the viewing angle, such as Figure 1 This is a normal chip in the image. This part of the chip is photographed completely.

[0103] In some embodiments, the target detection model based on deep learning is a binary classification model. Thus, when classifying the multi-light source image of each viewing angle, in addition to outputting the position coordinates of each chip in the first category, the position coordinates of each chip in the second category are also output. Therefore, when cropping any single-view multi-light source image, in addition to cropping the single chip image corresponding to the first category, the single chip image corresponding to the second category is cropped from the multi-light source stitched image according to the position coordinates of each chip in the second category. Among them, the chips in the second category are some chips that do not need to be defect-detected among the multiple LED chips included in the local wafer image corresponding to the viewing angle, and have obvious appearance differences from the chips in the first category, including standard chips for positioning, half chips at the edge of the image due to incomplete shooting, etc. Figure 1 Other chips are shown in the figure.

[0104] It should be noted that the embodiments of the present application do not impose restrictive requirements on target detection models based on deep learning, including but not limited to YOLOv8 networks, SSD networks, and ResNet networks.

[0105] In some embodiments, considering that the tasks of chip positioning and rough inspection under a single viewing angle are relatively simple to implement, when positioning and roughly inspecting the chip under a single viewing angle, the multi-light source stitched image can be replaced with a local wafer image taken at any viewing angle under a single light source, thereby improving the efficiency of chip positioning and rough inspection.

[0106] In some embodiments, when the local wafer image under a single light source provides inaccurate results for chip positioning and rough inspection, an additional local wafer image taken at the same viewing angle under another light source may be added, i.e., a multi-light source stitched image (L=2) may be used for chip positioning and rough inspection to ensure that each chip under the first category can be accurately detected. In other words, the positioning and rough inspection of the chip under a single viewing angle may use a single light source image or a multi-light source stitched image with a number of light sources less than or equal to the total number of light sources.

[0107] For example, four light sources are used to photograph the entire wafer, and a stitched image of two light sources can be used for classification using the target detection model.

[0108] In an embodiment of the present application, a deep learning-based target detection model mainly locates each chip in a multi-light source stitched image corresponding to a single perspective, and divides multiple LED chips into a first category that requires defect detection and a second category that does not require defect detection. In this way, the multi-light source stitched image can be cropped into single chip images corresponding to the first category and the second category according to the positioning result of each chip, thereby achieving rough inspection and positioning of a single chip.

[0109] In some embodiments, the position coordinates of the chip are the center point coordinates of the chip. In this case, the cropping process of a single chip image is as follows:

[0110] First, the size of the cropping frame of a single chip is determined according to the size of the single chip and the intervals between adjacent chips in the horizontal and vertical directions.

[0111] Considering that some defects occur on the periphery of the chip, it is necessary to expand some areas when cutting the chip, that is, to make the size of the cutting frame larger than the size of a single chip. The formula is expressed as:

[0112] h=height+ω·Intern h Formula 1

[0113] w=width+ω·Intern w Formula 2

[0114] Where height and width are the height and width of the chip respectively, Intern h and Intern w are the vertical and horizontal intervals between adjacent chips, respectively; ω is the expansion coefficient, and its value range is [0,1]; h and w are the height and width of the cropping box.

[0115] Optionally, ω=0.7, which can be adjusted according to actual needs, and the embodiment of the present application does not make any restrictive requirements.

[0116] Then, the center point coordinates of each chip are used as the center point coordinates of the corresponding cropping frame, and combined with the size of the corresponding cropping frame, a single chip image is cropped from the multi-light source stitching image.

[0117] After the size of the cropping frame is obtained, the center point coordinates of each chip are used as the center point coordinates of the corresponding cropping frame, so that the position of each cropping frame in the multi-light source stitching image is fixed, thereby cropping multiple single chip images. The matrix of a single chip image is represented as (h, w, L), where L is the total number of light sources used when photographing the wafer.

[0118] In the embodiments of the present application, taking into account that some defects occur on the periphery of the chip, when cropping the multi-light source stitched image, in addition to considering the size of a single chip, the chip spacing is also considered to ensure that the size of the cropping frame is larger than the size of a single chip. In this way, when defect detection is performed based on a single chip image, defects around the chip can be detected, thereby improving the accuracy of defect detection.

[0119] S404: Perform defect detection on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

[0120] Since the chips under the first category are the chips that need to be detected for defects, the single chip image corresponding to the first category cropped from any single-view multi-light source stitched image is input into the defect detection model based on the deep neural network for detection to determine the specific defect type of each chip under the first category.

[0121] In an embodiment of the present application, the defect detection model is divided into multiple stages, each stage contains multiple convolution blocks, each convolution block contains the same number of convolution layers, and different convolution layers use different convolution kernels. In this way, when the defect detection model is used to perform defect detection on a single chip image, chip features of different dimensions can be obtained, thereby more comprehensively describing the defects in the chip and improving the accuracy of defect detection.

[0122] Specifically, the defect detection process of each single chip image in the first category is as follows: Figure 7 As shown, it mainly includes the following steps:

[0123] S4041: Input a single chip image into the trained defect detection model, and extract chip features from the single chip image through convolution operation.

[0124] S4042: Process chip features in different dimensions based on multiple stages of the defect detection model to output deep chip features.

[0125] Each stage contains multiple convolution blocks, each convolution block contains the same number of convolution layers, and different convolution layers use different convolution kernels.

[0126] S4043: Identify the defect type of the corresponding chip based on the deep chip features.

[0127] In some embodiments, the defect detection model is a model based on a deep neural network, which mainly includes a convolution layer, a pooling layer and a normalization layer (ie, a softmax layer).

[0128] In some embodiments, the network structure of the defect detection model is as follows: the input image is first convolved with a convolution kernel of size 8*8 and stride 8, and then pooled. Then, after three stages of convolution operations, high-dimensional deep chip features are obtained. Finally, the softmax function is used as a multi-classifier to output the probability corresponding to each defect type according to the deep chip features, and the type with the highest probability is taken as the final defect type of the chip. Among them, the number of convolution blocks contained in the three stages are 2, 7, and 3 respectively. The blocks in each stage are the same, and each block contains 3 layers of convolution. The 3 layers of convolution in the block of the first stage use the convolution kernel of size 5 and channel 64, the convolution kernel of size 1 and channel 192, and the convolution kernel of size 1 and channel 64 respectively; the 3 layers of convolution in the block of the second stage use the convolution kernel of size 7 and channel 128, the convolution kernel of size 1 and channel 384, and the convolution kernel of size 1 and channel 128 respectively; the 3 layers of convolution in the block of the third stage use the convolution kernel of size 7 and channel 256, the convolution kernel of size 1 and channel 768, and the convolution kernel of size 1 and channel 256 respectively.

[0129] In an embodiment of the present application, the second stage of the two-stage chip defect detection performs defect detection on a cropped single chip image of the first category based on a deep neural network learning model, which effectively improves the accuracy of chip defect detection relative to defect detection on the entire wafer image. In addition, since the chips under the first category are some chips to be detected among multiple LED chips within a single viewing angle, relative to defect detection on single chip images of all LED chips within a single viewing angle, the detection accuracy is improved while also improving the detection efficiency.

[0130] In some embodiments, after two-stage chip defect detection, the position coordinates and type of the LED chip at each viewing angle can be obtained. Therefore, the complete wafer after defect detection can be restored based on all LED chips in multiple viewing angles.

[0131] Specifically, the complete wafer recovery process is as follows: Fig. 8A As shown, it mainly includes the following steps:

[0132] S405: For any single viewing angle, collect the single chip images corresponding to the first category and the second category in the viewing angle to obtain a chip set in the viewing angle.

[0133] Among them, each single chip image in the chip set is associated with the position coordinates and target type of the single chip. Since the single chip corresponding to the first category has been defect-detected, the target type of the single chip of the first category is the defect type after detection (for example, electrode scratches), and the single chip corresponding to the second category has not been defect-detected, so the target type of the single chip of the second category is the original type (for example, the original type can be represented by the original name of the chip (such as positioning chip)).

[0134] S406: Drawing a complete wafer image with defects marked according to the chip sets corresponding to the multiple viewing angles.

[0135] Since the chip sets of multiple viewpoints contain all LED chips on the wafer, and the positions and types of LED chips in each chip set are known, the chips in each chip set can be globally stitched to restore the complete wafer image after missing parts detection. The specific restoration process is as follows:

[0136] S4061: For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip.

[0137] Since LED chips are of uniform size and are neatly arranged in rows and columns on the wafer, and there is a certain order (such as Z-order) when photographing the wafer from multiple perspectives, the global position of each chip on the wafer can be determined based on the perspective and position coordinates of the chip.

[0138] S4062: Draw rectangles of the same size at multiple global position coordinates to output a complete wafer image with defects marked.

[0139] Each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

[0140] In some embodiments, different colors may be used to represent chips of different target types, such as dirt defects represented by red rectangles, scratch defects represented by green rectangles, needle marks represented by yellow rectangles, and so on.

[0141] It should be noted that the embodiment of the present application does not impose any restrictive requirements on the manner in which the rectangles are displayed. In addition to being distinguished by color, they can also be distinguished by different filling methods, or by using boxes with different lines, etc.

[0142] like Figure 8B The figure shows the restored complete wafer image, where each rectangle represents a chip, wherein defect-free chips, chips with three defect types, and other chips (chips of the second category that do not require defect detection) are represented by rectangles with different fillings.

[0143] In an embodiment of the present application, each chip is represented by a rectangle, and a complete wafer image is drawn according to the global position of each chip on the wafer. Since the target type has been determined for each chip, the rectangles corresponding to chips of different target types are displayed separately, which can more intuitively highlight the results of defect detection and provide a stronger visual effect.

[0144] See also Fig. 9 , which is an overall flow chart of the cutting and splicing of chip defect detection provided in the embodiment of the present application, mainly includes the following steps:

[0145] S1: Obtain local wafer images taken from multiple viewing angles under different light sources.

[0146] Among them, the local wafer images taken from multiple perspectives constitute a complete wafer image, and each local wafer image contains multiple LED chips.

[0147] S2: Read and stitch the local wafer images under different light sources corresponding to any single viewing angle to generate a multi-light source stitching image.

[0148] S3: Perform binary classification on the multi-light source stitching image, and output the position coordinates of each chip in the first category and the position coordinates of each chip in the second category.

[0149] Among them, the chips under the first category are some chips to be detected among multiple LED chips in a single viewing angle, and the chips under the second category are some chips that do not need to be defect-detected among multiple LED chips in a single viewing angle.

[0150] S4: cropping the multi-light source stitched image according to the position coordinates of each chip in the first category and the second category to obtain single chip images corresponding to the first category and the second category respectively.

[0151] S5: Perform defect detection on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

[0152] S6: Summarize the single chip images corresponding to the first category and the second category in any single viewing angle to obtain a chip set in the single viewing angle.

[0153] Each single chip image in the chip set is associated with the position coordinates and target type of the single chip, the target type of the single chip of the first category is the defect type, and the target type of the single chip of the second category is the original type.

[0154] S7: For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip.

[0155] S8: Rectangles of the same size are drawn at multiple global locations to output a complete wafer image with defects marked.

[0156] Each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

[0157] The chip defect detection method provided in the embodiment of the present application improves the detection speed by 50% through two-stage chip defect detection. Under the premise of meeting production efficiency, it can achieve a detection performance of a missed detection rate of less than 20ppm and a passed detection rate of less than 0.15%, which meets the delivery index requirements of chips in this field. There is no need for manual re-inspection, which effectively improves the quality and production efficiency of the delivered products and saves labor costs.

[0158] Based on the same technical concept, an embodiment of the present application provides a chip defect detection device that can implement the steps of the above-mentioned chip defect detection method and achieve the same technical effect.

[0159] See also Fig.10 The defect detection device includes an acquisition module 1001, a splicing module 1002, a first-stage detection module 1003, a cutting module 1004, and a second-stage detection module 1005, wherein:

[0160] An acquisition module 1001 is used to acquire partial wafer images taken from multiple viewing angles under different light sources, wherein the partial wafer images taken from multiple viewing angles constitute a complete wafer image, and each partial wafer image contains multiple LED chips;

[0161] The stitching module 1002 is used to stitch the local wafer images under different light sources corresponding to any single viewing angle among the multiple viewing angles to generate a multi-light source stitching image.

[0162] The first stage detection module 1003 is used to classify the multi-light source stitching image to output the position coordinates of each chip in the first category; wherein the chips in the first category are some chips to be detected among the multiple LED chips contained in the local wafer image corresponding to the single viewing angle;

[0163] A cropping module 1004 is used to crop a single chip image corresponding to the first category from the multi-light source stitched image according to the position coordinates of each chip in the first category;

[0164] The second stage detection module 1005 is used to perform defect detection on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

[0165] Optionally, the first-stage detection module 1003 is further used to classify the multi-light source stitched image to output the position coordinates of each chip in the second category; wherein the chips in the second category are some chips that do not need to be defect-detected among the multiple LED chips included in the local wafer image corresponding to the single viewing angle;

[0166] The cropping module 1004 is further used to crop a single chip image corresponding to the second category from the multi-light source stitched image according to the position coordinates of each chip in the second category;

[0167] The apparatus further includes a wafer recovery module 1006, configured to:

[0168] Summarize the single chip images corresponding to the first category and the second category in the single view to obtain a chip set under the single view; each single chip image in the chip set is associated with the position coordinates and target type of the single chip, the target type of the single chip of the first category is the defect type, and the target type of the single chip of the second category is the original type;

[0169] Draw an image of the entire wafer with defects marked based on the collection of chips corresponding to multiple views.

[0170] Optionally, the wafer recovery module 1006 is specifically used for:

[0171] For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip;

[0172] Rectangles of the same size are drawn at multiple global positions to output a complete wafer image marked with defects, wherein each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

[0173] Optionally, the first-stage detection module 1003 is further configured to replace the multi-light source stitched image with a local wafer image taken with a single light source and a single viewing angle.

[0174] Optionally, the cutting module 1004 is specifically used for:

[0175] Determine the size of the cutting frame of each chip according to the size of each chip and the intervals between adjacent chips in the horizontal and vertical directions; the size of the cutting frame is larger than the size of a single chip;

[0176] The center point coordinates of each chip are used as the center point coordinates of the corresponding cropping frame, and combined with the size of the corresponding cropping frame, a single chip image is cropped from the multi-light source stitching image.

[0177] Optionally, the second stage detection module 1005 is specifically used for:

[0178] For each single chip image under the first category, the single chip image is input into the trained defect detection model, and chip features are extracted from the single chip image through convolution operation;

[0179] Process chip features in different dimensions based on multiple stages of the defect detection model to output deep chip features; each stage contains multiple convolution blocks, each convolution block contains the same number of convolution layers, and different convolution layers use different convolution kernels;

[0180] Identify the defect type of the corresponding chip based on the deep chip features.

[0181] For the convenience of description, the above parts are divided into modules (or units) according to their functions and described separately. Of course, when implementing this application, the functions of each module (or unit) can be implemented in the same or multiple software or hardware.

[0182] After introducing the chip defect detection method and apparatus according to the exemplary embodiment of the present application, next, a defect detection device according to another exemplary embodiment of the present application is introduced.

[0183] Those skilled in the art will appreciate that various aspects of the present application may be implemented as a system, method or program product. Therefore, various aspects of the present application may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to as "circuit", "module" or "system" herein.

[0184] Based on the same inventive concept as the above method embodiment, the structure of the defect detection device provided in the embodiment of the present application can be as follows: Fig.11 As shown, it includes a processor 1101, a memory 1102 and a communication interface 1103;

[0185] The communication interface 1103 is used to obtain images captured by the camera;

[0186] The memory 1102 stores a computer program, and the processor 1101 executes the steps of any one of the chip defect detection methods in the above embodiments according to the computer program.

[0187] In the embodiment of the present application, the memory 1102 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, and programs required to run the instant messaging function, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc. The memory 1102 may be a volatile memory (volatile memory), such as a random-access memory (RAM); the memory may also be a non-volatile memory (non-volatile memory), such as a read-only memory, a flash memory (flash memory), a hard disk drive (HDD) or a solid-state drive (SSD); or the memory 1102 may be any other medium that can be used to carry or store a desired computer program in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 1102 may be a combination of the above memories.

[0188] The processor 1101 may include one or more central processing units (CPU), GPU or a digital processing unit, etc.

[0189] In the embodiment of the present application, the specific connection medium between the communication interface 1103, the memory 1102 and the processor 1101 is not limited. In the embodiment of the present application, the bus 1104 between the communication interface 1103, the memory 1102 and the processor 1101 is Fig.11 The connections between the other components are described with bold lines, which are only for illustration and are not intended to be limiting. The bus 1104 can be divided into an address bus, a data bus, a control bus, etc. For ease of description, Fig.11 The diagram shows that only one thick line is used, but this does not mean that there is only one bus or only one type of bus.

[0190] It should be noted that Fig.11 It is only the defect detection device necessary to implement the chip defect detection method in the embodiment of the present application. Optionally, the defect detection device may also include the hardware of conventional industrial quality inspection equipment such as the display screen 1105.

[0191] Not shown, the defect detection device may also include hardware of conventional industrial quality inspection equipment such as a power supply and buttons.

[0192] An embodiment of the present application also provides a computer-readable storage medium for storing some instructions, which, when executed, can complete the steps of any chip defect detection method in the aforementioned embodiments.

[0193] An embodiment of the present application also provides a computer program product for storing a computer program, wherein the computer program is used to execute the steps of any one of the chip defect detection methods in the aforementioned embodiments.

[0194] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0195] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0196] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0197] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0198] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip defect detection method, characterized in that: include: Acquire partial wafer images taken from multiple viewing angles under different light sources, wherein the partial wafer images taken from the multiple viewing angles constitute a complete wafer image, and each partial wafer image contains multiple LED chips; For any single viewing angle among the multiple viewing angles, local wafer images under different light sources corresponding to the single viewing angle are stitched together to generate a multi-light source stitched image. Classifying the multi-light source stitched image to output the position coordinates of each chip in a first category, and cropping a single chip image corresponding to the first category from the multi-light source stitched image according to the position coordinates of each chip in the first category; wherein the chips in the first category are some chips to be detected among the multiple LED chips contained in the local wafer image corresponding to the single viewing angle; Defect detection is performed on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

2. The method according to claim 1, characterized in that When classifying the multi-light source stitched image to output the position coordinates of each chip in the first category, the method further includes: Outputting the position coordinates of each chip in the second category, wherein the chips in the second category are some chips that do not need to be defect-detected among a plurality of LED chips included in the local wafer image corresponding to the single viewing angle; The step of cropping the multi-light source stitched image also includes: According to the position coordinates of each chip in the second category, cropping a single chip image corresponding to the second category from the multi-light source stitched image; After determining the defect type of the single chip under the first category, the method further includes: Summarizing the single chip images corresponding to the first category and the second category in the single viewing angle to obtain a chip set in the single viewing angle; each single chip image in the chip set is associated with the position coordinates and target type of a single chip, the target type of the single chip in the first category is the defect type, and the target type of the single chip in the second category is the original type; A complete wafer image with defects marked is drawn according to the chip sets corresponding to the multiple viewing angles.

3. The method according to claim 2, characterized in that Drawing a complete wafer image with defects marked according to the chip sets corresponding to the multiple perspectives includes: For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip; Rectangles of the same size are drawn at multiple global positions to output a complete wafer image marked with defects, wherein each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

4. The method according to claim 1, characterized in that When classifying the multiple LED chips corresponding to the single viewing angle, the method further includes: The multi-light source stitched image is replaced with a local wafer image taken with the single viewing angle under a single light source.

5. The method according to any one of claims 1 to 4, characterized in that The position coordinates are the center point coordinates of the chip, and a single chip image is cut out from the multi-light source stitched image, including: Determine the size of a cutting frame of each chip according to the size of each chip and the intervals between adjacent chips in the horizontal and vertical directions; the size of the cutting frame is larger than the size of the single chip; The center point coordinates of each chip are used as the center point coordinates of the corresponding cropping frame, and combined with the size of the corresponding cropping frame, a single chip image is cropped from the multi-light source stitched image.

6. The method according to any one of claims 1 to 4, characterized in that The performing defect detection on the single chip image corresponding to the first category to determine the defect type of the single chip under the first category includes: For each single chip image in the first category, perform the following steps: Inputting the single chip image into a trained defect detection model, and extracting chip features from the single chip image through a convolution operation; Processing the chip features in different dimensions based on multiple stages of the defect detection model to output deep chip features; wherein each stage includes multiple convolution blocks, each convolution block includes the same number of convolution layers, and different convolution layers use different convolution kernels; The defect type of the corresponding chip is identified according to the deep chip features.

7. A chip defect detection device, characterized in that: It includes a processor, a memory and a communication interface, wherein the communication interface, the memory and the processor are connected via a bus; The memory stores a computer program, and the processor performs the following operations according to the computer program: Acquire partial wafer images taken from multiple viewing angles under different light sources through the communication interface, wherein the partial wafer images taken from the multiple viewing angles constitute a complete wafer image, and each partial wafer image contains multiple LED chips; For any single viewing angle among the multiple viewing angles, local wafer images under different light sources corresponding to the single viewing angle are stitched together to generate a multi-light source stitched image. Classifying the multi-light source stitched image to output the position coordinates of each chip in a first category, and cropping a single chip image corresponding to the first category from the multi-light source stitched image according to the position coordinates of each chip in the first category; wherein the chips in the first category are some chips to be detected among the multiple LED chips contained in the local wafer image corresponding to the single viewing angle; Defect detection is performed on the single chip image corresponding to the first category to determine the defect type of each chip in the first category.

8. The device according to claim 7, characterized in that The processor is further configured to: Classifying the multi-light source stitched image to output the position coordinates of each chip in the second category, and cropping a single chip image corresponding to the second category from the multi-light source stitched image according to the position coordinates of each chip in the second category; wherein the chips in the second category are some chips that do not need to be defect-detected among the multiple LED chips included in the local wafer image corresponding to the single viewing angle; Summarizing the single chip images corresponding to the first category and the second category in the single viewing angle to obtain a chip set in the single viewing angle; each single chip image in the chip set is associated with the position coordinates and target type of a single chip, the target type of the single chip in the first category is the defect type, and the target type of the single chip in the second category is the original type; A complete wafer image with defects marked is drawn according to the chip sets corresponding to the multiple viewing angles.

9. The device according to claim 8, characterized in that The device also includes a display screen, and the processor specifically performs: For any chip in the plurality of chip sets, determine the global position of the chip on the wafer according to the viewing angle and position coordinates of the chip; Rectangles of the same size are drawn at multiple global positions to output a complete wafer image marked with defects, and displayed on the display screen; wherein each rectangle corresponds to a chip, and rectangles corresponding to chips of different target types are displayed differently.

10. The device according to claim 7, characterized in that When classifying the multiple LED chips corresponding to the single viewing angle, the processor further executes: The multi-light source stitched image is replaced with a local wafer image taken with the single viewing angle under a single light source.

Images