A gap detection device and capacitance detection device thereof

Abstract

The present application discloses a gap detection device and a capacitance detection device thereof, which are applied to the field of signal detection technology, including: a bipolar capacitive sensor having a first detection electrode and a second detection electrode, for outputting a first and a second capacitance signal reflecting the capacitance of the measured position; an excitation generation circuit, for applying excitation to the first and second capacitance signals based on symmetrically inverted first and second excitation carriers, to obtain modulated first and second detection signals; a capacitance-voltage conversion circuit, for receiving the first and second detection signals, and performing capacitance signal-to-voltage signal conversion and signal amplification in a differential amplification manner to obtain first and second conversion signals; a detection processing circuit for performing phase-sensitive demodulation, obtaining a phase-sensitive demodulation result, and extracting the detection result corresponding to the capacitance of the measured position from it. The solution of the present application has a strong common-mode interference suppression capability, which effectively improves the accuracy of capacitance detection.

Description

Technical Field

[0001] The present invention relates to the technical field of signal detection, and in particular to a gap detection device and a capacitance detection apparatus thereof. Background Art

[0002] Many signal detection applications require weak capacitance detection. For example, tip clearance of aircraft engines is a critical parameter affecting engine efficiency. Capacitive detection is the most widely used method for detecting tip clearance in aircraft engines. However, the signal detection circuits of currently used capacitive sensors suffer from insufficient accuracy and weak resistance to common-mode interference, making them unsuitable for long-distance transmission of weak capacitance signals. For example, most current tip clearance detection systems for aircraft engines use single-electrode capacitive sensors. These sensors require a long cable between the sensor probe and the detection circuit. This long-distance transmission introduces significant parasitic capacitance. During capacitive sensor detection, the output signal capacitance is very small, and this significant parasitic capacitance can severely interfere with the measurement process, affecting accuracy.

[0003] In summary, how to effectively improve the accuracy of capacitance detection is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] The object of the present invention is to provide a gap detection device and a capacitance detection apparatus thereof, so as to effectively improve the accuracy of capacitance detection.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a capacitance detection device, comprising:

[0007] a bipolar capacitive sensor having a first detection electrode and a second detection electrode, configured to output a first capacitance signal and a second capacitance signal respectively detected by the first detection electrode and the second detection electrode and reflecting the capacitance of the measured position;

[0008] an excitation generating circuit, configured to apply excitation to the first capacitance signal and the second capacitance signal based on a symmetrically anti-phased first excitation carrier and a second excitation carrier, to obtain modulated first detection signals and second detection signals;

[0009] a capacitance-to-voltage conversion circuit, configured to receive the first detection signal and the second detection signal, and convert the capacitance signal into a voltage signal and amplify the signal in a differential amplification manner to obtain a first conversion signal and a second conversion signal;

[0010] The detection processing circuit is used to perform phase-sensitive demodulation on the first conversion signal and the second conversion signal based on a reference signal to obtain a phase-sensitive demodulation result, and extract a detection result corresponding to the capacitance of the measured position from the phase-sensitive demodulation result.

[0011] In one embodiment, the capacitance-to-voltage conversion circuit is a capacitance-to-voltage conversion circuit based on a first fully differential operational amplifier, or a differentially symmetrical capacitance-to-voltage conversion circuit based on two operational amplifiers.

[0012] In one embodiment, when the capacitance-to-voltage conversion circuit is a capacitance-to-voltage conversion circuit based on a first fully differential operational amplifier, the capacitance-to-voltage conversion circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and a first fully differential operational amplifier;

[0013] The first end of the first resistor serves as the first input end of the capacitor-voltage conversion circuit to receive the first detection signal; the first end of the second resistor serves as the second input end of the capacitor-voltage conversion circuit to receive the second detection signal; the second end of the first resistor is respectively connected to the first end of the first capacitor, the first end of the third resistor, and the non-inverting input end of the first fully differential operational amplifier, and the second end of the second resistor is respectively connected to the first end of the second capacitor, the first end of the fourth resistor, and the inverting input end of the first fully differential operational amplifier;

[0014] The first output end of the first fully differential operational amplifier is connected to the second end of the first capacitor and the second end of the third resistor, respectively, and the connection end serves as the first output end of the capacitor-voltage conversion circuit to output the first conversion signal; the second output end of the first fully differential operational amplifier is connected to the second end of the second capacitor and the second end of the fourth resistor, respectively, and the connection end serves as the second output end of the capacitor-voltage conversion circuit to output the second conversion signal.

[0015] In one embodiment, the excitation generation circuit includes:

[0016] an oscillator circuit for providing a clock signal;

[0017] an anti-phase excitation generating circuit, configured to generate a first square wave signal and a second square wave signal of symmetrical anti-phase based on the clock signal;

[0018] a first bandpass filter circuit, configured to filter the first square wave signal and the second square wave signal to generate a first sinusoidal wave signal and a second sinusoidal wave signal that are symmetrical and inverted;

[0019] a first differential amplifier circuit, configured to differentially amplify the first sinusoidal wave signal and the second sinusoidal wave signal to generate a first excitation carrier wave and a second excitation carrier wave that are symmetrical and inversely phased;

[0020] The impedance matching circuit is used to apply excitation to the first capacitance signal and the second capacitance signal based on the first excitation carrier and the second excitation carrier, and perform impedance matching to obtain modulated first detection signal and second detection signal.

[0021] In one embodiment, the excitation generation circuit further includes:

[0022] A first low-pass filter circuit is provided between the first band-pass filter circuit and the first differential amplifier circuit and is used to suppress oscillation of high-frequency signals.

[0023] In one embodiment, the impedance matching circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor;

[0024] The first end of the fifth resistor is used to receive the first excitation carrier, the second end of the fifth resistor is connected to the first end of the sixth resistor, and the connection end is used to receive the first capacitance signal, the first end of the seventh resistor is used to receive the second excitation carrier, the second end of the sixth resistor is connected to the second end of the seventh resistor, and the connection end serves as the first output end of the impedance matching circuit to output the first detection signal;

[0025] The first end of the eighth resistor is used to receive the second excitation carrier, the second end of the eighth resistor is connected to the first end of the ninth resistor and the connection end is used to receive the second capacitance signal, the first end of the tenth resistor is used to receive the first excitation carrier, the second end of the ninth resistor is connected to the second end of the tenth resistor and the connection end serves as the second output end of the impedance matching circuit to output the second detection signal.

[0026] In one embodiment, it further includes:

[0027] a second bandpass filter circuit connected to the capacitor-to-voltage conversion circuit, configured to filter the first conversion signal and the second conversion signal;

[0028] a second differential amplifier circuit connected to the second band-pass filter circuit, configured to differentially amplify the output of the second band-pass filter circuit to generate a first signal to be processed and a second signal to be processed that are symmetrically inverted;

[0029] Correspondingly, the detection processing circuit is specifically used to: perform phase-sensitive demodulation on the first signal to be processed and the second signal to be processed based on the reference signal to obtain a phase-sensitive demodulation result, and extract the detection result corresponding to the capacitance of the measured position from the phase-sensitive demodulation result.

[0030] In one embodiment, the detection processing circuit includes:

[0031] a phase-sensitive detection circuit, configured to perform phase-sensitive detection on the first conversion signal and the second conversion signal based on a reference signal;

[0032] The demodulation circuit is used to demodulate the output of the phase-sensitive detection circuit to obtain a phase-sensitive demodulation result, and extract the detection result of the capacitance corresponding to the measured position from the phase-sensitive demodulation result.

[0033] In one embodiment, the phase-sensitive detection circuit includes:

[0034] a reference signal extraction subcircuit, configured to extract, based on the first conversion signal and the second conversion signal, a first reference signal and a second reference signal having the same frequency as the first conversion signal and the second conversion signal and a phase error within a set range;

[0035] The detection processing sub-circuit is used to perform phase-sensitive detection on the first conversion signal and the second conversion signal based on the first reference signal and the second reference signal.

[0036] In one embodiment, the reference signal extraction subcircuit is specifically configured to extract, based on the first conversion signal and the second conversion signal, a first reference signal and a second reference signal having the same frequency and phase as the first conversion signal and the second conversion signal.

[0037] In one embodiment, the reference signal extraction subcircuit includes: a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, an eleventh resistor, a first operational amplifier, a first OD gate, and a second OD gate;

[0038] The first end of the third capacitor is used to receive the first conversion signal, the first end of the fourth capacitor is used to receive the second conversion signal, the second end of the third capacitor is connected to the first end of the fifth capacitor and the first end of the eleventh resistor respectively, and the second end of the fourth capacitor is connected to the first end of the sixth capacitor and the second end of the eleventh resistor respectively;

[0039] The second end of the fifth capacitor is connected to the inverting input terminal of the first operational amplifier, the second end of the sixth capacitor is connected to the non-inverting input terminal of the first operational amplifier, the first output terminal of the first operational amplifier is connected to the input terminal of the first OD gate, and the second output terminal of the first operational amplifier is connected to the input terminal of the second OD gate; the output terminal of the first OD gate is used to output the extracted first reference signal, and the output terminal of the second OD gate is used to output the extracted second reference signal.

[0040] In one embodiment, the detection processing subcircuit includes: a seventh capacitor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, and a second operational amplifier;

[0041] The first end of the twelfth resistor is used to receive the first conversion signal, the second end of the twelfth resistor is connected to the first end of the thirteenth resistor, and the connection end is used to receive the first reference signal; the first end of the fourteenth resistor is used to receive the second conversion signal, the second end of the fourteenth resistor is connected to the first end of the fifteenth resistor, and the connection end is used to receive the second reference signal;

[0042] The second end of the thirteenth resistor is respectively connected to the second end of the fifteenth resistor, the first end of the sixteenth resistor, the first end of the seventh capacitor and the inverting input end of the second operational amplifier, and the non-inverting input end of the second operational amplifier is grounded; the output end of the second operational amplifier is respectively connected to the second end of the seventh capacitor and the second end of the sixteenth resistor, and the connection end serves as the output end of the detection processing sub-circuit for phase-sensitive detection.

[0043] In one embodiment, the demodulation circuit includes: a second low-pass filter circuit, a seventeenth resistor, an eighteenth resistor, and a third operational amplifier;

[0044] The input end of the second low-pass filter circuit is used to receive the output of the phase-sensitive detection circuit, so as to demodulate the output of the phase-sensitive detection circuit and output a phase-sensitive demodulation result;

[0045] The non-inverting input terminal of the third operational amplifier is connected to the output terminal of the second low-pass filter circuit, and the inverting input terminal of the third operational amplifier is connected to the first terminal of the seventeenth resistor and the first terminal of the eighteenth resistor respectively;

[0046] The second end of the seventeenth resistor is grounded, the second end of the eighteenth resistor is connected to the output end of the third operational amplifier, and the connection end serves as the output end of the demodulation circuit to use the output of the demodulation circuit as the detection result of the extracted capacitance corresponding to the measured position.

[0047] In one embodiment, it further includes:

[0048] The static capacitance compensation circuit is used to compensate the first detection signal and the second detection signal to eliminate the static capacitance component generated by the bipolar capacitive sensor in the first detection signal and the second detection signal.

[0049] In a second aspect, the present invention provides a gap detection device, comprising the capacitance detection device as described above.

[0050] The technical solution provided by the embodiments of the present invention utilizes a bipolar capacitive sensor driven by symmetrical, anti-phase voltages and transmits signals differentially. This provides strong immunity to parasitic capacitance interference from long transmission lines between two electrodes, which varies substantially synchronously and randomly, as well as synchronous (common-mode) interference from external electric fields. Specifically, the bipolar capacitive sensor comprises a first detection electrode and a second detection electrode, and can output first and second capacitance signals, respectively, reflecting the capacitance at the measured location, detected by the first and second detection electrodes. To achieve long-distance differential transmission, the first and second capacitance signals require modulation. Specifically, the first and second capacitance signals are excited by symmetrical, anti-phase first and second excitation carrier waves provided by an excitation generation circuit, thereby generating modulated first and second detection signals. Furthermore, since changes in the capacitance signal also generate changes in charge, and the first and second detection signals reflect these changes in charge and are relatively weak, a capacitance-to-voltage conversion circuit is required to convert the capacitance signal to a voltage signal and amplify the signal using differential amplification to generate the first and second converted signals. Subsequently, the detection processing circuit performs phase-sensitive demodulation on the first conversion signal and the second conversion signal based on the reference signal to obtain a phase-sensitive demodulation result. Finally, the detection result of the capacitance corresponding to the measured position can be extracted from the phase-sensitive demodulation result. It can be seen that from signal detection to the entire transmission process, it is completed in a differential manner. Therefore, it can have a strong suppression ability for common-mode interference such as parasitic capacitance interference and external electric fields that are basically synchronous and randomly changing in the long transmission line of the two electrodes, which effectively improves the accuracy of capacitance detection of the present application solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 A schematic structural diagram of a capacitance detection device provided in a specific embodiment of the present invention;

[0053] Figure 2 Schematic diagram of the structure of a bipolar capacitive sensor in a specific embodiment of the present invention;

[0054] Figure 3 Schematic diagram of the change in projected area of ​​an engine blade when it passes through a bipolar capacitive sensor;

[0055] Figure 4 A schematic structural diagram of a capacitance detection device provided in another specific embodiment of the present invention;

[0056] Figure 5 Schematic diagram of the structure of a first band-pass filter circuit and a first differential amplifier circuit in a specific embodiment of the present invention;

[0057] Figure 6 Schematic diagram of the structure of an impedance matching circuit in a specific embodiment of the present invention;

[0058] Figure 7 Schematic diagram of the structure of a capacitor-to-voltage conversion circuit in a specific embodiment of the present invention;

[0059] Figure 8 Schematic diagram of the structure of a second band-pass filter circuit and a second differential amplifier circuit in a specific embodiment of the present invention;

[0060] Figure 9 Schematic diagram of the structure of the reference signal extraction subcircuit and the detection processing subcircuit in a specific embodiment of the present invention;

[0061] Figure 10 Schematic diagram of the structure of a demodulation circuit in a specific embodiment of the present invention;

[0062] Figure 11 A schematic diagram of a simulation waveform in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0063] The core of the present invention is to provide a capacitance detection device with strong common-mode interference suppression capability, which effectively improves the accuracy of capacitance detection.

[0064] To help those skilled in the art better understand the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It is apparent that the embodiments described are only a portion of the present invention, not all of the embodiments. All other embodiments derived by those skilled in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.

[0065] Please refer to Figure 1 , Figure 1 This is a schematic structural diagram of a capacitance detection device provided in a specific embodiment of the present invention. The capacitance detection device may include:

[0066] A bipolar capacitive sensor 10 having a first detection electrode and a second detection electrode, configured to output a first capacitance signal and a second capacitance signal respectively detected by the first detection electrode and the second detection electrode, reflecting the capacitance of the measured position;

[0067] An excitation generating circuit 20 is configured to apply excitation to the first capacitance signal and the second capacitance signal based on a symmetrically anti-phased first excitation carrier and a second excitation carrier to obtain modulated first detection signals and second detection signals;

[0068] The capacitance-to-voltage conversion circuit 30 is configured to receive the first detection signal and the second detection signal, and convert the capacitance signal into a voltage signal and amplify the signal in a differential amplification manner to obtain a first conversion signal and a second conversion signal;

[0069] The detection processing circuit 40 is used to perform phase-sensitive demodulation on the first conversion signal and the second conversion signal based on the reference signal to obtain a phase-sensitive demodulation result, and extract a detection result corresponding to the capacitance of the measured position from the phase-sensitive demodulation result.

[0070] For details, please refer to Figure 2 and Figure 3 , Figure 2 FIG. 1 is a schematic structural diagram of a bipolar capacitive sensor 10 in a specific embodiment of the present invention. Figure 3 The figure is a schematic diagram of the change in the projected area of ​​the engine blades when they pass through the bipolar capacitive sensor 10. When detecting the tip clearance of the engine, the bipolar capacitive sensor 10 needs to be arranged at the detection position, for example, fixed on the casing to be opposite to the top of the blade. As the blades rotate, when the blades pass through the bipolar capacitive sensor 10, the flat plate capacitance value formed by the bipolar capacitive sensor 10 and the end face of the engine blade will change. The projected area of ​​the blade end face on the detection electrode of the bipolar capacitive sensor 10 is S. The flat plate capacitance value C can be expressed as C = (ε×S) / d, where d represents the distance between the blade end face and the detection electrode of the bipolar capacitive sensor 10, and ε is the dielectric constant of the medium. Figure 2 In the example of , the capacitance of the measured position detected by the first detection electrode is recorded as CD1, and the capacitance of the measured position detected by the second detection electrode is recorded as CD2. In this example, ideally, CD1 is equal to CD2. Figure 2 CJ shown in refers to the static capacitance between the first detection electrode and the second detection electrode.

[0071] The first capacitance signal and the second capacitance signal are low-frequency signals. In order to effectively transmit the first capacitance signal and the second capacitance signal over long distances, they need to be modulated by the excitation generation circuit 20. The excitation generation circuit 20 can generate symmetrical, anti-phase first and second excitation carriers, and then apply excitation to the first capacitance signal and the second capacitance signal based on the first and second excitation carriers, thereby obtaining modulated first detection signals and second detection signals. The specific structure of the excitation generation circuit 20 can be set and adjusted according to actual needs, as long as it can achieve the functional requirements of the excitation generation circuit 20 of the present application.

[0072] For example, in one embodiment of the present invention, see Figure 4 , the excitation generating circuit 20 specifically includes:

[0073] Oscillation circuit 21, used to provide a clock signal;

[0074] The anti-phase excitation generating circuit 22 is used to generate a first square wave signal and a second square wave signal with symmetrical anti-phases based on the clock signal;

[0075] A first bandpass filter circuit 23 is used to filter the first square wave signal and the second square wave signal to generate a first sine wave signal and a second sine wave signal that are symmetrical and inverted;

[0076] A first differential amplifier circuit 24 is configured to differentially amplify the first sine wave signal and the second sine wave signal to generate a first excitation carrier wave and a second excitation carrier wave of symmetrical and anti-phase components;

[0077] The impedance matching circuit 25 is used to apply excitation to the first capacitance signal and the second capacitance signal based on the first excitation carrier and the second excitation carrier, and perform impedance matching to obtain modulated first detection signals and second detection signals.

[0078] In this embodiment, the clock signal is provided by the oscillation circuit 21. For example, in a specific scenario, a clock signal with high precision and stable frequency can be generated by a crystal oscillator. The anti-phase excitation generating circuit 22 needs to generate a symmetrically inverted first square wave signal and a second square wave signal based on the clock signal. There are many specific implementation methods. For example, in a specific scenario, the clock signal is 20MHz, and the anti-phase excitation generating circuit 22 specifically uses a D flip-flop, which can divide the 20MHz clock signal into two 10MHz differential square wave signals (Q and / Q) as the symmetrically inverted first square wave signal and the second square wave signal generated by the anti-phase excitation generating circuit 22. For another example, in a specific scenario, the anti-phase excitation generating circuit 22 specifically uses a 6D flip-flop, and the 2-gate D flip-flop of the 6D flip-flop generates a 2-frequency divided output, which is then pushed out by the clock to eliminate the phase difference of the differential square wave signal, thereby obtaining a symmetrically inverted first square wave signal and a second square wave signal.

[0079] The first sine wave signal and the second sine wave signal need to be input into the first band-pass filter circuit 23 to obtain symmetrical and inverted sine wave signals, that is, the first sine wave signal and the second sine wave signal are obtained, and then synchronously enter the first differential amplifier circuit 24, and the first differential amplifier circuit 24 performs differential amplification to generate symmetrical and inverted first excitation carrier and second excitation carrier.

[0080] The specific structures of the first bandpass filter circuit 23 and the first differential amplifier circuit 24 can be set and adjusted according to actual needs. Figure 5 , is a schematic diagram of the structure of the first band-pass filter circuit 23 and the first differential amplifier circuit 24 in a specific embodiment. The first band-pass filter circuit 23 includes a resistor R51, a resistor R52, an inductor L51, an inductor L52, an inductor L53, a capacitor C51, a capacitor C52, and a capacitor C53. It is an LC series-parallel filter circuit that can achieve good filtering effect. The resistor R51, the inductor L51, and the capacitor C51 are connected in series. The first end of the series connection is used to receive the first square wave signal UR+, and the other end is connected to the first end of the capacitor C53 and the first end of the inductor L53, respectively. The connection end serves as the first output end of the first band-pass filter circuit 23. The resistor R52, the inductor L52, and the capacitor C52 are connected in series. The first end of the series connection is used to receive the second square wave signal UR-, and the other end is connected to the second end of the capacitor C53 and the second end of the inductor L53, respectively. The connection end serves as the second output end of the first band-pass filter circuit 23.

[0081] In addition, in some embodiments, the excitation generation circuit 20 may further include: a first low-pass filter circuit disposed between the first band-pass filter circuit 23 and the first differential amplifier circuit 24 for suppressing high-frequency signal oscillations. In this embodiment, by further adding a low-pass filter, i.e., a first low-pass filter circuit, after the first band-pass filter circuit 23, the high-frequency oscillation signal can be further suppressed, thereby ensuring signal quality. Of course, the specific structure of the first low-pass filter circuit can be set and adjusted according to actual needs.

[0082] exist Figure 5 In the example, the first differential amplifier circuit 24 is a differential amplifier circuit implemented based on the operational amplifier OP51 and the operational amplifier OP52, and includes a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R58, the operational amplifier OP51, and the operational amplifier OP52. The first end of the resistor R53 is connected to the first end of the resistor R54, and the connection end serves as the first input end of the first differential amplifier circuit 24, which is connected to the first output end of the first band-pass filter circuit 23. The second end of the resistor R53 is connected to the first end of the resistor R55, and the connection end serves as the second input end of the first differential amplifier circuit 24, which is connected to the second output end of the first band-pass filter circuit 23. The second end of the resistor R54 is connected to the non-inverting input end of the operational amplifier OP51, and the second end of the resistor R55 is connected to the non-inverting input end of the operational amplifier OP52. The inverting input terminal of the operational amplifier OP51 is connected to the first end of the resistor R56 and the first end of the resistor R57, respectively. The inverting input terminal of the operational amplifier OP52 is connected to the second end of the resistor R56 and the first end of the resistor R58, respectively. The output terminal of the operational amplifier OP51 is connected to the second end of the resistor R57, and this connection terminal serves as the first output terminal of the first differential amplifier circuit 24 to output the first excitation carrier UR+A. The output terminal of the operational amplifier OP52 is connected to the second end of the resistor R58, and this connection terminal serves as the second output terminal of the first differential amplifier circuit 24 to output the second excitation carrier UR-A. The first excitation carrier UR+A is symmetrical with the second excitation carrier UR-A and has opposite phases.

[0083] Through the impedance matching circuit 25, an excitation can be applied to the first capacitance signal and the second capacitance signal based on the first excitation carrier and the second excitation carrier, and impedance matching can also be achieved, thereby preventing signal reflection and ensuring effective signal transmission. After applying the excitation and performing impedance matching, a modulated first detection signal and a second detection signal can be obtained. It can be understood that when the first detection electrode and the second detection electrode do not detect capacitance, that is, when the first capacitance signal and the second capacitance signal approach 0, the first detection signal and the second detection signal are a set of symmetrical inverted signals without superimposed capacitance signals. After the first detection electrode and the second detection electrode detect capacitance, the first capacitance signal and the second capacitance signal will be superimposed with the corresponding excitation, thereby obtaining the first detection signal and the second detection signal carrying capacitance signals, that is, the modulated first detection signal and the second detection signal, which at this time carry information about the capacitance of the measured position detected by the first detection electrode and the second detection electrode, and the information can be extracted by demodulation later.

[0084] The specific structure of the impedance matching circuit 25 can be set and adjusted according to actual needs. For example, in a specific embodiment of the present invention, please refer to Figure 6 The impedance matching circuit 25 may include: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10;

[0085] A first end of the fifth resistor R5 is used to receive the first excitation carrier, a second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the connection end is used to receive the first capacitance signal, a first end of the seventh resistor R7 is used to receive the second excitation carrier, a second end of the sixth resistor R6 is connected to the second end of the seventh resistor R7, and the connection end serves as a first output end of the impedance matching circuit 25 to output the first detection signal;

[0086] The first end of the eighth resistor R8 is used to receive the second excitation carrier, the second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9 and the connection end is used to receive the second capacitance signal, the first end of the tenth resistor R10 is used to receive the first excitation carrier, the second end of the ninth resistor R9 is connected to the second end of the tenth resistor R10 and the connection end serves as the second output end of the impedance matching circuit 25 to output the second detection signal.

[0087] exist Figure 6In the example, the first capacitance signal and the second capacitance signal are recorded as DR+ and DR-, respectively, the first excitation carrier and the second excitation carrier are recorded as UR+A and UR-A, respectively, and the output first detection signal and the second detection signal are recorded as Z+ and Z-, respectively. The impedance matching circuit 25 in this embodiment has a simple structure and high reliability. Moreover, by setting appropriate values ​​of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10, the first detection signal Z+ and the second detection signal Z- can achieve the required amplitude level. The first excitation carrier UR+A is symmetrically inverted with the second excitation carrier UR-A. Since static capacitance inevitably exists in capacitive sensors and transmission cables, and the static capacitance value is much larger than the dynamic capacitance value to be detected, applying the first carrier excitation UR+A to the static capacitance will generate a very large static output, which may easily lead to saturation of the subsequent capacitor-voltage conversion circuit 30. By applying the second excitation carrier UR-A, which is symmetrically inverted with the first excitation carrier UR+A, to the detection signal input end through the impedance matching circuit 25, the static output caused by the first carrier excitation UR+A on the static capacitance can be offset, and impedance matching can be effectively achieved.

[0088] When an AC carrier wave is applied to the capacitor, according to the equation Q = U × C, a change in the capacitance signal will result in a change in charge. Therefore, the capacitance-to-voltage conversion circuit 30 can be used to convert the capacitance signal into a voltage signal. In other words, the capacitance at the measured position, detected by the first and second detection electrodes, is reflected in the first and second detection signals as a change in charge. To facilitate measurement, the capacitance-to-voltage conversion circuit 30 is used to convert the capacitance signal into a voltage signal and amplify the signal using differential amplification.

[0089] The specific structure of the capacitor-to-voltage conversion circuit 30 can be various. For example, it can be a differentially symmetrical capacitor-to-voltage conversion circuit 30 composed of two operational amplifiers, or a capacitor-to-voltage conversion circuit 30 based on a fully differential operational amplifier. In a specific embodiment of the present invention, the capacitor-to-voltage conversion circuit 30 is a capacitor-to-voltage conversion circuit 30 based on a first fully differential operational amplifier. A fully differential operational amplifier is an integrated operational amplifier that can achieve better common-mode rejection. In some cases, a differentially symmetrical capacitor-to-voltage conversion circuit 30 composed of two operational amplifiers can also be used. The differentially symmetrical capacitor-to-voltage conversion circuit 30 is also a more commonly used circuit structure in some cases.

[0090] In a specific embodiment of the present invention, please refer to Figure 7The capacitance-to-voltage conversion circuit 30 is a capacitance-to-voltage conversion circuit 30 based on a first fully differential operational amplifier OP1. The capacitance-to-voltage conversion circuit 30 may include: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and a first fully differential operational amplifier OP1.

[0091] The first end of the first resistor R1 serves as a first input end of the capacitance-to-voltage conversion circuit 30 to receive a first detection signal; the first end of the second resistor R2 serves as a second input end of the capacitance-to-voltage conversion circuit 30 to receive a second detection signal; the second end of the first resistor R1 is respectively connected to the first end of the first capacitor C1, the first end of the third resistor R3, and the non-inverting input end of the first fully differential operational amplifier OP1; the second end of the second resistor R2 is respectively connected to the first end of the second capacitor C2, the first end of the fourth resistor R4, and the inverting input end of the first fully differential operational amplifier OP1;

[0092] The first output terminal of the first fully differential operational amplifier OP1 is connected to the second terminal of the first capacitor C1 and the second terminal of the third resistor R3, respectively, and the connected terminals serve as the first output terminal of the capacitor-to-voltage conversion circuit 30 to output the first conversion signal; the second output terminal of the first fully differential operational amplifier OP1 is connected to the second terminal of the second capacitor C2 and the second terminal of the fourth resistor R4, respectively, and the connected terminals serve as the second output terminal of the capacitor-to-voltage conversion circuit 30 to output the second conversion signal.

[0093] exist Figure 7 In the embodiment, the capacitance-to-voltage conversion circuit 30 is based on the first fully differential operational amplifier OP1. The received first detection signal and the second detection signal are denoted as Z+ and Z-, respectively, and the output first conversion signal and the second conversion signal are denoted as QV+ and QV-, respectively, which are AC voltage signals related to the measured capacitance.

[0094] Conventional proportional amplifier circuits are linear voltage amplifier circuits, which offer superior linearity to integrating amplifiers but are more susceptible to the effects of distributed transmission line parameters. In this embodiment, while implementing a proportional amplifier circuit based on a first fully differential operational amplifier OP1, a first capacitor C1 and a second capacitor C2 are additionally provided, such that the capacitance-to-voltage conversion circuit 30 constitutes an integrating charge amplifier circuit. While the use of resistors and capacitors as feedback loops introduces phase shift, this circuit effectively reduces the effects of distributed transmission line parameters compared to conventional proportional amplifier circuits, ensuring the reliability of detection results.

[0095] In addition, Figure 7In the embodiment, resistors R71 and R72 for adjusting output impedance are respectively connected in series at the first output terminal and the second output terminal of the first fully differential operational amplifier OP1, so that the output power of the first fully differential operational amplifier OP1 can be maximized.

[0096] After obtaining the first conversion signal and the second conversion signal related to the measured capacitance through capacitor-voltage conversion, the signal related to the measured capacitance carried therein can be extracted through demodulation, thereby obtaining the capacitance of the measured position. This process can be implemented based on the detection processing circuit 40.

[0097] Further, in a specific embodiment of the present invention, please refer to Figure 4 , and may also include:

[0098] a second bandpass filter circuit 50 connected to the capacitor-voltage conversion circuit 30, for filtering the first conversion signal and the second conversion signal;

[0099] a second differential amplifier circuit 60 connected to the second band-pass filter circuit 50, configured to differentially amplify the output of the second band-pass filter circuit 50 to generate a first signal to be processed and a second signal to be processed that are symmetrically inverted;

[0100] Accordingly, the detection processing circuit 40 is specifically used to: perform phase-sensitive demodulation on the first signal to be processed and the second signal to be processed based on the reference signal to obtain a phase-sensitive demodulation result, and extract a detection result corresponding to the capacitance of the measured position from the phase-sensitive demodulation result.

[0101] See Figure 4 In this embodiment, a second band-pass filter circuit 50 and a second differential amplifier circuit 60 are further provided at the subsequent stage of the capacitor-voltage conversion circuit 30. The second band-pass filter circuit 50 can effectively reduce the high-frequency signal noise generated by the capacitor-voltage conversion circuit 30, and the second differential amplifier circuit 60 can further improve the dynamic signal gain, that is, the first conversion signal and the second conversion signal output by the capacitor-voltage conversion circuit 30 are further amplified.

[0102] The specific structure of the second bandpass filter circuit 50 and the second differential amplifier circuit 60 can be set and adjusted according to actual needs, for example, refer to Figure 8 , is a structural diagram of the second bandpass filter circuit 50 and the second differential amplifier circuit 60 in a specific implementation manner.

[0103] Figure 8In the example, the second band-pass filter circuit 50 includes a resistor R81, a resistor R82, an inductor L81, an inductor L82, an inductor L83, a capacitor C81, a capacitor C82, and a capacitor C83, and is an LC series-parallel filter circuit that can achieve a good filtering effect. The resistor R81, the inductor L81, and the capacitor C81 are connected in series in sequence, with a first end of the series connection being used to receive the first conversion signal QV+ and the other end serving as the first output end of the second band-pass filter circuit 50. The resistor R82, the inductor L82, and the capacitor C82 are connected in series in sequence, with a first end of the series connection being used to receive the second conversion signal QV- and the other end serving as the second output end of the second band-pass filter circuit 50. The connection end between the resistor R81 and the inductor L81 is connected to the first end of the capacitor C83 and the first end of the inductor L83, and the connection end between the resistor R82 and the inductor L82 is connected to the second end of the capacitor C83 and the second end of the inductor L83.

[0104] exist Figure 8 In the example, the second differential amplifier circuit 60 is a differential amplifier circuit based on the second fully differential operational amplifier OP81. As described above, the use of an integrated operational amplifier such as a fully differential operational amplifier can achieve better common-mode rejection. Specifically, the second differential amplifier circuit 60 includes a resistor R83, a resistor R84, a resistor R85, a resistor R86, a resistor R87, a resistor R88, and a second fully differential operational amplifier OP81. The first end of the resistor R83 serves as the first input end of the second differential amplifier circuit 60 and is connected to the first output end of the second bandpass filter circuit 50. The first end of the resistor R85 serves as the second input end of the second differential amplifier circuit 60 and is connected to the second output end of the second bandpass filter circuit 50. The second end of the resistor R83 is respectively connected to the first end of the resistor R84 and the non-inverting input end of the second fully differential operational amplifier OP81. The second end of the resistor R85 is respectively connected to the first end of the resistor R86 and the inverting input end of the second fully differential operational amplifier OP81.

[0105] The first output terminal of the second fully differential operational amplifier OP81 is connected to the second end of resistor R84 and the first end of resistor R87, respectively. The second output terminal of the second fully differential operational amplifier OP81 is connected to the second end of resistor R86 and the first end of resistor R88, respectively. The second end of resistor R87 serves as the first output terminal of the second differential amplifier circuit 60, outputting a first signal to be processed, denoted as CF+. The second end of resistor R88 serves as the second output terminal of the second differential amplifier circuit 60, outputting a second signal to be processed, denoted as CF-.

[0106] Furthermore, it is understandable that Figure 4In the embodiment, since the second bandpass filter circuit 50 and the second differential amplifier circuit 60 are provided, the first signal to be processed CF+ and the second signal to be processed CF- are input to the detection processing circuit 40, so that the detection processing circuit 40 specifically performs phase-sensitive demodulation on the first signal to be processed CF+ and the second signal to be processed CF-. In practical applications, the more commonly used one is Figure 4 In the following, such an implementation manner will be described in detail by taking the detection processing circuit 40 performing phase-sensitive demodulation on the first signal to be processed CF+ and the second signal to be processed CF- as an example.

[0107] The specific structure of the detection processing circuit 40 can be set and adjusted according to actual needs, and can generally include a detection part and a demodulation part. For example, in a specific implementation, the detection processing circuit 40 can specifically include a phase-sensitive detection circuit and a demodulation circuit 43.

[0108] The phase-sensitive detection circuit is used to perform phase-sensitive detection on the first converted signal and the second converted signal based on a reference signal. For example, it can be a product-type synchronous detection circuit constructed using a multiplier, or a superposition-type synchronous detection circuit constructed using a superpositioner. Furthermore, it will be understood that, as described above, if the second bandpass filter circuit 50 and the second differential amplifier circuit 60 are provided before the detection processing circuit 40, then the phase-sensitive detection circuit specifically performs phase-sensitive detection on the first to-be-processed signal CF+ and the second to-be-processed signal CF- based on the reference signal.

[0109] The demodulation circuit 43 is used to demodulate the output of the phase-sensitive detection circuit to obtain a phase-sensitive demodulation result, and to extract the detection result of the capacitance corresponding to the measured position from the phase-sensitive demodulation result. For example, the demodulation circuit 43 can obtain a low-frequency signal reflecting the measured capacitance through filtering, complete demodulation, and then, based on the subsequent circuit, extract the detection result of the capacitance corresponding to the measured position from the phase-sensitive demodulation result.

[0110] In a specific embodiment of the present invention, the phase-sensitive detection circuit may include:

[0111] The reference signal extraction subcircuit 41 is configured to extract, based on the first conversion signal and the second conversion signal, a first reference signal and a second reference signal having the same frequency as the first conversion signal and the second conversion signal and a phase error within a set range;

[0112] The detection processing sub-circuit 42 is configured to perform phase-sensitive detection on the first conversion signal and the second conversion signal based on the first reference signal and the second reference signal.

[0113] In order to facilitate understanding, we first briefly explain the principle of the "modulation-demodulation" process. During modulation, for the input signal U xmcosΩt, which is modulated by the carrier signal cosωt, where ω is the angular frequency of the carrier signal, U xm As the input signal amplitude, the modulated signal Us can be obtained, which is expressed as Us=U xm cosΩt×cosωt. The demodulation process is to restore the input signal U from Us xm In the process of cosΩt, the original carrier signal cosωt can be used as the reference signal of the demodulation process, and it is multiplied by the modulated signal Us using a multiplier to obtain the detection signal Uo, which is expressed as: Uo=Us×cosωt=(1 / 2)×U xm cosΩt+(1 / 4)×U xm [cos(2ω-Ω)t+cos(2ω+Ω)t]. [cos(2ω-Ω)t+cos(2ω+Ω)t] is a high-frequency carrier signal and its higher harmonic components, which can be filtered by a low-pass filter to obtain the input signal U xm cosΩt.

[0114] During the demodulation process, the phase of the reference signal is required to be consistent with the phase of the demodulated modulated signal (the first conversion signal and the second conversion signal). For example, in some cases, the first excitation carrier UR+A and the second excitation carrier UR-A can be directly used as the required reference signals.

[0115] However, this embodiment further considers that in some embodiments, the capacitor voltage conversion circuit 30 used is the above Figure 7 Such a capacitor-to-voltage conversion circuit 30 is an integrating charge amplifier circuit. While it helps reduce the impact of distributed transmission line parameters and ensures the reliability of detection results, the use of resistor-capacitor devices as a feedback loop introduces phase shift. Specifically, the first conversion signal QV+ and the second conversion signal QV- differ in phase with the first detection signal Z+ and the second detection signal Z-. This also means that the first conversion signal QV+ and the second conversion signal QV- differ in phase with the first excitation carrier UR+A and the second excitation carrier UR-A. Furthermore, in some embodiments, a second bandpass filter circuit 50 and a second differential amplifier circuit 60 are provided after the capacitor-to-voltage conversion circuit 30. These second bandpass filter circuits 50 and 60 also introduce phase shift. Directly using the first excitation carrier UR+A and the second excitation carrier UR-A as the required reference signals for detection can cause distortion. It should be noted that when detecting high-frequency signals, a small phase deviation can result in a large error output. Therefore, when detecting high-frequency signals from engine blades, it is necessary to minimize the phase difference.

[0116] In this regard, this embodiment takes into account that the first reference signal and the second reference signal can be extracted directly from the input signal of the phase-sensitive detection circuit, that is, the first reference signal and the second reference signal are directly extracted based on the first conversion signal and the second conversion signal, which have the same frequency as the first conversion signal and the second conversion signal and whose phase error is within the set range. That is, the phase error between the first reference signal and the first conversion signal is within the set range, and the phase error between the second reference signal and the second conversion signal is within the set range, so as to ensure that the phase difference is as small as possible and avoid distortion.

[0117] Furthermore, the reference signal extraction subcircuit 41 can be specifically used to: based on the first conversion signal and the second conversion signal, extract the first reference signal and the second reference signal that are of the same frequency and phase as the first conversion signal and the second conversion signal. This implementation is a more ideal implementation, which can achieve the purpose of ensuring that the phase of the reference signal is consistent with the phase of the detected signal, thereby avoiding distortion.

[0118] It can be understood that if a second band-pass filter circuit 50 and a second differential amplifier circuit 60 are provided so that the first signal to be processed CF+ and the second signal to be processed CF- are input to the detection processing circuit 40, then the reference signal extraction subcircuit 41 is specifically based on the first signal to be processed CF+ and the second signal to be processed CF-, and extracts the first reference signal and the second reference signal that are of the same frequency and phase as the first signal to be processed CF+ and the second signal to be processed CF-.

[0119] The specific structure of the reference signal extraction subcircuit 41 can be set and adjusted according to actual needs, as long as it can meet the functional requirements of the reference signal extraction subcircuit 41 of the present application solution. For example, in a specific embodiment of the present invention, please refer to Figure 9 The reference signal extraction subcircuit 41 may specifically include: a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, an eleventh resistor R11, a first operational amplifier OP91, a first OD gate D1-1, and a second OD gate D1-2;

[0120] A first end of the third capacitor C3 is used to receive the first conversion signal, a first end of the fourth capacitor C4 is used to receive the second conversion signal, a second end of the third capacitor C3 is connected to the first end of the fifth capacitor C5 and the first end of the eleventh resistor R11, respectively, and a second end of the fourth capacitor C4 is connected to the first end of the sixth capacitor C6 and the second end of the eleventh resistor R11, respectively;

[0121] A second end of the fifth capacitor C5 is connected to the inverting input terminal of the first operational amplifier OP91, a second end of the sixth capacitor C6 is connected to the non-inverting input terminal of the first operational amplifier OP91, a first output terminal of the first operational amplifier OP91 is connected to the input terminal of the first OD gate D1-1, and a second output terminal of the first operational amplifier OP91 is connected to the input terminal of the second OD gate D1-2; the output terminal of the first OD gate D1-1 is used to output the extracted first reference signal, and the output terminal of the second OD gate D1-2 is used to output the extracted second reference signal.

[0122] It is understandable that Figure 9 This description uses an embodiment incorporating a second bandpass filter circuit 50 and a second differential amplifier circuit 60 as an example. Therefore, the reference signal extraction subcircuit 41 specifically receives the first signal to be processed CF+ and the second signal to be processed CF-, and extracts the first and second reference signals from these signals. In this embodiment, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the eleventh resistor R11, and the first operational amplifier OP91 implement a comparator structure, capable of outputting positive and negative synchronization signals with the same frequency and phase as the inputs (CF+ and CF-) of the reference signal extraction subcircuit 41. These signals are then passed through the first and second operational amplifiers D1-1 and D1-2 to obtain the first and second reference signals with the same frequency and phase as the inputs (CF+ and CF-) of the reference signal extraction subcircuit 41. The OD gate (Open Drain Gate) is an open-drain gate implemented using a MOSFET. When the OD gate is on, the output is low; when the OD gate is off, the output is high-impedance. In some implementations, an OC gate (Open Collection Gate) can also be used. It is implemented based on a transistor and has a similar principle to an OD gate. The OC gate is an open collector gate. When the OC gate is turned on, the output is a low level. Conversely, when the OC gate is turned off, the output is a high impedance state.

[0123] In a specific embodiment of the present invention, please refer to Figure 9 The detection processing sub-circuit 42 may include: a seventh capacitor C7, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a second operational amplifier OP92;

[0124] A first end of the twelfth resistor R12 is used to receive the first conversion signal, a second end of the twelfth resistor R12 is connected to the first end of the thirteenth resistor R13, and the connection end is used to receive the first reference signal; a first end of the fourteenth resistor R14 is used to receive the second conversion signal, a second end of the fourteenth resistor R14 is connected to the first end of the fifteenth resistor R15, and the connection end is used to receive the second reference signal;

[0125] The second end of the thirteenth resistor R13 is respectively connected to the second end of the fifteenth resistor R15, the first end of the sixteenth resistor R16, the first end of the seventh capacitor C7, and the inverting input terminal of the second operational amplifier OP92, and the non-inverting input terminal of the second operational amplifier OP92 is grounded; the output end of the second operational amplifier OP92 is respectively connected to the second end of the seventh capacitor C7 and the second end of the sixteenth resistor R16, and the connected ends serve as the output ends of the detection processing sub-circuit 42 for phase-sensitive detection.

[0126] In this embodiment, a superposition type synchronous detection circuit is formed by a superposition device. The first end of the twelfth resistor R12 and the first end of the fourteenth resistor R14 are two input ends of the synchronous detection circuit to receive the first conversion signal and the second conversion signal that require phase-sensitive detection. And as described above, Figure 9 The following description is based on an embodiment in which a second bandpass filter circuit 50 and a second differential amplifier circuit 60 are provided. Therefore, the detection processing subcircuit 42 specifically performs phase-sensitive detection on the first signal to be processed CF+ and the second signal to be processed CF-. That is, the first end of the twelfth resistor R12 and the first end of the fourteenth resistor R14 specifically receive the first signal to be processed CF+ and the second signal to be processed CF- that require phase-sensitive detection. Through phase-sensitive detection, the output of the detection processing subcircuit 42, that is, the output of the phase-sensitive detection circuit, is obtained, which is called the phase-sensitive detection sum. Figure 9 Marked as XMJB.

[0127] The demodulation circuit 43 needs to filter out the high-frequency carrier signal component in the output of the phase-sensitive detection circuit, which can be achieved by a low-pass filter circuit, thereby obtaining a signal related to the measured capacitance. For example, in a specific embodiment of the present invention, see Figure 10 , the demodulation circuit 43 may include: a second low-pass filter circuit 431, a seventeenth resistor R17, an eighteenth resistor R18 and a third operational amplifier OP3;

[0128] The input end of the second low-pass filter circuit 431 is used to receive the output of the phase-sensitive detection circuit, so as to demodulate the output of the phase-sensitive detection circuit and output a phase-sensitive demodulation result;

[0129] The non-inverting input terminal of the third operational amplifier OP3 is connected to the output terminal of the second low-pass filter circuit 431, and the inverting input terminal of the third operational amplifier OP3 is connected to the first terminal of the seventeenth resistor R17 and the first terminal of the eighteenth resistor R18 respectively;

[0130] The second end of the seventeenth resistor R17 is grounded, and the second end of the eighteenth resistor R18 is connected to the output end of the third operational amplifier OP3, and the connection end serves as the output end of the demodulation circuit 43 to use the output of the demodulation circuit 43 as the detection result of the extracted capacitance corresponding to the measured position.

[0131] exist Figure 10 In the embodiment, second low-pass filter circuit 431 is specifically a second LC series-parallel low-pass filter circuit, which has smaller in-band ripple. In other embodiments, for example, a multi-order Butterworth low-pass filter composed of an operational amplifier and resistors and capacitors can be used to implement the required second low-pass filter circuit. The output of second low-pass filter circuit 431 is amplified by third operational amplifier OP3, and the result obtained is the output of demodulation circuit 43, which serves as the detection result of the capacitance corresponding to the measured position, recorded as XMJT. The capacitance of the measured position can be subsequently obtained by analyzing the value of XMJT.

[0132] In a specific embodiment of the present invention, please refer to Figure 4 , and may also include:

[0133] The static capacitance compensation circuit 70 is used to compensate the first detection signal and the second detection signal to eliminate the static capacitance component generated by the bipolar capacitive sensor 10 in the first detection signal and the second detection signal.

[0134] This embodiment takes into account the distributed capacitance of the wires of the bipolar capacitive sensor 10, and the bipolar capacitive sensor 10 itself also has a certain amount of leakage capacitance. These additional static capacitances will lead to reduced output accuracy. In particular, when the bipolar capacitive sensor 10 needs to use long-distance transmission, the distributed capacitance will be very large, which can easily cause the output of the capacitance detection device to exceed the limit. To this end, this embodiment provides a static capacitance compensation circuit 70 to compensate the first detection signal and the second detection signal, thereby effectively eliminating the output caused by the static capacitance component and reducing the impact of long-distance transmission on the output signal accuracy of the capacitance detection device of this application. The specific structure of the static capacitance compensation circuit 70 and the specific type of the compensation signal output can be determined according to actual needs. For example, in one scenario, in order to reduce costs, the output of the anti-phase excitation generating circuit 22 can be connected to the static capacitance compensation circuit 70, and the static capacitance compensation circuit 70 performs amplification to a certain extent to obtain a first compensation signal UR+B having the same frequency and phase as the first excitation carrier UR+A but a different amplitude, and a second compensation signal UR-B having the same frequency and phase as the second excitation carrier UR-A but a different amplitude, as the first compensation signal and the second compensation signal output by the static capacitance compensation circuit 70. The specific amplitudes of the first compensation signal and the second compensation signal can be set and adjusted through experiments so that when the capacitance of the measured position is not detected, the static capacitance component caused by the static capacitance does not exist in the compensated first detection signal and the second detection signal.

[0135] The technical solution provided by the embodiments of the present invention utilizes a bipolar capacitive sensor driven by symmetrical, anti-phase voltages and transmits signals differentially. This provides strong immunity to parasitic capacitance interference from long transmission lines between two electrodes, which varies substantially synchronously and randomly, as well as synchronous (common-mode) interference from external electric fields. Specifically, the bipolar capacitive sensor comprises a first detection electrode and a second detection electrode, and can output first and second capacitance signals, respectively, reflecting the capacitance at the measured location, detected by the first and second detection electrodes. To achieve long-distance differential transmission, the first and second capacitance signals require modulation. Specifically, the first and second capacitance signals are excited by symmetrical, anti-phase first and second excitation carrier waves provided by an excitation generation circuit, thereby generating modulated first and second detection signals. Furthermore, since changes in the capacitance signal also generate changes in charge, and the first and second detection signals reflect these changes in charge and are relatively weak, a capacitance-to-voltage conversion circuit is required to convert the capacitance signal to a voltage signal and amplify the signal using differential amplification to generate the first and second converted signals. Subsequently, the detection processing circuit performs phase-sensitive demodulation on the first conversion signal and the second conversion signal based on the reference signal to obtain a phase-sensitive demodulation result. Finally, the detection result of the capacitance corresponding to the measured position can be extracted from the phase-sensitive demodulation result. It can be seen that from signal detection to the entire transmission process, it is completed in a differential manner. Therefore, it can have a strong suppression ability for common-mode interference such as parasitic capacitance interference and external electric fields that are basically synchronous and randomly changing in the long transmission line of the two electrodes, which effectively improves the accuracy of capacitance detection of the present application solution.

[0136] See Figure 11 , is a schematic diagram of simulation waveforms in a specific embodiment of the present invention. The first curve is a simulated capacitance signal, that is, when performing this simulation, the capacitance of the measured position changes in the form of this curve. The second curve is a low-pass demodulation signal, that is, the phase-sensitive demodulation result output by the second low-pass filter circuit 431 in the demodulation circuit 43, and the third curve is the detection result, that is, the detection result output by the detection processing circuit 40, that is, the detection result output by the output end of the third operational amplifier OP3. It can be seen that the changes in the output detection results effectively reflect the changes in the capacitance of the measured position, which means that the capacitance detection device of the present application has high detection accuracy.

[0137] The fourth curve is the output XMJB of the phase-sensitive detection circuit. The fifth and sixth curves are the first signal to be processed, CF+, and the second signal to be processed, CF-, respectively. The seventh and eighth curves are the positive synchronization signal and the negative synchronization signal, respectively. The ninth and tenth curves are the first excitation carrier wave UR+A and the second excitation carrier wave UR-A, respectively. The signal generation locations in the respective circuits of curves 4 through 10 can be found in the relevant descriptions above and will not be repeated here.

[0138] Corresponding to the above embodiments of the capacitance detection device, the present invention also provides a gap detection device, which can be referenced in conjunction with the above. Of course, in other embodiments, in addition to gap detection, the capacitance detection device of the present application can also be used in other occasions.

[0139] It should also be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0140] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention. Specific examples are used in this application to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A capacitance detection device, characterized in that: include: a bipolar capacitive sensor having a first detection electrode and a second detection electrode, configured to output a first capacitance signal and a second capacitance signal respectively detected by the first detection electrode and the second detection electrode and reflecting the capacitance of the measured position; an excitation generating circuit, configured to apply excitation to the first capacitance signal and the second capacitance signal based on a symmetrically anti-phased first excitation carrier and a second excitation carrier, to obtain modulated first detection signals and second detection signals; a capacitance-to-voltage conversion circuit, configured to receive the first detection signal and the second detection signal, and convert the capacitance signal into a voltage signal and amplify the signal in a differential amplification manner to obtain a first conversion signal and a second conversion signal; a detection processing circuit, configured to perform phase-sensitive demodulation on the first conversion signal and the second conversion signal based on a reference signal to obtain a phase-sensitive demodulation result, and extract a detection result of the capacitance corresponding to the measured position from the phase-sensitive demodulation result; An impedance matching circuit is provided in the excitation generating circuit, and the impedance matching circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor; The first end of the fifth resistor is used to receive the first excitation carrier, the second end of the fifth resistor is connected to the first end of the sixth resistor, and the connection end is used to receive the first capacitance signal, the first end of the seventh resistor is used to receive the second excitation carrier, the second end of the sixth resistor is connected to the second end of the seventh resistor, and the connection end serves as the first output end of the impedance matching circuit to output the first detection signal; The first end of the eighth resistor is used to receive the second excitation carrier, the second end of the eighth resistor is connected to the first end of the ninth resistor, and the connection end is used to receive the second capacitance signal, the first end of the tenth resistor is used to receive the first excitation carrier, the second end of the ninth resistor is connected to the second end of the tenth resistor, and the connection end serves as the second output end of the impedance matching circuit to output the second detection signal; Wherein, the first excitation carrier and the second excitation carrier are symmetrically in anti-phase; The detection processing circuit includes: a phase-sensitive detection circuit, configured to perform phase-sensitive detection on the first conversion signal and the second conversion signal based on a reference signal; a demodulation circuit, configured to demodulate the output of the phase-sensitive detection circuit to obtain a phase-sensitive demodulation result, and extract a detection result of the capacitance corresponding to the measured position from the phase-sensitive demodulation result; The phase-sensitive detection circuit comprises: a reference signal extraction subcircuit, configured to extract, based on the first conversion signal and the second conversion signal, a first reference signal and a second reference signal having the same frequency as the first conversion signal and the second conversion signal and a phase error within a set range; The detection processing sub-circuit is used to perform phase-sensitive detection on the first conversion signal and the second conversion signal based on the first reference signal and the second reference signal.

2. The capacitance detection device according to claim 1, characterized in that: The capacitance-to-voltage conversion circuit is a capacitance-to-voltage conversion circuit based on a first fully differential operational amplifier, or a differentially symmetrical capacitance-to-voltage conversion circuit based on two operational amplifiers.

3. The capacitance detection device according to claim 2, characterized in that: When the capacitance-to-voltage conversion circuit is a capacitance-to-voltage conversion circuit based on a first fully differential operational amplifier, the capacitance-to-voltage conversion circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and a first fully differential operational amplifier; The first end of the first resistor serves as the first input end of the capacitor-voltage conversion circuit to receive the first detection signal; the first end of the second resistor serves as the second input end of the capacitor-voltage conversion circuit to receive the second detection signal; the second end of the first resistor is respectively connected to the first end of the first capacitor, the first end of the third resistor, and the non-inverting input end of the first fully differential operational amplifier, and the second end of the second resistor is respectively connected to the first end of the second capacitor, the first end of the fourth resistor, and the inverting input end of the first fully differential operational amplifier; The first output end of the first fully differential operational amplifier is connected to the second end of the first capacitor and the second end of the third resistor, respectively, and the connection end serves as the first output end of the capacitor-voltage conversion circuit to output the first conversion signal; the second output end of the first fully differential operational amplifier is connected to the second end of the second capacitor and the second end of the fourth resistor, respectively, and the connection end serves as the second output end of the capacitor-voltage conversion circuit to output the second conversion signal.

4. The capacitance detection device according to claim 1, wherein: The excitation generating circuit comprises: an oscillator circuit for providing a clock signal; an anti-phase excitation generating circuit, configured to generate a first square wave signal and a second square wave signal having symmetrical anti-phases based on the clock signal; a first bandpass filter circuit, configured to filter the first square wave signal and the second square wave signal to generate a first sinusoidal wave signal and a second sinusoidal wave signal that are symmetrical and inverted; a first differential amplifier circuit, configured to differentially amplify the first sinusoidal wave signal and the second sinusoidal wave signal to generate a first excitation carrier wave and a second excitation carrier wave that are symmetrical and inversely phased; The impedance matching circuit is used to apply excitation to the first capacitance signal and the second capacitance signal based on the first excitation carrier and the second excitation carrier, and perform impedance matching to obtain modulated first detection signal and second detection signal.

5. The capacitance detection device according to claim 4, characterized in that: The excitation generation circuit further includes: A first low-pass filter circuit is provided between the first band-pass filter circuit and the first differential amplifier circuit and is used to suppress oscillation of high-frequency signals.

6. The capacitance detection device according to claim 1, characterized in that: Also includes: a second bandpass filter circuit connected to the capacitor-to-voltage conversion circuit, configured to filter the first conversion signal and the second conversion signal; a second differential amplifier circuit connected to the second band-pass filter circuit, configured to differentially amplify the output of the second band-pass filter circuit to generate a first signal to be processed and a second signal to be processed that are symmetrically inverted; Correspondingly, the detection processing circuit is specifically used to: perform phase-sensitive demodulation on the first signal to be processed and the second signal to be processed based on the reference signal to obtain a phase-sensitive demodulation result, and extract the detection result corresponding to the capacitance of the measured position from the phase-sensitive demodulation result.

7. The capacitance detection device according to claim 1, characterized in that: The reference signal extraction subcircuit is specifically configured to extract, based on the first conversion signal and the second conversion signal, a first reference signal and a second reference signal having the same frequency and phase as the first conversion signal and the second conversion signal.

8. The capacitance detection device according to claim 7, characterized in that: The reference signal extraction subcircuit includes: a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, an eleventh resistor, a first operational amplifier, a first OD gate, and a second OD gate; The first end of the third capacitor is used to receive the first conversion signal, the first end of the fourth capacitor is used to receive the second conversion signal, the second end of the third capacitor is connected to the first end of the fifth capacitor and the first end of the eleventh resistor respectively, and the second end of the fourth capacitor is connected to the first end of the sixth capacitor and the second end of the eleventh resistor respectively; The second end of the fifth capacitor is connected to the inverting input terminal of the first operational amplifier, the second end of the sixth capacitor is connected to the non-inverting input terminal of the first operational amplifier, the first output terminal of the first operational amplifier is connected to the input terminal of the first OD gate, and the second output terminal of the first operational amplifier is connected to the input terminal of the second OD gate; the output terminal of the first OD gate is used to output the extracted first reference signal, and the output terminal of the second OD gate is used to output the extracted second reference signal.

9. The capacitance detection device according to claim 1, wherein: The detection processing sub-circuit includes: a seventh capacitor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a second operational amplifier; The first end of the twelfth resistor is used to receive the first conversion signal, the second end of the twelfth resistor is connected to the first end of the thirteenth resistor, and the connection end is used to receive the first reference signal; the first end of the fourteenth resistor is used to receive the second conversion signal, the second end of the fourteenth resistor is connected to the first end of the fifteenth resistor, and the connection end is used to receive the second reference signal; The second end of the thirteenth resistor is respectively connected to the second end of the fifteenth resistor, the first end of the sixteenth resistor, the first end of the seventh capacitor and the inverting input end of the second operational amplifier, and the non-inverting input end of the second operational amplifier is grounded; the output end of the second operational amplifier is respectively connected to the second end of the seventh capacitor and the second end of the sixteenth resistor, and the connection end serves as the output end of the detection processing sub-circuit for phase-sensitive detection.

10. The capacitance detection device according to claim 1, wherein: The demodulation circuit includes: a second low-pass filter circuit, a seventeenth resistor, an eighteenth resistor and a third operational amplifier; The input end of the second low-pass filter circuit is used to receive the output of the phase-sensitive detection circuit, so as to demodulate the output of the phase-sensitive detection circuit and output a phase-sensitive demodulation result; The non-inverting input terminal of the third operational amplifier is connected to the output terminal of the second low-pass filter circuit, and the inverting input terminal of the third operational amplifier is connected to the first terminal of the seventeenth resistor and the first terminal of the eighteenth resistor respectively; The second end of the seventeenth resistor is grounded, the second end of the eighteenth resistor is connected to the output end of the third operational amplifier, and the connection end serves as the output end of the demodulation circuit to use the output of the demodulation circuit as the detection result of the extracted capacitance corresponding to the measured position.

11. The capacitance detection device according to any one of claims 1 to 10, characterized in that: Also includes: The static capacitance compensation circuit is used to compensate the first detection signal and the second detection signal to eliminate the static capacitance component generated by the bipolar capacitive sensor in the first detection signal and the second detection signal.

12. A gap detection device, characterized in that: The device comprises a capacitance detection device as claimed in any one of claims 1 to 11.

Images