Parallel detection method, CIS test board card and semiconductor test equipment

Abstract

According to the parallel detection method, the CIS test board card and the semiconductor test equipment provided by the invention, the probe station is controlled to move so as to connect the probe connector on the probe station with the pin of the chip to be tested, and the light source system is controlled to provide the test light source for the chip to be tested; controlling a switching circuit to switch a signal detected by the probe station to an image test system or a DC test system; acquiring detection information of the chip to be tested acquired by the image test system or the DC test system; and testing the to-be-tested chip based on the detection information, so that automatic testing can be realized, and the testing time can be saved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing technology, and in particular, relates to a parallel detection method, a CIS test board and a semiconductor testing device. Background Art

[0002] CMOS image sensor (CIS, Complementary Metal-Oxide-Semiconductor ImageSensor) chip is the core component of the camera, and the camera is an important part of all smart technologies. At present, CIS chips have been widely used in mobile phones, cameras, automotive electronics, security and other fields. With the progress of the times, the functions of designed chips are becoming more and more diverse and complex. However, the existing ATE test machine has a cumbersome test process for high-end CIS chips, and the test time and test cost increase. Summary of the invention

[0003] The embodiments of the present application provide a parallel detection method, a CIS test board and a semiconductor test device, which can save test time.

[0004] In a first aspect, an embodiment of the present application provides a parallel detection method, comprising:

[0005] Controlling the probe station to move so as to connect the probe connector on the probe station to the pin of the chip to be tested, and controlling the light source system to provide a test light source for the chip to be tested;

[0006] Controlling the switching circuit to switch the signal detected by the probe station to the image testing system or the DC testing system;

[0007] Acquire detection information of the chip to be tested collected by the image testing system or the DC testing system;

[0008] The chip to be tested is tested based on the detection information.

[0009] In some embodiments, when the detection information is image information, obtaining the detection information of the chip to be tested collected by the image testing system includes:

[0010] Sending an image acquisition instruction to the image test system, wherein the image test system is used to control the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and create a corresponding number of virtual channels according to the number of virtual channels, and align the created virtual channels with the multiple virtual channels output by the chip under test, and perform pixel alignment on the image data of each virtual channel, compress the aligned image data in each virtual channel, and send it;

[0011] When compressed image data is received, decompression is performed to obtain the image data.

[0012] In some embodiments, when the detection information is electrical test information, acquiring the detection information of the chip to be tested collected by the DC test system includes:

[0013] Sending a test instruction to a DC test system, wherein upon receiving the test instruction, the DC test system controls the hardware in the DC test system to perform an electrical test on the chip to be tested based on a mapping definition file of hardware resources corresponding to chip pins, and collects and sends test data;

[0014] Acquire electrical test information of the chip to be tested collected by the DC test system.

[0015] In some embodiments, the method further comprises:

[0016] The detection information is sent to a plurality of test computers, wherein the test computers perform parallel calculations when acquiring the detection information.

[0017] In a second aspect, an embodiment of the present application provides a parallel detection device, comprising:

[0018] A first control module is used to control the probe station to move so as to connect the probe connector on the probe station with the pin of the chip to be tested, and control the light source system to provide a test light source for the chip to be tested;

[0019] A second control module is used to control the switching circuit to switch the signal detected by the probe station to the image testing system or the DC testing system;

[0020] An acquisition module, used for acquiring the detection information of the chip to be tested collected by the image test system or the DC test system;

[0021] A testing module is used to test the chip to be tested based on the detection information.

[0022] In a third aspect, an embodiment of the present application provides a CIS test board, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described in the first aspect when executing the computer program.

[0023] In a fourth aspect, an embodiment of the present application provides a semiconductor testing device, comprising: a CIS test board, an image testing system, a DC testing system, a light source system, a switching circuit and a probe station, wherein the CIS test board is communicatively connected to the image testing system, the DC testing system, the light source system and the probe station, the probe station is communicatively connected to the image testing system and the DC testing system through the switching circuit, the probe station is used to place the chip to be tested, and receives instructions from the CIS test board to move to connect the probe connector on the probe station with the pins of the chip to be tested, the light source system is used to provide a test light source for testing the chip to be tested, the switching circuit is electrically connected to the DC testing system, the switching circuit is used to receive control of the DC testing system, and transfer the signal detected by the probe station to the image testing system or the DC testing system, the image testing system is used to perform image acquisition test on the chip to be tested, and the DC testing system is used to perform electrical test on the chip to be tested.

[0024] In some embodiments, the image testing system includes: an image acquisition card and a test computer, wherein the image acquisition card is communicatively connected to the CIS test board and the test computer, and the test computer is communicatively connected to the CIS test board. The image acquisition card is used to transmit the image acquired by the chip to be tested to the test computer, and the test computer is used to test the image transmitted by the image acquisition card when receiving the image test instruction of the CIS test board. The test computer is also used to output the test result to the CIS test board, and the CIS test board is used to display the test result.

[0025] In some embodiments, the test computer is further used to issue an image acquisition instruction to the image acquisition card;

[0026] The image acquisition card is used to control the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and create a corresponding number of virtual channels according to the number of virtual channels, and align the created virtual channels with the multiple virtual channels output by the chip under test, and perform pixel alignment on the image data of each virtual channel, compress the aligned image data in each virtual channel, and send it to the test computer. After receiving the compressed image data, the test computer decompresses it to obtain the image data, wherein the image acquisition card immediately transmits the compressed data packet to the test computer.

[0027] In some embodiments, the test computer includes multiple test computers, and the multiple test computers are communicatively connected to the CIS test board through a switch. The probe connector of the probe station can connect to multiple chips to be tested. The image acquisition card sends an image of a chip to be tested to the corresponding test computer based on the image acquisition instruction sent by each test computer. Each test computer is used to test the image of a chip to be tested.

[0028] In some embodiments, the DC test system is used to:

[0029] Creating a test project engineering, wherein the test project engineering includes: a mapping definition file of hardware resources corresponding to chip pins, and a uniformly coded resource channel number corresponding to the chip pins;

[0030] Compile a test file based on the test project engineering, and deploy and load the compiled test file;

[0031] When a test instruction is received, the hardware in the DC test system is controlled based on a mapping definition file of hardware resources corresponding to chip pins to perform electrical testing on the chip to be tested, collect test data, and send the test data to the CIS test board.

[0032] In some embodiments, the light source system is capable of detecting and calibrating the quality of the light source.

[0033] In some embodiments, the light source system is used to:

[0034] Acquire image data of the chip to be tested acquired under different light source brightnesses, and calculate a light source calibration coefficient based on the image data of the chip to be tested acquired under different light source brightnesses;

[0035] Determining whether the light source calibration coefficient is within the card control range;

[0036] When the light source calibration coefficient is within the control range, the light source system is calibrated for color temperature.

[0037] In some embodiments, the light source system is further used for:

[0038] Get the set color temperature and light source brightness;

[0039] Acquire the light source calibration coefficient and time stored in the registration table based on the color temperature;

[0040] Determining whether a calibration inspection period has been exceeded based on the time;

[0041] When the calibration inspection period is exceeded, a prompt message is output to prompt that the light source system needs to be recalibrated for color temperature;

[0042] When the calibration check period is not exceeded, the brightness of the light source is compensated based on the light source calibration coefficient.

[0043] In some embodiments, the probe station is used to:

[0044] When the chip to be tested is loaded, sending instructions to the CIS test board so that the CIS test board sends instructions to the probe station;

[0045] When the instruction is obtained, detecting parameter information of the chip to be tested, and sending the parameter information to the CIS test board, so that the CIS test board sends an acupuncture instruction;

[0046] When the needle insertion instruction is obtained, a needle pressing operation is performed to connect the probe connector of the probe station to the chip to be tested, so as to test the chip to be tested.

[0047] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the methods described above is implemented.

[0048] In a sixth aspect, an embodiment of the present application provides a computer program product, which, when executed on a terminal device, enables a CIS test board to execute any of the methods described above.

[0049] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0050] The parallel detection method provided in the embodiment of the present application controls the movement of the probe station to connect the probe connector on the probe station with the pin of the chip to be tested, and controls the light source system to provide a test light source for the chip to be tested; controls the switching circuit to switch the signal detected by the probe station to the image testing system or the DC testing system; obtains the detection information of the chip to be tested collected by the image testing system or the DC testing system; and tests the chip to be tested based on the detection information, thereby realizing automated testing and saving testing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0052] Figure 1A schematic diagram of the structure of a semiconductor testing device provided in an embodiment of the present application;

[0053] Figure 2 A schematic diagram of image transmission provided in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of a data packet transmission provided in an embodiment of the present application;

[0055] Figure 4 A schematic diagram of a connection structure between a plurality of test computers and the CIS test board through a switch provided in an embodiment of the present application;

[0056] Figure 5 A schematic diagram of a calibration process of a light source system provided in an embodiment of the present application;

[0057] Figure 6 A schematic diagram of a spot inspection process of a light source system provided in an embodiment of the present application;

[0058] Figure 7 A schematic diagram of a parallel detection method for implementing the present invention;

[0059] Figure 8 A schematic diagram of the structure of the CIS test board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0061] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0062] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0063] As used in the specification of this application and the appended claims, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrases "if it is determined" or "if it is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce detected" or "in response to detecting" depending on the context.

[0064] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0065] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0066] Based on the technical problems of the related technology, an embodiment of the present application provides a semiconductor testing device, including: a CIS test board, an image testing system, a DC testing system, a light source system, a switching circuit and a probe station, wherein the CIS test board is communicatively connected with the image testing system, the DC testing system, the light source system and the probe station, the probe station is communicatively connected with the image testing system and the DC testing system through the switching circuit, the probe station is used to place the chip to be tested, and receives instructions from the CIS test board to move to connect the probe connector on the probe station with the pin of the chip to be tested, the light source system is used to provide a test light source for testing the chip to be tested, the switching circuit is electrically connected with the DC testing system, the switching circuit is used to receive control of the DC testing system, and transfer the signal detected by the probe station to the image testing system or the DC testing system, the image testing system is used to perform image acquisition test on the chip to be tested, and the DC testing system is used to perform electrical test on the chip to be tested.

[0067] In the embodiment of the present application, the CIS test board is responsible for the business logic of the entire semiconductor test equipment, data interaction processing and coordination of the process work of each system. The CIS test board can be an electronic control unit (ECU).

[0068] In the embodiment of the present application, the DC test system can be an automatic test machine (Automated Test Equipment, ATE), and the ATE adopts an embedded system architecture of FPGA+ARM, wherein the FPGA mainly realizes the parallel processing of high-speed data related to electrical testing, and the ARM mainly realizes the process control, human-computer interaction, external communication and FPGA control functions of the DC test system. The hardware resources of the DC test system are planned and defined at the software level to virtualize the resources, and the hardware circuit resources of the DC test system are uniformly coded by channel (AET channel), which does not correspond to the actual hardware channel (pogo pin) one by one. There are many ATE channels, including DCL, PMU, PPMU, BDPS, DPS, User Relay, GPIO, etc. Different types of ATE channels are independently coded, and the AC and DC test enable outputs of various types of ATE channels, compensation and other parameters are all uniformly allocated to storage space for independent storage. All hardware device channels are independent through software virtualization and unified coding, making the software internal communication, data processing, and resource access operations simpler and more convenient, and can realize multi-threaded concurrent processing, make full use of multi-core central processing units (CPUs) to complete multi-chip parallel testing, and reduce test time.

[0069] In the embodiment of the present application, with the customized software and hardware communication mechanism, while ensuring the synchronization and reliability of software and hardware instruction execution, the advantages of the communication mechanism within the system are fully utilized, the communication process is simplified, and the efficiency of software and hardware interaction is greatly improved. At the same time, the interdependence of accessing various hardware resources is reduced, so that all hardware resources of the same type have universality, resources are fully utilized, and it is also convenient for engineers to reduce the time cycle of test engineering development when programming and developing multi-chip test engineering.

[0070] In an embodiment of the present application, the image testing system may include: an image acquisition card and a testing computer.

[0071] In the embodiment of the present application, the image acquisition card can be based on the ARM architecture, and the image acquisition card has a high-speed Docking connector interconnecting the Prober Card, which can simultaneously acquire image data output by multiple virtual channels of the chip to be tested. The software architecture of the image acquisition card fully utilizes the processing power of the multi-core central processing unit (CPU) logic core, and uses a multi-process image acquisition and transmission scheme to bind the specified process to the specified logic core to ensure the image acquisition rate of multi-chip parallel testing. After the image acquisition is completed, a lossless image compression method is used to reduce the size of the transmitted data. When the image data is transmitted to the test computer, it can be transmitted based on the GigE Vision standard protocol of Gigabit Ethernet image transmission, thereby improving the bandwidth occupancy rate. The test computer stores a test program for testing the acquired image.

[0072] In the embodiment of the present application, the light source system can integrate a standard light source control protocol and encapsulate an open general serial communication control interface, so that users can control the test light source required by the test chip through the CIS test board. At the same time, the light source system has a built-in light source spot inspection and calibration algorithm, which can perform light source quality detection and precise calibration operations, and eliminate the changes in the test light intensity caused by the unstable light source driving power supply and the changes in light intensity caused by the long-term aging of the light source luminous material, thereby eliminating the test errors caused by this and achieving the purpose of improving the test accuracy.

[0073] In an embodiment of the present application, the probe station is used to store the chip to be tested. The probe station can control the chip to be tested by moving so as to make the pins of the chip at the specified coordinate position contact with the pin-card connector. The pin-card connector supports the Cable mode or the Docking mode to transfer the chip pin signal.

[0074] In the embodiment of the present application, the chip to be tested may be a CIS chip, which has image output MIPI signal pins in addition to conventional electrical characteristic IO signal pins.

[0075] In the embodiment of the present application, by setting up a switching circuit, the signals output by the electrical characteristic IO signal pin and the image output MIPI pin can be directly connected to the image acquisition card or the DC test system.

[0076] In an embodiment of the present application, when performing a DC test, the chip signal pin is transferred out from the DC connector via a Cable line, and the ATE tester completes the electrical test related to the chip signal pin, and the test data results interact with the main control ECU via the PICE communication protocol.

[0077] In the embodiment of the present application, when performing image testing, the image acquisition card completes image data acquisition. Since the image data of high-end CIS chips is huge, when multiple chips are tested in parallel, the image data is transmitted to multiple test PCs via high-speed optical fiber for algorithm data analysis and processing testing. Multiple test PCs are networked through switches and complete the interaction with the test result data of the main control ECU through network protocols.

[0078] In the embodiment of the present application, the switching circuit may include: a relay. When the DC test system obtains the test instruction sent by the CIS test board, the DC test system outputs high and low levels of the gpio to control the relay, thereby realizing the signal access of the chip signal pin to the DC test system or the image test system.

[0079] In the embodiment of the present application, the light source system can switch the light source according to the instructions of the CIS test board, and the probe station can perform automatic cycle testing according to the instructions of the CIS test board.

[0080] Figure 1 A schematic diagram of the structure of a semiconductor testing device provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, in Figure 1 In the test, the CIS test board takes the main control ECU as an example, the DC test system takes the ATE test machine as an example, the image test system includes: image acquisition card and test computer PC, and the probe station includes: pin card connector. Figure 1 As shown, high-speed MIPI signals can be transmitted between the image acquisition card and the signal switching circuit, 10GbE network communication can be used between the image acquisition card and the test PC, the test PC communicates with the main control ECU through a switch, a 1GbE network is used between the switch and the main control ECU, the main control ECU and the ATE test machine communicate using PCIE, the switching circuit is connected to the pin card connector, the light source system and the main control ECU can communicate through the serial port, and the main control ECU and the probe station communicate through the GPIB protocol.

[0081] The detection process of the semiconductor testing equipment provided in the embodiment of the present application is as follows:

[0082] First, place the chip to be tested on the probe station. The probe station controls the movement of the chip pins at the specified coordinate position to contact the pin card connector. The pin card connector supports the Cable method or the Docking method to transfer the chip pin signal. Since the CIS chip has image output MIPI signal pins in addition to the conventional electrical characteristic IO signal pins, in order to meet the different test requirements of chip DC test and image (IMAGE), the chip pin signal transferred out of the pin card connector is transferred to a transfer circuit to directly connect the DC test signal pin and the image test signal pin or to the image acquisition board or DC test system through relay switching. The DC test and IMAGE test switching can be flexibly controlled through relay switching. When performing DC test When the chip signal pins are transferred out from the DC connector through the Cable line, the ATE tester completes the electrical test related to the chip signal pins, and the test results interact with the main control ECU through the PICE communication protocol. When the IMAGE test is performed, the image acquisition card completes the image data acquisition. Due to the huge image data of high-end CIS chips, the image data is transmitted to multiple test PCs through high-speed optical fiber for algorithm data analysis and processing tests when multiple chips are tested in parallel. Multiple test PCs are networked through switches and complete the interaction of test result data with the main control ECU through network protocols. During image testing, the main control ECU completes the light source scene switching through the serial port control protocol. During automated testing, the main control ECU controls the probe station through the GPIB card through the standard IEEE 488 communication protocol to complete automated cycle testing.

[0083] In some embodiments, the image testing system includes: an image acquisition card and a test computer, wherein the image acquisition card is communicatively connected to the CIS test board and the test computer, and the test computer is communicatively connected to the CIS test board. The image acquisition card is used to transmit the image acquired by the chip to be tested to the test computer, and the test computer is used to test the image transmitted by the image acquisition card when receiving the image test instruction of the CIS test board. The test computer is also used to output the test result to the CIS test board, and the CIS test board is used to display the test result.

[0084] In the embodiment of the present application, since the CIS chip requires high resolution and high frame rate, high-speed data acquisition and transmission is particularly important. Therefore, the communication between the image acquisition card and the test computer can be optical fiber communication. The image acquisition card has a high-speed Docking connector to interconnect the Prober Card. The MIPI C-PHY acquisition rate is as high as 4.0Gsps / Trio and supports 1 / 2 / 3Trio. The high-speed optical fiber transmission solution can reach a rate of 40Gbps. The software architecture fully utilizes the logical core processing power of the multi-core central processing unit (CPU), and adopts a multi-process image acquisition and transmission solution to bind the specified process to the specified logical core. A single image acquisition board can open four Video devices at the same time, and the image data output by multiple virtual channels of 4 chip sensors are collected in parallel based on the V4l2 framework, which greatly optimizes the hardware structure space and hardware cost.

[0085] In some embodiments, the test computer is further configured to:

[0086] Sending an image acquisition instruction to the image acquisition card;

[0087] The image acquisition card is used to control the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and create a corresponding number of virtual channels according to the number of virtual channels, and align the created virtual channels with the multiple virtual channels output by the chip under test, and perform pixel alignment on the image data of each virtual channel, compress the aligned image data in each virtual channel, and send it to the test computer. After receiving the compressed image data, the test computer decompresses it to obtain the image data, wherein the image acquisition card immediately transmits the compressed data packet to the test computer.

[0088] In the embodiment of the present application, the test computer can send instructions through network communication to inform the data acquisition device to operate the currently connected image sensor device to output multi-virtual channel image data. Secondly, the image acquisition board receives the instruction, creates a corresponding number of drive objects according to the number of virtual channels, aligns the drive objects with the virtual channels in the data acquisition device, and each drive object only obtains the virtual channel image data related to itself.

[0089] The image acquisition card can be a data acquisition device, and the test computer can be a host computer.

[0090] Figure 2 A schematic diagram of an image transmission provided in an embodiment of the present application, such as Figure 2 As shown, the data acquisition device may include: an ARM chip, a communication module and application software, and the host computer includes: a communication module and test software.

[0091] The data output module of the image sensor outputs multi-virtual channel image data, and the image data of a single virtual channel will be sent to the virtual channel in the corresponding ARM. For example, the image data of virtual channel 1 will be sent to virtual channel 1 in the ARM chip, and the other virtual channels are similar. The application software compresses the acquired image data of multiple virtual channels using a lossless image compression method to reduce the size of the transmitted data, and then integrates them into one image data and sends it to the host computer through the communication module.

[0092] In the embodiment of the present application, the communication protocol of the communication module may be a GigE Vision standard protocol for image transmission based on 10 Gigabit Ethernet.

[0093] In the embodiment of the present application, the image is losslessly compressed in a pixel-aligned manner according to the 4-pixel 5-byte storage format transmitted on the MIPI line with the maximum MTU byte number. In the embodiment of the present application, a custom streaming transmission of a packet is immediately transmitted after a packet of data is packed, so as to minimize the idle time between algorithm processing and transmission. Figure 3 A schematic diagram of a data packet transmission provided in an embodiment of the present application, such as Figure 3 As shown, a data packet is sent immediately after being packaged, and the host computer decompresses and restores the transmitted data to the original data image after receiving it.

[0094] In some embodiments, the test computer includes multiple test computers, and the multiple test computers are communicatively connected to the CIS test board through a switch. The probe connector of the probe station can connect to multiple chips to be tested. The image acquisition card sends an image of a chip to be tested to the corresponding test computer based on the image acquisition instruction sent by each test computer. Each test computer is used to test the image of a chip to be tested.

[0095] Figure 4 A schematic diagram of a connection structure between a plurality of test computers and the CIS test board through a switch provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, a master control ECU can communicate with multiple test host computers through a switch.

[0096] In the embodiment of the present application, the test computer finally obtains the image data and performs corresponding algorithm calculation test.

[0097] In the embodiment of the present application, due to the huge amount of image data of high-end CIS chips and the complex and cumbersome image algorithm functions, the traditional single PC host computer performs multi-process or multi-threaded testing. Due to the limited CPU processing power, it is impossible to guarantee parallel testing of multiple chips. The disadvantage of serial testing is that image testing is time-consuming. This solution uses a single PC tester to be responsible for the test of one chip to be tested. When multiple chips are tested in parallel, multiple PC host testers are networked with the main control ECU through switch routing. The main control ECU is responsible for controlling the test instructions to be sent to the PC host tester for parallel testing through Socket network communication. After the test computer completes the test, it returns the test result data to the main control ECU. The main control ECU is only responsible for summarizing, analyzing and processing the test result data. The PC host computers perform image tests in parallel without interfering with each other, which greatly saves image testing time.

[0098] In some embodiments, the DC test system is used to:

[0099] Creating a test project engineering, wherein the test project engineering includes: a mapping definition file of hardware resources corresponding to chip pins, and a uniformly coded resource channel number corresponding to the chip pins;

[0100] Compile a test file based on the test project engineering, and deploy and load the compiled test file;

[0101] When a test instruction is received, the hardware in the DC test system is controlled based on a mapping definition file of hardware resources corresponding to chip pins to perform electrical testing on the chip to be tested, collect test data, and send the test data to the CIS test board.

[0102] In the embodiment of the present application, in multi-chip testing, the types and quantities of hardware resources required are large, which makes the development of the test program relatively difficult, and the resource circuits are uniformly coded for channel virtualization.

[0103] In the embodiment of the present application, the DC test system takes the full DIG digital single board ATE test machine as an example. The frame has a total of 9 slots (Slot), Slot5 is the ECU main control single board, Slots 1 to 4 and 6 to 9 are DC function test DIG digital single boards, and the DIG digital single board has a total of four block (Block) devices. Each block (Block) device adopts the ARM+FPGA design architecture, including PE, PMU, PPMU, BDPS, GPIO and other resources. PE and PPMU resources are 32 input and output channels, PMU resources are 4 input and output channels, BDPS resources are 2 input and output channels, and GPIO resources are 6 input and output channels. The hardware links of PE, PMU, and PPMU resources remain consistent to the outside, and the access operations are relatively independent through the switch (Relay), and the software virtualization is unified as IO resources. IO channel is uniformly coded as 0~1023 (8*4*32) according to the slot sequence and the single block device sequence of each slot, PMU channel is uniformly coded as 0~128 (8*4*4), BDPS channel is uniformly coded as 0~63 (8*4*2), GPIO channel is uniformly coded as 0~192 (4*4*6+24+4*4*6), ARM architecture has low cost, rich interface resources, low power consumption, and is good at logic control, etc. FPGA architecture is good at multi-channel or high-speed AD acquisition, interface expansion, and high-speed signal transmission, but the cost is very high. Compared with the traditional pure ARM or pure FPGA single architecture design, the DC test system based on ARM+FPGA distributed architecture can bring combined advantages such as performance, cost, and power consumption. ARM and FPGA quickly exchange data through internal custom high-speed communication protocols. The two perform their respective duties and give full play to the unique advantages of the original architecture, which can meet the fast sampling and high-precision requirements of DC test data of high-end CIS chips.

[0104] After unifying the hardware test resources, the measurement resources are uniformly described as ATE Channel. Multiple boards or boards of different types contain multiple ATE Channels, and multiple MCU+FPGA modules are used to process all control channels. Due to the strong controllability of ARM logic and rich interface resources, each MCU+FPGA module is controlled by a PCIe card. The host computer program Meta communicates with the internal MCU of the board using high-speed PCIE communication in a custom "function code + data length + frame sequence number request / response data + cumulative checksum" protocol frame format. The self-developed PCIE driver not only implements the basic communication protocol that satisfies the interaction of multi-chip test data according to the business logic encapsulation, but also has good real-time performance, high large file read and write rate, and multi-threaded concurrent call processing capabilities.

[0105] In the C800 model A1024, there are 32 FPGA+MCU modules to process these channels, and each MCU+FPGA module processes 32 channels at different locations. When multiple chips are tested in parallel, the test pins of the chips are distributed on multiple different ATE Channels. After the software uniformly encodes the hardware virtual resources, it can find the MCU+FPGA module that needs to perform measurement actions according to all ATE Channels specified by the user and send the ATE Channel that each module is concerned about. The control ATE Channel parameters sent by the upper-layer business interface need to be represented by a 32-bit bitmap according to the ATE Channel managed by the FPGA+MCU module on the current PCIe card.

[0106] In the embodiment of the present application, the software layer can simultaneously read and write data and issue test instructions to the PCIe card through multi-threaded concurrent execution, which lays an important foundation for parallel DC testing of multiple chips.

[0107] At the same time, the DC electrical test indicators of CIS chips are complex and cumbersome, and the accuracy requirements are very high. When the output of peripherals such as PPMU, PMU, and DPS is measured, correction compensation is required to meet the design performance indicators, and the correction values ​​of different channels are also different. If the MCU is used to control the FPGA so that the peripheral output measurement can only be performed in serial mode, the parallel execution efficiency of multiple chips will be greatly reduced. ARM uses a rich external interface to save the correction compensation value gain and offset of each channel and each function of each peripheral in the external eeprom memory. When in use, the MCU writes the correction compensation value gain and offset of each channel and each function of each peripheral into the FPGA through SPI, and the compensation correction value function action is decentralized to the FPGA end. When measuring the output, the FPGA searches for the corresponding gain and offset through channel addressing for algorithm fitting, giving full play to the high-speed signal transmission that FPGA is good at, and performing multi-channel and high-speed AD data acquisition.

[0108] In the embodiment of the present application, in order to facilitate the programming and development of multi-chip test projects by engineers and improve the time cycle of test project development, the connection between users and hardware device resources is reduced, and the mapping definition file of the hardware resources corresponding to the chip pins and the uniformly encoded resource channel number corresponding to the chip pins need to be defined. The compiler can perform lexical grammar analysis on this custom syntax and compile it into a machine language recognizable by the program. Users do not need to care about the hardware resource device objects in the future. It is more convenient and familiar for users to directly reference the chip pin operation for chip testing.

[0109] In order to meet the test efficiency, PCIE communication is selected for the interaction between the main control ECU and the underlying hardware devices during the test. In addition to implementing the basic communication protocol for multi-chip test data interaction according to the business logic encapsulation, the self-developed PCIE driver requires good real-time performance and high large file reading and writing speed, as well as multi-threaded concurrent call processing capabilities.

[0110] By uniformly encoding hardware virtual resources and compiling custom compiler resource mapping syntax, user engineering development achieves seamless access to hardware devices. However, when testing a single pin or multiple pins of multiple chips, the operated resources belong to multiple hardware device objects. The hardware device objects use PCIE cards for communication control. Internally, all test resources used by the test pins are reorganized and allocated to all test channels according to uniformly encoded channels. The resource channels that need to be operated are uniformly bound to the specified PCIE card, and then parallel operations are used to perform communication tests on the PCIE card. After receiving the instructions, the underlying MCU also uses parallel processing for the operations of each resource channel. Parallel operations use the characteristics of multi-core central processing units (CPUs) to greatly shorten the multi-chip test time.

[0111] During multi-chip testing, the AC and DC test enable outputs, compensation calls and other parameters of various types of ATE channels are all uniformly allocated to storage space and stored independently. The test instructions use the channel to find the parameters that need to be loaded and called to ensure that parameter access will not conflict and that the test is carried out in parallel.

[0112] After the test is completed, the CIS test board's test data is stored and the results are displayed.

[0113] In an embodiment of the present application, the test machine project may include *.pro files, *.pat / *.dec files and .h / .cpp files. The pro file is mainly a project management property maintenance file, the dec file is a mapping definition file of the hardware resources corresponding to the chip pins, and the pat file is a chip pin AC waveform level definition file. These two types of files use different custom compilers to generate .h / .cpp files, and finally are compiled as a whole into an executable .dll file with C++ syntax.

[0114] For example, suppose that the resource virtualization channel relationship of a certain project 4Site and chip pins are connected through PCB and other wiring is as follows:

[0115]

[0116]

[0117]

[0118]

[0119] The .dec file defines the uniformly encoded resource channel number corresponding to the chip pin. The format of the .dec file can be "chip pin name = test machine resource virtualization channel number = chip pin number = test machine resource type". When testing multiple chips, you only need to change the test machine resource virtualization channel number, separated by a colon to distinguish multiple chips. Taking the above resource channel mapping relationship as an example, the resource channel mapping definition of 4site parallel testing is as follows:

[0120] PIN_LIST(XX)

[0121] { / / PinName=site1:site2:site3:site4=dut#=type;

[0122] MD3NC2C=352:320:288:256=1=IO;

[0123] MD3PC2B=353:321:289:257=2=IO;

[0124] MD1NC2A=354:322:290:258=3=IO;

[0125] MD1PC1C=355:323:291:259=4=IO;

[0126] MCNC1B=356:324:292:260=5=IO;

[0127] MCPC1A=357:325:293:261=6=IO;

[0128] MD0NC0C=358:326:294:262=7=IO;

[0129] MD0PC0B=359:327:295:263=8=IO;

[0130] MD2NC0A=360:328:296:264=9=IO;

[0131] MD2P=361:329:297:265=10=IO;

[0132] GPIO0=362:330:298:266=11=IO;

[0133] GPIO1=363:331:299:267=12=IO;

[0134] GPIO2=364:332:300:268=13=IO;

[0135] GPIO3=365:333:301:269=14=IO;

[0136] GPIO4=366:334:302:270=15=IO;

[0137] GPIO5=367:335:303:271=16=IO;

[0138] EFSYNC=368:336:304:272=17=IO;

[0139] FSYNC=369:337:305:273=18=IO;

[0140] XSHUTDN0=370:338:306:274=19=IO;

[0141] XSHUTDN1=371:339:307:275=20=IO;

[0142] SID0=372:340:308:276=21=IO;

[0143] SID1=373:341:309:277=22=IO;

[0144] SID2=374:342:310:278=23=IO;

[0145] SCL=375:343:311:279=24=IO;

[0146] SDA=376:344:312:280=25=IO;

[0147] EXTCLK=377:345:313:281=26=IO;

[0148] PWDNB=378:346:314:282=27=IO;

[0149] I3CEN=379:347:315:283=28=IO;

[0150] LEDSTROBE=380:348:316:284=29=IO;

[0151] TM=381:349:317:285=30=IO;

[0152] ISPEN=382:350:318:286=31=IO;

[0153] DOVDD=383:351:319:287=32=IO;

[0154] AVDD=22:20:18:16=34=BDPS;

[0155] DVDD=23:21:19:17=33=BDPS;

[0156] }.

[0157] The definition format of the .pat file is "the start line specifies the reference resource definition channel mapping .dec file, and then the HEADER specifies the chip pin name to be tested, SPM_PATTERN represents each cycle by row, **The middle specifies the AC waveform level vector of the chip pin name input and output by column, followed by various microinstructions, and then ends with a semicolon". When testing multiple chips, only the waveform level vector of the chip pin needs to be defined, and the user does not need to care about the resource channel. The format is as follows:

[0158]

[0159] In the embodiment of the present application, the .dec file directly corresponds to the uniformly coded resource channel number of the chip pin. When testing a certain pin of multiple chips, it is actually a resource channel collection test. The .pat file directly references the pin definition of the .dec file. The user only needs to define the input and output levels of the corresponding chip pin. The compiler can perform lexical and grammatical analysis on this custom syntax and compile it into a machine language that can be recognized by the program. During the generation process, lexical and grammatical analysis is performed to check whether the resources are conflicting and valid. The user does not need to care about the hardware resource device object for subsequent test operations. The specified chip pin operation is directly referenced during the test, making it easier and more familiar for the user.

[0160] The C++ recognizable machine language generated after compiling the above chip pin resource channel mapping .dec file is as follows:

[0161] ATESDK::Pin MD3NC2C("MD3NC2C",ATESDK::IO,{352,320,288,256});

[0162] ATESDK::Pin MD3PC2B("MD3PC2B",ATESDK::IO,{353,321,289,257});

[0163] ATESDK::Pin MD1NC2A("MD1NC2A",ATESDK::IO,{354,322,290,258});

[0164] ATESDK::Pin MD1PC1C("MD1PC1C",ATESDK::IO,{355,323,291,259});

[0165] ATESDK::Pin MCNC1B("MCNC1B",ATESDK::IO,{356,324,292,260});

[0166] ATESDK::Pin MCPC1A("MCPC1A",ATESDK::IO,{357,325,293,261});

[0167] ATESDK::Pin MD0NC0C("MD0NC0C",ATESDK::IO,{358,326,294,262});

[0168] ATESDK::Pin MD0PC0B("MD0PC0B",ATESDK::IO,{359,327,295,263});

[0169] ATESDK::Pin MD2NC0A("MD2NC0A",ATESDK::IO,{360,328,296,264});

[0170] ATESDK::Pin MD2P("MD2P",ATESDK::IO,{361,329,297,265});

[0171] ATESDK::Pin GPIO0("GPIO0",ATESDK::IO,{362,330,298,266});

[0172] ATESDK::Pin GPIO1("GPIO1",ATESDK::IO,{363,331,299,267});

[0173] ATESDK::Pin GPIO2("GPIO2",ATESDK::IO,{364,332,300,268});

[0174] ATESDK::Pin GPIO3("GPIO3",ATESDK::IO,{365,333,301,269});

[0175] ATESDK::Pin GPIO4("GPIO4",ATESDK::IO,{366,334,302,270});

[0176] ATESDK::Pin GPIO5("GPIO5",ATESDK::IO,{367,335,303,271});

[0177] ATESDK::Pin EFSYNC("EFSYNC",ATESDK::IO,{368,336,304,272});

[0178] ATESDK::Pin FSYNC("FSYNC",ATESDK::IO,{369,337,305,273});

[0179] ATESDK::Pin XSHUTDN0("XSHUTDN0",ATESDK::IO,{370,338,306,274});ATESDK::Pin XSHUTDN1("XSHUTDN1",ATESDK::IO,{371,339,307,275});ATESDK::PinSID0("SID0",ATESDK::IO,{372,340,308,276});

[0180] ATESDK::Pin SID1("SID1",ATESDK::IO,{373,341,309,277});

[0181] ATESDK::Pin SID2("SID2",ATESDK::IO,{374,342,310,278});

[0182] ATESDK::Pin SCL("SCL",ATESDK::IO,{375,343,311,279});

[0183] ATESDK::Pin SDA("SDA",ATESDK::IO,{376,344,312,280});

[0184] ATESDK::Pin EXTCLK("EXTCLK",ATESDK::IO,{377,345,313,281});

[0185] ATESDK::Pin PWDNB("PWDNB",ATESDK::IO,{378,346,314,282});

[0186] ATESDK::Pin I3CEN("I3CEN",ATESDK::IO,{379,347,315,283});

[0187] ATESDK::Pin LEDSTROBE("LEDSTROBE",ATESDK::IO,{380,348,316,284});

[0188] ATESDK::Pin TM("TM",ATESDK::IO,{381,349,317,285});

[0189] ATESDK::Pin ISPEN("ISPEN",ATESDK::IO,{382,350,318,286});

[0190] ATESDK::Pin DOVDD("DOVDD",ATESDK::IO,{383,351,319,287});

[0191] ATESDK::Pin AVDD("AVDD",ATESDK::BDPS,{22,20,18,16,30});

[0192] ATESDK::Pin DVDD("DVDD",ATESDK::BDPS,{23,21,19,17,31});

[0193] ATESDK::PinGroup IO_ALL("IO_ALL",{&MD3NC2C,&MD3PC2B,&MD1NC2A,&MD1PC1C,&MCNC1B,&MCPC1A,&MD0NC0C,&MD0PC0B,&MD2NC0A,&MD2P,&GPIO0,&GPIO1,&GPIO2,&GPIO3,&GPIO4,&GPIO5,&EFSYNC,&FSYNC,&XSHUTDN0,&XSHUTDN1,&SID0,&SID1,&SID2,&SCL,&SDA,&EXTCLK,&PWDNB,&I3CEN,&LEDSTROBE,&TM,&ISPEN});

[0194] In the .cpp file programming of C / C++ syntax, the operation interfaces such as adding voltage and current to a chip pin, measuring voltage, current, frequency, etc. are encapsulated into operations according to chip pins and specifying the operation resource channel type. When developing multi-chip parallel testing programs, software development engineers do not need to care about the hardware device objects that need to be operated when operating a chip pin. After defining the chip pin mapping resource channel in .dec, all operations in the programming process refer to the chip pin name, which greatly reduces the difficulty of software development engineers in developing multi-chip test projects where they are unfamiliar with the equipment and have complex hardware connections. The software testing system rewrites operators such as "+" and "-". When the operations of multiple chip pins are the same, the resource channels of the pin set can be reorganized to traverse and specify a single chip for operation. When specifying a single chip pin for operation, the software testing system also friendly encapsulates convenient interfaces such as SiteINC, PinINC and ParallelINC (maximum parallel operation), which greatly improves the efficiency of multi-chip testing.

[0195] In the embodiment of the present application, the .pat file is compiled to generate a C++ recognizable machine language binary .ppo file. The .ppo file mainly contains header information and a data area. The core information of the header is a resource channel with a unified hardware code corresponding to the chip-enabled pins and a waveform vector in the data area. The host computer program sends all the data information of the .ppo file to the Block device through PCIE card communication. When multiple chips are performing AC testing, there is no need to care about the hardware resources corresponding to the pins. The software automatically parses the header information to derive the corresponding hardware resources, and loads the vector data in the data area for waveform input and output comparison.

[0196] After the project development is completed, a custom integrated Flex&Bison&C compiler is used to complete the lexical parsing and compilation of dec, pat, and cpp files, and then the underlying communication library is connected and finally deployed to generate an executable binary file. When the executable binary file generated by the deployment is loaded for electrical testing, the software automatically derives and calculates the device objects that need to be operated through the resource channel defined by the program. The upper layer sends the test instructions written by the test project to the MCU integrated in each device in parallel through PCIE communication. The MCU completes the reception and parsing of each test instruction. After the instruction parsing is completed, the input and output information required for the measurement is notified to the FPGA through SPI communication, which is responsible for the logical control of the entire measurement process. The FPGA side uses its own parallel advantages to perform input and output compensation calculations to complete the measurement action. After the measurement action is completed, the MCU returns the result to the CIS test board. The CIS test board completes the parsing of the result data and stores and displays it.

[0197] In some embodiments, the light source system is capable of detecting and calibrating the light source quality.

[0198] In the embodiment of the present application, Figure 5 A schematic diagram of a calibration process of a light source system provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the light source system is used to: obtain image data of the chip to be tested obtained under different light source brightnesses, calculate the light source calibration coefficient based on the image data of the chip to be tested obtained under different light source brightnesses; determine whether the light source calibration coefficient is within the card control range; and when the light source calibration coefficient is within the card control range, perform color temperature calibration on the light source system.

[0199] In the embodiment of the present application, the chip under test can be made to continuously output image data, and the brightness of the light source is switched at this time, so as to obtain image data of the chip under test obtained under different light source brightness. In some embodiments, when the light source calibration coefficient is within the card control range, the calibration system and calibration time are also stored in the registration table, so as to perform a spot inspection process through the registration table.

[0200] In the embodiment of the present application, if the light source calibration coefficient is not within the control range, the action of switching the light source brightness continues to be executed.

[0201] In some embodiments, Figure 6 A schematic diagram of a spot inspection process of a light source system provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, it includes: obtaining the set color temperature and light source brightness; obtaining the light source calibration coefficient and time stored in the registration table based on the color temperature; determining whether the calibration inspection cycle is exceeded based on the time; if the calibration inspection cycle is exceeded, outputting a prompt message to prompt that the light source system needs to re-calibrate the color temperature; if the calibration inspection cycle is not exceeded, compensating the light source brightness based on the light source calibration coefficient.

[0202] In the embodiment of the present application, the light source system has a built-in inspection mechanism and precise calibration operation that can perform light source quality detection, thereby eliminating changes in the test light intensity caused by changes in light intensity due to unstable light source driving power supply and aging of the light source luminescent material after long-term operation, thereby eliminating the test errors caused by this and achieving the purpose of improving the accuracy of CIS image testing.

[0203] In some embodiments, the probe station is used to: when the chip to be tested is loaded, send instructions to the CIS test board so that the CIS test board sends instructions to the probe station; when the instructions are obtained, detect parameter information of the chip to be tested, and send the parameter information to the CIS test board so that the CIS test board sends a needle-piercing instruction; when the needle-piercing instruction is obtained, perform a needle pressing operation so that the probe connector of the probe station is connected to the chip to be tested so as to test the chip to be tested.

[0204] In the embodiment of the present application, there can be multiple probe stations, and one probe station can correspond to one chip to be tested (Wafer). In some embodiments, one probe station can also correspond to multiple chips to be tested. The number of chips to be tested is related to the connection capability of the pin-card connector of each probe station. Manufacturers that do not pass the test can have different pin-card connector designs. Exemplarily, the probe station can be a Prober machine. The CIS test board first creates a GPIB communication connection with the Prober machine. After the Prober machine loads the test chip to be tested, it sends a WaferStart (0x46) instruction. After the CIS test board obtains this instruction, it will send parameters to obtain the relevant information of the test chip to be tested. Then, the CIS test board sends a needle-piercing instruction (Z). After receiving the instruction, the Prober machine presses the pin card to connect the wafer to the chip to be tested by the hardware. After the connection is completed, the Prober machine sends a TestStart (0x43) instruction. The CIS test board After receiving this instruction, it will send an instruction (O) to obtain the chip to be tested and the test site index, and send an instruction (Q) to obtain the coordinates of the chip to be tested at the starting site. The CIS test board will automatically deduce and calculate the coordinate information of other chips to be tested based on the coordinates of the chip to be tested at the starting site and the offset information of other chips to be tested relative to the starting chip to be tested, and then start DC testing and image testing. After the test is completed, the DC test data and image test data results are summarized. After the summary is completed, the results are returned to the Prober machine through the instruction (M). At the same time, the relevant test data will be uploaded and stored in the database, etc. After the Prober machine receives the command, when all tests on the current chip to be tested are completed, the Prober machine sends the WaferEnd (0x51) command to eject the wafer. After receiving this command, the CIS test board will complete the test data export and other operations. If the test is not completed, it will move the pin card connector to the next chip to be tested for needle insertion. Press the pin card connector down to connect the hardware to the chip to be tested. After the connection is completed, the Prober machine sends the TestStart (0x43) command. The test system responds by continuously polling the status command of the Prober machine to achieve cyclic automated testing.

[0205] In some embodiments, the CIS test board includes: engineering development mode, production mode, maintenance mode and system management mode, four different scenarios of working modes, by integrating the four different scenarios of working modes into one, different role users log in to the system will automatically obtain the corresponding mode permissions and available tool views, unified entrance, easy system deployment. The CIS test board is mainly responsible for the business logic of the entire test system, data interaction processing, and the smooth operation of each sub-module. The entire test system has high cohesion and low coupling, which fully meets the complex test scenario requirements of high-end CIS chips.

[0206] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0207] Based on the semiconductor testing device provided in the above embodiment, the embodiment of the present application provides a parallel detection method. Figure 7 A schematic diagram of the implementation flow of a parallel detection method provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, including:

[0208] Step S701, controlling the probe station to move so as to connect the probe connector on the probe station to the pin of the chip to be tested, and controlling the light source system to provide a test light source for the chip to be tested;

[0209] Step S702, controlling the switching circuit to switch the signal detected by the probe station to an image test system or a DC test system;

[0210] Step S703, acquiring the detection information of the chip to be tested collected by the image testing system or the DC testing system;

[0211] Step S704: testing the chip to be tested based on the detection information.

[0212] In some embodiments, when the detection information is image information, obtaining the detection information of the chip to be tested collected by the image testing system includes:

[0213] Sending an image acquisition instruction to the image test system, wherein the image test system is used to control the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and create a corresponding number of virtual channels according to the number of virtual channels, and align the created virtual channels with the multiple virtual channels output by the chip under test, and perform pixel alignment on the image data of each virtual channel, compress the aligned image data in each virtual channel, and send it;

[0214] When compressed image data is received, decompression is performed to obtain the image data.

[0215] In some embodiments, when the detection information is electrical test information, acquiring the detection information of the chip to be tested collected by the DC test system includes:

[0216] Sending a test instruction to a DC test system, wherein upon receiving the test instruction, the DC test system controls the hardware in the DC test system to perform an electrical test on the chip to be tested based on a mapping definition file of hardware resources corresponding to chip pins, and collects and sends test data;

[0217] Acquire electrical test information of the chip to be tested collected by the DC test system.

[0218] In some embodiments, the testing the chip to be tested based on the detection information includes:

[0219] Sending the detection information to multiple test computers, wherein the test computers perform parallel calculations upon acquiring the detection information and obtain test results;

[0220] Obtain the test result and output the test result.

[0221] It should be noted that the information interaction, execution process and other contents of the above method are based on the same concept as the semiconductor testing equipment. Their specific functions and technical effects can be found in the description of the semiconductor testing equipment embodiment section and will not be repeated here.

[0222] Based on the aforementioned method embodiments, the embodiments of the present application further provide a parallel detection device, wherein the modules included in the device and the units included in the modules can be implemented by a processor in a computer device; of course, they can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU, Central Processing Unit), a microprocessor (MPU, Microprocessor Unit), a digital signal processor (DSP, Digital Signal Processing) or a field programmable gate array (FPGA, Field Programmable Gate Array), etc.

[0223] A first control module is used to control the probe station to move so as to connect the probe connector on the probe station with the pin of the chip to be tested, and control the light source system to provide a test light source for the chip to be tested;

[0224] A second control module is used to control the switching circuit to switch the signal detected by the probe station to the image testing system or the DC testing system;

[0225] An acquisition module, used for acquiring the detection information of the chip to be tested collected by the image test system or the DC test system;

[0226] A testing module is used to test the chip to be tested based on the detection information.

[0227] In some embodiments, the acquisition module includes:

[0228] A first sending unit, used for sending an image acquisition instruction to the image test system, wherein the image test system is used for controlling the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and creating a corresponding number of virtual channels according to the number of virtual channels, and aligning the created virtual channels with the multiple virtual channels output by the chip under test, and performing pixel alignment on the image data of each virtual channel, compressing the aligned image data in each virtual channel, and sending the compressed image data;

[0229] The first receiving unit is used to decompress the compressed image data to obtain the image data when receiving the compressed image data.

[0230] In some embodiments, the acquisition module includes:

[0231] A second sending unit is used to send a test instruction to a DC test system, wherein, when the DC test system receives the test instruction, based on a mapping definition file of hardware resources corresponding to chip pins, the DC test system controls the hardware in the DC test system to perform an electrical test on the chip to be tested, collects test data, and sends the test data;

[0232] The second receiving unit is used to obtain the electrical test information of the chip under test collected by the DC test system.

[0233] In some embodiments, the detection module includes:

[0234] A third sending unit is used to send the detection information to multiple test computers, wherein the test computers perform parallel calculations and obtain test results when obtaining the detection information;

[0235] The third receiving unit is used to obtain the test result and output the test result.

[0236] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / network device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0237] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0238] Figure 8 This is a schematic diagram of the structure of the CIS test board provided in the embodiment of the present application. Figure 8 As shown, the CIS test board 3 of this embodiment may include: at least one processor 30 ( Figure 8 Only one processor 30 is shown in the figure), a memory 31, and a computer program 32 stored in the memory 31 and executable on at least one processor 30. When the processor 30 executes the computer program 32, the steps in any of the above-mentioned method embodiments are implemented; or, when the processor 30 executes the computer program 32, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0239] Exemplarily, the computer program 32 may be divided into one or more modules / units, one or more modules / units are stored in the memory 31, and executed by the processor 30 to complete the present application. One or more modules / units may be a series of computer program 32 instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program 32 in the CIS test board 3.

[0240] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program 32. When the computer program 32 is executed by the processor 30, the steps in the above-mentioned method embodiments can be implemented.

[0241] An embodiment of the present application provides a computer program product. When the computer program product runs on a CIS test board, the CIS test board can implement the steps in the above-mentioned method embodiments when executing.

[0242] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. According to this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program 32, and the computer program 32 can be stored in a computer-readable storage medium, and the computer program 32 can implement the steps of the above-mentioned various method embodiments when executed by the processor 30. Among them, the computer program 32 includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the terminal, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0243] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0244] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0245] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0246] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0247] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A parallel detection method, characterized in that: include: Controlling the probe station to move so as to connect the probe connector on the probe station to the pin of the chip to be tested, and controlling the light source system to provide a test light source for the chip to be tested; Controlling the switching circuit to switch the signal detected by the probe station to the image testing system or the DC testing system; Acquire detection information of the chip to be tested collected by the image testing system or the DC testing system; The chip to be tested is tested based on the detection information.

2. The method according to claim 1, characterized in that In the case where the detection information is image information, obtaining the detection information of the chip to be tested collected by the image testing system includes: Sending an image acquisition instruction to the image test system, wherein the image test system is used to control the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and create a corresponding number of virtual channels according to the number of virtual channels, and align the created virtual channels with the multiple virtual channels output by the chip under test, and perform pixel alignment on the image data of each virtual channel, compress the aligned image data in each virtual channel, and send it; When compressed image data is received, decompression is performed to obtain the image data.

3. The method according to claim 1, characterized in that In the case where the detection information is electrical test information, obtaining the detection information of the chip to be tested collected by the DC test system includes: Sending a test instruction to a DC test system, wherein upon receiving the test instruction, the DC test system controls the hardware in the DC test system to perform an electrical test on the chip to be tested based on a mapping definition file of hardware resources corresponding to chip pins, and collects and sends test data; Acquire electrical test information of the chip to be tested collected by the DC test system.

4. The method according to any one of claims 1 to 3, characterized in that: The testing the chip to be tested based on the detection information includes: Sending the detection information to multiple test computers, wherein the test computers perform parallel calculations upon acquiring the detection information and obtain test results; Obtain the test result and output the test result.

5. A parallel detection device, characterized in that: include: A first control module is used to control the probe station to move so as to connect the probe connector on the probe station with the pin of the chip to be tested, and control the light source system to provide a test light source for the chip to be tested; A second control module is used to control the switching circuit to switch the signal detected by the probe station to the image testing system or the DC testing system; An acquisition module, used for acquiring the detection information of the chip to be tested collected by the image test system or the DC test system; A testing module is used to test the chip to be tested based on the detection information.

6. A CIS test board, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 4 is implemented.

7. A semiconductor testing device, characterized in that: include: A CIS test board, an image test system, a DC test system, a light source system, a switching circuit and a probe station, wherein the CIS test board is communicatively connected with the image test system, the DC test system, the light source system and the probe station, the probe station is communicatively connected with the image test system and the DC test system through the switching circuit, the probe station is used to place the chip to be tested, and receives instructions from the CIS test board to move so as to connect the probe connector on the probe station with the pin of the chip to be tested, the light source system is used to provide a test light source for testing the chip to be tested, the switching circuit is electrically connected with the DC test system, the switching circuit is used to receive control of the DC test system, and transfer the signal detected by the probe station to the image test system or the DC test system, the image test system is used to perform image acquisition test on the chip to be tested, and the DC test system is used to perform electrical test on the chip to be tested.

8. The semiconductor testing device according to claim 7, characterized in that: The image testing system includes: an image acquisition card and a test computer. The image acquisition card is communicatively connected to the CIS test board and the test computer. The test computer is communicatively connected to the CIS test board. The image acquisition card is used to transmit the image acquired by the chip to be tested to the test computer. The test computer is used to test the image transmitted by the image acquisition card when receiving the image test instruction of the CIS test board. The test computer is also used to output the test result to the CIS test board. The CIS test board is used to display the test result.

9. The semiconductor testing device according to claim 8, characterized in that: The test computer is also used for: Sending an image acquisition instruction to the image acquisition card; The image acquisition card is used to control the chip under test to output image data of multiple virtual channels when the image acquisition instruction is obtained, and create a corresponding number of virtual channels according to the number of virtual channels, and align the created virtual channels with the multiple virtual channels output by the chip under test, and perform pixel alignment on the image data of each virtual channel, compress the aligned image data in each virtual channel, and send it to the test computer. After receiving the compressed image data, the test computer decompresses it to obtain the image data, wherein the image acquisition card immediately transmits the compressed data packet to the test computer.

10. The semiconductor testing device according to claim 9, characterized in that The test computers include multiple test computers, which are communicatively connected to the CIS test board through a switch. The probe connector of the probe station can connect to multiple chips to be tested. The image acquisition card sends an image of a chip to be tested to the corresponding test computer based on an image acquisition instruction sent by each test computer. Each test computer is used to test the image of a chip to be tested.

11. The semiconductor testing device according to claim 7, characterized in that: The DC test system is also used to: Creating a test project engineering, wherein the test project engineering includes: a mapping definition file of hardware resources corresponding to chip pins, and a uniformly coded resource channel number corresponding to the chip pins; Compile a test file based on the test project engineering, and deploy and load the compiled test file; When a test instruction is received, the hardware in the DC test system is controlled based on a mapping definition file of hardware resources corresponding to chip pins to perform electrical testing on the chip to be tested, collect test data, and send the test data to the CIS test board.

12. The semiconductor testing device according to claim 7, characterized in that: The light source system can detect and calibrate the quality of the light source.

13. The semiconductor testing device according to claim 12, characterized in that The light source system is used for: Acquire image data of the chip to be tested acquired under different light source brightnesses, and calculate a light source calibration coefficient based on the image data of the chip to be tested acquired under different light source brightnesses; Determining whether the light source calibration coefficient is within the card control range; When the light source calibration coefficient is within the control range, the light source system is calibrated for color temperature.

14. The semiconductor testing device according to claim 13, characterized in that The light source system is also used for: Get the set color temperature and light source brightness; Acquire the light source calibration coefficient and time stored in the registration table based on the color temperature; Determining whether a calibration inspection period has been exceeded based on the time; When the calibration inspection period is exceeded, a prompt message is output to prompt that the light source system needs to be recalibrated for color temperature; When the calibration check period is not exceeded, the brightness of the light source is compensated based on the light source calibration coefficient.

15. The semiconductor testing device according to claim 7, characterized in that The probe station is used for: When the chip to be tested is loaded, sending instructions to the CIS test board so that the CIS test board sends instructions to the probe station; In the case of obtaining the instruction, detecting parameter information of the chip to be tested, and sending the parameter information to the CIS test board, so that the CIS test board sends an acupuncture instruction; When the needle insertion instruction is obtained, a needle pressing operation is performed to connect the probe connector of the probe station to the chip to be tested.

16. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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