Wide-input-range low-power-consumption quick-response voltage pre-stabilizing circuit and analog chip

Abstract

The invention discloses a low-power-consumption quick-response pre-voltage-stabilizing circuit with a wide input range, and an analog chip. The low-power-consumption quick-response pre-voltage-stabilizing circuit comprises a reference current source used for generating first reference voltage and second reference voltage; the current comparator is used for comparing the driving current capabilities of two transistors connected with the first pre-stabilized voltage output circuit in the current comparator, and generating a first control voltage according to a comparison result under a first reference voltage; the control circuit is used for generating a second control voltage by using the mirror image transistor pair under a second reference voltage; the first pre-voltage-stabilizing output circuit is used for generating an output voltage changing along with the input power supply voltage under the first control voltage; the second pre-voltage-stabilizing output circuit is used for generating an output voltage changing along with the input power supply voltage under the second control voltage; and the high-voltage PMOS tube in the first pre-voltage-stabilizing output circuit and the high-voltage NMOS tube in the second pre-voltage-stabilizing output circuit are in a turn-off and turn-on state in the process of changing along with the voltage of the input power supply. The circuit has the characteristics of wide input range and low power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuit design, and in particular relates to a low-power, fast-response pre-voltage regulator circuit with a wide input range and an analog chip. Background Art

[0002] The pre-regulator circuit is a basic module of the analog chip, which is used to provide a stable power supply voltage for the related startup modules before the chip is started. With the increasing application of the power supply voltage working scenarios of analog chips, the pre-regulator circuit needs to meet the application requirements of a wide voltage input range.

[0003] Traditional pre-regulator circuits such as Figure 1 As shown, the high voltage PMOS tube is generally linearly controlled by charging the resistor R with current I ( Figure 1 Indicated as MP), the high voltage NMOS tube ( Figure 1 MN in the figure), the high-voltage PMOS tube is alternately turned on at different input power supply voltages. The linear control method adopted by this structure cannot ensure the rapid conversion of the working state of the high-voltage NMOS tube and the high-voltage PMOS tube when the input power supply voltage is higher than the breakdown voltage of the Zener diode, so that the output voltage changes slowly. The traditional pre-stabilization circuit controls the on and off of the high-voltage PMOS tube, which is affected by the threshold voltage and resistance of the MOS tube. It cannot accurately control the on and off of the high-voltage PMOS tube, and the current I cannot be ignored, which deteriorates the power consumption index of the pre-stabilization circuit. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-power, fast-response pre-regulator circuit and an analog chip with a wide input range. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides a low-power, fast-response pre-regulator circuit with a wide input range, the pre-regulator circuit comprising a reference current source, a current comparator, a control circuit, a first pre-regulator output circuit and a second pre-regulator output circuit, wherein:

[0006] The reference current source is used to generate a first reference voltage and a second reference voltage; the current comparator is connected to the reference current source and is used to compare the driving current capabilities of the low threshold PMOS tube and the high voltage NMOS tube connected to the first pre-regulated output circuit in the current comparator under the action of the first reference voltage when the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode, and generate a first control voltage according to the comparison result; the control circuit is connected to the reference current source and is used to generate a second control voltage using a mirror transistor pair under the action of the second reference voltage when the input power supply voltage is greater than the breakdown voltage of the Zener diode; the first pre-regulated output circuit is used to generate an output voltage that varies with the input power supply voltage under the control of the first control voltage; wherein the first pre-regulated output The output circuit includes a high-voltage PMOS tube MP1 and a first load capacitor, the gate of the high-voltage PMOS tube MP1 is connected to the current comparator, the source of the high-voltage PMOS tube MP1 is connected to the input end of the input power supply voltage, and the drain of the high-voltage PMOS tube MP1 is grounded through the first load capacitor and serves as the output end of the output voltage; a second pre-regulated output circuit is used to generate an output voltage that varies with the input power supply voltage under the control of the second control voltage; wherein the second pre-regulated output circuit includes a high-voltage NMOS tube MN1 and a first load capacitor, the gate of the high-voltage NMOS tube MN1 is connected to the control circuit, the drain of the high-voltage NMOS tube MN1 is connected to the input end of the input power supply voltage, and the source of the high-voltage NMOS tube MN1 is grounded through the second load capacitor and serves as the output end of the output voltage;

[0007] The high-voltage NMOS transistor MN1 and the high-voltage PMOS transistor MP1 must be in an off-on state as the input power voltage changes.

[0008] In one embodiment of the present invention, the pre-stabilization circuit further includes a clamping protection circuit;

[0009] The clamping protection circuit is connected to the current comparator and the gate of the high-voltage PMOS tube MP1, and is used to limit the gate-source voltage difference of the high-voltage PMOS tube MP1.

[0010] In one embodiment of the present invention, the reference current source includes transistors N1 to N5, transistors P1 to P4, and a resistor R1; wherein,

[0011] The source of transistor P1, the source of transistor P2, and the source of transistor P3 are all connected to the input end of the input power supply voltage, the gate of transistor P1 is connected to the drain of transistor P1, the gate of transistor P2, and the drain of transistor N1, the drain of transistor P2 is connected to the gate of transistor N1, the gate of transistor N3, and the drain of transistor N3, the source of transistor N1 is connected to the drain of transistor N2, the gate of transistor N2 is connected to the source of transistor N3, the drain of transistor N4, the gate of transistor N4, the gate of transistor N5, and the current comparator, the source of transistor N2 is connected to one end of resistor R1, the source of transistor N4, the other end of resistor R1, and the source of transistor N5 are all grounded, the drain of transistor N5 is connected to the drain of transistor P4, the gate of transistor P4, and the current comparator, and the source of transistor P4 is connected to the drain of transistor P3, the gate of transistor P3, and the control circuit.

[0012] In one embodiment of the present invention, transistors N1 to N5 are all high-voltage NMOS transistors; and transistors P1 to P4 are all high-voltage PMOS transistors.

[0013] In one embodiment of the present invention, the current comparator includes transistors P6 to P8, transistor N6, and a Zener diode D1; wherein,

[0014] The source of transistor P7 and the source of transistor P8 are both connected to the input end of the input power supply voltage, the source of transistor P6 is connected to the drain of transistor P7, the gate of transistor P7, and the gate of transistor P8, the gate of transistor P6 is connected to the gate of transistor P4, the drain of transistor P6 is connected to the negative electrode of Zener diode D1, the drain of transistor P8 is connected to the drain of transistor N6 and the gate of high-voltage PMOS tube MP1, the gate of transistor N6 is connected to the gate of transistor N2, and the positive electrode of Zener diode D1 and the source of transistor N6 are both grounded.

[0015] In one embodiment of the present invention, transistors P6 to P7 are all high-voltage PMOS transistors; transistor N6 is a high-voltage NMOS transistor; and transistor P8 is a low-threshold PMOS transistor.

[0016] In one embodiment of the present invention, the clamping protection circuit includes a Zener diode D2, a cathode of the Zener diode D2 is connected to the input end of the input power supply voltage, and an anode of the Zener diode D2 is connected to the gate of the high-voltage PMOS tube MP1.

[0017] In one embodiment of the present invention, the control circuit includes a transistor P9, a transistor P 10 , transistor N7, transistor N8, resistor R2, resistor R3, Zener diode D3, Zener diode D4; wherein,

[0018] The source of transistor P9, transistor P 10 The source of the resistor R2, one end of the resistor R3 are all connected to the input end of the input power supply voltage, and the gate of the transistor P9 is connected to the transistor P 10 The gate of transistor P is connected to the gate of transistor P3, the drain of transistor P9 is connected to the source of transistor N7, the gate of transistor N8, and the cathode of Zener diode D3, and transistor P 10 The drain of transistor N7 is connected to the source of transistor N8, the gate of transistor N7, the cathode of Zener diode D4, and the gate of high-voltage NMOS tube MN1, the drain of transistor N7 is connected to the other end of resistor R2, the drain of transistor N8 is connected to the other end of resistor R3, and the anode of Zener diode D3 and the anode of Zener diode D4 are both grounded; wherein transistor P9 and transistor P 10 The mirror transistor pair is formed.

[0019] In one embodiment of the present invention, transistor P9, transistor P 10 Both are high-voltage PMOS tubes; transistor N7 and transistor N8 are both high-voltage NMOS tubes.

[0020] In a second aspect, an analog chip is provided, the analog chip comprising any one of the low power consumption and fast response pre-regulator circuits with a wide input range as described in the first aspect.

[0021] Beneficial effects of the present invention:

[0022] The low-power, fast-response pre-stabilizer circuit with a wide input range proposed in the present invention solves the problem of a low input power supply voltage range and a large output voltage fluctuation of a traditional pre-stabilizer circuit from the perspective of circuit design. Specifically: during the input power supply voltage change process, the present invention controls the high-voltage NMOS tube MN1 to work in a scenario where the input power supply voltage is greater than the breakdown voltage of the Zener diode and the high-voltage PMOS tube MP1 to work in a scenario where the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode by real-time detection of the input power supply voltage and the size of the Zener diode, so that the pre-stabilizer circuit can work in two scenarios where the input power supply voltage is relatively low and relatively high, thereby realizing a pre-stabilizer circuit with a wide input range. The present invention accurately controls the on and off moments of the high-voltage PMOS tube MP1 by current comparison, which has the advantages of The invention has the characteristics of high accuracy and high consistency of the flip point. The high gain characteristic of the current comparator is used to realize the fast switching of the high-voltage PMOS tube MP1 to respond to the change of the input power supply voltage, which can effectively avoid the problem of large output voltage fluctuation caused by the slow switching of the high-voltage PMOS tube MP1. In addition, the current comparator is more power-saving than the traditional solution, reduces power consumption, and effectively avoids the problem that the breakdown voltage of the Zener diode increases synchronously with the input power supply voltage, resulting in the deterioration of the standby power consumption index; at the same time, when the high-voltage PMOS tube MP1 is turned off, it automatically switches to the high-voltage NMOS tube MN1 to respond to the change of the input power supply voltage, and uses the control circuit to realize the rapid increase of the gate voltage of the high-voltage NMOS tube MN1, thereby improving the switching speed of the high-voltage NMOS tube MN1 and accurately controlling the conduction and shutdown of the high-voltage NMOS tube MN1. It can be seen that the high-voltage NMOS tube MN1 and the high-voltage PMOS tube MP1 are controlled to be alternately turned on by the current comparator and the control circuit, so as to realize the high-precision and rapid transformation of the working mode of the power tube, facilitate the design of each module inside the chip, and provide a new circuit structure and design ideas for the design of the wide input voltage pre-regulator circuit.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a specific circuit diagram of a traditional pre-stabilization circuit;

[0025] Figure 2 It is a structural schematic diagram of a low-power, fast-response pre-voltage regulator circuit with a wide input range provided by an embodiment of the present invention;

[0026] Figure 3 This embodiment of the present invention provides a Figure 2 The specific circuit diagram of the pre-stabilization circuit is shown. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0028] See also Figure 2 The embodiment of the present invention provides a low-power, fast-response pre-regulator circuit with a wide input range. In a first aspect, the embodiment of the present invention provides a low-power, fast-response pre-regulator circuit with a wide input range. The pre-regulator circuit includes a reference current source, a current comparator, a control circuit, a first pre-regulator output circuit and a second pre-regulator output circuit, wherein:

[0029] A reference current source is used to generate a first reference voltage and a second reference voltage; a current comparator is connected to the reference current source and is used to compare the driving current capabilities of a low-threshold PMOS tube and a high-voltage NMOS tube connected to a first pre-regulated output circuit in the current comparator under the action of the first reference voltage when the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode, and generate a first control voltage according to the comparison result; a control circuit is connected to the reference current source and is used to generate a second control voltage using a mirror transistor pair under the action of the second reference voltage when the input power supply voltage is greater than the breakdown voltage of the Zener diode; a first pre-regulated output circuit is used to generate an output voltage that varies with the input power supply voltage under the control of the first control voltage; wherein the first pre-regulated output circuit includes a high-voltage PMOS tube MP1 and a first load capacitor, the gate of the high-voltage PMOS tube MP1 is connected to the current comparator, the source of the high-voltage PMOS tube MP1 is connected to the input end of the input power supply voltage, and the drain of the high-voltage PMOS tube MP1 is connected to the input end of the input power supply voltage through the first load capacitor ( Figure 3 The second pre-regulated output circuit is used to generate an output voltage that varies with the input power supply voltage under the control of the second control voltage; wherein the second pre-regulated output circuit includes a high-voltage NMOS tube MN1 and a first load capacitor, the gate of the high-voltage NMOS tube MN1 is connected to the control circuit, the drain of the high-voltage NMOS tube MN1 is connected to the input end of the input power supply voltage, and the source of the high-voltage NMOS tube MN1 is connected to the input end of the input power supply voltage through the second load capacitor ( Figure 3 In the figure, it is shown as C2) which is grounded and serves as the output terminal of the output voltage;

[0030] The high-voltage NMOS transistor MN1 and the high-voltage PMOS transistor MP1 must be in an off-on state as the input power voltage changes.

[0031] Here, high-voltage NMOS tube, high-voltage PMOS tube, and low-threshold PMOS tube are all conventional definitions in MOS tube devices. The specific selection of high-voltage NMOS tube, high-voltage PMOS tube, and low-threshold PMOS tube is determined by the application scenario.

[0032] Please see again Figure 2In the embodiment of the present invention, the pre-stabilizing circuit further includes: a clamping protection circuit; the clamping protection circuit is connected to the current comparator and the gate of the high-voltage PMOS tube MP1, and is used to limit the gate-source voltage difference of the high-voltage PMOS tube MP1.

[0033] In the embodiment of the present invention, when the input power supply voltage AVIN is less than or equal to the breakdown voltage of the Zener diode, the high-voltage PMOS tube MP1 is turned on and operates in the linear region. At this time, the output voltage VOUT of the first pre-regulated output circuit is equal to the input power supply voltage AVIN, so that the output voltage VOUT can still have a sufficiently high power supply capacity under the condition of low input power supply voltage; when the input power supply voltage AVIN gradually increases and is greater than the breakdown voltage of the Zener diode, the Zener diode breaks down, the driving current generated by the low-threshold PMOS tube is compared with the driving current generated by the high-voltage NMOS tube, and the conduction state of the high-voltage PMOS tube MP1 is synchronously controlled. When the driving current generated by the low-threshold PMOS tube is greater than the driving current generated by the high-voltage NMOS tube, the high-voltage PMOS tube MP1 will be immediately turned off, wherein the driving current generated by the high-voltage NMOS tube is provided by the reference current source. Before the Zener diode breaks down, the gate voltage of the high-voltage NMOS tube MN1 automatically follows the input power supply voltage AVIN, and after the Zener diode breaks down, the high-voltage NMOS tube MN1 enters the saturation region, and the output voltage VOUT of the second pre-regulated output circuit is equal to the Zener diode breakdown voltage minus Vthn (Vthn is the threshold voltage of the high-voltage NMOS tube MN1), so when the high-voltage PMOS tube MP1 is turned off, the output voltage VOUT will automatically be powered by the high-voltage NMOS tube MN1. It can be seen that through the input power supply voltage, the high-voltage NMOS tube MN1 can be controlled to work in the scenario where the input power supply voltage is greater than the Zener diode breakdown voltage, and the high-voltage PMOS tube MP1 can work in the scenario where the input power supply voltage is less than or equal to the Zener diode breakdown voltage, so that the pre-regulated circuit can work in two scenarios where the input power supply voltage is low and high, and a pre-regulated circuit with a wide input range is realized.

[0034] Next, Figure 2 Each part of the pre-stabilization circuit structure shown is introduced in detail.

[0035] In the embodiment of the present invention, the reference current source is as follows: Figure 3As shown, it includes transistors N1 to N5, transistors P1 to P4, and a resistor R1; wherein the source of transistor P1, the source of transistor P2, and the source of transistor P3 are all connected to the input end of the input power supply voltage, the gate of transistor P1 is connected to the drain of transistor P1, the gate of transistor P2, and the drain of transistor N1, the drain of transistor P2 is connected to the gate of transistor N1, the gate of transistor N3, and the drain of transistor N3, the source of transistor N1 is connected to the drain of transistor N2, the gate of transistor N2 is connected to the source of transistor N3, the drain of transistor N4, the gate of transistor N4, the gate of transistor N5, and the current comparator, the source of transistor N2 is connected to one end of resistor R1, the source of transistor N4, the other end of resistor R1, and the source of transistor N5 are all grounded, the drain of transistor N5 is connected to the drain of transistor P4, the gate of transistor P4, and the current comparator, and the source of transistor P4 is connected to the drain of transistor P3, the gate of transistor P3, and the control circuit. The embodiment of the present invention uses a reference current source composed of transistors N1 to N5, transistors P1 to P4, and resistor R1 to generate a first reference voltage and a second reference voltage for a subsequent current comparator and a control circuit: the output node of the first reference voltage is at the gate of transistor N2, Figure 3 V b1 , the output node of the second reference voltage is the gate of the transistor P3, Figure 3 V b2 .

[0036] In the embodiment of the present invention, transistors N1 to N5 are all high-voltage NMOS transistors; transistors P1 to P4 are all high-voltage PMOS transistors.

[0037] Furthermore, the current comparator in the embodiment of the present invention is as follows: Figure 3As shown, it includes transistors P6 to P8, transistor N6, and a Zener diode D1; wherein the source of transistor P7 and the source of transistor P8 are both connected to the input end of the input power supply voltage, the source of transistor P6 is connected to the drain of transistor P7, the gate of transistor P7, and the gate of transistor P8, the gate of transistor P6 is connected to the gate of transistor P4, the drain of transistor P6 is connected to the negative electrode of Zener diode D1, the drain of transistor P8 is connected to the drain of transistor N6 and the gate of high-voltage PMOS tube MP1, the gate of transistor N6 is connected to the gate of transistor N2, and the positive electrode of Zener diode D1 and the source of transistor N6 are both grounded. The embodiment of the present invention reasonably sets the width-to-length ratio of transistors P3, P4 and P6 so that when Zener diode D1 fails to break down, the voltage V3 at the gate of transistor P7 does not change with the rise of input power supply voltage AVIN, until the Zener diode D1 breaks down and the voltage difference between input power supply voltage AVIN and voltage V3 is greater than the threshold voltage of transistor P8, transistor P8 is turned on, at which time the driving current of transistor P8 is much greater than the current of transistor N6 copying the reference current source, transistor P8 enters the linear region and outputs the first control voltage, so that the high-voltage PMOS tube MP1 quickly enters the cut-off region, thereby improving the transient response speed of the system in the process of transitioning from low input power supply voltage to high input power supply voltage. The first control voltage output by the current comparator is Figure 3 In the figure, it is denoted as V1. When the input power voltage is less than or equal to the breakdown voltage of the Zener diode, the first control voltage V1 is the input power voltage AVIN; when the input power voltage AVIN is greater than the breakdown voltage of the Zener diode, the first control voltage V1 is 0, that is, AGND.

[0038] In the embodiment of the present invention, transistors P6 to P7 are all high-voltage PMOS transistors; transistor N6 is a high-voltage NMOS transistor; and transistor P8 is a low-threshold PMOS transistor.

[0039] Furthermore, the clamping protection circuit in the embodiment of the present invention is as follows: Figure 3 As shown, it includes a Zener diode D2, the cathode of the Zener diode D2 is connected to the input end of the input power supply voltage, and the anode of the Zener diode D2 is connected to the gate of the high-voltage PMOS tube MP1.

[0040] Furthermore, the control circuit in the embodiment of the present invention is as follows Figure 3 As shown, it includes transistor P9, transistor P 10 , transistor N7, transistor N8, resistor R2, resistor R3, Zener diode D3, Zener diode D4; wherein the source of transistor P9, transistor P 10 The source of the resistor R2, one end of the resistor R3 are all connected to the input end of the input power supply voltage, and the gate of the transistor P9 is connected to the transistor P 10The gate of transistor P is connected to the gate of transistor P3, the drain of transistor P9 is connected to the source of transistor N7, the gate of transistor N8, and the cathode of Zener diode D3, and transistor P 10 The drain of transistor N7 is connected to the source of transistor N8, the gate of transistor N7, the cathode of Zener diode D4, and the gate of high-voltage NMOS tube MN1, the drain of transistor N7 is connected to the other end of resistor R2, the drain of transistor N8 is connected to the other end of resistor R3, and the anode of Zener diode D3 and the anode of Zener diode D4 are both grounded; wherein transistor P9 and transistor P 10 When the high-voltage PMOS tube MP1 enters the cut-off region under the action of the first control voltage V1, the control circuit passes through the transistors P9 and P 10 The mirror transistor pair formed by the control circuit copies the current of the reference current source, and after stabilization, the transistor N7 and the transistor N8 enter the cut-off region and output the second control voltage. The second control voltage reaches the breakdown voltage of the Zener diode, the Zener diode D3 and the Zener diode D4 break down, and the high-voltage NMOS tube MN1 enters the saturation region. The second control voltage output by the control circuit is Figure 3 It is denoted as V2.

[0041] Here, through transistor P9, transistor P 10 The mirror transistor pair composed of the transistors N7 and N8 copies the current of the reference current source, and realizes the rapid power-on of the gate terminal parasitic capacitance of the high-voltage NMOS tube MN1 through the cross-coupling structure composed of the transistors N7 and N8, which improves the transient response speed of the system in the process of changing from a low input power supply voltage to a high input power supply voltage. After stabilization, the transistors N7 and N8 enter the cut-off region. Under the premise of improving the transient response, only the transistors P9 and P8 are added. 10 of static power consumption.

[0042] In the embodiment of the present invention, transistor P9 and transistor P 10 Both are high-voltage PMOS tubes, and transistor N7 and transistor N8 are both high-voltage NMOS tubes.

[0043] In the embodiment of the present invention, the Zener diodes D1 , D2 , D3 , and D4 have the same breakdown voltage.

[0044] The working process of the pre-stabilizing circuit of the present invention includes:

[0045] When the input power supply voltage AVIN is less than the breakdown voltage of the Zener diode, the Zener diode D1 fails to break down, the transistor P6 operates in the linear region, the voltage V3 changes with the input power supply voltage AVIN, the transistor P8 operates in the cut-off region, and its driving current is much smaller than the current of the reference current source copied by the transistor N6. The first control voltage V1 is pulled down to AGND, the high-voltage PMOS tube MP1 enters the linear region, the Zener diode D2 is used to limit the gate-source voltage difference of the high-voltage PMOS tube MP1 to prevent the high-voltage PMOS tube MP1 from breaking down, the output voltage VOUT of the first pre-regulated output circuit is equal to the input power supply voltage AVIN, because the Zener diode D4 fails to break down, the second control voltage V2 is equal to the input power supply voltage AVIN, the gate-source voltage difference of the high-voltage NMOS tube MN1 is zero, and the high-voltage NMOS tube MN1 enters the cut-off region.

[0046] When the input power supply voltage AVIN gradually exceeds the Zener diode breakdown voltage, the Zener diode D1 breaks down. By reasonably setting the width-to-length ratio of transistors P3, P4, and P6, the voltage V3 is kept constant until the voltage difference between the input power supply voltage AVIN and the voltage V3 is greater than the threshold voltage of transistor P8. Then, transistor P8 is turned on. By setting the width-to-length ratio of transistor P8, it is ensured that the driving current of transistor P8 when turned on is much greater than the current of transistor N6 copying the reference current source. The first control voltage V1 is quickly pulled up to the input power supply voltage AVIN, and the high-voltage PMOS tube MP1 enters the cut-off region. At the same time, the second control voltage V2 rises to the Zener diode breakdown voltage through the control circuit, and the Zener diodes D3 and D4 break down. The second control voltage V2 is constant, and the high-voltage NMOS tube MN1 enters the saturation region. The output voltage VOUT of the second pre-regulated output circuit is equal to the second control voltage V2 minus the threshold voltage of the high-voltage NMOS tube MN1.

[0047] Here, the width-to-length ratio of transistors P3, P4, P6, and P8 is not limited as long as the requirements are met. For example, the width-to-length ratio of transistors P3, P4, and P6 is designed to ensure that the voltage V3 remains constant when the input voltage is less than the breakdown voltage of the Zener diode, and the width-to-length ratio of transistor P8 is designed to ensure that the driving current of transistor P8 is much larger than the current of the reference current source copied by transistor N6.

[0048] Compared with the traditional pre-stabilization circuit, the present invention uses current comparison to control the on and off of the high-voltage PMOS tube MP1, accurately controls the on and off moments of the high-voltage PMOS tube MP1 and the high-voltage NMOS tube MN1, and utilizes the high gain characteristics of the current comparator to enable the node first control voltage V1 to change rapidly, thereby achieving a rapid transition of the working state of the high-voltage PMOS tube MP1. In terms of power consumption, after the output state of the current comparator is stable, the power consumption is only determined by the transistor with a small current in transistor N6 and transistor P8. Therefore, compared with the traditional pre-stabilization circuit, it has the advantage of low power consumption. In addition, the pre-stabilization circuit proposed in the present invention also uses transistors P9 and transistors P 10 The method of copying the current of the reference current source replaces the traditional solution of using resistors to charge the Zener diodes D3 and D4, which further reduces the power consumption and improves the consistency of the overall control solution.

[0049] The pre-stabilization circuit of the present invention can quickly respond to output a stable VOUT when the input power supply voltage AVIN is powered on quickly. When the input power supply voltage AVIN is powered on quickly, the high-voltage NMOS tube MN1 is affected by the parasitic capacitance of the gate terminal, and the transistor P 10 The speed at which the current generated at the drain of the transistor P9 charges the node second control voltage V2 is much lower than the speed at which the drain of the transistor P9 charges the node voltage V4. At this time, the transient voltage difference between the second control voltage V2 and the voltage V4 is greater than the threshold voltage of the transistor N8. The transistor N8 is turned on and the current is supplied to the Zener diode D4 to realize accelerated charging until the transistor N8 enters the cut-off region and the accelerated charging ends. The resistor R2 and the resistor R3 are used to reduce the transient overshoot current of the transistor N7 and the transistor N8.

[0050] In summary, the low-power, fast-response pre-stabilizer circuit with a wide input range proposed in the embodiment of the present invention solves the problem of low input power supply voltage range and large output voltage fluctuation of the traditional pre-stabilizer circuit from the perspective of circuit design. Specifically: during the change of the input power supply voltage, the embodiment of the present invention controls the high-voltage NMOS tube MN1 to work in a scenario where the input power supply voltage is greater than the breakdown voltage of the Zener diode and the high-voltage PMOS tube MP1 to work in a scenario where the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode by real-time detection of the input power supply voltage and the size of the Zener diode, so that the pre-stabilizer circuit can work in two scenarios where the input power supply voltage is low and high, thereby realizing a pre-stabilizer circuit with a wide input range; the embodiment of the present invention accurately controls the conduction and switching of the high-voltage PMOS tube MP1 by current comparison. At the turn-off moment, it has the characteristics of high accuracy and high consistency of the flip point. The high gain characteristic of the current comparator is used to realize the fast switching of the high-voltage PMOS tube MP1 to respond to the change of the input power supply voltage, which can effectively avoid the problem of large output voltage fluctuation caused by the slow switching of the high-voltage PMOS tube MP1. In addition, the current comparator is more power-saving than the traditional solution, reduces power consumption, and effectively avoids the problem that the breakdown voltage of the Zener diode increases synchronously with the input power supply voltage, resulting in the deterioration of the standby power consumption index; at the same time, when the high-voltage PMOS tube MP1 is turned off, it automatically switches to the high-voltage NMOS tube MN1 to respond to the change of the input power supply voltage, and uses the control circuit to realize the rapid increase of the gate voltage of the high-voltage NMOS tube MN1, thereby improving the switching speed of the high-voltage NMOS tube MN1 and accurately controlling the conduction and shutdown of the high-voltage NMOS tube MN1. It can be seen that the high-voltage NMOS tube MN1 and the high-voltage PMOS tube MP1 are controlled to be alternately turned on by the current comparator and the control circuit, realizing the high-precision and rapid transformation of the power tube working mode, facilitating the design of each module inside the chip, and providing a new circuit structure and design idea for the design of wide input voltage pre-regulator circuit.

[0051] In a second aspect, an analog chip is provided, the analog chip comprising any one of the low power consumption and fast response pre-regulator circuits with a wide input range as described in the first aspect.

[0052] As for the analog chip embodiment of the second aspect, since it is basically similar to the circuit embodiment of the first aspect, the description is relatively simple, and the relevant parts may refer to the partial description of the circuit embodiment of the first aspect.

[0053] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0054] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0055] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A low power consumption fast response pre-regulator circuit with wide input range, characterized in that: The pre-stabilization circuit includes a reference current source, a current comparator, a control circuit, a first pre-stabilization output circuit and a second pre-stabilization output circuit, wherein: The reference current source is used to generate a first reference voltage and a second reference voltage; the current comparator is connected to the reference current source and is used to compare the driving current capabilities of the low threshold PMOS tube and the high voltage NMOS tube connected to the first pre-regulated output circuit in the current comparator under the action of the first reference voltage when the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode, and generate a first control voltage according to the comparison result; the control circuit is connected to the reference current source and is used to generate a second control voltage using a mirror transistor pair under the action of the second reference voltage when the input power supply voltage is greater than the breakdown voltage of the Zener diode; the first pre-regulated output circuit is used to generate an output voltage that varies with the input power supply voltage under the control of the first control voltage; wherein the first pre-regulated output The output circuit includes a high-voltage PMOS tube MP1 and a first load capacitor, the gate of the high-voltage PMOS tube MP1 is connected to the current comparator, the source of the high-voltage PMOS tube MP1 is connected to the input end of the input power supply voltage, and the drain of the high-voltage PMOS tube MP1 is grounded through the first load capacitor and serves as the output end of the output voltage; a second pre-regulated output circuit is used to generate an output voltage that varies with the input power supply voltage under the control of the second control voltage; wherein the second pre-regulated output circuit includes a high-voltage NMOS tube MN1 and a first load capacitor, the gate of the high-voltage NMOS tube MN1 is connected to the control circuit, the drain of the high-voltage NMOS tube MN1 is connected to the input end of the input power supply voltage, and the source of the high-voltage NMOS tube MN1 is grounded through the second load capacitor and serves as the output end of the output voltage; The high-voltage NMOS transistor MN1 and the high-voltage PMOS transistor MP1 must be in an off-on state as the input power voltage changes.

2. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 1, characterized in that: The pre-stabilization circuit also includes a clamping protection circuit; The clamping protection circuit is connected to the current comparator and the gate of the high-voltage PMOS tube MP1, and is used to limit the gate-source voltage difference of the high-voltage PMOS tube MP1.

3. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 1, characterized in that: The reference current source includes transistors N1 to N5, transistors P1 to P4, and resistor R1; wherein, The source of transistor P1, the source of transistor P2, and the source of transistor P3 are all connected to the input end of the input power supply voltage, the gate of transistor P1 is connected to the drain of transistor P1, the gate of transistor P2, and the drain of transistor N1, the drain of transistor P2 is connected to the gate of transistor N1, the gate of transistor N3, and the drain of transistor N3, the source of transistor N1 is connected to the drain of transistor N2, the gate of transistor N2 is connected to the source of transistor N3, the drain of transistor N4, the gate of transistor N4, the gate of transistor N5, and the current comparator, the source of transistor N2 is connected to one end of resistor R1, the source of transistor N4, the other end of resistor R1, and the source of transistor N5 are all grounded, the drain of transistor N5 is connected to the drain of transistor P4, the gate of transistor P4, and the current comparator, and the source of transistor P4 is connected to the drain of transistor P3, the gate of transistor P3, and the control circuit.

4. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 3, characterized in that: The transistors N1 to N5 are all high-voltage NMOS transistors; the transistors P1 to P4 are all high-voltage PMOS transistors.

5. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 3, characterized in that: The current comparator includes transistors P6 to P8, transistor N6, and Zener diode D1; wherein, The source of transistor P7 and the source of transistor P8 are both connected to the input end of the input power supply voltage, the source of transistor P6 is connected to the drain of transistor P7, the gate of transistor P7, and the gate of transistor P8, the gate of transistor P6 is connected to the gate of transistor P4, the drain of transistor P6 is connected to the negative electrode of Zener diode D1, the drain of transistor P8 is connected to the drain of transistor N6 and the gate of high-voltage PMOS tube MP1, the gate of transistor N6 is connected to the gate of transistor N2, and the positive electrode of Zener diode D1 and the source of transistor N6 are both grounded.

6. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 5, characterized in that: Transistors P6 to P7 are all high-voltage PMOS tubes; transistor N6 is a high-voltage NMOS tube; and transistor P8 is a low-threshold PMOS tube.

7. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 2, characterized in that: The clamping protection circuit includes a Zener diode D2, a cathode of the Zener diode D2 is connected to the input end of the input power supply voltage, and an anode of the Zener diode D2 is connected to the gate of the high-voltage PMOS tube MP1.

8. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 3, characterized in that: The control circuit includes a transistor P9, a transistor P 10 , transistor N7, transistor N8, resistor R2, resistor R3, Zener diode D3, Zener diode D4; wherein, The source of transistor P9, transistor P 10 The source of the resistor R2, one end of the resistor R3 are all connected to the input end of the input power supply voltage, and the gate of the transistor P9 is connected to the transistor P 10 The gate of transistor P is connected to the gate of transistor P3, the drain of transistor P9 is connected to the source of transistor N7, the gate of transistor N8, and the cathode of Zener diode D3, and transistor P 10 The drain of transistor N7 is connected to the source of transistor N8, the gate of transistor N7, the cathode of Zener diode D4, and the gate of high-voltage NMOS tube MN1, the drain of transistor N7 is connected to the other end of resistor R2, the drain of transistor N8 is connected to the other end of resistor R3, and the anode of Zener diode D3 and the anode of Zener diode D4 are both grounded; wherein transistor P9 and transistor P 10 The mirror transistor pair is formed.

9. The low power consumption and fast response pre-regulator circuit with wide input range according to claim 8, characterized in that: Transistor P9, transistor P 10 Both are high-voltage PMOS tubes; transistor N7 and transistor N8 are both high-voltage NMOS tubes.

10. An analog chip, characterized in that: The analog chip comprises a low-power, fast-response pre-regulator circuit with a wide input range as claimed in any one of claims 1 to 9.

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