Reference-free low-noise LDO circuit

Abstract

The invention discloses a reference-free low-noise LDO (Low Dropout Regulator) circuit, which relates to the field of power supply circuits and is characterized in that a connection node of a resistor R1 and a resistor R4 is grounded after sequentially passing through a resistor R2, a transistor Q5 and a resistor R3, and a control end of the transistor Q5 is connected to the connection node of the resistor R2 and the transistor Q5. A voltage input end n1 of the error amplifier module is connected to a connection node of the transistor MP6 and the transistor Q3, a voltage input end n2 of the error amplifier module is connected to a connection node of the transistor MP7 and the transistor Q4, a connection end ibias is simultaneously connected to control ends of the transistor MN7 and the transistor MN5, and an output end of the error amplifier module is connected to a control end of the power tube MPpower. The input end of the bias current module is connected to the voltage output end Vout, and the output end of the bias current module is connected to the connecting end ibias of the error amplifier module. According to the low dropout regulator, the reference circuit is contained in the whole LDO loop, a reference circuit does not need to be independently designed, the reference can be prevented from being interfered by an external circuit and directly influencing voltage output, and the low dropout regulator has better noise characteristics in low and medium frequencies.

Description

Technical Field

[0001] The invention relates to the field of power supply circuits, and in particular to a reference-free low-noise LDO circuit. Background Art

[0002] The LDO circuit, or Low Dropout Regulator, is a power management circuit used to stabilize voltage. Figure 1 and Figure 2 As shown, the main architecture of the current LDO circuit is that the PMOS device is used as the power tube (such as Figure 1 ), one is to use NMOS as the power tube (such as Figure 2 ), these two mainstream LDO architectures both consist of a reference voltage circuit, an error amplifier, a power tube, and a feedback network. However, their reference and LDO negative feedback loops are independent of each other, and the interference or noise generated by the reference cannot be suppressed by the loop. The reference noise will be directly transmitted to the output, which may cause greater noise. Summary of the invention

[0003] The purpose of the present invention is to provide a reference-free low-noise LDO circuit, which aims to overcome the problem in the prior art that interference generated by the reference or noise cannot be suppressed by the loop, and the reference noise will be directly transmitted to the output, which may cause greater noise.

[0004] To achieve the above object, the present invention provides the following technical solutions: A reference-free low-noise LDO circuit comprises a voltage input terminal Vbat, an error amplifier module, a voltage output terminal Vout, a power tube MP_power, a resistor R1 and a resistor R4; one end of the power tube MP_power is connected to the voltage input terminal Vbat, and a control end is connected to the output end of the error amplifier module; the other end of the power tube MP_power is connected to the voltage output terminal Vout; the voltage output terminal Vout is grounded via the resistor R1 and the resistor R4, and further comprises a resistor R2, a transistor Q5 and a resistor R3, a connection node between the resistor R1 and the resistor R4 is grounded via the resistor R2, the transistor Q5 and the resistor R3 in sequence, and the control end of the transistor Q5 is connected to the connection node between the resistor R2 and the transistor Q5; Also includes transistor MP7, transistor MP11, transistor Q4, transistor MP8, transistor MP9, transistor MN6, transistor MN7, transistor MP6, transistor Q3, transistor MP10, transistor MP5 and transistor MN5; The voltage output terminal Vout is connected to ground via transistor MP7, transistor Q4, transistor MP11, transistor MP8, transistor MP9, transistor MN6, transistor MN7, transistor MP6, transistor Q3, transistor MP10, transistor MP5, and transistor MN5; The control ends of the transistors MP7, MP8, MP6 and MP5 are all connected to the connection node between the transistor MP5 and the transistor MN5; the control ends of the transistors Q3 and Q4 are all connected to the connection node between the transistors MP8 and MP9; the control end of the transistor MP11 is connected to the connection node between the transistor Q5 and the resistor R2; the control end of the transistor MP9 is connected to the connection node between the transistors MN6 and MN7; the control end of the transistor MN6 is connected to the connection node between the transistors MP6 and Q3; the control end of the transistor MP10 is grounded via a resistor; The voltage input terminal n1 of the error amplifier module is connected to the connection node between transistor MP6 and transistor Q3, the voltage input terminal n2 is connected to the connection node between transistor MP7 and transistor Q4, the connection terminal ibias is simultaneously connected to the control terminals of the transistor MN7 and transistor MN5, and the output terminal is connected to the control terminal of the power tube MP_power.

[0005] Furthermore, it also includes a capacitor CL, and the voltage output terminal Vout is grounded after passing through the capacitor CL; Furthermore, a capacitor C is included, and the voltage output terminal Vout is connected to a connection node between the transistor MP7 and the transistor Q4 via the capacitor C.

[0006] Furthermore, a resistor R0 is included, and the control end of the power tube MP_power is connected to a connection node between the power tube MP_power and the voltage input end Vbat via the resistor R0.

[0007] Furthermore, the transistor Q3 , the transistor Q4 , and the transistor Q5 are all NPN transistors, and the size ratio of the transistor Q4 to the transistor Q3 is N:1.

[0008] Furthermore, the transistor MP10 and the transistor MP11 are both NMOS transistors.

[0009] Furthermore, the transistor MN6 and the transistor MN7 are both PMOS transistors, and the transistor MP9 is an NMOS transistor.

[0010] Furthermore, it also includes a bias current module, the input end of the bias current module is connected to the voltage output end Vout, and the output end is connected to the connection end ibias of the error amplifier module.

[0011] Compared with the prior art, the present invention has the following beneficial effects: In the LDO circuit disclosed in the present invention, the reference circuit is included in the entire LDO loop, and there is no need to design a separate reference circuit. This can prevent the reference from being interfered by an external circuit and directly affecting the voltage output of the LDO circuit, and can obtain better noise characteristics at medium and low frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The invention is an existing LDO circuit.

[0013] Figure 2 This is another existing LDO circuit.

[0014] Figure 3 It is a circuit schematic diagram of the present invention.

[0015] Figure 4 This is the circuit schematic diagram of the bias current module.

[0016] Figure 5 This is a partial circuit diagram of the voltage output terminal in the present invention.

[0017] Figure 6 This is a small signal model of a part of the circuit in the present invention.

[0018] Figure 7 In the present invention, Figure 6 Bode plot of the small signal model shown.

[0019] Figure 8 This is a Bode diagram of a zero and pole design scheme in the present invention.

[0020] Fig. 9 This is a Bode diagram of another zero and pole design scheme in the present invention. DETAILED DESCRIPTION

[0021] The specific implementation of the present invention is described below with reference to the accompanying drawings. In order to fully understand the present invention, many details are described below, but for those skilled in the art, the present invention can be implemented without these details.

[0022] like Figure 3 and Figure 4As shown, a reference-free low-noise LDO circuit includes a voltage input terminal Vbat, an error amplifier module, a voltage output terminal Vout, a power tube MP_power, a resistor R1 and a resistor R4. Among them, one end of the power tube MP_power is connected to the voltage input terminal Vbat for connecting to the power supply VDD. The control end of the power tube MP_power is connected to the output end of the error amplifier module, and the other end of the power tube MP_power is connected to the voltage output terminal Vout for connecting to the load. The voltage output terminal Vout is grounded after passing through the resistor R1 and the resistor R4.

[0023] The power tube MP_power includes but is not limited to an NMOS tube. Preferably, the control end of the power tube MP_power is connected to the connection node of the power tube MP_power and the voltage input end Vbat via a resistor R0. The resistor R0 can reduce the impedance of the control end of the power tube MP_power to avoid loop instability caused by the control end of the power tube MP_power being too low.

[0024] like Figure 3 As shown, the LDO circuit further includes a resistor R2, a transistor Q5 and a resistor R3, the connection node of the resistor R1 and the resistor R4 is connected to the ground via the resistor R2, the transistor Q5 and the resistor R3 in sequence, and the control end of the transistor Q5 is connected to the connection node of the resistor R2 and the transistor Q5. The resistor R1, the resistor R4, the resistor R2 and the resistor R3 form a temperature coefficient and feedback coefficient adjustment network.

[0025] As a preferred embodiment, the voltage output terminal Vout is grounded after passing through the capacitor CL. Adding the capacitor CL to the load end of the LDO circuit provides a low-frequency pole for the output, thereby improving the stability of the entire loop.

[0026] like Figure 3 As shown, the LDO circuit further includes a transistor MP7, a transistor MP11, a transistor Q4, a transistor MP8, a transistor MP9, a transistor MN6, a transistor MN7, a transistor MP6, a transistor Q3, a transistor MP10, a transistor MP5 and a transistor MN5; The voltage output terminal Vout is connected to ground via transistor MP7, transistor Q4, and transistor MP11 in sequence, connected to ground via transistor MP8 and transistor MP9 in sequence, connected to ground via transistor MN6 and transistor MN7 in sequence, connected to ground via transistor MP6, transistor Q3, and transistor MP10 in sequence, and connected to ground via transistor MP5 and transistor MN5 in sequence. In addition, the control terminals of transistor MP7, transistor MP8, transistor MP6, and transistor MP5 are all connected to the connection node between transistor MP5 and transistor MN5. The control terminals of transistor Q3 and transistor Q4 are all connected to the connection node between transistor MP8 and transistor MP9. The control terminal of transistor MP11 is connected to the connection node between transistor Q5 and resistor R2. The control terminal of transistor MP9 is connected to the connection node between transistor MN6 and transistor MN7. The control terminal of transistor MN6 is connected to the connection node between transistor MP6 and transistor Q3. The control terminal of transistor MP10 is connected to ground via a resistor.

[0027] Preferably, transistor Q3, transistor Q4, and transistor Q5 are all NPN transistors, and the size ratio of transistor Q4 to transistor Q3 is N: 1. These three devices need to be matched when drawing the layout, and transistor Q3 and transistor Q5 can be set as a single device, while the number N of transistor Q4 can be 7, 14, 23, etc., so that these three devices can be made into a square when drawing the layout, achieving a better matching process.

[0028] Preferably, the transistor MP10, the transistor MP11 and the transistor MP9 are all NMOS transistors, and the transistor MN6 and the transistor MN7 are all PMOS transistors.

[0029] Transistor MN6, transistor MN7, and transistor MP9 provide internal negative feedback to transistor Q3 and provide appropriate base potentials to transistor Q3 and transistor Q4. The reason why the ground terminal (collector) of transistor Q3 is not directly connected to its control terminal (base) is that the current gain β of the NPN transistor in the general CMOS process is small, resulting in a large base current, which ultimately leads to a large deviation in the collector current of transistor Q3 and transistor Q4, causing the temperature characteristics of the LDO circuit to deteriorate.

[0030] like Figure 3 As shown, the voltage input terminal n1 of the error amplifier module is connected to the connection node of the transistor MP6 and the transistor Q3. The voltage input terminal n2 of the error amplifier module is connected to the connection node of the transistor MP7 and the transistor Q4. The connection terminal ibias of the error amplifier module is simultaneously connected to the control terminals of the transistor MN7 and the transistor MN5, and the output terminal is connected to the control terminal of the power tube MP_power.

[0031] Preferably, the voltage output terminal Vout is connected to the connection node between the transistor MP7 and the transistor Q4 via the capacitor C. That is, the capacitor C is added between the voltage output terminal Vout and the voltage input terminal n2, and is an internal device of the LDO circuit. The capacitor C provides a zero point for the loop to improve the stability of the loop.

[0032] like Figure 3 As shown, the error amplifier module specifically includes transistor MP1, transistor MP2, transistor MP3, transistor MP4, transistor MN3, transistor MN4, transistor MN11, transistor MN12, transistor MN1 and transistor MN2. After transistor MP4 is connected in series with transistor MN4 and transistor MP3 is connected in series with transistor MN3, transistor MP4 and transistor MP3 are both connected to the voltage output terminal Vout, transistor MN4 and transistor MN3 are both connected to one end of transistor MN2, and the other end of transistor MN2 is grounded. Among them, the control end of transistor MP4 is connected to the connection node between it and transistor MN4, the control end of transistor MP3 is connected to the connection node between it and transistor MN3, the control end of transistor MN4 is the voltage input terminal n2 of the error amplifier module, the control end of transistor MN3 is the voltage input terminal n1 of the error amplifier module, the control end of transistor MN2 is connected to the control end of transistor MN1, and the control end of transistor MN2 is connected to one end thereof, and the other end of transistor MN2 is grounded. The control end of transistor MN1 is connected to the connection end ibias to generate a bias voltage, which is given to transistor MN2, so that transistor MN2 generates a bias current, thereby providing a bias for the error amplifier. Transistor MP2 and transistor MN12 are connected in series between the voltage output end Vout and the ground line GND, the control end of transistor MP2 is connected to the control end of transistor MP3, and the control end of transistor MN12 is connected to the connection node between it and transistor MP2. Transistor MP1 and transistor MN11 are connected in series between the voltage input end Vbat and the ground line GND. Among them, the control end of transistor MP1 is connected to the connection node between it and transistor MN11, and is also connected to the control end of the power tube MP_power, which is the output end of the error amplifier. The control end of transistor MN11 is connected to the control end of transistor MN12.

[0033] like Figure 3 and Figure 4 As shown, the LDO circuit also includes a bias current module, the input end of the bias current module (i.e. Figure 4In the embodiment, the connection node of the resistor R1, the transistor M2 and the transistor M4 is connected to the voltage output terminal Vout, and the output terminal is connected to the connection terminal ibias of the error amplifier module. Therefore, the bias current module uses the voltage output terminal Vout of the LDO as the power source. The circuit structure and principle of the bias current module are relatively simple and will not be described in detail here.

[0034] like Figure 4 As shown, the bias current module specifically includes a resistor R1, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6 and a transistor M7. A resistor R1, a transistor M1 and a transistor M6 are connected in series between the input end of the bias current module and the ground line, and a transistor M2, a transistor M3 and a transistor M7 are also connected in series. Among them, the control end of the transistor M1 is connected to the control end of the transistor M3, and is also connected to the connection node of the transistor M3 and the transistor M7; the control end of the transistor M2 is connected to the connection node of the resistor R17 and the transistor M1; the control end of the transistor M6 is connected to the control end of the transistor M7, and is also connected to the connection node of the transistor M1 and the transistor M6. The input end of the bias current module is connected to the transistor M4 and the transistor M5 in series in sequence to form the output end of the bias current module. Among them, the control end of the transistor M4 is connected to the control end of the transistor M2, and the control end of the transistor M5 is connected to the connection node of the transistor M3 and the transistor M7.

[0035] like Figure 3 As shown, by analyzing the loop of the entire LDO circuit, it can be found that the feedback introduced by the entire LDO circuit is a positive feedback. This is because the equivalent resistance of the LDO circuit from the voltage output terminal Vout and the ground terminal GND is a negative resistance. When the device size of the transistor MP2 is large enough and the voltage output terminal Vout increases, the current of the transistor MP2 drops rapidly, resulting in the LDO circuit in the case of small signals. The output voltage and current of the voltage output terminal Vout are in an inverse relationship. The size of this negative resistance is inversely proportional to the gain of the difference amplifier, that is, the greater the gain of the error amplifier, the smaller the resistance.

[0036] like Figure 3 As shown, the working process of the entire circuit is analyzed below.

[0037] In the normal working state of the LDO circuit, the voltages of the voltage input terminal n1 and the voltage input terminal n2 are basically the same. The specific difference depends on the whole loop gain. For the sake of simplicity, it is assumed that the voltage input terminal n1 and the voltage input terminal n2 are completely equal, and the currents (i.e., the collector currents) flowing through the transistors Q3 and Q4 are exactly the same.

[0038] In the normal working state of the LDO circuit, on the one hand, since the transistors MP10 and MP11 work in the saturation region and have the same device size, theoretically the transistors MP10 and MP11 flow the same current and have the same VGS voltage. On the other hand, due to the different sizes of transistors Q3 and Q4, the potential difference between the upper end (i.e., source end) of transistors MP10 and MP11 is △VBE (i.e., the difference between the forward bias voltage of transistor MP10 and the forward bias voltage of transistor MP11). Since the potential of the control end (i.e., gate end) of transistor MP10 is 0, in order to keep the VGS voltages of transistors MP10 and MP11 consistent, the potential of the control end (i.e., gate end) of transistor MP11 should be △V BE .

[0039] The voltage expression of the voltage output terminal Vout is derived below: like Figure 5 As shown, according to Ampere's law of resistance, the following expression is obtained: The partial current flowing through resistor R3 is:

[0040] The partial current flowing through resistor R4 is:

[0041] Total current:

[0042] The voltage at the voltage output terminal Vout is:

[0043] Finally, we get:

[0044] Among them, V BE The forward bias voltage of transistor MP11, R1, R2, R 3、 R1, R2, R3, R4 are the impedances of resistors R1, R2, R3, and R4 respectively. BE is the potential of the control terminal (i.e., gate terminal) of transistor MP11, By setting the appropriate resistance value, a voltage with zero temperature coefficient can be obtained. This part will be explained in detail later and will not be repeated here. When the resistance ratio is set properly, a voltage of about 1.2V can be obtained. This part can get an output of more than 1.2V. This is also a design limitation of this application. Only an LDO output with a voltage greater than 1.2V can be obtained.

[0045] When the output voltage fluctuates, the changes of the entire loop are as follows: Assuming that the output voltage of the voltage output terminal Vout is disturbed and suddenly increases, the output passes through the resistors R1-R4 and the transistor Q5 to increase the control terminal (i.e., gate) voltage of the transistor MP11. At the same time, because the current flowing through the transistor MP11 is constant and the voltage of VGS remains constant, the increase in the control terminal voltage of the transistor MP11 will cause the upper terminal (i.e., source terminal) voltage of the transistor MP11 to increase, that is, the lower terminal (i.e., emitter) voltage of the transistor Q4 to increase. The control terminal (i.e., base) voltage of the transistor Q4 remains unchanged. At this time, the connection mode of the transistor Q4 is a common base amplifier circuit structure. The increase in the lower terminal (i.e., emitter) voltage of the transistor Q4 will cause the voltage of the voltage input terminal n2 to increase, while the voltage of the voltage input terminal n1 remains basically unchanged. At this time, the current flowing through transistor MN4 and transistor MP4 increases, causing the current of transistor MN3 and transistor MP3 to decrease, while the current of transistor MP2 is N times that of transistor MP3, the current of transistor MP2 becomes lower, and the current of transistor MN11 also decreases at the same time, causing the control terminal (i.e., gate) voltage of transistor MP1 and power tube MP_power to increase, thereby reducing the output current and reducing the output voltage of the voltage output terminal Vout, until the current of the power tube MP_power just meets the voltage of the node of the voltage input terminal n1 and the voltage input terminal n2, and the output voltage is stabilized. When the output voltage of the voltage output terminal Vout is suddenly reduced due to interference, the whole process is completely opposite to the above process, and the output voltage is finally stabilized to the preset voltage.

[0046] like Figure 3 As shown, disconnect the control end (gate) of the power tube MP_power and analyze the loop from the control end: A large capacitor, namely, capacitor CL, is connected in parallel to the voltage output terminal Vout, which will generate a relatively low frequency pole 1. Since the output resistance is a negative number, this pole 1 is a right half plane pole. When the load resistance becomes smaller, the pole frequency of pole 1 becomes lower (this is different from the traditional LDO circuit. When the load RL of the traditional LDO circuit becomes smaller, the pole frequency increases). There is a large parasitic capacitor at the control end (i.e., the gate) of the transistor MP_power. Therefore, a relatively low frequency pole 2 is generated at the control end of the transistor MP_power. This pole 2 is a left half plane pole. The pole frequencies of poles 1 and 2 are both relatively low. If the two pole frequencies are close, the phase is a positive value slightly greater than 0° at low frequency, and increases with the increase of frequency (not exceeding 90°). After approaching the pole frequency of pole 2, the phase begins to decrease continuously. When the phase drops to 0°, if the gain is greater than 1, the loop will be unstable. Especially when the load increases, the gm value of the power tube MP_power will increase, and the equivalent resistance of the output resistor will also increase. The overall loop gain will increase, and the stability will deteriorate. Therefore, when the phase curve passes through the zero point, it is very likely that the loop gain is still greater than 1, resulting in loop instability. Therefore, a capacitor, namely capacitor C, is added between the voltage input terminal n2 and the voltage output terminal Vout. A zero-pole pair is introduced by capacitor C. The small signal model of this part of the circuit is drawn, as shown in the figure. Figure 6 shown.

[0047] like Figure 6 and Figure 7 As shown, write the KCL equation in the Vo column as follows: ; ; in, is the impedance of capacitor C; is the transconductance of the power tube MP_power; The solution is: ; Depend on , the frequency of the zero point is:

[0048] Depend on , the frequency of the pole is:

[0049] The zeros and poles here are opposite to the actual situation, because the negative resistance of the equivalent resistance is inversely proportional to Vo / Vi, and the gain of the entire loop is proportional to the negative resistance, so the zeros and poles are opposite. That is, the frequency of the actual zero point of the loop is: ;The frequency of the actual pole of the loop is: .

[0050] Through observation, it is found that the frequency of the zero point is much smaller than the frequency of the pole. Therefore, the frequency of the pole can be designed to be very high (outside the unit gain bandwidth UGB, no need to consider), and the frequency of the zero point can be designed to be relatively low. In this way, we can get something like Figure 7 The Bode plot is shown below.

[0051] In the Bode diagram, sp1 represents the frequency of the pole 1 where the voltage output terminal Vout is located. Pole 1 is a right half plane pole, and the frequency sp1 of pole 1 basically does not change with the change of load. When encountering pole 1, the gain of the loop begins to decrease at a rate of 20dB / dec, but the phase increases.

[0052] sp2 represents the frequency of the second pole at the control end (i.e., the gate end) of the transistor MP_power. The second pole sp2 is a left half plane pole. The frequency sp2 of the second pole increases with the increase of the load current. At this time, the stability of the circuit will deteriorate, because when the frequency sp2 of the second pole is low, the gain will drop rapidly and the unit gain bandwidth UGB will drop; if the frequency sp2 of the second pole is too high, the rate of gain decrease will decrease, the frequency of the unit gain bandwidth UGB will increase, and the phase will rise by nearly 90° after the frequency sp1 of the first pole, and then drop to nearly 0° after encountering the frequency sp2 of the second pole. Therefore, when encountering the frequency sp2 of the second pole, the rate of gain decrease increases to 40dB / dec, and the phase also begins to decrease.

[0053] sz1 represents the frequency of the zero introduced by capacitor C. This zero is a left half plane zero, and the frequency of the zero sz1 will not change. When encountering the frequency sz1 of the zero, the gain decreases at a rate of 20dB / dec, and the phase recovers.

[0054] After the frequency sz1 of the zero point, the frequency of the unity gain bandwidth UGB is reached soon. The various high-frequency poles (such as sp3) or right half-plane zeros generated afterwards will cause a sharp drop in phase. After the gain of the loop is less than 0dB, as long as there is no gain rebound, that is, the gain is no longer greater than 0dB, the subsequent zeros and poles can be ignored.

[0055] Therefore, as long as the frequency of each zero and pole is designed reasonably to ensure that the phase margin is not less than the required value before the frequency of the unity gain bandwidth UGB, the entire circuit can work normally.

[0056] Through the above analysis, we further analyze the loop stability under the maximum load state, and there are two schemes for the frequency design of zeros and poles.

[0057] like Figure 3 and Figure 8As shown in the figure, design scheme 1: design the frequency sz1 of the zero point to be closer to the frequency sp1 of the pole 1. At this time, the frequency sp1 of the pole 1 and the frequency sz1 of the zero point produce a phase shift of +180°. The next design is similar to the design of a three-pole circuit. It only needs to design the frequency sp2 of the next pole 2 to be relatively low to stabilize the entire loop. The Bode diagram of this scheme is as follows Figure 8 This design method is relatively simple, but there must be a zero point with a very low frequency, which requires the capacitor C to be designed to be very large, which will result in a large area. At this time, if the phase margin is not enough, you only need to reduce the frequency of the second pole sp2, so that the frequency of the second pole sp2 is far away from other parasitic high-frequency poles, and the loop can be stable.

[0058] like Figure 3 and Fig. 9 As shown, if the frequency of the zero point sz1 is greater than the frequency of the pole two sp2, through Fig. 9 It can be clearly seen from the Bode diagram shown that the frequency sp1 of pole one can be designed to be higher than that of design scheme one, the required capacitance CL will be smaller, the capacitance C introduced into the zero point can also be designed to be smaller, and the frequency sp2 of pole two can also be designed to be relatively high. The specific relationship is analyzed as follows: like Figure 3 and Fig. 9 As shown, design scheme 2: This is a design of a multi-zero and pole system, and the unit gain bandwidth UGB and the frequency of the pole two sp2 change with the load. The design is more flexible. Here is a reference scheme: In the above analysis of zero and pole, the frequency of zero sz1 and the frequency of pole 1 sp1 can be adjusted flexibly. Now first determine the frequency of zero and pole under heavy load conditions. Specifically, through simulation software, adjust the frequency of zero and pole, from Fig. 9The Bode diagram shown shows that when the load is the largest, the frequency of the unit gain bandwidth UGB is the largest. The frequency of the high-frequency pole is first found through the simulation software, and then the frequency sz1 of the zero point can be determined according to the ratio of the maximum load current to the minimum load current. The larger the ratio of the maximum load current to the minimum load current, the smaller the frequency sz1 of the zero point is designed to be, away from the high-frequency pole, but all designed within the unit gain bandwidth UGB. For example, assuming that the high-frequency pole is sp3, the frequency of the unit gain bandwidth UGB is designed to be half of the frequency sp3 of the high-frequency pole, and the frequency sz1 of the zero point is designed to be half of the frequency of the unit gain bandwidth UGB. At this time, the phase shift introduced by the high-frequency pole is 26.5°, and the phase shift compensated by the zero point is 63.43°. There is a right half-plane pole (i.e., pole one), a left half-plane pole (i.e., pole two), and a left half-plane zero point before the unit gain bandwidth UGB. The entire system is stable. The frequency adjustment of the unit gain bandwidth UGB can be adjusted by adjusting the value of the load capacitor. For convenience, the capacitor CL can be directly set as a variable using the simulation software, and then a parameter scan can be performed to determine the appropriate value of the capacitor CL. At this time, the frequency sp1 of the pole one is also determined.

[0059] When the frequency sp1 of pole one and the frequency sz1 of zero are determined, start the verification under small load current, adjust the load to the required minimum value, simulate the stability of the loop, and get the phase margin value at this time. If the phase margin does not meet the design requirements, you can reduce the frequency sz1 of the zero point, and then redesign the circuit according to the previous steps. If it still does not meet the requirements, you need to design the frequency of the unit gain bandwidth UGB to be smaller. As mentioned above, the frequency of the unit gain bandwidth UGB is designed to be half of the high-frequency pole. If you want to improve the phase margin, you can continue to appropriately reduce the frequency of the unit gain bandwidth UGB to ensure that the loop has better stability.

[0060] Since the entire system is a multi-zero and multi-pole system, it is difficult to quantitatively analyze the stability of the system. However, it can be seen that as long as the frequency of the unit gain bandwidth UGB is designed to be sufficiently lower than the frequency of the high-frequency pole, the entire loop system is absolutely stable. Because the phase shift caused by the first two poles (i.e., pole one and pole two) can basically be offset, and there is a zero point in front, the phase shift caused by this zero point is greater than the phase shift caused by the high-frequency pole behind, so at the frequency of the unit gain bandwidth UGB, the phase will not be lower than the dividing line of 0°. In addition, if you want to obtain better phase margin and faster stabilization time, you can further optimize the proportional relationship between the high-frequency poles and zeros of the unit gain bandwidth UGB.

[0061] The voltage across resistor R3 is △VBE, which is a voltage with a positive temperature coefficient. This voltage makes the current flowing through resistors R3, R2 and transistor Q5 a current with a positive temperature coefficient, while the voltage on resistor R4 is the sum of the voltages of resistors R3, R2 and VBE. VBE is a voltage with a negative temperature coefficient. Although the voltages of resistors R2 and R3 are positive temperature coefficients, as long as the resistance values ​​are designed according to the ratio described above, the voltage on resistor R4 will eventually be a voltage with a negative temperature coefficient. This voltage will generate a current with a negative temperature coefficient. After the positive temperature coefficient current flowing through resistor R2 and the negative temperature coefficient current flowing through resistor R4 are added together, the ratio between resistors R1-R4 is designed according to the previous method to obtain a current with a positive temperature coefficient. This current generates a voltage with a positive temperature coefficient on resistor R1. The temperature coefficients of this voltage and the negative temperature coefficient voltage on resistor R4 cancel each other out, and finally the voltage output terminal Vout is generated. A reference voltage with a zero temperature coefficient is obtained, and the voltage output terminal Vout is the output of the LDO circuit. Therefore, Vout is both the reference voltage and the output voltage of the LDO.

[0062] Through the analysis of the entire circuit, we found that in this LDO circuit, the reference circuit is included in the entire LDO loop. There is no need to design a separate reference loop. This can prevent the reference from being directly affected by external circuit interference and affecting the LDO output, and can obtain better noise characteristics at medium and low frequencies.

[0063] The above is only a specific implementation of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial changes to the present invention using this concept shall be deemed as an infringement of the protection scope of the present invention.

Claims

1. A reference-free low-noise LDO circuit, comprising a voltage input terminal Vbat, an error amplifier module, a voltage output terminal Vout, a power tube MP_power, a resistor R1 and a resistor R4; one end of the power tube MP_power is connected to the voltage input terminal Vbat, and the control end is connected to the output end of the error amplifier module; the other end of the power tube MP_power is connected to the voltage output terminal Vout; the voltage output terminal Vout is grounded after passing through the resistors R1 and R4, characterized in that: It also includes a resistor R2, a transistor Q5 and a resistor R3, wherein a connection node between the resistor R1 and the resistor R4 is connected to ground via the resistor R2, the transistor Q5 and the resistor R3 in sequence, and a control end of the transistor Q5 is connected to a connection node between the resistor R2 and the transistor Q5; Also includes transistor MP7, transistor MP11, transistor Q4, transistor MP8, transistor MP9, transistor MN6, transistor MN7, transistor MP6, transistor Q3, transistor MP10, transistor MP5 and transistor MN5; The voltage output terminal Vout is grounded via transistor MP7, transistor Q4, transistor MP11, grounded via transistor MP8, transistor MP9, grounded via transistor MN6, transistor MN7, grounded via transistor MP6, transistor Q3, transistor MP10, grounded via transistor MP5 and transistor MN5; The control ends of the transistors MP7, MP8, MP6 and MP5 are all connected to the connection node between the transistor MP5 and the transistor MN5; the control ends of the transistors Q3 and Q4 are all connected to the connection node between the transistor MP8 and the transistor MP9; the control end of the transistor MP11 is connected to the connection node between the transistor Q5 and the resistor R2; the control end of the transistor MP9 is connected to the connection node between the transistor MN6 and the transistor MN7; the control end of the transistor MN6 is connected to the connection node between the transistor MP6 and the transistor Q3; the control end of the transistor MP10 is grounded via a resistor; The voltage input terminal n1 of the error amplifier module is connected to the connection node between the transistor MP6 and the transistor Q3, the voltage input terminal n2 is connected to the connection node between the transistor MP7 and the transistor Q4, the connection terminal ibias is simultaneously connected to the control terminals of the transistor MN7 and the transistor MN5, and the output terminal is connected to the control terminal of the power tube MP_power.

2. The reference-free low-noise LDO circuit according to claim 1, characterized in that: The capacitor CL is also included, and the voltage output terminal Vout is grounded after passing through the capacitor CL.

3. The reference-free low-noise LDO circuit according to claim 1, characterized in that: A capacitor C is also included, and the voltage output terminal Vout is connected to a connection node between the transistor MP7 and the transistor Q4 via the capacitor C.

4. The reference-free low-noise LDO circuit according to claim 1, characterized in that: It also includes a resistor R0, and the control end of the power tube MP_power is connected to the connection node between the power tube MP_power and the voltage input end Vbat through the resistor R0.

5. A reference-free low-noise LDO circuit according to any one of claims 1 to 4, characterized in that: The transistor Q3, the transistor Q4 and the transistor Q5 are all NPN-type triodes, and the size ratio of the transistor Q4 to the transistor Q3 is N:

1.

6. The reference-free low-noise LDO circuit according to claim 5, characterized in that: The transistor MP10 and the transistor MP11 are both NMOS transistors.

7. The reference-free low-noise LDO circuit according to claim 5, characterized in that: The transistor MN6 and the transistor MN7 are both PMOS transistors, and the transistor MP9 is an NMOS transistor.

8. A reference-free low-noise LDO circuit according to any one of claims 1 to 4, characterized in that: It also includes a bias current module, the input end of the bias current module is connected to the voltage output end Vout, and the output end is connected to the connection end ibias of the error amplifier module.

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