Transient enhancement circuit for suppressing overshoot and undershoot and applied to LDO (Low Dropout Regulator)

Abstract

The invention belongs to the field of integrated circuit power supply chip design, and particularly relates to an overshoot and undershoot suppression transient enhancement circuit applied to an LDO (Low Dropout Regulator), which consists of a band-gap reference circuit, an error amplifier, a power tube PMOS (P-channel Metal Oxide Semiconductor) tube MP1, a second-stage amplifier tube NMOS (N-channel Metal Oxide Semiconductor) tube MN1, a resistor R4, a load resistor RL and an on-chip load capacitor CL, the self-adaptive zero point module consists of a resistor R3, a capacitor C1 and an NMOS (N-channel Metal Oxide Semiconductor) tube MN2, the LDO feedback network consists of a resistor R1 and a resistor R2, and the module is used for inhibiting output voltage uprush and downrush. According to the invention, through the upshoot suppression circuit and the undershoot suppression circuit, effective suppression of upshoot and undershoot generated during load sudden change is realized, the recovery time of upshoot and undershoot voltage is shortened, and the upshoot suppression circuit only generates a small amount of quiescent current consumption; the undershoot suppression circuit does not generate extra static consumption under the whole LDO working state due to the effect of the capacitor.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit power chip design, and in particular relates to a transient enhancement circuit for suppressing overshoot and undershoot applied to LDO. Background Art

[0002] In the selection of power chips, low dropout linear regulators (LDO) are widely used due to their simple structure, low ripple, low EMI noise and other advantages. In order to facilitate integration, LDOs without external capacitors came into being. Its output capacitance is usually within 1pF to 200pF, which is easier to integrate into the chip, so it has become a hot topic of research. However, due to the reduction of output capacitance, the transient response of LDO without external capacitors becomes worse, so enhancing transient response has become a factor that must be considered.

[0003] Transient response refers to the maximum output voltage change allowed when the load current changes in step, which reflects the response speed and stability of the LDO circuit to the load current change. In modern electronic systems, changes in load current are normal. If the transient response characteristics of the LDO circuit are not good, it may cause large output voltage fluctuations (i.e. overshoot or undershoot) when the load changes, thereby affecting the performance and stability of the entire electronic system. Therefore, good transient response characteristics are one of the important performance indicators of the LDO circuit. The design goal of the transient enhancement circuit is mainly to improve the circuit's response speed and stability to load changes, and to reduce the fluctuation of the output voltage, so that the LDO circuit has a good transient response.

[0004] Figure 1 This is a schematic diagram of a traditional transient enhancement circuit. A slew rate enhancement module SER is introduced to increase the error amplifier's drive current to the power tube gate, thereby enhancing the transient response. The transient enhancement circuit consists of an error amplifier EA, a buffer Buffer, a slew rate enhancement module SER, and a power PMOS tube M. P , resistor feedback network R 1 , R 2 , output capacitor C OUT Load resistance R L 、On-chip load capacitance C L And the power tube gate capacitance C P Composition, where V FB is the output voltage of the resistor feedback network, V REF is the bandgap reference output voltage. Due to the negative feedback, the feedback voltage V FB It will eventually stabilize at the reference voltage V REF , that is, the LDO output voltage V OUT It will eventually stabilize to formula (1);

[0005]

[0006] Figure 2 It is a specific circuit diagram of a traditional transient enhancement circuit, where M1~M11 form an error amplifier EA, M12 and M13 form a buffer, M14~M18 form a slew rate enhancement module SER, M19 is a power tube, resistors R1 and R2 form a feedback network, RL is a load resistor, COUT is an output capacitor, CC is a compensation capacitor, and Vb1~Vb5 are bias voltages.

[0007] Overshoot analysis: When the LDO changes from heavy load to light load, that is, the load current decreases, the output voltage V OUT The voltage rises and is fed back to the error amplifier EA through the feedback network, causing the output voltage of the error amplifier to rise. P The gate-source voltage decreases, thereby reducing the output current and the output capacitor C OUT Discharging, the output voltage decreases. Due to the effect of negative feedback, the feedback voltage VFB will eventually stabilize at the reference voltage VREF, that is, the LDO output voltage will stabilize as shown in formula (1).

[0008] Undershoot suppression analysis: When the LDO changes from light load to heavy load, that is, the load current increases, the output voltage V OUT The voltage of the error amplifier EA decreases and is fed back to the error amplifier EA through the feedback network, causing the output voltage of the error amplifier to decrease. P The gate-source voltage increases, thereby increasing the output current on the output capacitor C OUT Charging is performed to raise the output voltage. Figure 3 The drop in the error amplifier output voltage will also increase the transient current I boost That is, the gate voltage of M18 will decrease as the source voltage of M12 decreases, and the current I flowing through M14 through current mirrors M14 to M17 is boost The current flowing through the M12 tube decreases, which further lowers the source voltage of the M12 tube, that is, the gate voltage of the power tube M19. P The gate-source voltage further increases, and the output current also further increases, accelerating the output capacitance C OUT Charging is performed to raise the output voltage, enhance the transient response of the LDO, and suppress the undershoot of the output voltage. Finally, due to the negative feedback and undershoot suppression, the output voltage will be stabilized as shown in formula (1).

[0009] It can be seen that the introduction of the transient enhancement module increases the redundant current consumption, the LDO static current increases, and the static consumption of the circuit is increased. In addition, the traditional transient enhancement circuit can only reduce the undershoot of the output voltage and shorten the recovery time by introducing the transient enhancement module SER when the load current suddenly increases, but it has no improvement effect on the output voltage overshoot caused by the sudden decrease of the load current.

[0010] In summary, the traditional transient enhancement circuit increases the overall quiescent current of the LDO circuit due to the introduction of excess current, thereby increasing the circuit power consumption; the transient enhancement module can only slow down the output voltage undershoot and shorten the recovery time when the load current suddenly increases, and cannot improve the output voltage overshoot generated when the load current suddenly decreases. Summary of the invention

[0011] In order to solve the above technical problems, the present invention provides a transient enhancement circuit for suppressing overshoot and undershoot applied to LDO, comprising: a bandgap reference circuit BG, an error amplifier EA, a power tube PMOS tube MP1, amplifier tubes NMOS tubes MN1, MN2, resistors R1-4, a load resistor R L , on-chip load capacitance C L , capacitor C 1 , undershoot suppression module Reduce Undershoot and overshoot suppression module Reduce Overshoot;

[0012] The bandgap reference circuit BG is connected to the positive input terminal of the error amplifier EA to provide a reference voltage VREF, and its negative input terminal is connected to the feedback voltage VFB;

[0013] The output end of the error amplifier EA is connected to one end of the resistor R3 and the gates of the second-stage amplifier tubes NMOS tubes MN1 and MN2;

[0014] The other end of the resistor R3 is connected to the capacitor C 1 One end of the capacitor C 1 The other end is connected to the drain of the amplifier tube NMOS tube MN2;

[0015] The source of the amplifier tube NMOS tube MN2 is grounded;

[0016] The source of the second-stage amplifier tube NMOS tube MN1 is grounded, and the drain thereof is connected to one end of the resistor R4 and the gate of the power tube PMOS tube MP1;

[0017] The other end of the resistor R4 serves as the input end of the overall circuit and is connected to the source of the power tube PMOS tube MP1;

[0018] The drain of the power tube PMOS tube MP1 is used as the output end of the overall circuit and is connected to the load resistor R L One end of the chip, the internal load capacitance C L one end of , one end of the resistor R1, the input end of the undershoot suppression module Reduce Undershoot, and the output end of the overshoot suppression module Reduce Overshoot;

[0019] The load resistance R L The other end is grounded and connected to the on-chip load capacitor C L The other end of the resistor R2;

[0020] The other end of the R1 is connected to the other end of the resistor R2 and the input end of the overshoot suppression module ReduceOvershoot, and outputs a feedback voltage VFB;

[0021] The output end of the undershoot suppression module Reduce Undershoot is connected to the error amplifier EA.

[0022] Beneficial effects of the present invention:

[0023] The present invention provides a transient enhancement circuit for suppressing overshoot and undershoot applied to an LDO. The circuit realizes effective suppression of overshoot and undershoot generated when a load suddenly changes and shortens the recovery time of the overshoot and undershoot voltages through an overshoot suppression circuit and an undershoot suppression circuit. Moreover, the overshoot suppression circuit generates only a small amount of static current consumption, and the undershoot suppression circuit does not generate additional static consumption in the entire LDO working state due to the effect of a capacitor.

[0024] The present invention can effectively reduce the overshoot and undershoot phenomena of the output voltage when the load current jumps, and greatly shorten the voltage stabilization time, thereby ensuring the fast transient response of the LDO circuit.

[0025] On the basis of improving transient response, the present invention adds an undershoot suppression circuit that does not generate additional static consumption, and an overshoot suppression circuit generates only a small amount of static current, thereby solving the problem of excessive static consumption of traditional transient enhancement circuits, reducing the static consumption of the circuit and improving the efficiency of the circuit.

[0026] Instruction Manual

[0027] Figure 1 It is a schematic diagram of a conventional transient enhancement circuit;

[0028] Figure 2 This is the schematic diagram of the traditional transient enhancement circuit;

[0029] Figure 3 It is a schematic diagram of the circuit framework of the present invention;

[0030] Figure 4 Obtain a circuit schematic diagram for the present invention;

[0031] Figure 5 This is a load transient response simulation diagram of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] A transient enhancement circuit for suppressing overshoot and undershoot applied to LDO, comprising: a bandgap reference circuit BG, an error amplifier EA, a power tube PMOS tube MP1, amplifier tubes NMOS tubes MN1 and MN2, resistors R1-4, a load resistor R L , on-chip load capacitance C L , capacitor C 1 , undershoot suppression module Reduce Undershoot and overshoot suppression module Reduce Overshoot;

[0034] The bandgap reference circuit BG is connected to the positive input terminal of the error amplifier EA to provide a reference voltage VREF, and its negative input terminal is connected to the feedback voltage VFB;

[0035] The output end of the error amplifier EA is connected to one end of the resistor R3 and the gates of the second-stage amplifier tubes NMOS tubes MN1 and MN2;

[0036] The other end of the resistor R3 is connected to the capacitor C 1 One end of the capacitor C 1 The other end is connected to the drain of the amplifier tube NMOS tube MN2;

[0037] The source of the amplifier tube NMOS tube MN2 is grounded;

[0038] The source of the second-stage amplifier tube NMOS tube MN1 is grounded, and the drain thereof is connected to one end of the resistor R4 and the gate of the power tube PMOS tube MP1;

[0039] The other end of the resistor R4 serves as the input end of the overall circuit and is connected to the source of the power tube PMOS tube MP1;

[0040] The drain of the power tube PMOS tube MP1 is used as the output end of the overall circuit and is connected to the load resistor R L One end of the chip, the internal load capacitance CL one end of , one end of the resistor R1, the input end of the undershoot suppression module Reduce Undershoot, and the output end of the overshoot suppression module Reduce Overshoot;

[0041] The load resistance R L The other end is grounded and connected to the on-chip load capacitor C L The other end of the resistor R2;

[0042] The other end of the R1 is connected to the other end of the resistor R2 and the input end of the overshoot suppression module ReduceOvershoot, and outputs a feedback voltage VFB;

[0043] The output end of the undershoot suppression module Reduce Undershoot is connected to the error amplifier EA.

[0044] A transient enhancement circuit structure block diagram for suppressing overshoot and undershoot applied to LDO is shown in the figure Figure 3 As shown, it consists of a bandgap reference circuit BG, an error amplifier EA, a power tube PMOS tube MP1, a second-stage amplifier tube NMOS tube MN1, a resistor R4 that provides bias current for the MN1 tube, and a load resistor R L , on-chip load capacitance C L , resistor R 3 , capacitor C 1 The adaptive zero point module composed of NMOS tube MN2 and resistor R 1 and resistor R 2The feedback network of the LDO, the modules ReduceOvershoot and Reduce Undershoot for suppressing the overshoot and undershoot of the output voltage, are composed of the above, wherein EA_OUT is the output voltage of the error amplifier EA. The bandgap reference circuit BG provides the reference voltage VREF to the error amplifier EA, and compares it with the feedback voltage VFB generated by the feedback network to generate the voltage signal EA_OUT to control the gate voltage of the MN1 tube, thereby generating a current flowing through the resistor R4 to generate a voltage signal to control the gate of the power tube MP1, so as to sense the fluctuation of the output voltage through the feedback network, and stabilize the output voltage through the error amplifier and the power tube. The module Reduce Overshoot for suppressing the overshoot of the output voltage senses the feedback voltage VFB generated by the feedback network, and generates a signal to the output end of the LDO to suppress the overshoot; the module Reduce Undershoot for suppressing the undershoot of the output voltage senses the output voltage OUT of the LDO, and generates a signal to the error amplifier EA module to suppress the undershoot. When a light load suddenly changes to a heavy load, that is, the load current suddenly increases, causing the output voltage to undershoot, the undershoot suppression module Reduce Undershoot is started to slow down the output voltage undershoot and shorten the recovery time; when a heavy load suddenly changes to a light load, that is, the load current suddenly drops, causing the output voltage to overshoot, the overshoot suppression module Reduce Overshoot is started to slow down the output voltage overshoot and shorten the recovery time.

[0045] The schematic diagram of the transient enhancement circuit designed by the present invention for suppressing overshoot and undershoot in LDO is as follows: Figure 4 As shown, resistors R5, R6 and capacitor C2 constitute an undershoot suppression circuit module; NMOS tubes MN9-MN11, PMOS tubes MP6, MP7, due to the width-to-length ratio (W / L) of PMOS tubes MP6, MP7 MP6 :(W / L) MP7 =n:2 (n≥4), the equivalent offset voltage Vos introduced, the resistor R4, and the fixed bias current I1 constitute an overshoot suppression circuit module; the NMOS pair MN3, MN4, the PMOS tubes MP4, MP5 and the fixed bias current I2 constitute the first stage of the error amplifier EA, the current mirror composed of the PMOS tubes MP2, MP3 that mirror the current in MP4, MP5 and the NMOS tubes MN5~MN8 constitutes the second stage of the error amplifier, and EA_OUT is the output voltage of the error amplifier.

[0046] Overshoot suppression analysis: When the load changes suddenly from heavy load to light load, that is, the load current drops suddenly and the output voltage rises suddenly, since the circuit loop response takes a certain amount of time, a voltage overshoot will be generated at this time, and the feedback voltage VFB will also rise accordingly, that is, the source-gate voltage of the PMOS tube MP6 decreases, resulting in a decrease in the leakage current of MP6. The current is copied through the current mirrors MN9 and MN10. At this time, the leakage current of the PMOS tube MP7 is greater than the leakage current of MP6, that is, the current flowing through MN10, which raises the drain voltage of MP7, that is, the gate voltage of MN11 is raised, the MN11 tube is turned on, and the output voltage VOUT is pulled down. Finally, due to the negative feedback and overshoot suppression, the output voltage will stabilize at the value shown in formula (1), achieving the effect of slowing down the output overshoot, shortening the overshoot recovery time, and enhancing the transient response of the circuit.

[0047] When the load is in a steady state and remains unchanged, due to the width-to-length ratio (W / L) of the PMOS tubes MP6 and MP7 MP6 :(W / L) MP7 =n:2 (n≥4) will introduce an equivalent offset voltage Vos to ensure that when the overshoot suppression circuit does not work, that is, when there is no sudden change in the load, since the MOS tube drain current is proportional to the width-to-length ratio, there is an MP6 tube drain current I D6 Greater than the MP7 tube drain current I D7 At this time, the leakage current of MP6 is always greater than the leakage current of MP7 after the action of the current mirror, ensuring that the leakage voltage of MN10, that is, the gate voltage of MN11, is at a low potential. At this time, the gate-source voltage of MN11 is less than the threshold voltage, and MN11 is turned off, that is, no current flows through MN11 at this time, the overshoot suppression circuit does not work and only generates a static current of 100nA level, that is, the overshoot suppression circuit only generates a small amount of static current.

[0048] According to the above analysis, when I D7 ≥I D6 When the comparator flips and turns on the MN11 tube, the overshoot suppression circuit is started. The flip point is analyzed below, that is, I D7 =I D6 When the comparator is biased by a fixed current source I 1 Provides quiescent current, I D7 +I D6 =I 1 Therefore, at this time, both MP6 and MP7 work in the saturation region and the current is I 1 / 2, according to the formula (2) of drain current when the MOS tube is in the saturation region, it can be obtained that at the flip point I D7 and I D6 The respective current values ​​are expressed as equation (3), where it is assumed that the MP6 tube and the MP7 tube have the same parameters except that the width-to-length ratio is n:2.

[0049]

[0050] Among them, μ p is the electron mobility of the PMOS tube, Cox is the gate oxide capacitance per unit area, is the width-to-length ratio of the MP6 tube, is the width-to-length ratio of MP7 tube, VA is the source voltage of MP6 tube and MP7 tube, and VTH is the threshold voltage of PMOS tube MP6 and MP7.

[0051] From formula (3) I D7 The current expression can be used to obtain the MP7 tube source voltage V at the flip point. A Formula (4):

[0052]

[0053] According to formula (3), I D6 The current expression and the source voltage V in equation (4) A The expression can be used to obtain the MP6 gate voltage at the flip point, that is, the feedback voltage V FB The voltage value is as shown in formula (5), that is, when an overshoot occurs, as the output voltage V OUT The feedback voltage V FB When the value rises to the value of formula (5), the comparator flips and turns on the MN11 tube, thereby starting the overshoot suppression circuit.

[0054]

[0055] Therefore, the width-to-length ratio (W / L) of the PMOS tubes MP6 and MP7 can be MP6 :(W / L) MP7 =n:2(n≥4) The value of n is discussed as follows:

[0056] (1) n cannot be too small. If n is too small, the width-to-length ratio n:2 is close to 1:1. From formula (5), it can be seen that at the flip point, VFB is equal to VREF. At this time, due to the system imbalance of the circuit, it is easy to accidentally turn on the MN11 tube when the LDO circuit is stable, resulting in the premature opening of the overshoot suppression module. When overshoot occurs, the module will not play a role in suppressing overshoot. In addition, the opening of the MN11 tube will also introduce excess static current I D11 As shown in formula (6), the static consumption of LDO is increased;

[0057]

[0058] Among them, Ron is the on-resistance of MN11 tube when it is working normally.

[0059] (2) n cannot be too large. If n is too large, as shown in formula (5), as n increases, the value of VFB required for the overshoot suppression module to be turned on will increase accordingly, that is, the overshoot voltage required for VOUT to be reached will increase, resulting in the overshoot suppression module being triggered too late when the overshoot occurs, and the overshoot suppression effect will be poor.

[0060] (3) In the aspect ratio n:2, the value of n is generally an even number greater than 4, such as 4 or 6, in order to facilitate layout matching design.

[0061] Undershoot suppression analysis: When the load changes suddenly from light load to heavy load, that is, the load current suddenly rises and the output voltage suddenly drops, since the circuit loop response takes a certain amount of time, a voltage undershoot will be generated at this time, and the feedback voltage VFB will also decrease accordingly. It can be seen that the error amplifier EA will first respond to the feedback voltage, that is, at this time, the gate-source voltage of the NMOS tube MN3 decreases, and the current flowing through MP4 decreases, and flows through the NMOS tube MN6 through the current mirror replication effect. Similarly, the current on the NMOS tube MN4 flows through the PMOS tube MP3 after passing through the current mirror. At this time, ID3>ID6, so the output voltage VEA_OUT of the error amplifier EA is raised, such as Figure 3 , that is, the gate voltage of the NMOS tube MN1 is raised, thereby lowering the gate voltage of the power tube MP1, increasing the output current to charge the output capacitor, and thus raising the output voltage. The undershoot suppression circuit adds resistors R5, R6 and capacitor C2 to the error amplifier EA. It can be seen that when the output voltage VOUT suddenly drops and generates an undershoot, since the voltage across the capacitor C2 cannot change suddenly, in order to ensure that the voltage across C2 remains unchanged, the gate voltage of MN7 also generates an undershoot. At this time, the drain current of MN7 is further reduced, that is, after the current mirror is copied, the current flowing through the NMOS tube MN6 is further reduced. At this time, the output voltage of the error amplifier is further raised, that is, the output voltage can be better raised. Similarly, due to the negative feedback and overshoot suppression, the output voltage will be stable at the value shown in formula (1), achieving the effect of slowing down the output voltage undershoot, shortening the undershoot recovery time, and enhancing the transient response of the circuit. Similarly, it can be seen that due to the effect of the capacitor blocking DC and passing AC, the undershoot suppression circuit will not generate additional static DC current, that is, no additional static consumption will be generated.

[0062] pass Figure 5This phenomenon can be clearly seen from the simulation results. When the load current jumps from 10mA to 200mA, the output voltage produces an obvious undershoot, and when the load current jumps from 200mA to 10mA, the output voltage produces an obvious overshoot. After adding the transient enhancement module designed by the present invention, that is, the overshoot suppression circuit and the undershoot suppression circuit, the undershoot is reduced by 90mV, the overshoot is reduced by 150mV, and the undershoot stabilization time is shortened by 70us, and the overshoot stabilization time is shortened by 152us, which well suppresses the overshoot and undershoot phenomena, and greatly shortens the stabilization time, achieving the effect of enhancing the transient response of the circuit, and only the overshoot suppression circuit generates a small amount of static current, and the undershoot suppression circuit does not generate additional current consumption, thereby reducing static consumption and improving the efficiency of the circuit.

[0063] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A transient enhancement circuit for suppressing overshoot and undershoot applied to LDO, characterized in that: Including bandgap reference circuit BG, error amplifier EA, power tube PMOS tube MP1, amplifier tube NMOS tube MN1, MN2, resistors R1-4, load resistor R L , on-chip load capacitance C L , capacitor C1, undershoot suppression module Reduce Undershoot and overshoot suppression module Reduce Overshoot; The bandgap reference circuit BG is connected to the positive input terminal of the error amplifier EA to provide a reference voltage VREF, and its negative input terminal is connected to the feedback voltage VFB; The output end of the error amplifier EA is connected to one end of the resistor R3 and the gates of the second-stage amplifier tubes NMOS tubes MN1 and MN2; The other end of the resistor R3 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the drain of the amplifier tube NMOS tube MN2; The source of the amplifier tube NMOS tube MN2 is grounded; The source of the second-stage amplifier tube NMOS tube MN1 is grounded, and the drain thereof is connected to one end of the resistor R4 and the gate of the power tube PMOS tube MP1; The other end of the resistor R4 serves as the input end of the overall circuit and is connected to the source of the power tube PMOS tube MP1; The drain of the power tube PMOS tube MP1 is used as the output end of the overall circuit and is connected to the load resistor R L One end of the chip, the internal load capacitance C L one end of , one end of the resistor R1, the input end of the undershoot suppression module Reduce Undershoot, and the output end of the overshoot suppression module Reduce Overshoot; The load resistance R L The other end is grounded and connected to the on-chip load capacitor C L The other end of the resistor R2; The other end of the R1 is connected to the other end of the resistor R2 and the input end of the overshoot suppression module Reduce Overshoot, and outputs a feedback voltage VFB; The output end of the undershoot suppression module Reduce Undershoot is connected to the error amplifier EA.

2. The transient enhancement circuit for suppressing overshoot and undershoot applied to LDO according to claim 1, characterized in that: The adaptive zero point module composed of the resistor R3, the capacitor C1 and the NMOS tube MN2, and the LDO feedback network composed of the resistor R1 and the resistor R2; The bandgap reference circuit BG provides a reference voltage VREF to the error amplifier EA, and compares it with the feedback voltage VFB generated by the feedback network to generate a voltage signal EA_OUT to control the gate voltage of the MN1 tube, thereby generating a current flowing through the resistor R4 to generate a voltage signal to control the gate of the power tube MP1, so as to sense the fluctuation of the output voltage through the feedback network, and stabilize the output voltage through the error amplifier and the power tube; The output voltage overshoot suppression module Reduce Overshoot senses the feedback voltage VFB generated by the feedback network and generates a signal to the LDO output end to suppress overshoot; the output voltage undershoot suppression module Reduce Undershoot senses the LDO output voltage OUT and generates a signal to the error amplifier EA module to suppress undershoot.

3. The transient enhancement circuit for suppressing overshoot and undershoot applied to LDO according to claim 1, characterized in that: When the light load suddenly changes to a heavy load, that is, the load current suddenly increases, causing the output voltage to undershoot, the transient enhancement circuit starts the undershoot suppression module Reduce Undershoot to slow down the output voltage undershoot and shorten the recovery time.

4. The transient enhancement circuit for suppressing overshoot and undershoot applied to LDO according to claim 1, characterized in that: When the load suddenly changes from heavy load to light load, that is, the load current suddenly drops, causing the output voltage to overshoot, the transient enhancement circuit starts the overshoot suppression module Reduce Overshoot to slow down the output voltage overshoot and shorten the recovery time.

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