Phase-adjustable trilateral competitive true random number generator based on FPGA (Field Programmable Gate Array) and related method

Abstract

The invention discloses a phase-adjustable trilateral competition true random number generator based on an FPGA (Field Programmable Gate Array) and an implementation method. The true random number generator comprises a phase-adjustable trilateral competition ring oscillator, a crash event detection circuit and an automatic tuning control module, wherein the phase-adjustable trilateral competition ring oscillator is formed through a carry chain of the FPGA; the trilateral competition ring oscillator is realized on the FPGA and serves as an entropy source circuit, and can be transplanted to a pure digital logic hardware realization platform; the crash event detection circuit can correctly give an edge crash signal, accurately reflect the occurrence time of a crash event and reduce the occurrence probability of a metastable state; the automatic tuning control module can control the phase adjustment parameters of the ring oscillator, can control the working time and phase configuration of the trilateral competition ring oscillator in a manual or automatic mode, remarkably improves the throughput rate of random numbers, intercepts proper low significant bits from a system clock counter to serve as random numbers to be output, and improves the throughput rate of the random numbers. Therefore, the random number generation quality is met.

Description

Technical Field

[0001] The present invention relates to the field of information security and integrated circuit technology, and in particular to a phase-adjustable three-side competition true random number generator based on FPGA and a related method. Background Art

[0002] With the rapid development of communication technology, cloud computing and big data technology, the importance of information security issues has become increasingly prominent. In modern security systems, random numbers play an important role. They are often used in key generation, protocol handshakes and digital signatures. However, pseudo-random numbers are not truly random because they are generated by deterministic algorithms. They have a certain degree of predictability, which brings potential security risks to security systems that rely on random numbers. In view of the urgent need for highly reliable information encryption, pseudo-random numbers can no longer meet today's high standards. Therefore, the development of true random numbers is gradually receiving widespread attention. True random number generators (TRNGs) harvest entropy from physical noise sources. They are non-periodic, unpredictable, and have real-time randomness, which can provide protection for high-reliability encryption systems.

[0003] The structure of a traditional true random number generator can be divided into three parts according to its functions: entropy source circuit, sampling circuit and post-processing circuit.

[0004] The entropy source circuit is the source of randomness of the random number generator. There are four common ways to implement the entropy source: thermal noise amplification, oscillator sampling, chaotic system sampling, and metastable sampling. The source of randomness in the above methods is the thermal noise in the circuit. The sampling circuit is responsible for converting the random information collected by the entropy source circuit into a digital signal. The post-processing circuit is mainly used to repair some random defects in the sampled output sequence. For example, by post-processing the original sampled random sequence, the correlation of the sampling circuit output sequence is reduced. Typical post-processing methods of random number generators include XOR post-processing, hash post-processing, and von Neumann post-processing.

[0005] A survey of the implementation methods of entropy sources found that if entropy sources are implemented using analog design methods, the traditional method is to directly amplify the noise with high-gain and high-bandwidth amplifiers and then quantize it. These designs require careful calibration of the amplifiers and ADCs (analog-to-digital converters) to eliminate bias in the generated random numbers. Peripheral circuits such as sampling will introduce new noise that interferes with the entropy source, and the widespread use of analog designs has also reduced their attractiveness in terms of system integration and technology portability.

[0006] If the entropy source is realized by digital circuit design, the true random number generator based on metastable state has strict requirements on manufacturing process and working conditions, and has poor robustness to PVT (process, voltage, temperature) changes. In the TRNG of oscillator jitter sampling, because the phase jitter range caused by noise is very small, when using triggers for sampling, many certain values ​​will also be sampled, resulting in poor random quality of the random sequence generated by sampling. Generally speaking, the generated random sequence can only have better random quality after post-processing.

[0007] FPGA-based TRNG usually relies on physical noise sources to generate true random numbers. FPGA can use existing physical resources (such as power supply fluctuations, clock jitter, etc.) to generate random numbers. Compared with ASIC-based TRNG, the development cycle is short, and designers can dynamically configure and optimize hardware resources according to different system requirements, power consumption, speed, etc., which has better flexibility and scalability.

[0008] The TRNG based on three-edge competitive ring oscillator has attracted more and more attention because it overcomes the shortcomings of the traditional TRNG based on ring oscillator. The sampling clock and oscillation ring clock of the traditional TRNG based on ring oscillator will have jitter coupling, which will reduce the quality of random numbers. The three-edge competitive ring oscillator introduces three competitive edges to the same ring oscillator. The adjacent edges will collapse due to the accumulation of jitter, resulting in the remaining edge of the oscillation loop continuing to oscillate. The arrival time of the collapse event is only caused by the accumulation of jitter, eliminating the jitter coupling caused by the direct sampling of the ring oscillator by the sampling clock.

[0009] However, there are also some problems in the application of three-sided competitive ring oscillators in TRNG. The initial phase difference of adjacent edges of the three-sided competitive ring oscillator will be jointly affected by the injection position and the delay difference of the enable signal to the three injection positions. If the phase difference between two adjacent edges is close to 180°, these two edges will have a tendency to preferentially experience edge collapse. If the three edges are evenly injected into the three-sided competitive ring oscillator, the phase difference between adjacent edges is 120°, and it will become unpredictable between which two edges the edge collapse event will occur. Therefore, the randomness of the three-sided competitive ring oscillator will depend on the combined effect of the jitter accumulation caused by the thermal noise experienced by each edge, which can produce stronger randomness than the former. Therefore, the working state of the three-sided competitive ring oscillator is particularly sensitive to the delay of the path. Compared with ASIC, the path delay controllability of FPGA is poor. This poses a challenge to the implementation of the three-sided competitive ring oscillator on FPGA.

[0010] How to correctly detect whether an edge crash event has occurred is the key to extracting randomness from a three-sided competition ring oscillator. After a crash event occurs, the frequency of the three-sided competition ring oscillator will drop to one-third of the original frequency, so the crash event can be detected by reducing the frequency of the ring oscillator output. Existing methods use phase detectors to detect crash events, but the phase detector needs a reference clock of a suitable frequency to detect crash events, and the frequency of the reference clock needs to be between the frequency before the crash and the frequency after the crash. Due to the poor controllability of the path delay of FPGA, it is difficult to implement the reference clock on the FPGA. And because the output phase of the three-sided competition ring oscillator is uncertain before the crash event occurs, the output of the phase detector has the problem of Glitch (burr), and the results of the abnormal detection need to be filtered, so the structure of the crash event detection is complex. At the same time, due to the uncertainty of the phase of the three-sided competition ring oscillator, the method of directly counting edges to extract random numbers has the risk of metastable state, and the obtained count value has missing values ​​caused by metastable state.

[0011] In view of this, the present invention is proposed. Summary of the invention

[0012] The purpose of the present invention is to provide a phase-adjustable three-sided competition true random number generator based on FPGA and an implementation method thereof. A three-sided competition ring oscillator is formed by a carry chain of FPGA. Compared with the currently available three-sided competition ring oscillator, the phase of adjacent competition edges can be adjusted. At the same time, the detection circuit of the edge collapse event is simplified, and the edge collapse event is used to control the system clock counter, thereby accurately reflecting the occurrence time of the collapse event.

[0013] The objective of the present invention is achieved through the following technical solutions:

[0014] A phase-adjustable three-sided competition true random number generator based on FPGA, comprising: a three-sided competition ring oscillator, a crash event detection circuit and an automatic tuning control module formed by a carry chain of FPGA; wherein:

[0015] The three-sided competition ring oscillator is used as an entropy source circuit of a true random number generator; the automatic tuning control module is used to control the number of system clock cycles and phase configuration of the three-sided competition ring oscillator; the collapse event detection circuit is used to observe the working state of the three-sided competition ring oscillator, and when an edge collapse event is detected, the effective number of bits that meet the random number generation quality is extracted from the count value of the system clock counter as a random number output.

[0016] A random number generation method is implemented by the aforementioned phase-adjustable three-sided competition true random number generator based on FPGA, the method comprising:

[0017] The number of system clock cycles and phase configuration of the three-sided competition ring oscillator are controlled through the automatic tuning control module; the working state of the three-sided competition ring oscillator is observed through the collapse event detection circuit, and when an edge collapse event is detected, the system clock counter in the automatic tuning control module is controlled to output a count value, from which the effective number of bits that meet the random number generation quality is extracted as the random number output.

[0018] It can be seen from the technical solution provided by the present invention that in order to solve the problem that the ring oscillator in the existing three-sided competition ring oscillator true random number generator is difficult to implement on FPGA, a phase-adjustable three-sided competition ring oscillator based on FPGA is designed, and the phase-adjustable three-sided competition ring oscillator that can be implemented on FPGA is implemented with a pure digital unit, so that the entropy source can be transplanted to a pure digital logic hardware implementation platform; in order to solve the problem that the existing crash event detection scheme is complex and has low reliability, a simple and reliable crash event detection circuit is designed to judge the edge crash, and a correct edge crash signal is given after the edge crash event occurs, which can accurately reflect the occurrence time of the crash event and reduce the probability of the occurrence of metastable state. In addition, for the phase-adjustable three-sided competition ring oscillator, an automatic tuning control module is also designed to complete the control of the phase adjustment parameters of the ring oscillator; and the appropriate low-significant bits of the system clock counter in the automatic tuning control module are intercepted as random number output to meet the random number generation quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a phase-adjustable three-sided competition true random number generator based on FPGA provided in an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a phase-adjustable three-sided competitive ring oscillator provided in an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of a crash event detection circuit structure provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of edge collapse of a three-sided competition ring oscillator provided by an embodiment of the present invention;

[0024] Figure 5A schematic diagram of the output variation law of a three-sided competition ring oscillator before edge collapse provided by an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of the output variation law of a three-sided competition ring oscillator after edge collapse provided by an embodiment of the present invention;

[0026] Figure 7 A state transition diagram of a state machine of an automatic tuning control module provided by an embodiment of the present invention;

[0027] Figure 8 A schematic diagram of the structure of a phase-adjustable three-sided competition true random number generator based on FPGA provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0029] First, the terms that may be used in this article are explained as follows:

[0030] The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0031] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than the technical feature elements explicitly listed, except for the conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in the clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0032] Unless otherwise specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0033] The following is a detailed description of a phase-adjustable three-sided competition true random number generator based on FPGA and related methods provided by the present invention. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in this field. If no specific conditions are specified in the embodiments of the present invention, the conventional conditions in the field or the conditions recommended by the manufacturer are followed. The instruments used in the embodiments of the present invention, if the manufacturer is not specified, are all conventional products that can be purchased commercially.

[0034] Embodiment 1

[0035] The embodiment of the present invention provides a phase-adjustable three-sided competition true random number generator based on FPGA, such as Figure 1 As shown, it mainly includes: a phase-adjustable three-sided competitive ring oscillator (hereinafter referred to as a three-sided competitive ring oscillator), a crash event detection circuit and an automatic tuning control module are formed through a carry chain of an FPGA; wherein: the three-sided competitive ring oscillator is used as an entropy source circuit of a true random number generator; the automatic tuning control module is used to control the number of system clock cycles and phase configuration of the three-sided competitive ring oscillator; the crash event detection circuit is used to observe the working state of the three-sided competitive ring oscillator, and when an edge crash event is detected, the appropriate low-significant bit of the system clock counter in the automatic tuning control module is intercepted as a random number output.

[0036] In the embodiment of the present invention, the appropriate low-significant bit measurement indicator here is to be able to meet the quality of random number generation. Specifically, the least significant bit of the corresponding counter can be selected according to the randomness test result, and the present invention is not limited thereto. For example, when the counter is 16 bits, the lower 4 bits can be output as a random number and pass the test, but the lower 5 bits cannot pass the randomness test as a random number output. Therefore, under the condition of meeting the quality of random number generation, the lower 4 significant bits of the system clock counter can be intercepted as the random number output.

[0037] Preferably, the three-sided competition ring oscillator includes: three delay chains with programmable delays, each delay chain is composed of several (for example, 8) fast carry chains (Fast Carry Chain) connected end to end, and the first stage S0 of each delay chain is connected to the last stage CO3 of the adjacent delay chain.

[0038] Preferably, the crash event detection circuit is mainly composed of 8 cascaded D flip-flops, and uses the output difference before and after the crash event to detect the edge crash event. Compared with the existing design, the crash event detection circuit has the characteristics of simple structure, no reference clock, no Glitch, no error detection output, sufficient cross-clock domain design, and easy implementation on FPGA.

[0039] Preferably, the automatic tuning control module includes two working modes; the first is a manual mode, which determines the number of system clock cycles and phase configuration of the three-sided competition ring oscillator according to the current input, and the current input is the information input by the user to the automatic tuning control module in the manual mode, and the information content can be adjusted as needed; the second is an automatic mode, by calculating the average absolute deviation of the edge collapse cycle number under each phase configuration, and selecting the phase configuration corresponding to the largest average absolute deviation as the phase configuration of the three-sided competition ring oscillator, and selecting the sum of the edge collapse cycle number and the average absolute deviation as the number of system clock cycles of the three-sided competition ring oscillator. Through automatic tuning, the discreteness of the collapse time can be maximized, thereby significantly improving the throughput rate of the random number of TRNG.

[0040] The above-mentioned true random number generator provided by the embodiment of the present invention mainly has the following advantages:

[0041] (1) Design of a phase-adjustable three-sided competitive ring oscillator based on FPGA. In view of the problem that the existing three-sided competitive ring oscillator is difficult to implement on FPGA, the present invention proposes a phase-adjustable three-sided competitive ring oscillator that is composed of FPGA on-chip carry chain resources and can be implemented on FPGA. The three-sided competitive ring oscillator is implemented with pure digital units, so that the entropy source can be transplanted to a pure digital logic hardware implementation platform.

[0042] (2) Design of crash event detection circuit. Different from the traditional method of using phase detector to judge edge crash, the present invention designs a simple and reliable crash event detection circuit to judge edge crash, which can correctly give edge crash signal, extract random number from system clock counter, accurately reflect the occurrence time of crash event, and reduce the probability of metastable state.

[0043] (3) Design of automatic tuning control module. For the phase-adjustable three-sided competition ring oscillator proposed in the present invention, an automatic tuning control module is designed to control the phase adjustment parameters of the ring oscillator. Not only can the phase parameters of the ring oscillator and the number of working cycles per round be manually configured, but also the working time and phase configuration with the maximum collapse time discreteness can be automatically selected, thereby significantly improving the throughput of random numbers.

[0044] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the solution provided by the embodiment of the present invention is described in detail with specific embodiments below.

[0045] 1. Phase-adjustable three-sided competition true random number generator based on FPGA.

[0046] 1. Three-sided competitive ring oscillator.

[0047] like Figure 2 As shown, it is a schematic diagram of the structure of a three-sided competitive ring oscillator. The three-sided competitive ring oscillator has three delay chains with programmable delays, and each delay chain is composed of several (for example, 8) CARRY4 carry chain units. In the CARRY4 carry chain unit, S0-S3 are the selection ports of the two-to-one multiplexer, DI0-DI3 are the input ports of the data, CO0-CO3 are the carry result output ports, and CIN is the carry input port of the previous stage. The first stage S0 of each delay chain is connected to the last stage CO3 of the adjacent delay chain, thereby forming a three-sided competitive ring oscillator; the redundant S ports of the carry chain (i.e. Figure 2 The port connected to the signals SEL0, SEL1 and SEL2 in the three-sided competition ring oscillator is used as the phase configuration and oscillation start and stop control of the three-sided competition ring oscillator. The three competition edges of the three-sided competition ring oscillator are injected into the ring through SEL0, SEL1 and SEL2. In the oscillation start state, all bits of SEL0, SEL1 and SEL2 are 1. In the oscillation stop state, only one of all bits of SEL0, SEL1 and SEL2 is 0, and the rest are 1. By changing the position of 0 in SEL0, SEL1 and SEL2, the relative positions of the three edges injected into the three delay chains from oscillation stop to oscillation start can be adjusted, so that the phase difference of adjacent edges can be adjusted. By adjusting the phase difference of adjacent edges, not only can the delay difference of the wiring paths from the three CO3 to S0 be compensated, but also the discreteness of the time when the crash event occurs can be maximized, thereby improving the throughput of random number output.

[0048] Figure 2 In the figure, signals SEL0, SEL1 and SEL2 correspond to a delay chain respectively, and their values ​​correspond to the phase configuration information of the delay chain one by one. The numbers in [.] represent the delay programming signal index of the corresponding delay chain.

[0049] 2. Crash event detection circuit.

[0050] like Figure 3 As shown in FIG. 1 , a schematic diagram of the structure of a crash event detection circuit is shown, which includes a plurality of cascaded D flip-flops, such as Figure 3 As shown, an example of a collapse event detection circuit composed of 8 cascaded D flip-flops is provided. Figure 3In the example shown, REG0-REG4 belongs to the three-sided competition ring oscillator clock domain, REG5-REG7 belongs to the system clock domain, REG0, REG1, REG5 and REG6 are used for cross-clock domain synchronization, SYSCLK represents the system clock signal, rst_n represents the reset signal, and COLLAPSE represents the detection of a collapse event. If three rising edges of consecutive RO_OUT0 (the output of the first delay chain) arrive, the value of RO_OUT1 (the output of the second delay chain) is 1, and the value of RO_OUT2 (the output of the third delay chain) is 0, and it remains for two consecutive system cycles, a collapse event will be detected.

[0051] The schematic diagram of the edge collapse waveform of the three-sided competition ring oscillator is as follows Figure 4 As shown. The figure shows an example of three edges A, B, and C injected into the ring oscillator and their output at the output port RO_OUT0, where f represents the falling edge of the waveform and r represents the rising edge of the waveform. The three-edge competitive ring oscillator can inject three edges into the ring at the same time. Each edge propagates in the same way as a traditional ring oscillator, with the same period of each edge, and the frequency of the oscillation ring is increased by three times. These three edges independently accumulate jitter from thermal noise, resulting in increasing variations in the pulse width between two adjacent edges at each completed cycle. Eventually, the two adjacent edges will merge and collapse, forcing the three-edge competitive ring oscillator to return to the operating mode of the traditional ring oscillator at one times the frequency. The collapse time reflects the accumulation of jitter and is used as an entropy source for random number generation.

[0052] Before the edge collapse event occurs, there are three types of edges in the loop of the three-sided competition ring oscillator. The change rules of the three outputs of the three-sided competition ring oscillator and the three edges A, B, and C observed from RO_OUT0 are as follows: Figure 5 As shown. When the first rising edge of RO_OUT0 arrives, it is assumed that the rising edge is generated by A. If the value of RO_OUT1 is 1, the value of RO_OUT2 is 0. When the second rising edge of RO_OUT0 arrives, the rising edge is generated by B. From the waveform in the figure, it can be seen that the value of RO_OUT1 is 0 and the value of RO_OUT2 is 0. When the third rising edge of RO_OUT0 arrives, the rising edge is generated by C. From the waveform in the figure, it can be seen that the value of RO_OUT1 is 1 and the value of RO_OUT2 is 1. It can be seen that before the edge collapse occurs, it is impossible to achieve three consecutive rising edges of RO_OUT0 with the value of RO_OUT1 being 1 and the value of RO_OUT2 being 0. Therefore, the assumption is not true, and there will be no misjudgment of the collapse event.

[0053] When an edge collapse event occurs, there is only one edge in the loop of the three-sided competitive ring oscillator. The change rules of the three outputs of the three-sided competitive ring oscillator and the edges A, B, and C observed from RO_OUT0 are as follows: Figure 6 Whenever the rising edge of RO_OUT0 arrives, the value of RO_OUT1 is 1 and the value of RO_OUT2 is 0, so the output of REG1 is always 1. If the value of REG6 is 1 for two consecutive system clock cycles, the output COLLAPSE is 1, indicating that an edge collapse event is detected.

[0054] 3. Automatic tuning control module.

[0055] In the embodiment of the present invention, an automatic tuning control module is designed for the proposed phase-adjustable three-sided competition ring oscillator that can be implemented on an FPGA. The automatic tuning control module mainly includes: a phase configuration decoding module, a system clock counter, a statistical calculation module of the mean absolute deviation, and a state machine module; it has two working modes, namely, a manual mode and an automatic mode.

[0056] (1) In manual mode, the current input includes: the number of system clock cycles of each round of operation of the three-sided competition ring oscillator, the phase configuration signal and the effective number of bits of the generated random number; the phase configuration decoding module decodes the phase configuration signal into the selection signal of the corresponding delay chain in the three-sided competition ring oscillator (that is, the signals SEL0, SEL1 and SEL2 mentioned above), injects three competition edges into the three-sided competition ring oscillator, and observes the output of the crash event detection circuit. The meanings of the three competition edges here are as follows: in the oscillation stop state, only one of the bits of SEL0, SEL1 and SEL2 is 0, and the rest are 1. The position of 0 is the position of the three competition edges to be injected. In the oscillation start state, all the bits of SEL0, SEL1 and SEL2 are 1, SEL0, SEL1 and SEL2 will each undergo a process from 0 to 1 in the process from oscillation stop to start, and these three processes from 0 to 1 are the three competitive edges injected into the oscillation ring; when the effective output of the crash event detection circuit is observed, the oscillation of the three-sided competitive ring oscillator is terminated, the effective number of bits of the random number is extracted from the count value of the system clock counter, and the next oscillation is started; if the effective output of the crash event detection circuit is not observed within the working time of the input system clock cycle number, the oscillation is terminated after the system clock counter reaches the set number of cycles, the random number output is invalid, and the next oscillation is started; wherein, the effective output of the crash event detection circuit refers to the output generated when the crash event detection circuit detects an edge crash event.

[0057] (2) The automatic mode adds a statistical calculation module of the mean absolute deviation based on the manual mode. The automatic tuning process calculates the mean absolute deviation of the number of edge collapse cycles under each phase configuration, and selects the phase configuration corresponding to the largest mean absolute deviation as the phase configuration of the three-sided competition ring oscillator. The sum of the number of edge collapse cycles and the mean absolute deviation is selected as the number of system clock cycles for the three-sided competition ring oscillator. After the tuning is completed, the phase configuration generated by the tuning, the number of cycles of each round of the ring oscillator, and the number of effective bits of the random number are output. Through automatic tuning, the discreteness of the collapse time can be maximized, thereby significantly improving the throughput of random numbers.

[0058] The above state machine module is mainly used to configure the working state and conversion process of the automatic tuning control module. Figure 7 As shown, the working states of the automatic tuning control module include: state S0: default idle state; state S1: load the default three-sided competition ring oscillator phase configuration (in manual mode, the phase configuration is loaded according to the current input, and in automatic mode, the initial phase configuration of the traversal is loaded); state S2: the three-sided competition ring oscillator starts to oscillate until an edge collapse event occurs or a specified number of oscillation cycles is reached; state S3: the three-sided competition ring oscillator stops oscillating, obtains the count value of the system counter, and determines whether the random number output is valid (the three-sided competition ring oscillator reaches the number of oscillation cycles and stops, and the output is invalid, and the oscillator has an edge The output is valid if the system stops due to a crash event), and the result is stored, and the mean absolute deviation is not calculated for the stored result; state S4: the three-sided competition ring oscillator stops oscillating, the count value of the system counter is obtained, whether the random number output is valid is determined, and the result is stored, and the mean absolute deviation is calculated for the stored result; state S5: waiting for the mean absolute deviation calculation; state S6: obtaining the calculation result of the mean absolute deviation; state S7: maintaining the previous three-sided competition ring oscillator phase configuration; state S8: updating the three-sided competition ring oscillator phase configuration; state S9: automatic tuning is completed, and the best three-sided competition ring oscillator phase configuration is loaded.

[0059] Under the condition of turning on TRNG, the triggering conditions of each state transition path of the state machine of the automatic tuning control module are: 1. Default trigger; 2. Default trigger; 3. The edge collapse event does not occur and the system counter does not reach the count value; 4. In the automatic working mode, the edge collapse event occurs or the system counter reaches the count value, the tuning is completed or not enough data is collected to complete the calculation of the average absolute deviation, or in the manual working mode, the edge collapse event occurs or the system counter reaches the count value; 5. Default trigger; 6. Default trigger; 7. In the automatic working mode, the edge collapse event occurs or the system counter reaches the count value, the tuning is not completed and enough data is collected to complete the calculation of the average absolute deviation; 8. Default trigger; 9. The average absolute deviation calculation is not completed; 10. The average absolute deviation calculation is completed; 11. The phase configuration is not traversed; 12. Default trigger; 13. The phase configuration traversal is completed; 14. Default trigger. The sufficient here mainly refers to meeting the set number, which can be set according to the actual situation. The present invention is not limited. As an example, the number can be set to 64.

[0060] Based on the above introduction, the transition process of the automatic tuning control module state machine can be described as including:

[0061] The jump from state S0 to state S1 and from state S1 to state S2 are both default.

[0062] In state S2, if the system counter reaches the count value in automatic working mode, or an edge collapse event occurs, and the set amount of data is not collected to complete the calculation of the average absolute deviation, the state will be transferred to S3; or if the system counter reaches the count value in manual working mode, or an edge collapse event occurs, the state will be transferred to S3; if the system counter reaches the count value in automatic working mode, or an edge collapse event occurs, and the set amount of data is collected to complete the calculation of the average absolute deviation, the state will be transferred to S4; if the system counter does not reach the count value and no edge collapse event occurs, the state S2 will be maintained.

[0063] When in state S3, the default jump is to state S7; when in state S4, the default trigger is to state S5.

[0064] In state S5, if the mean absolute deviation calculation is not completed, then state S5 is maintained; if the mean absolute deviation calculation is completed, then the process jumps to state S6.

[0065] In state S6, if the phase configuration traversal is not completed, the state is transferred to S8; if the phase configuration traversal is completed, the state is transferred to S9.

[0066] In states S7, S8 and S9, the system jumps to state S2 by default.

[0067] Based on the above introduction, the overall structure of the phase-adjustable three-sided competition true random number generator based on FPGA is as follows: Figure 8 As shown, the three-sided competition ring oscillator is used as an entropy source circuit, and the automatic tuning control module contains a state machine module, a phase configuration decoding module, a system clock counter module and a mean absolute deviation calculation module. The automatic tuning control module is used to control the duration of each round of oscillation of the three-sided competition ring oscillator and adjust the phase configuration of the three-sided competition ring oscillator. The crash detection module is used to observe the working state of the three-sided competition ring oscillator, and the control system clock counter outputs the appropriate low-significant bit of the count value as a random number output, avoiding the metastable risk of directly counting the edges of the three-sided competition ring oscillator.

[0068] 2. Test instructions.

[0069] The random numbers generated by the phase-adjustable three-sided competition true random number generator based on FPGA of the present invention are tested using NIST SP 800-22 standard randomness test software. The NIST test suite contains 15 test items. The NIST randomness test suite outputs the P value of each test item according to the input random number: if the P value of all test items is greater than 0.01, it is considered that the randomness of the random number meets the requirements. Table 1 shows the test results of 100 groups of 1M data generated experimentally under normal temperature and voltage.

[0070] Table 1: NIST SP 800-22 test results

[0071]

[0072] In Table 1, * indicates that the minimum proportion of the sub-test is taken as the test result. The test results shown in Table 1 indicate that the random numbers generated by the phase-adjustable three-sided competition true random number generator based on FPGA of the present invention can pass all NIST randomness tests without post-processing.

[0073] Embodiment 2

[0074] The present invention also provides a random number generation method, which is mainly implemented by the phase-adjustable three-sided competition true random number generator based on FPGA provided in the above embodiment, and the method comprises:

[0075] The number of system clock cycles and phase configuration of the three-sided competition ring oscillator are controlled through the automatic tuning control module; the working state of the three-sided competition ring oscillator is observed through the collapse event detection circuit, and when an edge collapse event is detected, the system clock counter in the automatic tuning control module is controlled to output a count value, from which the effective number of bits that meet the random number generation quality is extracted as the random number output.

[0076] Considering that the main technical details involved in this method have been introduced in detail in the previous embodiments, they will not be repeated here.

[0077] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A phase-adjustable three-sided competition true random number generator based on FPGA, characterized in that: include: A three-side competition ring oscillator, a crash event detection circuit and an automatic tuning control module are formed through the carry chain of the FPGA; wherein: The three-sided competition ring oscillator is used as an entropy source circuit of a true random number generator; the automatic tuning control module is used to control the number of system clock cycles and phase configuration of the three-sided competition ring oscillator; the collapse event detection circuit is used to observe the working state of the three-sided competition ring oscillator, and when an edge collapse event is detected, the effective number of bits that meet the random number generation quality is extracted from the count value of the system clock counter as a random number output.

2. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 1, characterized in that: The three-side competition ring oscillator comprises: three delay chains with programmable delays, each delay chain is composed of a number of fast carry chains connected end to end, and the first stage S0 of each delay chain is connected to the last stage CO3 of the adjacent delay chain.

3. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 2, characterized in that: The competing edges of the three-sided competing ring oscillator are injected through SEL0, SEL1 and SEL2, and SEL0, SEL1 and SEL2 correspond to a delay chain respectively; In the oscillation start state, all bits of SEL0, SEL1 and SEL2 are 1, and in the oscillation stop state, only one bit of SEL0, SEL1 and SEL2 is 0, and the rest are 1; by changing the position of 0 in SEL0, SEL1 and SEL2, the relative positions of the three edges injected into the three delay chains from oscillation stop to oscillation start are adjusted, so that the phase difference of adjacent edges can be adjusted.

4. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 1, characterized in that: The collapse event detection circuit includes 8 cascaded D flip-flops, and uses the output difference before and after the collapse event to detect the edge collapse event.

5. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 1 or 4, characterized in that: Edge collapse event detection methods include: The output ports of the three delay chains in the three-sided competition ring oscillator are recorded as RO_OUT0, RO_OUT1, and RO_OUT2 respectively; if when a set number of consecutive rising edges of RO_OUT0 arrive, the value of RO_OUT1 is 1 and the value of RO_OUT2 is 0, and they are maintained for multiple consecutive system cycles, it means that an edge collapse event is detected.

6. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 1, characterized in that: The automatic tuning control module includes two working modes; The first is the manual mode, which determines the number of system clock cycles and phase configuration of the three-sided competition ring oscillator according to the current input; The second is the automatic mode, which calculates the average absolute deviation of the number of edge collapse cycles under each phase configuration, and selects the phase configuration corresponding to the largest average absolute deviation as the phase configuration of the three-sided competition ring oscillator, and selects the sum of the number of edge collapse cycles and the average absolute deviation as the number of system clock cycles of the three-sided competition ring oscillator.

7. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 6, characterized in that: The automatic tuning control module includes: a phase configuration decoding module and a system clock counter; In manual mode, the current input includes: the number of system clock cycles of each round of operation of the three-sided competition ring oscillator, the phase configuration signal and the effective number of bits of the generated random number; The phase configuration decoding module decodes the phase configuration signal into a selection signal of the corresponding delay chain in the three-sided competition ring oscillator, injects three competition edges into the three-sided competition ring oscillator, and observes the output of the crash event detection circuit; when the valid output of the crash event detection circuit is observed, the oscillation of the three-sided competition ring oscillator is terminated, the count value of the system clock counter is output as a random number, the valid number of bits of the random number is output, and the next oscillation is started; if the valid output of the crash event detection circuit is not observed within the working time of the input system clock cycle number, the oscillation is terminated after the system clock counter reaches the set number of cycles, the random number output is invalid, and the next oscillation is started; wherein, the valid output of the crash event detection circuit refers to the output generated when the crash event detection circuit detects an edge crash event.

8. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 6, characterized in that: The automatic tuning control module includes: a statistical calculation module of mean absolute deviation, which is used to calculate the mean absolute deviation in the automatic mode.

9. The phase-adjustable three-sided competition true random number generator based on FPGA according to claim 1, 6, 7 or 8, characterized in that: The automatic tuning control module includes: a state machine module, which is used to configure the working state and conversion process of the automatic tuning control module; The working states of the automatic tuning control module include: state S0: default idle state; state S1: load the default three-sided competition ring oscillator phase configuration, wherein the phase configuration is loaded according to the current input in manual mode, and the initial phase configuration traversed is loaded in automatic mode; state S2: the three-sided competition ring oscillator starts to oscillate until an edge collapse event occurs or a specified number of oscillation cycles is reached; state S3: the three-sided competition ring oscillator stops oscillating, obtains the count value of the system counter, and determines whether the random number output is valid, wherein the output of the three-sided competition ring oscillator is invalid if it stops when the three-sided competition ring oscillator reaches the number of oscillation cycles, and the three-sided competition ring oscillator stops oscillating. If the device stops due to an edge collapse event, the output is valid, and the result is stored, and the average absolute deviation is not calculated for the stored result; State S4: the three-sided competition ring oscillator stops oscillating, the count value of the system counter is obtained, whether the random number output is valid, and the result is stored, and the average absolute deviation is calculated for the stored result; State S5: waiting for the average absolute deviation calculation; State S6: obtaining the calculation result of the average absolute deviation; State S7: maintaining the previous three-sided competition ring oscillator phase configuration; State S8: updating the three-sided competition ring oscillator phase configuration; State S9: automatic tuning is completed, and the best three-sided competition ring oscillator phase configuration is loaded; The conversion process includes: The jump from state S0 to state S1 and from state S1 to state S2 are both default; In state S2, if the system counter reaches the count value in the automatic working mode, or an edge collapse event occurs, and the set amount of data is not collected to complete the calculation of the average absolute deviation, then the state is transferred to S3; or in the manual working mode, the system counter reaches the count value, or an edge collapse event occurs, then the state is transferred to S3; if the system counter reaches the count value in the automatic working mode, or an edge collapse event occurs, and the set amount of data is collected to complete the calculation of the average absolute deviation, then the state is transferred to S4; if the system counter does not reach the count value and no edge collapse event occurs, the state S2 is maintained; When in state S3, the default jump is to state S7; when in state S4, the default trigger is to state S5; In state S5, if the mean absolute deviation calculation is not completed, then the state S5 is maintained; if the mean absolute deviation calculation is completed, then the state S6 is jumped to; In state S6, if the phase configuration traversal is not completed, the state is transferred to S8; if the phase configuration traversal is completed, the state is transferred to S9; In states S7, S8 and S9, the system jumps to state S2 by default.

10. A random number generation method, characterized in that: The method is implemented by the FPGA-based phase-adjustable three-sided competition true random number generator according to any one of claims 1 to 9, and comprises: The number of system clock cycles and phase configuration of the three-sided competition ring oscillator are controlled through the automatic tuning control module; the working state of the three-sided competition ring oscillator is observed through the collapse event detection circuit, and when an edge collapse event is detected, the system clock counter in the automatic tuning control module is controlled to output a count value, from which the effective number of bits that meet the random number generation quality is extracted as the random number output.

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