Data prefetching method and device and processor

Abstract

The invention provides a data prefetching method and device and a processor, and relates to the technical field of computer processors, a data prefetcher generates a prefetching mode and records a resequencing queue number of a failure instruction according to a data cache access failure by responding to the data cache access failure, and adds the resequencing queue number to the corresponding prefetching mode; receiving a branch misprediction cancelling signal sent by the branch predictor, and analyzing the branch misprediction cancelling signal to obtain a resequencing queue number of the branch misprediction instruction; the method comprises the following steps of: receiving a branch misprediction instruction from a data prefetcher, matching a resequencing queue number of the branch misprediction instruction with a resequencing queue number in a prefetch mode, and cancelling a prefetch training and a prefetch request triggered by the branch misprediction instruction in the data prefetcher according to a matching result. And the internal logic of the data prefetcher is cancelled, so that the training of the prefetcher and the sent prefetch request are more accurate, the demand on the memory access bandwidth is reduced, and the overall performance of the processor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer processors, and in particular to a data pre-fetching method, device and processor. Background Art

[0002] Cache is a storage mechanism designed using the principle of program access locality. Its purpose is to make up for the huge gap between the processor's computing speed and storage access speed as much as possible. Prefetching technology is the key to improving the processor's memory access performance. An important way to improve the processor's memory system access performance is to reduce the failure rate of cache access. Prefetching is a way to reduce the computational miss by taking the cache blocks that the processor may need in advance. Inevitably, prefetching will occupy the processor's memory bandwidth and generate additional power consumption. In addition, if unnecessary cache blocks are taken or the prefetching timing is wrong, it may also cause cache pollution. Memory access failure requests on the branch instruction misprediction path will also train the data prefetcher and generate prefetch requests. This actually uses the memory access address that the processor does not really need to access the storage system to train the data prefetcher, resulting in the issuance of erroneous prefetch requests, resulting in a waste of memory access bandwidth and reducing the overall performance of the processor. Summary of the invention

[0003] The present invention provides a data prefetching method, device and processor, which are used to solve the defect that in the traditional data prefetching method, the failure of memory access instruction on the branch instruction misprediction path will cause the data prefetcher to be incorrectly trained, resulting in the issuance of erroneous prefetching requests, causing waste of memory access bandwidth and reducing the overall performance of the processor.

[0004] The present invention provides a data pre-fetching method, comprising: In response to a data cache access failure, the data prefetcher generates a prefetch pattern according to the data cache access failure and records a reordering queue number of a failed instruction corresponding to the data cache access failure, and appends the reordering queue number to the corresponding prefetch pattern; Receiving a branch misprediction cancellation signal sent by a branch predictor, parsing the branch misprediction cancellation signal to obtain a reordering queue number of the branch misprediction instruction; The reordering queue number of the branch misprediction instruction is matched with the reordering queue numbers in all prefetch modes, and the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher are cancelled according to the matching result.

[0005] According to the data pre-fetching method provided by the present invention, the data pre-fetcher comprises a pre-fetching training component, a pre-fetching filtering component and a pre-fetching issuing component; The pre-fetch training component is used to receive a data cache failure memory access instruction and generate a pre-fetch pattern according to the data cache access failure; The pre-fetch filter component is used to record the access request or pre-fetch request that has been issued by the pre-fetch training component. When the pre-fetch training component sends a new pre-fetch request, it is first filtered by the pre-fetch filter component. If it successfully matches the access request or pre-fetch request in the pre-fetch filter component, a new pre-fetch request with the same address will not be repeatedly issued; The pre-fetch issuing component issues a pre-fetch request to a next-level storage system according to the pre-fetch pattern generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

[0006] According to the data prefetching method provided by the present invention, each prefetching pattern generated by the prefetching training component includes a reordering queue number corresponding to a memory access invalid instruction. When a branch misprediction cancellation occurs, based on the reordering queue number of the canceled branch misprediction instruction, it is determined which prefetching pattern training is generated by the memory access instruction training on the wrong path after the canceled branch prediction instruction, and only the prefetching pattern training generated by the memory access instruction invalidation after the branch misprediction is canceled.

[0007] According to the data prefetching method provided by the present invention, each prefetching pattern issued by the prefetch issuing component includes a reordering queue number corresponding to the memory access failure instruction; When a branch misprediction cancellation occurs, it is determined based on the reordering queue number of the canceled branch misprediction instruction which prefetch request or prefetch requests to be issued are generated by the training of the memory access instruction on the wrong path after the canceled branch prediction instruction, and no prefetch requests generated by the failure of the memory access instruction after the branch misprediction are issued.

[0008] According to the data prefetching method provided by the present invention, the prefetching filtering component is also used to learn the prefetching addresses that are filtered multiple times in succession to generate a reverse training signal, and the reverse training signal is used to suppress the prefetching training of the same address by the prefetching training component.

[0009] According to the data prefetching method provided by the present invention, the reordering queue number is used to identify the order of instructions in the reordering queue; Instructions of a correct path and an erroneous prediction path are distinguished according to the sequence of the reordering queue numbers.

[0010] The present invention also provides a data pre-fetching device, comprising: A data prefetcher, for generating a prefetch pattern according to a data cache access failure and recording a reordering queue number of a failed instruction corresponding to the data cache access failure when a data cache access failure occurs, and appending the reordering queue number to a corresponding prefetch pattern; A branch predictor, configured to send a branch misprediction cancellation signal to the data prefetcher; The data prefetcher is also used to receive a branch misprediction cancellation signal sent by a branch predictor, parse the branch misprediction cancellation signal to obtain the reordering queue number of the branch misprediction instruction; match the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, and cancel the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

[0011] According to the data prefetch device provided by the present invention, the branch predictor is connected to the data prefetcher for transmitting the misprediction cancellation signal and the reordering queue number of the branch misprediction instruction in real time.

[0012] According to the data pre-fetching device provided by the present invention, the data pre-fetcher comprises a pre-fetching training component, a pre-fetching filtering component and a pre-fetching issuing component; The pre-fetch training component is used to receive a data cache failure memory access instruction and generate a pre-fetch pattern according to the data cache access failure; The pre-fetch filter component is used to record the access request or pre-fetch request that has been issued by the pre-fetch training component. When the pre-fetch training component sends a new pre-fetch request, it is first filtered by the pre-fetch filter component. If it successfully matches the access request or pre-fetch request in the pre-fetch filter component, a new pre-fetch request with the same address will not be repeatedly issued; The pre-fetch issuing component issues a pre-fetch request to a next-level storage system according to the pre-fetch pattern generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

[0013] The present invention also provides a processor, comprising: the data pre-fetching device and cache as described above.

[0014] The data prefetch method, device and processor provided by the present invention, in response to data cache access failure, a data prefetcher generates a prefetch mode according to the data cache access failure and records the reordering queue number of the failed instruction corresponding to the data cache access failure, and adds the reordering queue number to the corresponding prefetch mode; receives a branch misprediction cancellation signal sent by a branch predictor, parses the branch misprediction cancellation signal to obtain the reordering queue number of the branch misprediction instruction; matches the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, cancels the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result, and cancels the logic inside the data prefetcher according to the reordering queue number of the failed instruction and the branch misprediction cancellation signal, so that the training of the data prefetcher and the prefetch request issued are more accurate, reducing the demand for memory access bandwidth, thereby improving the overall performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a flowchart of a data pre-fetching method provided by an embodiment of the present invention; Figure 2 It is a logical schematic diagram of canceling data prefetching due to branch prediction error provided by an embodiment of the present invention.

[0017] Figure 3 It is a functional structure diagram of a data pre-fetching device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] Figure 1 A flowchart of a data pre-fetching method provided by an embodiment of the present invention, such as Figure 1 As shown, the data pre-fetching method provided by the embodiment of the present invention includes: Step 101, in response to a data cache access failure, a data prefetcher generates a prefetch pattern according to the data cache access failure and records a reordering queue number of a failed instruction corresponding to the data cache access failure, and adds the reordering queue number to the corresponding prefetch pattern; Step 102: receiving a branch misprediction cancellation signal sent by a branch predictor, parsing the branch misprediction cancellation signal to obtain a reordering queue number of the branch misprediction instruction; Step 103: Match the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, and cancel the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

[0020] In an embodiment of the present invention, the reordering queue number is used to identify the order of instructions in the reordering queue; the instructions of the correct path and the misprediction path are distinguished according to the order of the reordering queue numbers. The reordering queue is a circular queue, and the reordering queue numbers are allocated cyclically according to the order in which the instructions enter the pipeline, and the reordering queue numbers of the instructions after the branch misprediction instruction are arranged after the reordering queue number of the branch misprediction instruction.

[0021] In traditional data prefetching methods, invalid requests will also train the data prefetcher and generate prefetch requests. This actually uses memory addresses that are not actually needed by the processor to access the storage system to train the data prefetcher, resulting in erroneous prefetch requests, causing a waste of memory access bandwidth and reducing the overall performance of the processor.

[0022] The data prefetch method provided by the embodiment of the present invention, in response to data cache access failure, a data prefetcher generates a prefetch mode according to the data cache access failure and records the reordering queue number of the failed instruction corresponding to the data cache access failure, and adds the reordering queue number to the corresponding prefetch mode; receives a branch misprediction cancellation signal sent by a branch predictor, parses the branch misprediction cancellation signal to obtain the reordering queue number of the branch misprediction instruction; matches the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, cancels the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result, and cancels the logic inside the data prefetcher according to the reordering queue number of the failed instruction and the branch misprediction cancellation signal, so that the training of the data prefetcher and the prefetch request issued are more accurate, the memory access bandwidth is reduced, and the overall performance of the processor is improved.

[0023] Based on any of the above embodiments, Figure 2 As shown, the data prefetcher includes a prefetch training component, a prefetch filtering component and a prefetch issuing component; The pre-fetch training component is used to receive a data cache failure memory access instruction and generate a pre-fetch pattern according to the data cache access failure; The pre-fetch filter component is used to record the access request or pre-fetch request that has been issued by the pre-fetch training component. When the pre-fetch training component sends a new pre-fetch request, it is first filtered by the pre-fetch filter component. If it successfully matches the access request or pre-fetch request in the pre-fetch filter component, a new pre-fetch request with the same address will not be repeatedly issued; The pre-fetch issuing component issues a pre-fetch request to a next-level storage system according to the pre-fetch pattern generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

[0024] In an embodiment of the present invention, failed memory access instructions include data cache misses of load instructions and store instructions. The pre-fetch filtering component records the access requests and pre-fetch requests that have been issued to the next-level storage system from the memory access miss queue. When there is a new pre-fetch request sent by the pre-fetch training component, the pre-fetch filtering component is checked first. If the access request or pre-fetch request for the same address has been issued, a new pre-fetch request for the same address will not be repeatedly issued to save memory access bandwidth. The pre-fetch issuing component sends a pre-fetch request to the next-level storage system according to the pre-fetch mode generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

[0025] In an embodiment of the present invention, each prefetch pattern generated by the prefetch training component includes a reordering queue number corresponding to a memory access invalidation instruction. When a branch misprediction cancellation occurs, based on the reordering queue number of the canceled branch misprediction instruction, it is determined which prefetch pattern training is generated by the memory access instruction training on the wrong path after the canceled branch prediction instruction, and only the prefetch pattern training generated by the memory access instruction invalidation after the branch misprediction is canceled.

[0026] In an embodiment of the present invention, each prefetch pattern issued by the prefetch issuing component includes a reordering queue number corresponding to a memory access failure instruction; when a branch misprediction cancellation occurs, based on the reordering queue number of the canceled branch misprediction instruction, it is determined which prefetch request or prefetch requests to be issued are generated by the memory access instruction training on the wrong path after the canceled branch prediction instruction, and no prefetch request generated by the memory access instruction failure after the branch misprediction is issued.

[0027] In the embodiment of the present invention, the source path of the pre-fetch request can be accurately traced by reordering the queue number (Reorder Buffer Id, robid), so as to avoid affecting the pre-fetch of the correct path.

[0028] In the embodiment of the present invention, the pre-fetch filtering component is further used to learn the pre-fetch addresses that are filtered multiple times in succession to generate a reverse training signal, and the reverse training signal is used to suppress the pre-fetch training of the pre-fetch training component on the same address.

[0029] Based on any of the above embodiments, in the branch prediction stage, the processor encounters a branch misprediction instruction (e.g., if (x>0)), and the branch predictor predicts it as a "jump" and jumps to address A (assuming that the correct path should be address B). At this point, the processor begins to execute subsequent instructions out of order according to the predicted path (address A), including data prefetch operations.

[0030] On the wrong path (address A), there is a memory access instruction Load [addr_A_data], but this instruction fails when accessing the data cache (Cache Miss). The prefetch training unit of the data prefetcher generates a prefetch pattern based on this failed address and plans to prefetch data at adjacent addresses (such as addr_A_data + 64).

[0031] When the pipeline finds that the branch should actually jump to address B, the branch predictor sends a branch misprediction cancellation signal with the robid of the branch misprediction instruction (for example, robid=50). After receiving the cancellation signal, the prefetch training unit of the data prefetcher checks the robid corresponding to all prefetch patterns being trained. If a prefetch pattern is generated by an instruction with a robid number after 50 (that is, the instruction after the branch error path), the training is canceled directly.

[0032] In the implementation of the present invention, the robid of Load [addr_A_data] = 55 (belonging to the wrong path), and the prefetch pattern (addr_A_data + 64) generated by it will be marked as invalid.

[0033] The prefetch issuing unit originally planned to issue a prefetch request addr_A_data + 64, but after receiving the branch cancellation signal, it checked the robid (55) of the request. Since the instruction with robid 55 is after the instruction with robid 50, it is determined that the request belongs to the wrong path and is directly canceled to avoid prefetching useless data.

[0034] The processor starts executing the correct path (address B), and the new memory access instruction Load [addr_B_data] triggers a data cache invalidation.

[0035] The data prefetcher is retrained based on the invalid address of the correct path, generates a new prefetch request (such as addr_B_data + 64), and is issued normally through the filtering component.

[0036] The embodiment of the present invention can avoid bandwidth waste, cancel the pre-fetch request (addr_A_data+64) on the wrong path, save storage bandwidth. In addition, the data of the wrong path will not be pre-fetched into the cache, avoiding squeezing out valid data.

[0037] In the data prefetching method provided by the embodiment of the present invention, the data prefetcher is trained and requests are issued only for the correct path, thereby improving the prefetching hit rate and accelerating program execution; the branch misprediction signal is triggered in real time to ensure that the prefetcher state is consistent with the actual execution path of the processor.

[0038] The data pre-fetching device provided by the present invention is described below. The data pre-fetching device described below and the data pre-fetching method described above can be referred to each other.

[0039] Figure 3 A schematic diagram of the structure of a data pre-fetching device provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the data pre-fetching device provided by the embodiment of the present invention includes: A data prefetcher 301, configured to generate a prefetch pattern according to a data cache access failure when the data cache access fails, record a reordering queue number of a failed instruction corresponding to the data cache access failure, and append the reordering queue number to a corresponding prefetch pattern; A branch predictor 302, configured to send a branch misprediction cancellation signal to the data prefetcher; The data prefetcher 301 is also used to receive a branch misprediction cancellation signal sent by the branch predictor, parse the branch misprediction cancellation signal to obtain the reordering queue number of the branch misprediction instruction; match the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, and cancel the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

[0040] In an example of the present invention, the branch predictor is connected to the data prefetcher for transmitting a misprediction cancellation signal and a reordering queue number of a branch misprediction instruction in real time.

[0041] In an embodiment of the present invention, a branch misprediction cancellation signal of a branch predictor is connected to a prefetch training unit and a prefetch issuing unit of a data prefetcher. When a branch misprediction of a branch misprediction instruction occurs, a branch misprediction signal is transmitted to the data predictor, and the data predictor cancels the prefetch training and the prefetch issuing according to the branch misprediction signal, thereby avoiding the memory access instruction failure (Miss) on the branch misprediction path from erroneously training the data prefetcher, thereby issuing an erroneous prefetch request.

[0042] In an example of the present invention, the data prefetcher includes a prefetch training component, a prefetch filtering component and a prefetch issuing component; The pre-fetch training component is used to receive a data cache failure memory access instruction and generate a pre-fetch pattern according to the data cache access failure; The pre-fetch filter component is used to record the access request or pre-fetch request that has been issued by the pre-fetch training component. When the pre-fetch training component sends a new pre-fetch request, it is first filtered by the pre-fetch filter component. If it successfully matches the access request or pre-fetch request in the pre-fetch filter component, a new pre-fetch request with the same address will not be repeatedly issued; The pre-fetch issuing component issues a pre-fetch request to a next-level storage system according to the pre-fetch pattern generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

[0043] The data prefetch device provided by the embodiment of the present invention, in response to a data cache access failure, a data prefetcher generates a prefetch mode according to the data cache access failure and records the reordering queue number of the failed instruction corresponding to the data cache access failure, and adds the reordering queue number to the corresponding prefetch mode; receives a branch misprediction cancellation signal sent by a branch predictor, parses the branch misprediction cancellation signal to obtain the reordering queue number of the branch misprediction instruction; matches the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, cancels the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result, and cancels the logic inside the data prefetcher according to the reordering queue number of the failed instruction and the branch misprediction cancellation signal, so that the training of the data prefetcher and the prefetch request issued are more accurate, reducing the demand for memory access bandwidth, thereby improving the overall performance of the processor.

[0044] An embodiment of the present invention further provides a processor, comprising: the data pre-fetching device and cache as described in the above embodiment.

[0045] Instructions that access the storage system in traditional processors, including load instructions and store instructions, will access the data cache (DCache). Both load instructions and store instructions may cause a miss in the data cache access. The miss request will train the data prefetcher and generate a prefetch request.

[0046] High-performance superscalar processors use out-of-order pipeline technology, which brings with it the problem of branch instruction misprediction. When the processor is executed out of order, the memory access instruction to access the data cache may come from the branch misprediction path, which causes the memory access instruction from the branch misprediction path to fail (Miss), and the data prefetcher is trained incorrectly. In fact, the data prefetcher is trained with a memory access address that is not actually needed by the processor to access the storage system, resulting in an erroneous prefetch request.

[0047] In the embodiment of the present invention, the instructions of the processor all have a reordering queue number that can identify the instruction sequence. When a branch is canceled, the robid of the branch misprediction instruction where the branch misprediction occurs is sent to the data prefetcher together with the branch misprediction signal.

[0048] The prefetch training component and the prefetch issuing component of the data prefetcher generate each prefetch pattern and also carry the robid corresponding to the memory access invalidation instruction that generated the prefetch pattern. When a branch misprediction cancellation occurs, the robid number of the canceled branch misprediction instruction is used to determine which prefetch pattern training is generated by the memory access instruction training on the wrong path after the canceled branch prediction instruction, and only the prefetch pattern training generated by the memory access instruction invalidation after the branch misprediction is canceled.

[0049] Similarly, for the prefetch issuing component, when a branch misprediction cancellation occurs, it is determined based on the robid number of the canceled branch misprediction instruction which prefetch requests to be issued are generated by the memory access instruction training on the wrong path after the canceled branch prediction instruction, and only the prefetch requests generated by the prefetch mode training caused by the failure of the memory access instruction after the branch misprediction are canceled and no longer issued.

[0050] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0051] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data pre-fetching method, characterized in that: include: In response to a data cache access failure, the data prefetcher generates a prefetch pattern according to the data cache access failure and records a reordering queue number of a failed instruction corresponding to the data cache access failure, and appends the reordering queue number to the corresponding prefetch pattern; Receiving a branch misprediction cancellation signal sent by a branch predictor, parsing the branch misprediction cancellation signal to obtain a reordering queue number of the branch misprediction instruction; The reordering queue number of the branch misprediction instruction is matched with the reordering queue numbers in all prefetch modes, and the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher are cancelled according to the matching result.

2. The data pre-fetching method according to claim 1, characterized in that: The data prefetcher comprises a prefetch training component, a prefetch filtering component and a prefetch issuing component; The pre-fetch training component is used to receive a data cache failure memory access instruction and generate a pre-fetch pattern according to the data cache access failure; The pre-fetch filter component is used to record the access request or pre-fetch request that has been issued by the pre-fetch training component. When the pre-fetch training component sends a new pre-fetch request, it is first filtered by the pre-fetch filter component. If it successfully matches the access request or pre-fetch request in the pre-fetch filter component, a new pre-fetch request with the same address will not be repeatedly issued; The pre-fetch issuing component issues a pre-fetch request to a next-level storage system according to the pre-fetch pattern generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

3. The data pre-fetching method according to claim 2, characterized in that: Each prefetch pattern generated by the prefetch training component includes a reordering queue number corresponding to a memory access invalid instruction. When a branch misprediction cancellation occurs, based on the reordering queue number of the canceled branch misprediction instruction, it is determined which prefetch pattern training is generated by the memory access instruction training on the wrong path after the canceled branch prediction instruction, and only the prefetch pattern training generated by the memory access instruction invalidation after the branch misprediction is canceled.

4. The data pre-fetching method according to claim 2, characterized in that: Each prefetch pattern issued by the prefetch issuing component includes a reordering queue number corresponding to the memory access failure instruction; When a branch misprediction cancellation occurs, it is determined based on the reordering queue number of the canceled branch misprediction instruction which prefetch request or prefetch requests to be issued are generated by the training of the memory access instruction on the wrong path after the canceled branch prediction instruction, and no prefetch requests generated by the failure of the memory access instruction after the branch misprediction are issued.

5. The data pre-fetching method according to claim 2, characterized in that: The pre-fetch filtering component is further used to learn the pre-fetch addresses that are filtered for multiple consecutive times and generate a reverse training signal, wherein the reverse training signal is used to suppress the pre-fetch training of the pre-fetch training component for the same address.

6. The data pre-fetching method according to any one of claims 1 to 5, characterized in that: The reordering queue number is used to identify the order of instructions in the reordering queue; Instructions of a correct path and an erroneous prediction path are distinguished according to the sequence of the reordering queue numbers.

7. A data pre-fetching device, characterized in that: include: A data prefetcher, for generating a prefetch pattern according to a data cache access failure and recording a reordering queue number of a failed instruction corresponding to the data cache access failure when a data cache access failure occurs, and attaching the reordering queue number to a corresponding prefetch pattern; A branch predictor, configured to send a branch misprediction cancellation signal to the data prefetcher; The data prefetcher is also used to receive a branch misprediction cancellation signal sent by a branch predictor, parse the branch misprediction cancellation signal to obtain the reordering queue number of the branch misprediction instruction; match the reordering queue number of the branch misprediction instruction with the reordering queue numbers in all prefetch modes, and cancel the prefetch training and prefetch request triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

8. The data pre-fetching device according to claim 7, characterized in that: The branch predictor is connected to the data prefetcher via a bus, and is used to transmit a misprediction cancellation signal and a reordering queue number of a branch misprediction instruction in real time.

9. The data pre-fetching device according to claim 7, characterized in that: The data prefetcher comprises a prefetch training component, a prefetch filtering component and a prefetch issuing component; The pre-fetch training component is used to receive a data cache failure memory access instruction and generate a pre-fetch pattern according to the data cache access failure; The pre-fetch filter component is used to record the access request or pre-fetch request that has been issued by the pre-fetch training component. When the pre-fetch training component sends a new pre-fetch request, it is first filtered by the pre-fetch filter component. If it successfully matches the access request or pre-fetch request in the pre-fetch filter component, a new pre-fetch request with the same address will not be repeatedly issued; The pre-fetch issuing component issues a pre-fetch request to a next-level storage system according to the pre-fetch pattern generated by the pre-fetch training component and after filtering by the pre-fetch filtering component.

10. A processor, characterized in that: include: A data pre-fetching device and cache as claimed in any one of claims 7 to 9.

Images