Memory screening method, electronic equipment and computer readable storage medium

Abstract

The invention discloses a memory screening method, electronic equipment and a computer readable storage medium, and belongs to the field of chip design. The method comprises the steps of generating a target data file of each designed memory based on target configuration information for memory design; the target data file comprises performance information, power consumption information and area information; determining a performance score, a power consumption score and an area score of each designed memory based on the performance information, the power consumption information and the area information of each designed memory; wherein the performance score is a score obtained by performing normalization processing on the performance information; the power consumption score is a score obtained based on normalization processing of the power consumption information; the area score is a score obtained based on normalization processing of the area information; determining a comprehensive score of each designed memory based on the performance score, the power consumption score and the area score; and determining a target memory based on the comprehensive score of each designed memory.

Description

Technical Field

[0001] The present application belongs to the field of chip design, and specifically relates to a memory screening method, an electronic device and a computer-readable storage medium. Background Art

[0002] In the chip design process, memory is often used to store data. In the process of memory selection, different modules have different focuses on various memory performances. Some modules have higher requirements for timing, while some modules hope to minimize the area. Therefore, it may happen that the memory used in the early stage is found in the middle and late stages that a certain data does not meet the requirements, so the memory type needs to be changed and iterated, which may even affect the R&D progress in serious cases. In order to solve these problems, an efficient memory screening method is needed.

[0003] The related technology will traverse all memory configuration items during the process of screening memory, retain the memory that meets the timing, record the configuration with the smallest area during the traversal process, and finally screen out the memory with the smallest area.

[0004] However, the related technology only selects the memory with the smallest area. It may happen that the memory that meets the requirements in the early stage may be found to fail to meet the requirements for a certain data in the middle and late stages. This may easily lead to the need to replace the memory in the project, resulting in too many iterations and affecting the project progress. Summary of the invention

[0005] The embodiments of the present application provide a memory screening method, an electronic device, and a computer-readable storage medium, which can solve the problem that the memory screened by the related technology still needs to be replaced, resulting in too many iterations.

[0006] In a first aspect, an embodiment of the present application provides a method for screening a memory, comprising: Based on the target configuration information for memory design, generating target data files for each designed memory; the target data files include performance information, power consumption information and area information; Determine a performance score of each designed memory based on the performance information of each designed memory; wherein the performance score is a score obtained by normalizing the performance information; Based on the power consumption information of each designed memory, determine the power consumption score of each designed memory; wherein the power consumption score is a score obtained by normalizing the power consumption information; Based on the area information of each designed memory, determine the area score of each designed memory; wherein the area score is a score obtained by normalizing the area information; Determine a comprehensive score of each designed memory based on the performance score, the power consumption score and the area score; A target memory is determined from the plurality of designed memories based on comprehensive scores of the designed memories.

[0007] In a second aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0008] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed, the steps of the method described in the first aspect are implemented.

[0009] In a fourth aspect, an embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the method described in the first aspect.

[0010] At least one of the above technical solutions provided in the embodiments of the present application can achieve the following technical effects: In an embodiment of the present application, based on target configuration information for memory design, a target data file of each designed memory is generated; the target data file includes performance information, power consumption information and area information; based on the performance information of each designed memory, a performance score of each designed memory is determined; wherein the performance score is a score obtained by normalizing the performance information; based on the power consumption information of each designed memory, a power consumption score of each designed memory is determined; wherein the power consumption score is a score obtained by normalizing the power consumption information; based on the area information of each designed memory, an area score of each designed memory is determined; wherein the area score is a score obtained by normalizing the area information; based on the performance score, the power consumption score and the area score, a comprehensive score of each designed memory is determined; based on the comprehensive score of each designed memory, a target memory is determined from multiple designed memories. In this way, by comprehensively considering the performance score, power consumption score and area score, the comprehensive score of each designed memory is obtained, and then the target memory is determined, which can automatically screen out the better memory, help to screen out the memory with more suitable performance (such as timing), area and power consumption in advance, reduce the number of iterations of memory selection, and solve the problem of too many iterations caused by the memory obtained by related technology screening still needing to be replaced in the middle and late stages. In addition, the performance score, power consumption score and area score are all obtained through normalization processing, so that the scores of these three dimensions can be measured uniformly, ensuring the universality and accuracy of the scores, making the final comprehensive score more objective and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 is a flow chart of a memory screening method provided in an embodiment of the present application; Figure 2 is a flow chart of another memory screening method provided in an embodiment of the present application; Figure 3 is a flow chart of another memory screening method provided in an embodiment of the present application; Figure 4 is a flow chart of another memory screening method provided in an embodiment of the present application; Figure 5is a flow chart of another memory screening method provided in an embodiment of the present application; Figure 6 It is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0015] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] The memory design process in the related technology generally only compares whether the timing is met in the process. If the timing is met, the memory with the smallest area is compared and selected. This comparison method is more feasible in projects and modules that are not sensitive to power consumption. However, many applications currently have to take power consumption into consideration, which can easily lead to the discovery that the power consumption data does not meet the expected target during the power consumption evaluation stage, so the design needs to be modified, and it may even be necessary to use ECO (Engineering Change Order) to replace it with a memory with lower power consumption. In addition, more real physical parameters will be introduced during the back-end layout and routing. The memory that meets the timing in the memory generation stage may find that the timing is not met when the back-end performs timing convergence, or the back-end finds that the shape of the memory is not conducive to the layout and routing of the memory during layout and routing, resulting in memory iteration.

[0017] The embodiments of the present application provide a method for the tool to automatically select the optimal memory, which helps R&D personnel to select memories with more suitable timing, area, and power consumption in advance, thereby reducing or avoiding the iteration of memory replacement selection.

[0018] In addition, some memories may have the need for error detection, error correction, or power consumption control. This part of the logic circuit is generally related to the structural characteristics of the memory such as type, width, depth, and multiplexing (mux), and it is difficult to make a fixed module for calling. Therefore, this part of the logic circuit often requires R&D personnel to learn, design, and verify the algorithm. If multiple modules have such requirements, the R&D personnel of each module need to go through the process of learning, development, and verification, and the independent development of each module is not conducive to the version upgrade and maintenance of the algorithm circuit. In the embodiment of the present application, a universal top-level interface is used to encapsulate the contents of the encapsulated memory (for example, containing the target functional circuit) to obtain a target encapsulated memory, and the target encapsulated memory is used for unified calling by different callers. The entire process does not require the module R&D personnel to develop from scratch. The embodiment of the present application can integrate the generation script of the target functional circuit, such as the script of the ECC (Error Correcting Coding) circuit and the power consumption control circuit. By entering the type (type), width (width), depth (depth), multiplexing (mux) and other structural information into the script, the relevant logic circuit can be directly generated, saving development time. If there is a version update for this part of the circuit function, the script can be updated to uniformly upgrade all functional circuits, which is more conducive to version management.

[0019] The memory screening method provided in the embodiment of the present application can be executed by a target device, and software for memory design can be deployed on the target device. The target device can be a terminal device such as a personal computer, or a server.

[0020] Figure 1 is a flow chart of a memory screening method provided in an embodiment of the present application. Figure 1 , the memory screening method provided in the embodiment of the present application includes: Step 110, generating a target data file of each designed memory based on the target configuration information for memory design; the target data file includes performance information, power consumption information and area information; In an embodiment of the present application, the target configuration information may be in the form of a configuration file. The target configuration information may be obtained based on the requirement items in the memory requirement table. The requirement items include memory depth, memory width, and memory clock frequency. Of course, the requirement items in the embodiment of the present application may also include at least one of memory type, number of instantiations, built-in self-test (BIST) enable, power gating (PG) enable, ECC enable, power consumption control circuit enable, and frequency weight, area weight, static power consumption weight, and dynamic power consumption weight.

[0021] Before generating target data files of each designed memory based on the target configuration information for memory design in step 110, an embodiment of the present application may first establish a depth and width range support table, and then ensure that the depth and width in the requirement items meet the requirements of the depth and width range support table based on the depth and width range support table, thereby obtaining the target configuration information for memory design.

[0022] Specifically, in one embodiment of the present application, before step 110, the memory screening method provided by the embodiment of the present application may also include: obtaining a memory requirement table, the memory requirement table including requirement items, the requirement items including memory depth and memory width; based on a pre-established depth and width range support table, determining whether the memory depth and memory width in the requirement items meet the configuration requirements; if the memory depth and memory width in the requirement items do not meet the configuration requirements, splitting the target entries in the requirement items to obtain memory depth and memory width that meet the configuration requirements; the target entries include at least one of memory depth and memory width; if the memory depth and memory width in the requirement items meet the configuration requirements, based on the memory depth and memory width in the requirement items, obtaining target configuration information for memory design. In this way, by using the depth and width range support table and splitting the target entries in the requirement items, it can be ensured that the obtained target configuration information meets the requirements of the pre-established depth and width range support table.

[0023] Step 120, determining a performance score of each designed memory based on the performance information of each designed memory; wherein the performance score is a score obtained by normalizing the performance information; In an embodiment of the present application, the performance information may include timing information. In step 120, based on the performance information of each designed memory, determining the performance score of each designed memory may include: determining a normalized timing factor based on the timing information of each designed memory; and determining the performance score of each designed memory based on the normalized timing factor. Wherein, the normalized timing factor is obtained by normalizing the timing information. Determining the performance score of each designed memory based on the normalized timing factor may include: determining the performance score of each designed memory based on the normalized timing factor and the timing weight, wherein the timing weight may be a preset weight or a normalized weight.

[0024] Step 130, determining a power consumption score of each designed memory based on the power consumption information of each designed memory; wherein the power consumption score is a score obtained by normalizing the power consumption information; In an embodiment of the present application, determining the performance score of each designed memory based on the power consumption information of each designed memory in step 130 may include: determining a normalized power consumption factor based on the power consumption information of each designed memory; and determining the power consumption score of each designed memory based on the normalized power consumption factor. The normalized power consumption factor is obtained by normalizing the power consumption information. Determining the power consumption score of each designed memory based on the normalized power consumption factor may include: determining the power consumption score of each designed memory based on the normalized power consumption factor and the power consumption weight, wherein the power consumption weight may be a preset weight or a normalized weight.

[0025] In an embodiment of the present application, the power consumption information may include at least one of a static power consumption value and a dynamic power consumption value. The normalized power consumption factor includes at least one of a normalized static power consumption factor and a normalized dynamic power consumption factor. In the case where the power consumption information includes a static power consumption value and a dynamic power consumption value, a normalized static power consumption factor may be determined based on the static power consumption value of each designed memory; and a static power consumption score of each designed memory may be determined based on the normalized static power consumption factor. At the same time, a normalized dynamic power consumption factor may be determined based on the dynamic power consumption value of each designed memory; and a dynamic power consumption score of each designed memory may be determined based on the normalized dynamic power consumption factor.

[0026] In an embodiment of the present application, the power consumption score may include at least one of a static power consumption score and a dynamic power consumption score. Wherein, based on the normalized static power consumption factor, determining the static power consumption score of each designed memory may include: based on the normalized static power consumption factor and the static power consumption weight, determining the static power consumption score of each designed memory, wherein the static power consumption weight may be a preset weight or a normalized weight. Accordingly, based on the normalized dynamic power consumption factor, determining the dynamic power consumption score of each designed memory may include: based on the normalized dynamic power consumption factor and the dynamic power consumption weight, determining the dynamic power consumption score of each designed memory, wherein the dynamic power consumption weight may be a preset weight or a normalized weight.

[0027] Step 140, determining an area score of each designed memory based on the area information of each designed memory; wherein the area score is a score obtained by normalizing the area information; In an embodiment of the present application, determining the area score of each designed memory based on the area information of each designed memory in step 140 may include: determining a normalized area factor based on the area information of each designed memory; and determining the area score of each designed memory based on the normalized area factor. The normalized area factor is obtained by normalizing the area information. Determining the performance score of each designed memory based on the normalized area factor may include: determining the area score of each designed memory based on the normalized area factor and the area weight, wherein the area weight may be a preset weight or a normalized weight.

[0028] Step 150, determining a comprehensive score of each designed memory based on the performance score, the power consumption score and the area score; In step 150, the performance score, the power consumption score, and the area score may be added together, and the sum obtained is used as a comprehensive score.

[0029] Step 160 , determining a target memory from a plurality of designed memories based on the comprehensive scores of the designed memories.

[0030] In step 160, the minimum comprehensive score can be selected from the comprehensive scores of the designed memories, and the designed memory corresponding to the minimum comprehensive score is used as the target memory. Of course, in the embodiment of the present application, the target memory can be selected based on the comprehensive score with reference to multiple set dimensions.

[0031] In an embodiment of the present application, based on target configuration information for memory design, a target data file of each designed memory is generated; the target data file includes performance information, power consumption information and area information; based on the performance information of each designed memory, a performance score of each designed memory is determined; wherein the performance score is a score obtained by normalizing the performance information; based on the power consumption information of each designed memory, a power consumption score of each designed memory is determined; wherein the power consumption score is a score obtained by normalizing the power consumption information; based on the area information of each designed memory, an area score of each designed memory is determined; wherein the area score is a score obtained by normalizing the area information; based on the performance score, the power consumption score and the area score, a comprehensive score of each designed memory is determined; based on the comprehensive score of each designed memory, a target memory is determined from multiple designed memories. In this way, by comprehensively considering the performance score, power consumption score and area score, the comprehensive score of each designed memory is obtained, and then the target memory is determined, which can automatically screen out the better memory, help to screen out the memory with more suitable performance (such as timing), area and power consumption in advance, reduce the number of iterations of memory selection, and solve the problem of too many iterations caused by the memory obtained by related technology screening still needing to be replaced in the middle and late stages. In addition, the performance score, power consumption score and area score are all obtained through normalization processing, so that the scores of these three dimensions can be measured uniformly, ensuring the universality and accuracy of the scores, making the final comprehensive score more objective and accurate.

[0032] Figure 2 is a flow chart of a memory screening method provided in an embodiment of the present application. Figure 2 , the memory screening method provided in the embodiment of the present application includes: Step 210, based on the target configuration information for memory design, generate target data files for each designed memory; the target data files include performance information, power consumption information and area information; the performance information includes timing information.

[0033] Step 215, determining a normalized timing factor based on the timing information of each designed memory; The timing information may include a target delay time and a setup time, wherein the target delay time indicates a time interval from clock triggering to data output.

[0034] In step 215, a normalized timing factor is determined based on the timing information of each designed memory, including: determining a target time value of each designed memory to obtain multiple target time values; the target time value is the sum of the target delay time and the setup time; determining a specified time value from the multiple target time values; the specified time value is the maximum time value among the multiple target time values ​​or the minimum time value among the multiple target time values; and determining the ratio of the target time value of each designed memory to the specified time value as the normalized timing factor.

[0035] Step 220, obtaining normalized timing weights; In step 220, the ratio of the preset timing weight to the total weight can be determined as the normalized timing weight; wherein the total weight can be the sum of the preset timing weight, the preset power consumption weight and the preset area weight. In the embodiment of the present application, the total weight can also be a fixed value, such as 1.

[0036] Step 225, determining a performance score of each designed memory based on the normalized timing factor and the normalized timing weight; In the embodiment of the present application, the product of the normalized timing factor and the normalized timing weight may be used as the performance score of the designed memory.

[0037] Step 230, determining a normalized power consumption factor based on the power consumption information of each designed memory; The power consumption information includes a power consumption value. Step 230 may include: obtaining the power consumption value of each designed memory to obtain multiple power consumption values; determining a specified power consumption value from the multiple power consumption values; the specified power consumption value is the maximum power consumption value of the multiple power consumption values ​​or the minimum power consumption value of the multiple power consumption values. The ratio of the power consumption value of each designed memory to the specified power consumption value is determined as a normalized power consumption factor.

[0038] Step 235, obtaining a normalized power consumption weight; In step 235, the ratio of the preset power consumption weight to the total weight can be determined as the normalized power consumption weight; wherein the total weight can be the sum of the preset timing weight, the preset power consumption weight and the preset area weight. In the embodiment of the present application, the total weight can also be a fixed value, such as 1.

[0039] Step 240, determining a power consumption score of each designed memory based on the normalized power consumption factor and the normalized power consumption weight; In the embodiment of the present application, the product of the normalized power consumption factor and the normalized power consumption weight may be used as the power consumption score of the designed memory.

[0040] Step 245, determining a normalized area factor based on the area information of each designed memory; The area information may include an area value for indicating the size of the area. Step 245 may include: obtaining the area value of each designed memory to obtain a plurality of area values; determining a specified area value from the plurality of area values; the specified area value is the maximum area value of the plurality of area values ​​or the minimum area value of the plurality of area values; and determining the ratio of the area value of each designed memory to the specified area value as a normalized area factor.

[0041] Step 250, obtaining a normalized area weight; In step 250, the ratio of the preset area weight to the total weight can be determined as the normalized area weight; wherein the total weight can be the sum of the preset timing weight, the preset power consumption weight and the preset area weight. In the embodiment of the present application, the total weight can also be a fixed value, such as 1.

[0042] Step 255, determining an area score of each designed memory based on the normalized area factor and the area weight; In the embodiment of the present application, the product of the normalized area factor and the normalized area weight may be used as the area score of the designed memory.

[0043] Step 260, determining a comprehensive score of each designed memory based on the performance score, the power consumption score and the area score; In the embodiment of the present application, the performance score, the power consumption score and the area score may be added together, and the obtained sum may be used as a comprehensive score.

[0044] Step 270 , determining a target memory from a plurality of designed memories based on the comprehensive scores of the designed memories.

[0045] In the embodiment of the present application, the smallest comprehensive score may be selected from the obtained comprehensive scores of the designed memories, and the designed memory corresponding to the smallest comprehensive score may be used as the target memory.

[0046] In the embodiment of the present application, by comprehensively considering the performance score, power consumption score and area score, a comprehensive score of each designed memory is obtained, and then the target memory is determined, which can automatically screen out a better memory, and help to screen out in advance a memory with more suitable performance (such as timing), area, and power consumption, thereby reducing the number of iterations of memory selection, and solving the problem of too many iterations caused by the memory obtained by related technical screening still needing to be replaced in the middle and late stages. Moreover, the performance score, power consumption score and area score are all obtained through normalization processing, so that the scores of these three dimensions can be uniformly measured, ensuring the universality and accuracy of the scores, making the final comprehensive score more objective and accurate. In addition, Figure 2 In the illustrated embodiment, the timing weight, power consumption weight, and area weight are all obtained by normalization, which can ensure that the obtained weights have higher accuracy, thereby further ensuring the accuracy of the performance score, power consumption score, and area score.

[0047] Figure 3 is a flow chart of a memory screening method provided in an embodiment of the present application. Figure 3 , the memory screening method provided in the embodiment of the present application includes: Step 310, based on the target configuration information for memory design, generate target data files for each designed memory; the target data files include performance information, power consumption information and area information. The performance information includes timing information; the timing information includes target delay time and setup time, and the target delay time indicates the time interval from clock trigger to data output. The power consumption information includes: static power consumption value and dynamic power consumption value. The area information includes area value.

[0048] Step 320, determining the target time value of each designed memory to obtain a plurality of target time values; the target time value is the sum of the target delay time and the setup time; Step 322, determining a designated time value from the multiple target time values; the designated time value is the maximum time value among the multiple target time values ​​or the minimum time value among the multiple target time values; Step 324, determining the ratio of the target time value of each designed memory to the specified time value as a normalized timing factor; Step 326, determining the ratio of the preset timing weight to the total weight as the normalized timing weight; wherein the total weight is the sum of the preset timing weight, the preset power consumption weight and the preset area weight; Step 328, determining a performance score of each designed memory based on the normalized timing factor and the normalized timing weight; Step 330, obtaining the static power consumption value of each designed memory to obtain a plurality of static power consumption values; Step 332: determine a first specified power consumption value from the multiple static power consumption values; the first specified power consumption value is the maximum power consumption value among the multiple static power consumption values ​​or the minimum power consumption value among the multiple static power consumption values; Step 334, determining the ratio of the static power consumption value of each designed memory to the first specified power consumption value as a normalized static power consumption factor; Step 336, taking the ratio of the preset static power consumption weight to the total weight as the normalized static power consumption weight; Step 338, determining a static power consumption score of each designed memory based on the normalized static power consumption factor and the normalized static power consumption weight; Step 340, obtaining the dynamic power consumption value of each designed memory to obtain a plurality of dynamic power consumption values; Step 342, determining a second specified power consumption value from the multiple dynamic power consumption values; the second specified power consumption value is a maximum power consumption value among the multiple dynamic power consumption values ​​or a minimum power consumption value among the multiple dynamic power consumption values; Step 344, determining the ratio of the dynamic power consumption value of each designed memory to the second specified power consumption value as a normalized dynamic power consumption factor; Step 346, taking the ratio of the preset dynamic power consumption weight to the total weight as the normalized dynamic power consumption weight; Step 348, determining a dynamic power consumption score of each designed memory based on the normalized dynamic power consumption factor and the normalized dynamic power consumption weight; Step 350, obtaining the area value of each designed memory to obtain a plurality of area values; Step 352, determining a designated area value from the multiple area values; the designated area value is the maximum area value among the multiple area values ​​or the minimum area value among the multiple area values; Step 354, determining the ratio of the area value of each designed memory to the specified area value as a normalized area factor; Step 356, taking the ratio of the preset area weight to the total weight as the normalized area weight; Step 358, determining an area score of each designed memory based on the normalized area factor and the area weight; Step 360, determining a comprehensive score of each designed memory based on the performance score, the static power consumption score, the dynamic power consumption score and the area score; The sum of the performance score, the static power consumption score, the dynamic power consumption score and the area score may be calculated, and the sum may be used as a comprehensive score.

[0049] Step 370 , determining a target memory from a plurality of designed memories based on the comprehensive scores of the designed memories.

[0050] Among them, a memory with the minimum comprehensive score can be selected from the comprehensive scores of various designed memories as the target memory.

[0051] In an embodiment of the present application, by comprehensively considering the performance score, power consumption score and area score, a comprehensive score of each designed memory is obtained, and then the target memory is determined, which can automatically screen out a better memory, which helps to screen out memories with more suitable performance (such as timing), area and power consumption in advance, reducing the number of iterations of memory selection, and solving the problem that the memory obtained by the related technology screening still needs to be replaced in the middle and late stages, resulting in too many iterations. Moreover, the performance score, power consumption score and area score are all obtained through normalization processing, so that the scores of these three dimensions can be uniformly measured, ensuring the versatility and accuracy of the scores, making the final comprehensive score more objective and accurate. In addition, in the process of considering the power consumption information, static power consumption and dynamic power consumption are subdivided, which can further refine the different situations of static power consumption and dynamic power consumption, making the consideration of the power consumption dimension more refined and rich, ensuring that the comprehensive score obtained fully considers both static power consumption and dynamic power consumption, and is more accurate.

[0052] Figure 4 is a flow chart of a memory screening method provided in an embodiment of the present application. Figure 4 , the memory screening method provided in the embodiment of the present application includes: Step 410, generating a target data file of each designed memory based on the target configuration information for memory design; the target data file includes performance information, power consumption information and area information; Step 420, determining a performance score of each designed memory based on the performance information of each designed memory; wherein the performance score is a score obtained by normalizing the performance information; Step 430, determining a power consumption score of each designed memory based on the power consumption information of each designed memory; wherein the power consumption score is a score obtained by normalizing the power consumption information; Step 440, determining an area score of each designed memory based on the area information of each designed memory; wherein the area score is a score obtained by normalizing the area information; Step 450, determining a comprehensive score of each designed memory based on the performance score, the power consumption score and the area score; Step 460 , determining a target memory from a plurality of designed memories based on the comprehensive scores of the designed memories; Among them, steps 410 to 460 can refer to the previous discussion.

[0053] Step 470, obtaining memory configuration information corresponding to the target memory; Step 480, generating a memory output file corresponding to the target memory based on the memory configuration information; The memory output file corresponding to the target memory may be a complete memory output file, that is, all required memory output files.

[0054] Step 485, obtaining the memory content to be packaged based on the memory output file; In the embodiment of the present application, the memory output file can be used as the memory content to be packaged, or the target functional circuit and the memory output file can be used together as the memory content to be packaged. Among them, the target functional circuit can be generated by a circuit generation script. Accordingly, this step is based on the memory output file to obtain the memory file to be packaged, which may include: generating a target functional circuit by a circuit generation script, the target functional circuit is used to provide the target function to the target memory; using the target functional circuit and the memory output file together as the memory content to be packaged.

[0055] The target functional circuit is not limited in the embodiment of the present application. For example, the target functional circuit can be an ECC circuit, a power consumption control circuit, or a similar additional functional circuit. The memory design in the embodiment of the present application can integrate an ECC circuit or a power consumption control circuit. The ECC circuit is used for data error detection and correction, and the power consumption control circuit is used to reduce dynamic power consumption. The ECC circuit or the power consumption control circuit can be integrated in the memory generation process by means of a switch. Taking the power consumption control circuit as an example, generating a power consumption control circuit through a circuit generation script may include: obtaining the type of memory, the depth of the memory, the width of the memory, and write-related information, wherein the write-related information includes byte write or bit write information; based on the type of memory, generating a clock control circuit; based on the depth of the memory, generating an address control circuit; based on the width of the memory and write-related information, generating a data control circuit; based on the write-related information, generating a bit control circuit; based on the clock control circuit, the address control circuit, the data control circuit, and the bit control circuit, obtaining a power consumption control circuit.

[0056] Step 490: Use a universal top-level interface to encapsulate the contents of the memory to be encapsulated to obtain a target encapsulated memory, wherein the target encapsulated memory is used for unified calling by different callers.

[0057] In an embodiment of the present application, by comprehensively considering the performance score, power consumption score and area score, a comprehensive score of each designed memory is obtained, and then the target memory is determined, which can automatically screen out a better memory, help to screen out in advance a memory with more suitable performance (such as timing), area, and power consumption, reduce the number of iterations of memory selection, and solve the problem that the memory obtained by the related technology screening still needs to be replaced in the middle and late stages, resulting in too many iterations. Moreover, the performance score, power consumption score and area score are all obtained through normalization processing, so that the scores of these three dimensions can be uniformly measured, ensuring the universality and accuracy of the scores, making the final comprehensive score more objective and accurate. In addition, the content of the memory to be encapsulated is encapsulated using a universal top-level interface to obtain a target encapsulated memory, and the target encapsulated memory is used for unified calling by different callers, which can form a unified usage specification, facilitate developers to use, and reduce misuse during use.

[0058] It should be understood that in various embodiments of the present application, the same or similar steps can be referenced to each other. Figure 1-Figure 4 Different embodiments are shown, Figure 1-Figure 4 The contents of each step in the illustrated embodiment can be referenced to each other. Figure 1 The explanation of steps 110 to 160 in Figure 4 Steps 410 to 460 in .

[0059] Figure 5 is a specific flow chart of a memory screening method provided in an embodiment of the present application. Figure 5 , the memory screening method provided in the embodiment of the present application is further explained in detail below.

[0060] According to the documentation provided by the memory vendor, create a depth and width range support table. For example, the memory range description provided by the vendor is: for the memory with mux=2, the minimum depth is 32, the maximum depth is 1024, and the depth step is 16; the minimum width is 8, the maximum width is 256; the width step is 2 (that is, when mux=2, the depth can be 32, 48, 64, ..., 1024; the width can be 8, 10, 12, ..., 256). Enter the above information to create a data table of all memory ranges that can be generated. It is worth mentioning that the operation of creating a range data table only needs to be performed once, and each subsequent memory generation will read the depth and width range of the memory from this data table.

[0061] The memory requirement table received from the user includes: memory name (Name), memory type (MemType), depth (Depth), width (Width), size (Size), bit / byte (bit / byte) read / write enable (Bit / ByteWrEna), clock frequency, instantiation times (InstNum), vendor (Vendor), built-in self-test function (Built-in Self-Test, BIST) enable (BistEna), PG (Power gating, PG) enable (PGEN), ECC enable, power control (Low Power) circuit enable, frequency weight (Q_Freq), area weight (Q_Area), static power weight (Q_Static), dynamic power weight (Q_Dynamic). The instantiation times indicates the number of times the current memory is instantiated, and the PG signal is used to control whether the memory enters the low power mode. The clock frequency includes the write clock frequency (Wclk) and the read clock frequency (Rclk). The memory type is, for example, 1P, 2P, DP, etc., where 1P is a single-port memory, 2P is a synchronous or asynchronous pseudo-dual-port memory, and DP is a true dual-port memory.

[0062] An example memory requirement table may be as follows:

[0063] The embodiment of the present application can read the requirement items in the user requirement table line by line, query the depth and width range support table, and determine whether the depth and width combination currently input by the user meets the configuration requirements of the memory design software; if the current depth and width combination cannot be generated, the memory is split, and the width split is given priority. If the width split cannot meet the requirements, the depth split is performed again. The split adopts a binary method. For example, the user requires a 1P memory depth and width of 2048x1024, and the maximum width supported by the memory design software is 256. At this time, the embodiment of the present application can update the current user requirements to a depth and width of 2048x256, respectively, and the number of decompositions is 4, and records are made. Four physical memories need to be called in subsequent packaging. If the configuration requirements of the memory design software are still not met after the split, this information will be recorded and fed back to the user so that the user can reconsider and update the requirements.

[0064] After obtaining the user's needs, the embodiment of the present application can decompose the memory requirement table, and after the decomposition, it will generate configuration files that meet the needs of different memory design software suppliers. In general, there is more than one memory that meets the user's needs, so each memory requirement of the user will generate several corresponding configuration files. In order to reduce the time of generating the memory, these configuration files are set to generate only the corresponding target data files (the memory design software has many output files. In this case, not all output files are generated, only data files containing PPA (Performance / Power / Area, performance / power consumption / area) information, i.e., target data files). The memory design software reads the configuration files in turn to generate the memory, and obtains the key PPA information of the memory from the output data files, including T setup (SetupTiming, establishment time), T hold (Hold Timing, hold time), T cyc (clock cycle), T cd (delay time from clock to data output), static power consumption (Static Power), dynamic power consumption (Dynamic Power), area and length and width information. The embodiment of the present application can be based on T cyc Filter out the memories that do not meet the user's frequency requirements, and filter out memories with too large aspect ratios based on the length-to-width information, and save the remaining memories that meet the timing requirements. For a certain user requirement, if all memories do not meet the timing requirements, this information will be recorded and fed back to the user.

[0065] The comprehensive score of each memory is calculated based on the input weight coefficients of each parameter and the saved PPA information. The calculation method is as follows: First, for all memories, the T corresponding to each memory is cd With T setup Add together the delay time of the timing path and obtain T cd With T setup The minimum value of the sum of cd With T setup Divide the sum of and the minimum value of to get the normalized timing factor, and then use the same method to get the area factor, static power factor, and dynamic power factor. Sum the frequency weight, area weight, static power weight, and dynamic power weight entered in the demand table to get the total weight, and divide each weight coefficient by the total weight to get the proportion of each weight. Finally, multiply each normalized factor by the corresponding weight proportion and add them together to get the final score (i.e., comprehensive score) of each memory, and select the memory with the smallest score as the better memory.

[0066] The memory generation process mentioned above is executed in the order of filling in the memory requirement table. For a row in the table, several configuration files and a memory data information table will be generated, and then the next row of requirements will be processed in turn until all requirements are traversed. If the requirements of a row do not meet the requirements of the memory depth, width or clock frequency, it will be recorded. Only the requirements that meet the requirements will be used for subsequent comprehensive score calculations. For example, the area of ​​a memory is A, T setup =T0,T cd =T1, static power consumption is L, dynamic power consumption is D, frequency weight is W0, area weight is W1, static power consumption weight is W2, dynamic power consumption weight is W3, all of which are positive integers between 0 and 10. Among them, T1 is the target delay time, which is used to indicate the time interval from clock trigger to data output. (T0+T1) min is the minimum value of the target time value of each designed memory (the sum of the target delay time and the setup time), A min is the minimum area of ​​each designed memory, L min is the minimum static power consumption of each designed memory, D min is the minimum value of dynamic power consumption of each designed memory. The specific calculation formula is as follows: Normalized frequency weight u0=W0 / (W0+W1+W2+W3); Normalized area weight u1=W1 / (W0+W1+W2+W3); Normalized static power consumption weight u2=W2 / (W0+W1+W2+W3); Normalized dynamic power consumption weight u3=W3 / (W0+W1+W2+W3); Normalized timing factor P_timing=(T0+T1) / (T0+T1) min Normalized area factor P_area=A / A min Normalized static power consumption factor P_static=L / L min Normalized dynamic power factor P_dynamic = D / D min The comprehensive score of each designed memory = P_timing* u0+ P_area*u1+ P_static*u2+ P_dynamic*u3. It should be understood that in the embodiment of the present application, the normalized frequency weight can be the normalized timing weight mentioned above.

[0067] After obtaining the comprehensive scores of the memories of various designs, the memory with the smallest comprehensive score can be taken as the target memory, that is, the better memory.

[0068] After acquiring the target memory, the embodiment of the present application can generate a new configuration file of the memory design software, in which all output files required for generating the project are specified, and all required memory output files are generated according to the new configuration file.

[0069] After the designed physical memory is generated, it is packaged. If the memory requirement table indicates that an ECC circuit or a power consumption control circuit is to be generated, the type, depth, width, multiplexer, byte write or bit write information of the target memory can be read first and input into the corresponding circuit generation script, and the script can generate a logic circuit based on this information. Then, the embodiment of the present application can automatically generate a unified memory interface and clock automatic switching circuit, and at the same time, according to the personalized content specified by the user, the physical memory, the generated ECC, the power consumption control circuit, etc. are packaged into the top layer of the memory, which is convenient for R&D personnel to use.

[0070] The following uses the power consumption control circuit as an example to illustrate the process of generating a power consumption control circuit through a script. The purpose of the power consumption control circuit is to reduce the flipping of clock signals, data signals, address signals, and bit write enable signals when the memory is not read or written, thereby reducing dynamic power consumption. Therefore, the parameters read by the script may include the type, depth, width, byte write or bit write information of the memory. Specifically, the script first reads the parameters of the memory and generates a port list, where single-port and dual-port memories have different numbers of ports, and the port bit width depends on the width of the memory data. Then, based on the type of memory, a clock control circuit is generated. For a single-port memory, there is only one clock, so only one clock control circuit needs to be generated. For an asynchronous dual-port memory, a clock control circuit is required for each read clock and write clock. Finally, based on the width of the memory and write-related information (i.e., byte write information or bit write information), a data control circuit is generated; based on the depth of the memory, an address control circuit is generated; and based on the write-related information, a bit control circuit is generated. This part of the logic circuit needs to call a corresponding number of AND logic gates according to the depth and width of the memory to control the flipping of data, address, and bit write enable. When the memory enable signal is invalid, the output of the AND logic gate is kept at 0. For example, in the generation process of address control logic, for a memory with a depth of 64, the address width is calculated to be 6, and then each address bit and the memory enable signal are connected to the input port of the AND logic gate. In addition, different types of memory control circuits are also different. Similarly, if the ECC circuit is generated by a script, the type, depth and width of the memory can be obtained first, and then the ECC circuit can be generated based on the type, depth and width of the memory.

[0071] After the above circuit packaging is completed, the user can directly call the corresponding memory packaging top layer. In addition, in order to facilitate the use of FPGA (Field Programmable Gate Array, field programmable gate array), the embodiment of the present application can generate a corresponding FPGA model.

[0072] Finally, all output files, packaged memory top layers, and FPGA models are classified and stored in a fixed directory. These contents in the directory are provided to the front-end, verification department, mid-end, and back-end as needed, which is also convenient for project management.

[0073] As can be seen from the above, the screening method of the memory provided by the embodiment of the present application not only considers the timing and area in the process of selecting the designed memory, but also takes power consumption as an important factor in selecting the memory. Due to the different emphases of different projects and modules, a better target memory can be selected based on the comprehensive score for different projects and modules. Moreover, a personalized custom circuit is also added to the process of generating the memory. The personalized custom circuit can be obtained by filling in the requirement form. The personalized custom circuit is, for example, an ECC circuit and a low-power control circuit. If there are other application requirements, switches for other functional circuits can also be added, which improves development efficiency and reduces the probability of error. In addition, between different processes and projects, the same top-level interface is encapsulated to form a unified usage specification, which is convenient for developers to use and reduces misuse during use.

[0074] like Figure 6As shown, the embodiment of the present application further provides an electronic device 600. The electronic device 600 includes: a processor 610 and a memory 620, the memory 620 stores programs or instructions, and when the programs or instructions are executed by the processor 610, the steps of any of the methods described above (such as the memory screening method) are implemented. For example, when the program is executed by the processor 610, the following process is implemented: based on the target configuration information for memory design, a target data file of each designed memory is generated; the target data file includes performance information, power consumption information and area information; based on the performance information of each designed memory, a performance score of each designed memory is determined; wherein the performance score is a score obtained by normalizing the performance information; based on the power consumption information of each designed memory, a power consumption score of each designed memory is determined; wherein the power consumption score is a score obtained by normalizing the power consumption information; based on the area information of each designed memory, an area score of each designed memory is determined; wherein the area score is a score obtained by normalizing the area information; based on the performance score, the power consumption score and the area score, a comprehensive score of each designed memory is determined; based on the comprehensive score of each designed memory, a target memory is determined from multiple designed memories. In this way, by comprehensively considering the performance score, power consumption score and area score, the comprehensive score of each designed memory is obtained, and then the target memory is determined, which can automatically screen out the better memory, help to screen out the memory with more suitable performance (such as timing), area and power consumption in advance, reduce the number of iterations of memory selection, and solve the problem of too many iterations caused by the memory obtained by related technology screening still needing to be replaced in the middle and late stages. In addition, the performance score, power consumption score and area score are all obtained through normalization processing, so that the scores of these three dimensions can be measured uniformly, ensuring the universality and accuracy of the scores, making the final comprehensive score more objective and accurate.

[0075] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of each embodiment of the method for determining application security are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0076] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0077] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0078] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0079] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0080] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0081] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for screening a memory, characterized in that: include: generating target data files for each designed memory based on the target configuration information for the memory design; The target data file includes performance information, power consumption information and area information; Determine a performance score of each designed memory based on the performance information of each designed memory; wherein the performance score is a score obtained by normalizing the performance information; Based on the power consumption information of each designed memory, determine the power consumption score of each designed memory; wherein the power consumption score is a score obtained by normalizing the power consumption information; Based on the area information of each designed memory, determine the area score of each designed memory; wherein the area score is a score obtained by normalizing the area information; Determine a comprehensive score of each designed memory based on the performance score, the power consumption score and the area score; A target memory is determined from the plurality of designed memories based on comprehensive scores of the designed memories.

2. The method according to claim 1, characterized in that: The performance information includes timing information; and determining the performance score of each designed memory based on the performance information of each designed memory includes: Determine a normalized timing factor based on the timing information of each designed memory; Get the normalized timing weight; Based on the normalized timing factor and the normalized timing weight, a performance score of each designed memory is determined.

3. The method according to claim 2, characterized in that The timing information includes a target delay time and a setup time, wherein the target delay time indicates a time interval from a clock trigger to a data output; The step of determining a normalized timing factor based on the timing information of each designed memory includes: Determine the target time value of each designed memory to obtain multiple target time values; the target time value is the sum of the target delay time and the setup time; determine a specified time value from the multiple target time values; the specified time value is the maximum time value among the multiple target time values ​​or the minimum time value among the multiple target time values; determine the ratio of the target time value of each designed memory to the specified time value as a normalized timing factor; The obtaining of the normalized timing weight includes: The ratio of the preset timing weight to the total weight is determined as the normalized timing weight; wherein the total weight is the sum of the preset timing weight, the preset power consumption weight and the preset area weight.

4. The method according to claim 1, characterized in that The step of determining the power consumption score of each designed memory based on the power consumption information of each designed memory includes: Determine a normalized power consumption factor based on power consumption information of each designed memory; Get the normalized power consumption weight; Based on the normalized power consumption factor and the normalized power consumption weight, a power consumption score of each designed memory is determined.

5. The method according to claim 4, characterized in that The power consumption information includes: a static power consumption value and a dynamic power consumption value; the normalized power consumption factor includes a normalized static power consumption factor and a normalized dynamic power consumption factor; The determining of a normalized power consumption factor based on power consumption information of each designed memory includes: Obtain the static power consumption value of each designed memory to obtain multiple static power consumption values; obtain the dynamic power consumption value of each designed memory to obtain multiple dynamic power consumption values; determine a first specified power consumption value from the multiple static power consumption values; the first specified power consumption value is the maximum power consumption value among the multiple static power consumption values ​​or the minimum power consumption value among the multiple static power consumption values; determine a second specified power consumption value from the multiple dynamic power consumption values; the second specified power consumption value is the maximum power consumption value among the multiple dynamic power consumption values ​​or the minimum power consumption value among the multiple dynamic power consumption values; determine the ratio of the static power consumption value of each designed memory to the first specified power consumption value as a normalized static power consumption factor; determine the ratio of the dynamic power consumption value of each designed memory to the second specified power consumption value as a normalized dynamic power consumption factor; The normalized power consumption weight includes a normalized static power consumption weight and a normalized dynamic power consumption weight; and obtaining the normalized power consumption weight includes: The ratio of the preset static power consumption weight to the total number of weights is determined as the normalized static power consumption weight; the ratio of the preset dynamic power consumption weight to the total number of weights is determined as the normalized dynamic power consumption weight; wherein the total number of weights is the sum of the preset timing weight, the preset static power consumption weight, the preset dynamic power consumption weight and the preset area weight.

6. The method according to claim 1, characterized in that The step of determining the area score of each designed memory based on the area information of each designed memory includes: Determine a normalized area factor based on area information of each designed memory; Get the normalized area weight; An area score of each designed memory is determined based on the normalized area factor and the area weight.

7. The method according to claim 6, characterized in that The area information includes an area value; and determining a normalized area factor based on the area information of each designed memory includes: Acquire the area value of each designed memory to obtain a plurality of area values; determine a specified area value from the plurality of area values; the specified area value is the maximum area value among the plurality of area values ​​or the minimum area value among the plurality of area values; determine the ratio of the area value of each designed memory to the specified area value as a normalized area factor; The obtaining of the normalized area weight comprises: The ratio of the preset area weight to the total weight is determined as the normalized area weight; wherein the total weight is the sum of the preset timing weight, the preset power consumption weight and the preset area weight.

8. The method according to any one of claims 1 to 7, characterized in that: After determining the target memory from a plurality of designed memories, the method further includes: Obtaining memory configuration information corresponding to the target memory; Based on the memory configuration information, generate a memory output file corresponding to the target memory; Based on the memory output file, obtaining the memory content to be packaged; The content of the memory to be encapsulated is encapsulated using a universal top-level interface to obtain a target encapsulated memory, and the target encapsulated memory is used for unified calling by different callers.

9. The method according to claim 8, characterized in that The obtaining the memory content to be packaged based on the memory output file includes: Generate a target function circuit by using a circuit generation script, wherein the target function circuit is used to provide a target function to the target memory; The target functional circuit and the memory output file are used together as the memory content to be packaged.

10. The method according to any one of claims 1 to 7, characterized in that: Before generating target data files of each designed memory based on the target configuration information for memory design, the method further includes: Obtaining a memory requirement table, wherein the memory requirement table includes requirement items, and the requirement items include a memory depth and a memory width; Determining whether the memory depth and memory width in the requirement item meet the configuration requirements based on a pre-established depth and width range support table; In the case where the memory depth and the memory width in the requirement item do not meet the configuration requirements, splitting the target item in the requirement item to obtain the memory depth and the memory width that meet the configuration requirements; the target item includes at least one of the memory depth and the memory width; In a case where the memory depth and the memory width in the requirement item meet the configuration requirement, target configuration information for memory design is acquired based on the memory depth and the memory width in the requirement item.

11. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction running on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 10 are implemented.

12. A computer-readable storage medium, characterized in that: The medium stores a program or an instruction, and when the program or the instruction is executed, the steps of the method according to any one of claims 1 to 10 are implemented.

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