Logic mapping table updating method of storage device, controller, equipment and medium

Abstract

The invention discloses a logic mapping table updating method of a storage device, a controller, equipment and a medium, and relates to the technical field of logic mapping table management. The method comprises the following steps: storing first logic mapping information of written logic data one by one; when the first storage quantity of the accumulatively stored first logic mapping information is equal to a storage quantity threshold value, writing the accumulatively stored first logic mapping information into the SLC block to obtain second logic mapping information; when the second storage quantity of the accumulated second logic mapping information is equal to a preset threshold value or a mapping table forced updating instruction is responded, the currently accumulated second logic mapping information is read, and after the second logic mapping information is sorted according to the logic address, the second logic mapping information is stored; updating the corresponding first logic mapping table according to the sorted second logic mapping information to obtain a second logic mapping table; the switching frequency of a logic mapping table in a random write scene can be reduced, the random write performance is improved, and the read-write loss of a memory device is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of logical mapping table management, and in particular to a method for updating a logical mapping table of a storage device, a controller, a device, and a medium. Background Art

[0002] NAND storage devices have a mapping table to record the mapping relationship between logical addresses and physical addresses, where the logical to physical mapping table is called the L2P table (Logical to Physical mapping table). When reading data, the physical location of the data stored in the flash memory is found through the logical mapping table, so that the correct data can be read. The size of the logical mapping table is relatively large, and it increases linearly with the capacity of the storage device. For example, the mainstream FTL (flash memory management algorithm) uses 4K mapping. If each 4K data uses 4Bytes of space to maintain mapping information, a 32GB storage device has a 32MB logical mapping table, and a 128GB storage device has a 128MB logical mapping table. However, general storage devices do not have enough memory space to completely cache these logical mapping tables in the memory, and can only cache part of the logical mapping table. During the reading and writing process, according to the address of the logical data accessed by the host, the hit logical mapping table is read into the memory, and before switching the logical mapping table, the partially updated logical mapping table already in the memory needs to be written to the flash memory to release the free memory space.

[0003] Storage products such as eMMC, UFS, SD card, and USB flash drive have very small internal RAM (Random Access Memory) space. Generally speaking, only part of the logical mapping table is cached in the memory. In the random write scenario, the logical mapping table update method used in the related art is: immediately update the mapping information corresponding to the data to the logical mapping table L2P after writing the data. This solution is limited by the memory space, and the switching frequency of the logical mapping table is very high during random writing; it leads to more reading and writing of the logical mapping table, and affects the read and write performance of the logical data, reduces the random write performance, and affects the life of the storage device. Therefore, it is urgent to optimize the update method of the logical mapping table. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for updating a logical mapping table of a storage device, a controller, a device, and a medium, which can update the logical mapping table through sorted logical mapping information based on an optimized logical mapping table update strategy, reduce the switching frequency of the logical mapping table in a random write scenario, improve random write performance, and reduce the read and write loss of the storage device.

[0005] In a first aspect, an embodiment of the present application provides a method for updating a logical mapping table of a storage device, which is applied to a controller of the storage device, wherein the storage device further comprises: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit comprises: a data block, wherein the data block comprises a plurality of SLC blocks;

[0006] The method comprises:

[0007] storing first logical mapping information of the logical data written into the data block one by one into the memory unit; wherein the first logical mapping information includes a logical address of the logical data and a corresponding physical address;

[0008] When a first storage quantity of the first logical mapping information accumulated and stored in the memory unit is equal to a storage quantity threshold, writing the first storage quantity of the first logical mapping information accumulated and stored in the memory unit into an SLC block to obtain second logical mapping information;

[0009] When the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a mapping table forced update instruction, the second logical mapping information currently accumulated is read from the SLC block and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain sorted second logical mapping information;

[0010] Perform table update processing according to the sorted second logical mapping information, update the corresponding first logical mapping table, and obtain a second logical mapping table; wherein the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain a second logical mapping table.

[0011] In a second aspect, an embodiment of the present application provides a controller comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for updating a logical mapping table of a storage device as described in any one of the embodiments of the first aspect.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising a controller as described in the embodiment of the second aspect.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute a method for updating a logical mapping table of a storage device as described in any one of the embodiments of the first aspect.

[0014] The embodiments of the present application include:

[0015] The storage device comprises: a memory unit and a flash memory unit; wherein the flash memory unit comprises: a data block, and the data block comprises a plurality of SLC blocks; when it is necessary to update the logical mapping table of the storage device, firstly, the first logical mapping information of the logical data written into the data block is stored one by one in the memory unit; wherein the first logical mapping information comprises the logical address of the logical data and the corresponding physical address; then, when the first storage quantity of the first logical mapping information accumulated in the memory unit is equal to the storage quantity threshold, the first logical mapping information of the accumulated first storage quantity is written into the SLC block to obtain the second logical mapping information; then, when the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to the preset threshold, or in response to the forced update instruction of the mapping table, the SLC block is updated from the SLC block; The currently accumulated second logical mapping information is read from the block and cached into the temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information; thereby, it is helpful to determine multiple adjacent second logical mapping information that hit the same first logical mapping table, and further, it is helpful to reduce the switching frequency of the logical mapping table in the subsequent table update processing; finally, the table update processing is performed according to the sorted second logical mapping information, and the corresponding first logical mapping table is updated to obtain the second logical mapping table; wherein, the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain the second logical mapping table; implement an optimized logical mapping table update strategy; and after reading the first logical mapping table once, multiple adjacent second logical mapping information that hit the same first logical mapping table can be written into the first logical mapping table, thereby reducing the switching frequency of the logical mapping table in the scenario of random writing of logical data, improving random write performance, reducing the read and write loss of the storage device, and reducing the loss of the life of the storage device. That is to say, the embodiment of the present application can update the logical mapping table through sorted logical mapping information based on the optimized logical mapping table update strategy, reduce the switching frequency of the logical mapping table in the random write scenario, improve the random write performance, and reduce the read and write loss of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a system architecture of a storage device provided by an embodiment of the present application;

[0017] Figure 2 It is a flowchart of a method for updating a logical mapping table of a storage device provided by an embodiment of the present application;

[0018] Figure 3 It is a schematic diagram of the overall process of storing and processing accumulated logical mapping information provided by an embodiment of the present application;

[0019] Figure 4 It is a schematic diagram of the overall process of reading, processing and updating the accumulated second logical mapping information provided by an embodiment of the present application;

[0020] Figure 5 It is a schematic diagram of the overall process of reading and writing a logical mapping table provided by an embodiment of the present application;

[0021] Figure 6 It is a schematic diagram of the hardware structure of a controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0023] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0024] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0026] First, some terms used in this application are explained:

[0027] OOB (out of band) area: There is an OOB area after each page in the NAND flash, which is used to store hardware ECC checksums, bad block marks, and file system organization information. It is mainly used for hardware error correction and bad block processing. Generally, a NAND with a page size of 512 bytes allocates 16 bytes of OOB per page; if it is a 2k page, each page allocates 64 bytes of OOB.

[0028] SLC BLOCK refers to the storage block of single-level cell flash memory. SLC is a NAND flash memory technology, and each cell can only store one bit of data.

[0029] The present application discloses a method for updating a logical mapping table of a storage device, a controller, an electronic device, and a computer-readable storage medium, and relates to the field of logical mapping table management technology. The method includes: storing the first logical mapping information of the written logical data one by one; when the first storage quantity of the accumulated first logical mapping information is equal to the storage quantity threshold, writing the accumulated first logical mapping information into the SLC block to obtain the second logical mapping information; when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold, or in response to the mapping table forced update instruction, reading the currently accumulated second logical mapping information and caching it to the temporarily applied memory unit, sorting the second logical mapping information according to the logical address, and updating the corresponding first logical mapping table according to the sorted second logical mapping information to obtain the second logical mapping table; it can reduce the switching frequency of the logical mapping table in the random write scenario, improve the random write performance, and reduce the read and write loss of the storage device.

[0030] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0031] like Figure 1 As shown, the storage device includes: a controller, a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit includes: a data block, the data block includes a plurality of SLC blocks, wherein each data block includes a plurality of data pages, and each of the data pages also includes an OOB area.

[0032] Data block refers to a block that stores data. Data blocks include SLC blocks and TLC blocks, which are blocks in nand flash. SLC BLOCK is a block that stores data in SLC mode.

[0033] The flash memory unit is used to store the logical mapping table, the logical data, and the second logical mapping information; the memory unit is used to store the accumulated first logical mapping information; the temporarily applied memory unit is used to cache the logical mapping table and the second logical mapping information to be updated. The controller is used to execute the logical mapping table update method of the storage device provided in the embodiment of the present application.

[0034] Specifically, the memory unit refers to RAM (Random Access Memory). It can be understood that the memory unit stores the accumulated logic mapping information, the logic mapping table, data and other global variables, and the different types of data (accumulated first logic mapping information, the logic mapping table to be updated and the second logic mapping information) are just placed in different positions of the memory unit.

[0035] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0036] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0037] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0038] Based on the above system structure, various embodiments of the method for updating the logical mapping table of the storage device of the present application are proposed below.

[0039] First, as Figure 2 As shown, the logic mapping table updating method of the storage device can be applied to Figure 1 In the controller of the storage device shown, the storage device further includes: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit includes: a data block, and the data block includes a plurality of SLC blocks. The logical mapping table updating method of the storage device may include but is not limited to steps S110 to S140.

[0040] Step S110: storing first logical mapping information of the logical data written into the data block into the memory unit one by one; wherein the first logical mapping information includes the logical address of the logical data and the corresponding physical address.

[0041] Step S120: When the first storage quantity of the first logical mapping information accumulated in the memory unit is equal to the storage quantity threshold, the first storage quantity of the first logical mapping information accumulated is written into the SLC block to obtain the second logical mapping information.

[0042] Step S130: When the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a forced update instruction of the mapping table, the currently accumulated second logical mapping information is read from the SLC block and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information.

[0043] Step S140: Perform table update processing according to the sorted second logical mapping information, update the corresponding first logical mapping table, and obtain a second logical mapping table; wherein the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain a second logical mapping table.

[0044] It is understandable that in step S110, due to limited memory space, only a small fixed memory unit can be applied for storing the first logical mapping information corresponding to the written logical data. The limited storage capacity of the memory unit defines the storage quantity threshold of the first logical mapping information. It is understandable that the storage quantity threshold is determined by the storage capacity of the memory unit, and the embodiment of the present application does not impose specific restrictions on the value of the storage quantity threshold.

[0045] According to some embodiments of the present application, in step S120, before writing the first logical mapping information of the accumulated first storage quantity into the SLC block, the method also includes: when the first storage quantity is equal to the storage quantity threshold, recording the address range of the data block where the logical data corresponding to the accumulated first logical mapping information is located; and recording the physical storage address of the accumulated first logical mapping information.

[0046] The embodiment of the present application records the address range of the data block where the logical data corresponding to the first logical mapping information is located, so as to facilitate the reconstruction of the logical mapping information when the logical mapping information is erroneous; and records the physical storage address of the first logical mapping information, so as to facilitate the subsequent orderly reading of the second logical mapping information stored in the SLC block.

[0047] According to some embodiments of the present application, the first logical mapping information of the accumulated first storage quantity is written into the SLCblock, including: writing the first logical mapping information into the SLC block, and when confirming that the first logical mapping information is successfully written into the SLCblock, obtaining the second logical mapping information, and clearing the first logical mapping information accumulated in the memory unit; and continuing to write the first logical mapping information of the logical data into the memory unit until the second logical mapping information is equal to a preset threshold.

[0048] It is understandable that since the memory unit is fixed and can only store a limited amount of first logical mapping information, whenever the accumulated first logical mapping information reaches the storage quantity threshold, it is necessary to write the first logical mapping information cached in the memory unit into the SLC block to implement phased storage of the first logical mapping information, rather than storing the logical mapping information once each time logical data is written, thereby reducing the frequency of reading and writing the first logical mapping information, which is beneficial to reducing read and write losses.

[0049] The embodiment of the present application implements the processing flow of storing the accumulated logical mapping information through steps S110 to S120. Figure 3 , describing the overall process of processing the storage accumulated logical mapping information provided by the embodiment of the present application.

[0050] Step S301: write logical data into a data block.

[0051] Step S302: storing first logic mapping information corresponding to the written logic data into a memory unit.

[0052] Step S303: determine whether the first storage quantity of the first logical mapping information is equal to the storage quantity threshold; if so, jump to the steps after step S304; if not, repeat steps S301 to S302.

[0053] Step S304: Record the address range of the data block where the logical data corresponding to the accumulated first logical mapping information is located and the physical storage address of the accumulated first logical mapping information.

[0054] Step S305: Write the accumulated first logical mapping information into the SLC block to obtain second logical mapping information.

[0055] Step S306: clearing the first logic mapping information accumulated in the memory unit.

[0056] Step S307: determine whether the accumulated second logic mapping information is equal to a preset threshold; if so, end; if not, jump to execute step S301 and subsequent steps.

[0057] It can be understood that two conditions for triggering the update of the logical mapping table are set in step S130. The first condition is: setting a preset threshold value, when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold value, the subsequent logical mapping information reading and sorting processing and the logical mapping table update processing of step S140 are triggered. The second condition is: in some scenarios, when it is necessary to forcibly update the accumulated second logical mapping information to the logical mapping table, in response to the mapping table forced update instruction sent by the administrator, the subsequent logical mapping information reading and sorting processing and the logical mapping table update processing of step S140 are triggered.

[0058] It is understandable that the preset threshold can be configured according to actual needs. Therefore, the embodiment of the present application does not impose any specific limitation on the value of the preset threshold.

[0059] It is understandable that under the second trigger condition, the amount of second logical mapping information updated to the logical mapping table is less than or equal to the preset threshold. However, the present application does not impose any specific restrictions on the scenario where the accumulated second logical mapping information needs to be forcibly updated to the logical mapping table.

[0060] Steps S110 to S140, when it is necessary to update the logical mapping table of the storage device, first, the first logical mapping information of the logical data written into the data block is stored one by one in the memory unit; wherein the first logical mapping information includes the logical address of the logical data and the corresponding physical address; then, when the first storage quantity of the first logical mapping information accumulated in the memory unit is equal to the storage quantity threshold, the first logical mapping information of the accumulated first storage quantity is written into the SLC block to obtain the second logical mapping information; then, when the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to the preset threshold, or in response to the mapping table forced update instruction, the SLC block is updated from the SLC block to the SLC block to obtain the second logical mapping information. The currently accumulated second logical mapping information is read from the block and cached into the temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information; thereby, it is helpful to determine multiple adjacent second logical mapping information that hit the same first logical mapping table, and further, it is helpful to reduce the switching frequency of the logical mapping table in the subsequent table update processing; finally, the table update processing is performed according to the sorted second logical mapping information, and the corresponding first logical mapping table is updated to obtain the second logical mapping table; wherein, the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain the second logical mapping table; implement an optimized logical mapping table update strategy; and after reading the first logical mapping table once, multiple adjacent second logical mapping information that hit the same first logical mapping table can be written into the first logical mapping table, thereby reducing the switching frequency of the logical mapping table in the scenario of random writing of logical data, improving random write performance, reducing the read and write loss of the storage device, and reducing the loss of the life of the storage device. That is to say, the embodiment of the present application can update the logical mapping table through sorted logical mapping information based on the optimized logical mapping table update strategy, reduce the switching frequency of the logical mapping table in the random write scenario, improve the random write performance, and reduce the read and write loss of the storage device.

[0061] According to some embodiments of the present application, step S130 is further described, wherein the currently accumulated second logical mapping information is read from the SLC block and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information, including but not limited to steps S131 to S133.

[0062] Step S131: Read the second logical mapping information stored in the SLC blocks one by one according to the writing order of the physical storage addresses.

[0063] Step S132: When it is determined that the read second logic mapping information is correct and the number of temporarily applied memory units is sufficient, the read second logic mapping information is stored in the temporarily applied memory units in the order of writing.

[0064] Step S133: in the temporarily applied memory unit, the second logic mapping information is sorted according to the order of the logical address from large to small, or the second logic mapping information is sorted according to the order of the logical address from small to large, to obtain the sorted second logic mapping information.

[0065] It can be understood that through step S131, the second logical mapping information can be read in an orderly manner to avoid errors and omissions, so as to ensure the integrity of data reading.

[0066] It is understandable that the read second logical mapping information may be erroneous. Updating the erroneous second logical mapping information to the logical mapping table is not conducive to the subsequent correct reading of the logical data. Through step S132, the correctness of the second logical mapping information is ensured and then the second logical mapping information is stored in the temporarily applied memory unit, laying the foundation for subsequent updates to obtain the correct logical mapping table.

[0067] It should be noted that the amount of the accumulated second logic mapping information read needs to be determined based on the number of temporarily applied memory units that can be used currently. When the number of available temporarily applied memory units is sufficient, all the accumulated second logic mapping information is read out and placed in the temporarily applied memory units in order. When the number of available temporarily applied memory units is insufficient, part of the second logic mapping information is read out and placed in the temporarily applied memory units in order.

[0068] To further explain step S133, when all or part of the accumulated logical mapping information has been read into the temporarily applied memory unit, in order to improve the random write performance, reduce the frequent switching of the logical mapping table, and reduce the loss of the flash memory life caused by writing a large number of logical mapping tables into the flash memory, the logical mapping information cached in the data buffer can be sorted in the order of logical addresses from small to large or from large to small. After the sorting adjustment, in the subsequent process of updating the second logical mapping information to the logical mapping table, the adjacent second logical mapping information hits the same logical mapping table, reads this logical mapping table once, and updates the adjacent second logical mapping information that hits the same logical mapping table one by one to the logical mapping table, thereby reducing the number of switching times of the logical mapping table. That is to say, step S133 is conducive to determining multiple adjacent second logical mapping information that hit the same first logical mapping table by sorting the second logical mapping information.

[0069] Through step S131 to step S133, it is helpful to determine multiple adjacent second logical mapping information that hit the same first logical mapping table, thereby helping to reduce the switching frequency of the logical mapping table in the subsequent table update processing; and improve the efficiency of updating the logical mapping table.

[0070] According to some embodiments of the present application, each data block includes multiple data pages, and each data page also includes an OOB area; step S131: after reading the second logical mapping information stored in the SLC block one by one, the method also includes but is not limited to steps S134 to S135.

[0071] Step S134: when it is determined that the read second logical mapping information is erroneous, all data pages within the address range are read according to the address range of the data block where the logical data corresponding to the recorded first logical mapping information is located.

[0072] Step S135: acquiring the first logic mapping information corresponding to each written logic data and the writing sequence of each logic data from the OOB area of ​​the read data page, and reconstructing the erroneous second logic mapping information.

[0073] Through steps S134 to S135, when the read second logical mapping information is erroneous, the erroneous second logical mapping information is quickly rebuilt based on the address range of the data block where the logical data corresponding to the previously recorded first logical mapping information is located, so as to facilitate the subsequent correct and rapid update of the logical mapping table.

[0074] The embodiment of the present application implements a partial processing flow of reading the accumulated second logical mapping information through steps S131 to S135. Figure 4 , further illustrating the overall process of processing the read update accumulated second logical mapping information provided by the embodiment of the present application.

[0075] Step S401: when the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a mapping table forced update instruction.

[0076] Step S402: Read the second logic mapping information stored in the SLC block one by one according to the recorded writing order of the physical storage addresses of the corresponding first mapping logics.

[0077] Step S403: determine whether the read second logic mapping information is wrong; if so, jump to step S404 and subsequent steps; if not, jump to step S405 and subsequent steps.

[0078] Step S404: read all data pages within the address range according to the address range of the data block where the logical data corresponding to the recorded first mapping logic is located, obtain the first logical mapping information corresponding to each written logical data from the OOB area of ​​the read data page, and reconstruct the erroneous second logical mapping information.

[0079] Step S405: Determine whether the number of temporarily applied memory units is sufficient; if so, jump to step S409 to step S410; if not, jump to step S406 to step S408.

[0080] Step S406: Cache the read portion of the accumulated second logical mapping information into the temporarily applied memory unit.

[0081] Step S407: updating the second logic mapping information of part of the temporarily applied memory unit to the logic mapping table.

[0082] Step S408: Clear the temporarily applied memory unit and jump to re-execute step S401 and subsequent steps.

[0083] Step S409: determine whether all accumulated second logic mapping information has been stored in the temporarily applied memory unit. If so, execute step S410; if not, re-execute step S401 and subsequent steps.

[0084] Step S410: updating all the accumulated second logic mapping information in the temporarily applied memory unit to the logic mapping table, and then ending.

[0085] According to some embodiments of the present application, step S140 is further described. Step S140: perform table update processing according to the sorted second logical mapping information, update the corresponding first logical mapping table, and obtain the second logical mapping table, including but not limited to steps S141 to S144.

[0086] Step S141: Acquire mapping numbers of all first logical mapping tables corresponding to the sorted second logical mapping information.

[0087] Step S142: In response to the read cache command, asynchronously read the first logic mapping table indicated by the mapping number from the flash memory unit, and cache it in the temporarily applied memory unit.

[0088] Step S143: when a first logic mapping table is read successfully, in the temporarily applied memory unit, the currently hit first logic mapping table is updated according to multiple adjacent second logic mapping information that hit the same first logic mapping table to obtain a corresponding second logic mapping table.

[0089] Step S144: after the currently hit first logic mapping table is updated, the next first logic mapping table is updated in response to the next read cache command, until all second logic mapping information is updated to each corresponding first logic mapping table, and all corresponding second logic mapping tables are obtained.

[0090] Through steps S141 to S144, multiple adjacent second logical mapping information that hit the same first logical mapping table can be updated one by one to the currently hit first logical mapping table, thereby reducing the switching frequency of the logical mapping table, improving random write performance, and reducing the read and write loss of the storage device.

[0091] According to some embodiments of the present application, after obtaining the second logical mapping table, the method further includes: receiving a write cache command; in response to the write cache command, each time a second logical mapping table is obtained, writing the second logical mapping table updated in the temporarily applied memory unit into the flash memory unit, thereby completing the update of all logical mapping tables.

[0092] Further explanation of the update process of the accumulated second logical mapping information provided by the embodiment of the present application: when all or part of the accumulated second logical mapping information has been read into the temporarily applied memory unit, the second logical mapping information cached in the temporarily applied memory unit is sorted in the order of logical address from small to large or from large to small. After adjustment, in the subsequent process of updating the logical mapping information to the logical mapping table L2P, the logical mapping information is updated one by one to the logical mapping table L2P according to the sorted logical mapping information, wherein the adjacent logical mapping information that hits the same logical mapping table is updated to the logical mapping table until all the second logical mapping information cached in the temporarily applied memory unit is updated. If only part of the accumulated second logical mapping information is cached in the temporarily applied memory unit, after the second logical mapping information of the currently temporarily applied memory unit is updated, it is necessary to re-read the unupdated accumulated second logical mapping information from the SLC block and place it in the temporarily applied memory unit, and repeat the above-mentioned second logical mapping information update process. Until the second logical mapping information in the SLC block is updated.

[0093] Combination Figure 5 , further illustrating the overall process of reading and writing the logical mapping table provided in the embodiment of the present application.

[0094] The reading and writing process of the logical mapping table L2P: obtain the map no of all logical mapping tables L2P corresponding to the sorted logical mapping information, use the flash cache read command to asynchronously read the logical mapping table from the flash memory, until the data of a certain logical mapping table is determined to have been read successfully, update the logical mapping information that hits this logical mapping table one by one, until the logical mapping information that hits this logical mapping table is completely updated, send the next cache read command of the logical mapping table that has not sent the flash read command, and repeat the above process until the upper limit of the number of logical mapping table caches in the memory is reached. After completing the update of the logical mapping information corresponding to all cached logical mapping tables in the memory, use the flash cache write command to write all the updated cached logical mapping tables to the flash memory. Repeat the above process until all sorted logical mapping information is updated to the logical mapping table.

[0095] Step S501: Acquire mapping numbers of all first logical mapping tables corresponding to the sorted second logical mapping information.

[0096] Step S502: determine whether all second logical mapping information has been updated; if so, end; if not, continue to execute step S503 and subsequent steps.

[0097] Step S503: determine whether all logical mapping tables have sent read commands; if so, execute step S508 and subsequent steps; if not, execute step S504 and subsequent steps.

[0098] Step S504: Use the Cache read command (ie, read cache command) of the flash memory to asynchronously read the logic mapping table.

[0099] Step S505: Determine whether there is a logic mapping table that has read back data. If yes, execute step S506 and subsequent steps; if no, jump to execute step S507 and subsequent steps.

[0100] Step S506: Update all logical mapping information that hits this logical mapping table into the logical mapping table.

[0101] Step S507: determine whether the number of logical mapping tables read by the Cache read command reaches the upper limit of the number of logical mapping tables cached in the memory unit; if so, continue to execute step S508; if not, jump to execute step S503 and subsequent steps.

[0102] Step S508: Entering a synchronization state to ensure that the data of all logic mapping tables in the memory unit have been read back.

[0103] Step S509: All logic mapping information of the logic mapping table that hits the memory unit is updated into the logic mapping table accordingly.

[0104] Step S510: Use the cache write command (write cache command) of the flash memory to write all updated logical mapping tables in the cache into the flash memory unit, and jump to execute step S502.

[0105] like Figure 6 As shown, the present invention also provides a controller, comprising:

[0106] The processor 601 may be implemented by a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0107] The memory 602 may be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 may store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 602, and the processor 601 calls and executes the logical mapping table update method of the storage device in the embodiment of this application;

[0108] Input / output interface 603, used to implement information input and output;

[0109] Communication interface 604, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WI FI, Bluetooth, etc.);

[0110] Bus 605 , which transmits information between various components of the device (e.g., processor 601 , memory 602 , input / output interface 603 , and communication interface 604 );

[0111] The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0112] An embodiment of the present application also provides an electronic device, including the controller as described above.

[0113] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the method for updating the logical mapping table of the above-mentioned storage device is implemented.

[0114] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0115] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0116] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for updating a logical mapping table of a storage device, characterized in that: A controller applied to a storage device, the storage device further comprising: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit comprises: a data block, the data block comprising a plurality of SLC blocks; The method comprises: storing first logical mapping information of the logical data written into the data block one by one into the memory unit; wherein the first logical mapping information includes a logical address of the logical data and a corresponding physical address; When a first storage quantity of the first logical mapping information accumulated and stored in the memory unit is equal to a storage quantity threshold, writing the first storage quantity of the first logical mapping information accumulated and stored in the memory unit into an SLC block to obtain second logical mapping information; When the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a mapping table forced update instruction, the second logical mapping information currently accumulated is read from the SLC block and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain sorted second logical mapping information; Perform table update processing according to the sorted second logical mapping information, update the corresponding first logical mapping table, and obtain a second logical mapping table; wherein the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain a second logical mapping table.

2. The method for updating the logical mapping table of a storage device according to claim 1, characterized in that: Before writing the first logical mapping information of the first accumulated storage quantity into an SLC block, the method further includes: When the first storage quantity is equal to the storage quantity threshold, recording the address range of the data block where the logical data corresponding to the accumulated first logical mapping information is located; The physical storage address of the first logical mapping information that is accumulated and stored is recorded.

3. The method for updating the logical mapping table of a storage device according to claim 2, characterized in that: The step of writing the first logical mapping information of the first accumulated storage quantity into an SLC block comprises: Writing the first logical mapping information into the SLC block, obtaining the second logical mapping information when confirming that the first logical mapping information is successfully written into the SLC block, and clearing the first logical mapping information accumulated in the memory unit; The first logic mapping information of the logic data continues to be written into the memory unit until the second logic mapping information is equal to a preset threshold.

4. The method for updating the logic mapping table of a storage device according to claim 2, characterized in that: The second logical mapping information currently accumulated is read from the SLCblock and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain sorted second logical mapping information, including: Reading the second logical mapping information stored in the SLC blocks one by one according to the writing order of the physical storage addresses; When it is determined that the read second logical mapping information is correct and the number of temporarily applied memory units is sufficient, the read second logical mapping information is stored in the temporarily applied memory units according to the writing order; In the temporarily applied memory unit, the second logical mapping information is sorted according to the order of the logical address from large to small, or the second logical mapping information is sorted according to the order of the logical address from small to large to obtain the sorted second logical mapping information.

5. The method for updating the logic mapping table of a storage device according to claim 4, characterized in that: Each data block includes a plurality of data pages, each of the data pages also includes an OOB area; After reading the second logical mapping information stored in the SLC blocks one by one, the method further includes: When it is determined that the read second logical mapping information is wrong, according to the address range of the data block where the logical data corresponding to the recorded first logical mapping information is located, all data pages within the address range are read; The first logic mapping information corresponding to each written logic data and the writing sequence of each logic data are obtained from the OOB area of ​​the read data page, and the erroneous second logic mapping information is reconstructed.

6. The method for updating the logical mapping table of a storage device according to claim 3, characterized in that: The performing table updating processing according to the sorted second logical mapping information to update the corresponding first logical mapping table to obtain the second logical mapping table includes: Obtaining mapping numbers of all first logical mapping tables corresponding to the sorted second logical mapping information; In response to a read cache command, asynchronously read the first logic mapping table indicated by the mapping number from the flash memory unit and cache it in a temporarily applied memory unit; When a first logic mapping table is read successfully, in the temporarily applied memory unit, the first logic mapping table currently hit is updated according to a plurality of adjacent second logic mapping information that hit the same first logic mapping table, to obtain a corresponding second logic mapping table; After the currently hit first logical mapping table is updated, the next first logical mapping table is updated in response to the next read cache command until all the second logical mapping information is updated to each corresponding first logical mapping table, thereby obtaining all the corresponding second logical mapping tables.

7. The method for updating the logic mapping table of a storage device according to claim 6, characterized in that: After obtaining the second logical mapping table, the method further includes: Receive a write cache command; In response to the write cache command, each time a second logical mapping table is obtained, the second logical mapping table updated in the temporarily applied memory unit is written into the flash memory unit.

8. A controller, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the logical mapping table updating method of the storage device as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising a controller as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for updating a logical mapping table of a storage device according to any one of claims 1 to 7.

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