Logic mapping information reconstruction method of storage device, controller, equipment and medium

Abstract

The invention discloses a logic mapping information reconstruction method of a memory device, a controller, equipment and a medium, and relates to the technical field of memories. The method comprises the following steps: segmenting and storing accumulated first logic mapping information of logic data written into a data page to obtain second logic mapping information and a storage address association relationship; updating the accumulated second logic mapping information of which the second storage quantity is equal to the preset threshold value to the corresponding first logic mapping table to obtain an updated second logic mapping table, and generating checkpoint information after the table is updated each time; and when the storage device is restarted after power failure, rereading according to the last checkpoint information and the storage address association relationship to obtain second logic mapping reconstruction information in the SLC block, and reconstructing the first logic mapping reconstruction information in the memory unit to complete FTL initialization. Time consumed for reconstructing the mapping relation from the logic address to the physical address can be reduced, and initialization of the storage device is accelerated.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a method for reconstructing logical mapping information of a memory device, a controller, a device, and a medium. Background Art

[0002] Usually, storage devices such as eMMC, UFS, SD card, and USB flash drive need to be initialized in a very short time so that the main control device can access the storage device. Among them, flash memory devices are an important storage medium, and the speed of their initialization will directly affect the startup speed experience of the terminal device. Before the flash memory device works normally, that is, during the initialization process, it is necessary to establish a mapping relationship between the logical address and the physical address. This mapping relationship can be reflected and maintained by a logical mapping table (Logical address To Physical address, L2P), so that when reading data, the physical location of the data in the flash memory can be found through the L2P table, and then the correct data can be read. There are many tasks to be completed for the initialization of flash memory devices, and among them, the reconstruction of the mapping relationship between the logical address and the physical address of the flash translation layer (FTL) accounts for a high proportion of the total initialization time. Reducing the time required to rebuild the mapping relationship between the FTL logical address and the physical address can greatly reduce the entire initialization time of the flash memory device. When the flash translation layer is running, every once in a while or when a certain amount of logical data is accumulated, the updated logical mapping table in the memory will be written into the flash memory to form a checkpoint. After an abnormal power failure, the L2P table in the memory and the accumulated logical mapping information that has not been updated to the L2P table will be lost. Therefore, after the flash memory device is restarted after an abnormal power failure, the address mapping relationship of the data written after the last checkpoint needs to be rebuilt.

[0003] In the related art, in order to reduce the time required to rebuild the mapping relationship between the FTL logical address and the physical address, the amount of logical data written between two adjacent checkpoints is usually reduced as much as possible, so that the amount of logical mapping information cached in the memory that has not been written to the flash memory is reduced. After power failure, only the logical mapping information previously accumulated in the memory needs to be rebuilt, thereby reducing the time required to rebuild the mapping relationship between the FTL logical address and the physical address. However, reducing the amount of logical data written between two adjacent checkpoints means that more data other than logical data needs to be written, such as metadata and other control information to ensure the normal operation and fault recovery of the flash memory; but this will reduce write performance and accelerate the life consumption of the storage device. Therefore, how to reduce the time required to rebuild the mapping logical information and accelerate the initialization of the storage device without affecting the write performance and device life is an urgent problem to be solved. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for reconstructing the logical mapping information of a storage device, a controller, a device, and a medium, which can reduce the time required to reconstruct the mapping relationship between the logical address and the physical address without writing more other data and without affecting the write performance and device life of the storage device, and accelerate the initialization of the storage device.

[0005] In a first aspect, an embodiment of the present application provides a method for reconstructing logical mapping information of a storage device, which is applied to a controller of the storage device, wherein the storage device further comprises: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit comprises: a data block, wherein the data block comprises a plurality of SLC blocks; wherein the data block comprises a plurality of data pages;

[0006] The method comprises:

[0007] storing first logic mapping information of the logic data written into the data page one by one in the memory unit;

[0008] Performing segmented storage processing on the accumulated first logical mapping information, storing the accumulated first logical mapping information in segments to the SLC block, and obtaining second logical mapping information and a storage address association relationship;

[0009] When the second storage quantity of the accumulated second logical mapping information is equal to a preset threshold, performing table update processing according to the currently accumulated second logical mapping information, and updating the corresponding first logical mapping table to obtain an updated second logical mapping table;

[0010] Each time the table update process is completed, a checkpoint information is generated;

[0011] When the storage device is powered off and restarted, the last checkpoint information is obtained during the FTL initialization process;

[0012] Reread the information according to the last checkpoint information and the storage address association relationship to obtain second logical mapping reconstruction information in the SLC block;

[0013] Reconstruction processing is performed according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit; and FTL initialization is completed according to the second logical mapping reconstruction information and the first logical mapping reconstruction information.

[0014] In a second aspect, an embodiment of the present application provides a controller comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a method for reconstructing logical mapping information of a storage device as described in any one of the embodiments of the first aspect.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, comprising a controller as described in the embodiment of the second aspect.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute a method for reconstructing logical mapping information of a storage device as described in any one of the embodiments of the first aspect.

[0017] The embodiment of the present application includes: in the process of using a storage device to store logical mapping information, first, the first logical mapping information of the logical data of the written data page is stored one by one in the memory unit; secondly, the accumulated first logical mapping information is segmented and stored in the SLC block to obtain the second logical mapping information and the storage address association relationship; then, when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold, the table update processing is performed according to the currently accumulated second logical mapping information, and the corresponding first logical mapping table is updated to obtain the updated second logical mapping table; then, each time the table update processing is completed, a checkpoint information is generated; then, when the storage device is powered off and restarted, the last checkpoint information is obtained during the FTL initialization process; and then, the SLC is re-read according to the last checkpoint information and the storage address association relationship to obtain the SLC block; finally, reconstruction processing is performed according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit; the FTL initialization is completed according to the second logical mapping reconstruction information and the first logical mapping reconstruction information; on the one hand, the present application reconstructs the logical mapping information stored in the memory unit before power failure through reconstruction processing; on the other hand, the second logical mapping reconstruction information in the SLC block is directly obtained by rereading, which can save the time of reading the mapping relationship from the storage page used to store logical data to reconstruct the accumulated logical mapping information, thereby effectively reducing the FTL initialization time, which is conducive to accelerating the initialization of the storage device; that is, the embodiment of the present application can reduce the time required to reconstruct the mapping relationship between the logical address and the physical address without writing more other data and without affecting the write performance and device life of the storage device, thereby accelerating the initialization of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a system architecture of a storage device provided by an embodiment of the present application;

[0019] Figure 2 It is a flowchart of a method for reconstructing logical mapping information of a storage device provided by an embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of the overall steps of segment storage processing and table update processing provided by an embodiment of the present application;

[0021] Figure 4 This is a schematic diagram of a specific process of reconstructing the accumulated second logical mapping information with errors provided by an embodiment of the present application;

[0022] Figure 5 It is a schematic diagram of the hardware structure of a controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0024] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0025] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0027] First, some terms used in this application are explained:

[0028] OOB (out of band) area: There is an OOB area after each page in Nand flash, which is used to store hardware ECC checksum, bad block mark, and file system organization information, mainly used for hardware error correction and bad block processing. Generally, a 512-byte NAND page allocates 16 bytes of OOB per page; if it is a 2k page, each page allocates 64 bytes of OOB.

[0029] SLC block refers to the storage block of single-level cell flash memory. SLC is a NAND flash memory technology, and each cell can only store one bit of data.

[0030] The present application discloses a method for reconstructing the logical mapping information of a storage device, a controller, an electronic device, and a computer-readable storage medium, and relates to the field of memory technology. The method includes: storing the accumulated first logical mapping information of the logical data written to the data page in segments to obtain the second logical mapping information and the storage address association relationship; updating the accumulated second logical mapping information whose second storage quantity is equal to the preset threshold to the corresponding first logical mapping table to obtain an updated second logical mapping table, and generating a checkpoint information after each table update; when the storage device is powered off and restarted, the second logical mapping reconstruction information in the SLC block is reread according to the last checkpoint information and the storage address association relationship, and the first logical mapping reconstruction information in the memory unit is reconstructed to complete the FTL initialization. It can reduce the time required to reconstruct the mapping relationship from the logical address to the physical address, and accelerate the initialization of the storage device.

[0031] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0032] like Figure 1 As shown, the storage device includes: a controller, a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit includes: a data block, the data block includes a plurality of SLC blocks, wherein each data block includes a plurality of data pages, and each data page also includes an OOB area.

[0033] Specifically, the memory unit refers to RAM (Random Access Memory).

[0034] Data block refers to a block that stores data. Data blocks include SLC block and TLC block, which are blocks in Nand flash. SLC block is a block that stores data in SLC mode.

[0035] It should be noted that there are multiple blocks in Nand flash, and multiple pages in each block. Each time logical data is written, a page needs to be written. Page is the basic unit of Nand flash writing and reading. Logical data is stored in each page.

[0036] The flash memory unit is used to store the logic mapping table, the logic data, and the second logic mapping information; the memory unit is used to store the accumulated first logic mapping information. The controller is used to execute the logic mapping information reconstruction method of the storage device provided in the embodiment of the present application.

[0037] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0038] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0039] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0040] Based on the above system structure, various embodiments of the method for reconstructing logical mapping information of the storage device of the present application are proposed below.

[0041] In a first aspect, the present application provides a method for reconstructing logical mapping information of a storage device, which is applicable to Figure 1 In the controller of the storage device shown, the storage device also includes: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit includes: a data block, the data block includes a plurality of SLC blocks; the data block includes a plurality of data pages. The logical mapping information reconstruction method of the storage device includes but is not limited to steps S110 to S170.

[0042] Step S110: storing first logic mapping information of the logic data written into the data page into the memory units one by one.

[0043] Step S120: performing segmented storage processing on the accumulated first logical mapping information, storing the accumulated first logical mapping information in segments into SLC blocks, and obtaining second logical mapping information and storage address association relationship.

[0044] Step S130: when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold, a table update process is performed according to the currently accumulated second logical mapping information, and the corresponding first logical mapping table is updated to obtain an updated second logical mapping table.

[0045] Step S140: Generate a checkpoint information each time a table update process is completed.

[0046] Step S150: when the storage device is powered off and restarted, during the FTL initialization process, the last checkpoint information is obtained.

[0047] Step S160: reread the data according to the last checkpoint information and the storage address association relationship to obtain the second logical mapping reconstruction information in the SLC block.

[0048] Step S170: Reconstruction processing is performed according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit; and FTL initialization is completed according to the second logical mapping reconstruction information and the first logical mapping reconstruction information.

[0049] It should be noted that in this application, the logical mapping information stored in the memory unit is referred to as the first logical mapping information, and the logical mapping information stored in the SLC block is referred to as the second logical mapping information. The first logical mapping information and the second logical mapping information are both logical mapping information. For the sake of distinction, they are described as "first" and "second".

[0050] Specifically, the checkpoint information includes but is not limited to: the table storage address information of the logical mapping table, datablock attribute information (including the sequential number of each block written), all datablock numbers and the last written page number when writing the checkpoint, the storage address information of the partially accumulated second logical mapping information stored in the flash memory unit, etc.

[0051] The checkpoint information records the data block attribute information, which includes the order in which data blocks are written. The order in which data blocks are written is used to represent the order in which each block is written. Specifically, the block numbers are used for sorting. The block numbers of data blocks can be sorted by the order in which data blocks are written.

[0052] For the writing order of pages in different data blocks, the page writing order information can be obtained in the OOB area data of each page. The page writing order information is used to represent: the order in which each page in a block is written, specifically, it is sorted by page number. It should be noted that the checkpoint information records all the data blocks when the checkpoint information is written and the page number of each data block that was last written. The order of the logical pages written after the checkpoint information is generated and the page number of the last data page that wrote the logical data can be obtained by reading the data page.

[0053] The present application generates Checkpoint information, which provides a reliable reference for directly reading the second logical mapping information stored in the SLC block and rebuilding the first logical mapping information in the memory unit during power-on reconstruction.

[0054] It is understandable that the present application sets a trigger condition for triggering the table update process: when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold. The preset threshold can be set by those skilled in the art according to actual needs. Therefore, the present application does not impose any specific restrictions on the value of the preset threshold.

[0055] The present application, through steps S110 to S170, in the process of using a storage device to store logical mapping information, first, stores the first logical mapping information of the logical data of the written data page into the memory unit one by one; secondly, performs segmented storage processing on the accumulated first logical mapping information, and stores the accumulated first logical mapping information into the SLC block in segments to obtain the second logical mapping information and the storage address association relationship; then, when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold, performs table update processing according to the currently accumulated second logical mapping information, updates the corresponding first logical mapping table to obtain an updated second logical mapping table; then, generates a checkpoint information each time the table update processing is completed; then, when the storage device is powered off and restarted, the last checkpoint information is obtained during the FTL initialization process; and then, performs rereading processing according to the last checkpoint information and the storage address association relationship to obtain the SLC block; finally, reconstruction processing is performed according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit; the FTL initialization is completed according to the second logical mapping reconstruction information and the first logical mapping reconstruction information; on the one hand, the present application reconstructs the logical mapping information stored in the memory unit before power failure through reconstruction processing; on the other hand, the second logical mapping reconstruction information in the SLC block is directly obtained by rereading, which can save the time of reading the mapping relationship from the storage page used to store logical data to reconstruct the accumulated logical mapping information, thereby effectively reducing the FTL initialization time, which is conducive to accelerating the initialization of the storage device; therefore, the embodiment of the present application can reduce the time required for reconstructing the mapping relationship between the logical address and the physical address without writing more other data and without affecting the write performance and device life of the storage device, thereby accelerating the initialization of the storage device.

[0056] Further explanation: The embodiment of the present application provides a segmented storage process for the accumulated first logical mapping information.

[0057] According to some embodiments of the present application, step S120 is further described. Step S120: the accumulated first logical mapping information is segmented and stored in the SLC block to obtain the second logical mapping information, including but not limited to steps S121 to 124.

[0058] Step S121: in the process of storing the first logic mapping information in the memory unit, counting a first storage quantity of the first logic mapping information stored in the memory unit.

[0059] Step S122: When the first storage quantity is equal to the storage quantity threshold, the currently accumulated first logical mapping information is stored in the SLC block to obtain the second logical mapping information.

[0060] Step S123: continue to write the first logical mapping information into the memory unit, and continue to store the accumulated first logical mapping information in segments into the SLC block until the second logical mapping information is equal to the preset threshold.

[0061] It is understandable that, due to the limitation of memory space, only a small fixed memory unit can be applied to store the first logical mapping information (including the logical address and the corresponding physical address) corresponding to the written logical data. Therefore, the storage quantity threshold is determined by the actual size of the memory unit used, and those skilled in the art can use a memory unit of a certain size according to the actual situation. Therefore, the embodiment of the present application does not impose specific restrictions on the value of the storage quantity threshold.

[0062] According to some embodiments of the present application, step S122 is further described, wherein the currently accumulated first logical mapping information is stored in the SLC block, and before the second logical mapping information is obtained, the method further includes: when the first storage quantity is equal to the storage quantity threshold, recording the address range information of the storage location where the logical data corresponding to each accumulated first logical mapping information is located, storing the physical storage address information of each accumulated first logical mapping information; generating storage management information based on the associated address range information and physical storage address information; and writing the storage management information into the SLC block. In this way, by generating the storage management information, a reliable reference is provided for the subsequent reconstruction processing and reconstruction of the first logical mapping reconstruction information in the memory unit.

[0063] According to some embodiments of the present application, step S122 is further described, wherein, after the currently accumulated first logical mapping information is stored in the SLC block and the second logical mapping information is obtained, the method further includes: each time the accumulated first logical mapping information is stored in the SLC block, the storage address of the currently stored accumulated second logical mapping information is recorded in the OOB area of ​​the data page where the next accumulated second logical mapping information is stored; the storage address of the last accumulated second logical mapping information is recorded in the OOB area data corresponding to each logical data, forming a storage address association relationship. In this way, the storage address association relationship is used to quickly perform a reread process in the subsequent step to obtain the second logical mapping reconstruction information in the SLC block, providing a reliable reference.

[0064] The embodiment of the present application implements a segmented storage mechanism for the accumulated first logical mapping information through steps S121 to S123, and stores the accumulated first logical mapping information in segments to the SLC block, so that when the storage device is restarted after power failure, the second logical mapping information stored in the SLC block can be quickly and directly read, thereby greatly reducing the time required to rebuild the mapping relationship from the logical address to the physical address.

[0065] like Figure 3 As shown, an example is given to illustrate the complete process of the segmented storage processing of the accumulated first logical mapping information and the table update processing of the accumulated second logical mapping information provided by the embodiment of the present application.

[0066] Step S301: write logical data into a data block.

[0067] Step S302: storing first logic mapping information corresponding to the written logic data into a memory unit.

[0068] Step S303: determine whether the first storage quantity of the first logical mapping information is equal to the storage quantity threshold; if so, jump to the steps after step S304; if not, repeat steps S301 to S302.

[0069] Step S304: record the address range information of the storage location where the logical data corresponding to each accumulated first logical mapping information is located, and store the physical storage address information of each accumulated first logical mapping information; generate storage management information according to the associated address range information and physical storage address information.

[0070] Step S305: Write the accumulated first logical mapping information into the SLC block to obtain the second logical mapping information; and write the storage management information into the SLC block.

[0071] Step S306: Record the storage address of the last accumulated second logic mapping information in the OOB area data corresponding to each piece of logic data to form a storage address association relationship, and subsequently write it into the data block along with the logic data.

[0072] Step S307: determine whether the accumulated second logic mapping information is equal to a preset threshold; if not, jump to execute step S301 and subsequent steps; if yes, execute step S308 and step S309.

[0073] Step S308: Read all accumulated second logical mapping information from the SLC block, and update it into the corresponding first logical mapping table to obtain an updated second logical mapping table.

[0074] Step S309: Record a checkpoint information.

[0075] To further illustrate step S306, the page of the flash memory unit can be divided into a main area and a spare area. The main area is used to store the logical data written by the host, and the spare area stores FTL management information (OOB data), ECC encoding and decoding information, etc. Each piece of logical data corresponds to an OOB data, and the OOB data is stored in the OOB area of ​​the page.

[0076] It is understandable that in the related art, it is necessary to read all the data written after the checkpoint information, obtain the logical address stored in each data page, and rebuild the logical mapping information of all the logical data written after the checkpoint information. And through steps S301 to S309, it can be known that the accumulated logical mapping information formed by the logical data written after the checkpoint information in this application will be divided into multiple times and written to the SLC block in segments, and the page of the data block storing the user data records: the storage address of the part of the accumulated second logical mapping information that has been stored in the SLC block in batches. During reconstruction, the part of the accumulated second logical mapping information stored in the SLC block can be read directly, and there is no need to read all the pages to obtain the logical address to rebuild this part of the accumulated logical mapping information, thereby saving the time required to rebuild the mapping relationship between the logical address and the physical address; this application mainly revolves around: the design of how to quickly obtain this part of the accumulated second logical mapping information when updating the accumulated logical mapping information in batches and rebuilding.

[0077] It can be understood that in the process of writing logical data, the embodiment of the present application continuously executes steps S301 to S309, and multiple checkpoint information will be obtained. When the storage device loses power, the last checkpoint information can be obtained from the multiple checkpoint information. Obtaining the data page range of the data block that needs to be rebuilt refers to: determining the storage address range of the logical data written after the last checkpoint information, and determining the range of the logical mapping information that needs to be rebuilt. In the data page range of the data block that needs to be rebuilt, on the one hand, part of the accumulated first logical mapping information has been stored as the second logical mapping information in the SLC block of the flash memory unit before power off, and the second logical mapping information in the SLC block can be read directly; on the other hand, the first logical mapping information stored in the memory unit before power off and not yet stored in the SLC block of the flash memory unit will be lost after power off. In this way, it is necessary to read the mapping information corresponding to the logical data from the page to reconstruct the lost part of the first logical mapping information.

[0078] An example is given to illustrate the process of restoring the logical mapping information of the logical data written by the last checkpoint information. After a checkpoint information is generated, subsequent logical data is written from data block 100, page 50. The checkpoint information records the information of data block 100, page 50. If after writing page 100, page 150, and page 200, the accumulated logical mapping information of this part of data is stored in the SLC block of the flash memory unit, when the power is turned off after writing to page 230, and the mapping information of the data written before page 50 is already in the mapping table stored in the flash memory after powering on again, it does not need to be rebuilt. What needs to be rebuilt is the page written after data block 100, page 50, among which, the accumulated logical mapping information within the range of page 50 to page 200 can be directly read from the page of the SLC block of the flash memory unit, and the accumulated logical mapping information within the range of page 200 to page 230 needs to read all pages within the range of page 200 to page 230, obtain the mapping information corresponding to the logical data, and reconstruct this part of the accumulated logical mapping information; at this point, the logical mapping information of all logical data written to the page after data block 100, page 50 is restored.

[0079] It should be emphasized that, compared with the related art, in order to reduce the time required to rebuild the mapping relationship between the FTL logical address and the physical address, the amount of logical data written between two adjacent checkpoints is usually reduced as much as possible. The present application does not reduce the amount of logical data written between two adjacent checkpoints. Therefore, there is no need to write more data other than logical data, so as not to affect the write performance and device life of the storage device. In order to quickly restore the logical mapping information of the logical data written after the last checkpoint information during the power-off restart process, a segmented storage mechanism is designed. In the segmented storage mechanism, due to the limitation of the memory space, a smaller fixed memory unit can be applied first to store the first logical mapping information corresponding to the written logical data (including the logical address and the corresponding physical address); then, the corresponding first logical mapping information of the written logical data is stored one by one in the fixed memory unit until the accumulated first logical mapping information reaches the storage quantity threshold of the memory unit, and the accumulated first logical mapping information is written to the SLC block. Repeat this process until the accumulated second logical mapping information in the SLC block reaches the preset threshold set by the program, read all the accumulated second logical mapping information from the SLC block, update it to the logical mapping table, and record a checkpoint information. It can be seen that the mapping relationship of the logical data written before the checkpoint information has been stored in the logical mapping table of the flash memory unit and can be read directly without reconstruction. What needs to be restored is the mapping relationship of the logical data written after the last checkpoint information. After power failure, when the FTL is rebuilt, the last checkpoint information is obtained, and then all data blocks written after the last checkpoint and the corresponding write order are obtained, and the range of data blocks that need to be rebuilt is obtained. When restoring the mapping relationship of the logical data written after the last checkpoint information: on the one hand, a reread process is performed: multiple copies of the accumulated second logical mapping information (including the logical address and the corresponding physical address) recorded in the SLC block are directly obtained. There is no need to obtain the mapping information corresponding to the logical data from the page storing each logical data, but directly read and restore the accumulated second logical mapping information; on the other hand, a reconstruction process is performed: because the mapping information corresponding to the last written logical data exists in the memory and is lost after power failure, it is necessary to reconstruct the first mapping information of the logical data of the storage memory unit lost due to power failure. During reconstruction, it is necessary to obtain the mapping information corresponding to the logical data from the page storing each logical data, and then reconstruct the accumulated first logical mapping information.Through the above recovery process, the time for reading mapping information from the page storing logical data of the Nand flash to rebuild the accumulated logical mapping information can be greatly saved, thereby reducing the time consumption of FTL initialization.

[0080] According to some embodiments of the present application, step S150 is further described. Step S150: rereading is performed according to the last checkpoint information and the storage address association relationship to obtain the second logical mapping reconstruction information in the SLC block, including but not limited to steps S151 to S154.

[0081] Step S151: Determine the data page reconstruction range and data block writing order according to the last checkpoint information.

[0082] Step S152: Determine the data page storing the last written logical data according to the data page reconstruction range and the data block writing order.

[0083] Step S153: obtaining the first physical storage address of the last accumulated second logical mapping information from the OOB area of ​​the data page of the last written logical data.

[0084] Step S154: directly acquiring second logical mapping information currently stored in the data page of the SLC block and not updated to the first logical mapping table according to the association relationship between the first physical storage address and the storage address, and obtaining second logical mapping reconstruction information.

[0085] The embodiment of the present application implements a storage address association mechanism for the accumulated second logical mapping information in step S120, and further illustrates the rapid reading of the accumulated second logical mapping information by utilizing the storage address association relationship in step S154.

[0086] Because there are multiple copies of the accumulated second logical mapping information, and the locations where the multiple copies of the accumulated second logical mapping information are stored in the SLC block of the flash memory unit are not continuous, a storage address association mechanism for the accumulated second logical mapping information is designed. Based on this storage address association mechanism, the first physical storage address of the last copy of the accumulated second logical mapping information can be obtained from the OOB area of ​​the last data page, and from the data page indicated by the first physical storage address, the following can be obtained: the data write range of the logical data corresponding to all the accumulated second logical mapping information previously stored in the SLC block, and the third physical storage address of all the accumulated second logical mapping information; it can be seen that the storage address association mechanism means that the data page (page) storing each copy of the accumulated second logical mapping information stores: the data write range and storage address information corresponding to all the accumulated second logical mapping information previously stored in the SLC block. By analogy, there is no need to scan each page one by one, so as to quickly read the accumulated second logical mapping information in all SLC blocks of the flash memory unit.

[0087] Take an example to illustrate the specific process of quickly reading the accumulated second logical mapping information in the example SLC block based on the storage address association mechanism. If there are 5 accumulated second logical mapping information segments, which are respectively block100page 3, block100page 30, block 100page 100, block 200page 5, and block 200page 60, and the last written logical data is in block 200page 80. In the process of rereading, first read block 200page80, obtain the OOB area data of block 200page 80, and obtain the physical storage address of the last accumulated first logical mapping information: block 200page 60; read the data page according to the physical storage address: block 200page 60; then read block 200page 60 to obtain the last accumulated logical mapping information, and obtain in the page: the data write range of the logical data corresponding to all the accumulated second logical mapping information previously stored in the SLC block and not updated to the first logical mapping table, and the physical storage addresses of all the accumulated second logical mapping information. Finally, all the second logical mapping information stored in the SLC block but not updated in the logical mapping table is found.

[0088] The embodiment of the present application directly reads multiple copies of accumulated second logical mapping information recorded in the SLC block through steps S151 to S154, thereby reducing the time required to rebuild the mapping relationship between the logical address and the physical address and accelerating the initialization of the storage device.

[0089] The embodiment of the present application also configures a reconstruction mechanism for erroneous second logical mapping information during the rereading process of the SLC block.

[0090] According to some embodiments of the present application, step S154 directly obtains the second logical mapping information currently stored in the data page of the SLC block and not updated to the first logical mapping table, and also includes steps S210 to S240.

[0091] Step S210: when a data page storing the second logical mapping information is partially erroneous and the second logical mapping information cannot be correctly read, obtaining a second physical storage address of the erroneous second logical mapping information;

[0092] Step S220: determining address range information associated with the second physical storage address according to the storage management information;

[0093] Step S230: determining the address range information of the storage location where the logic data corresponding to the second logic mapping information is located according to the address range information;

[0094] Step S240: within the address range information, obtain the relationship between the logical address and the physical address corresponding to the logical data from the data page corresponding to the storage of the logical data, reconstruct the erroneous second logical mapping information, obtain the correct second logical mapping information, and record the correct second logical mapping information into the SLC block.

[0095] The erroneous second logical mapping information is reconstructed through steps S210 to S240 to ensure the correctness of the mapping relationship from the reconstructed logical address to the physical address, so as to perform the FLT initialization normally.

[0096] like Figure 4 As shown, an example is given to illustrate the specific process of reconstructing the erroneous accumulated second logical mapping information provided by the embodiment of the present application.

[0097] Step S401: determine whether all data pages storing the accumulated second logical mapping information are wrong; if so, execute steps S402 to S403; if not, execute steps S404 to S405.

[0098] Step S402: Get the data page range of all Pages written after the last checkpoint information.

[0099] Step S403: According to the data page range, mapping information corresponding to the logical data is obtained from the data page storing each logical data, the accumulated logical mapping information is rebuilt, and recorded in the SLC block.

[0100] Step S404: Obtain the storage address of the erroneous accumulated second logical mapping information.

[0101] Step S405: Obtain the data storage range corresponding to the erroneous accumulated logical mapping information from the data writing range of all the acquired logical data corresponding to the second logical mapping information that has not been updated to the first logical mapping table; based on this data storage range, obtain the mapping information corresponding to the logical data from the data page storing each logical data, reconstruct the erroneous accumulated second logical mapping information, and record it to the SLC block.

[0102] The data writing range of the logic data in step S405 is the address range information of the storage location where the logic data is located.

[0103] It can be understood that the page storing each accumulated second logical mapping information stores: the data write range and storage address information corresponding to all the accumulated logical mapping information previously stored in the SLC block. Therefore, the data storage range corresponding to all the accumulated second logical mapping information has been obtained when the data corresponding to the last accumulated second logical mapping information is obtained. In the error handling process again, it is only necessary to rebuild the erroneous second logical mapping information according to the data storage range.

[0104] According to some embodiments of the present application, step S170 is further described, step S170: reconstruction processing is performed according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit, including but not limited to: determining the first address range information according to the data page reconstruction range and the writing range of the logical data corresponding to the second logical mapping reconstruction information; reading all target data pages within the address range indicated by the first address range information; obtaining the relationship between the logical address and the physical address of the logical data from the target data page storing the logical data, and reconstructing to obtain the first logical mapping reconstruction information; wherein the first logical mapping reconstruction information is the first logical mapping information stored in the memory unit before power failure. In this way, the first logical mapping information stored in the memory unit before power failure and lost after power failure is reconstructed to obtain the first logical mapping reconstruction information, and then combined with the second logical mapping reconstruction information obtained after the rereading process, the logical mapping information of all logical data written after the last checkpoint information is restored.

[0105] like Figure 5 As shown, the present application also provides a controller, including:

[0106] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0107] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the logical mapping information reconstruction method of the storage device in the embodiment of the present application;

[0108] Input / output interface 503, used to implement information input and output;

[0109] Communication interface 504, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WI FI, Bluetooth, etc.);

[0110] A bus 505 that transmits information between the various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0111] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via the bus 505 .

[0112] An embodiment of the present application also provides an electronic device, including the controller as described above.

[0113] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the method for reconstructing the logical mapping information of the above-mentioned storage device is implemented.

[0114] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0115] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0116] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for reconstructing logical mapping information of a storage device, characterized in that: A controller applied to a storage device, the storage device further comprising: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit comprises: a data block, the data block comprises a plurality of SLC blocks; the data block comprises a plurality of data pages; The method comprises: storing first logic mapping information of the logic data written into the data page one by one in the memory unit; Performing segmented storage processing on the accumulated first logical mapping information, storing the accumulated first logical mapping information in segments to the SLC block, and obtaining second logical mapping information and a storage address association relationship; When the second storage quantity of the accumulated second logical mapping information is equal to a preset threshold, performing table update processing according to the currently accumulated second logical mapping information, and updating the corresponding first logical mapping table to obtain an updated second logical mapping table; Each time the table update process is completed, a checkpoint information is generated; When the storage device is powered off and restarted, the last checkpoint information is obtained during the FTL initialization process; Reread the information according to the last checkpoint information and the storage address association relationship to obtain second logical mapping reconstruction information in the SLC block; Reconstruction processing is performed according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit; and FTL initialization is completed according to the second logical mapping reconstruction information and the first logical mapping reconstruction information.

2. The method for reconstructing logical mapping information of a storage device according to claim 1, characterized in that: The performing segmented storage processing on the accumulated first logical mapping information, and storing the accumulated first logical mapping information segmentedly in the SLC block to obtain second logical mapping information, includes: In the process of storing the first logical mapping information in the memory unit, counting a first storage quantity of the first logical mapping information stored in the memory unit; When the first storage quantity is equal to a storage quantity threshold, storing the currently accumulated first logical mapping information into the SLC block to obtain second logical mapping information; The first logical mapping information continues to be written into the memory unit, and the accumulated first logical mapping information continues to be stored in segments into the SLC block until the second logical mapping information is equal to a preset threshold.

3. The method for reconstructing logical mapping information of a storage device according to claim 2, characterized in that: Before storing the currently accumulated first logical mapping information in the SLC block to obtain the second logical mapping information, the method further includes: When the first storage quantity is equal to the storage quantity threshold, recording the address range information of the storage location where the logical data corresponding to each accumulated first logical mapping information is located, and storing the physical storage address information of each accumulated first logical mapping information; Generate storage management information according to the associated address range information and the physical storage address information; The storage management information is written into the SLC block.

4. The method for reconstructing logical mapping information of a storage device according to claim 3, characterized in that: After storing the currently accumulated first logical mapping information in the SLC block to obtain the second logical mapping information, the method further includes: Each time the accumulated first logical mapping information is stored in the SLC block, the storage address of the currently stored accumulated second logical mapping information is recorded in the OOB area of ​​the data page where the next accumulated second logical mapping information is stored; The storage address of the last accumulated second logic mapping information is recorded in the OOB area data corresponding to each piece of logic data to form the storage address association relationship.

5. The method for reconstructing logical mapping information of a storage device according to claim 4, characterized in that: The rereading process is performed according to the last checkpoint information and the storage address association relationship to obtain the second logical mapping reconstruction information in the SLC block, including: Determine the data page reconstruction range and data block writing order according to the last checkpoint information; Determine, according to the data page reconstruction range and the data block writing order, a data page storing the last written logical data; Acquire the first physical storage address of the last accumulated second logical mapping information from the OOB area of ​​the data page of the last written logical data; According to the association relationship between the first physical storage address and the storage address, second logical mapping information currently stored in the data page of the SLCblock and not updated to the first logical mapping table is directly acquired to obtain the second logical mapping reconstruction information.

6. The method for reconstructing logical mapping information of a storage device according to claim 5, characterized in that: The directly acquiring the second logical mapping information currently stored in the data page of the SLC block and not updated to the first logical mapping table also includes: When a data page storing the second logical mapping information is partially erroneous and the second logical mapping information cannot be correctly read, obtaining a second physical storage address of the erroneous second logical mapping information; Determining address range information associated with the second physical storage address according to the storage management information; Determine, according to the address range information, address range information of a storage location where the logic data corresponding to the second logic mapping information is located; Within the address range information, the relationship between the logical address and the physical address corresponding to the logical data is obtained from the data page corresponding to the storage of the logical data, the erroneous second logical mapping information is reconstructed to obtain the correct second logical mapping information, and the correct second logical mapping information is recorded in the SLC block.

7. The method for reconstructing logical mapping information of a storage device according to claim 5, characterized in that: The performing reconstruction processing according to the last checkpoint information and the second logical mapping reconstruction information to obtain the first logical mapping reconstruction information in the memory unit includes: Determine first address range information according to the data page reconstruction range and a writing range of logical data corresponding to the second logical mapping reconstruction information; Reading all target data pages within the address range indicated by the first address range information; The relationship between the logical address and the physical address of the logical data is obtained from the target data page storing the logical data, and the first logical mapping reconstruction information is reconstructed; wherein the first logical mapping reconstruction information is the first logical mapping information stored in the memory unit before power failure.

8. A controller, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the logical mapping information reconstruction method of the storage device as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising a controller as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for reconstructing logical mapping information of a storage device according to any one of claims 1 to 7.

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