Multi-host access control method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a multi-host access control method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving transmission requests sent by a plurality of hosts; performing arbitration processing on the plurality of hosts, and determining priority information of each host; determining the host with the maximum priority information as a first host, controlling the first host to access a slave, and storing access information of a second host in a cache space corresponding to the second host; and under the condition that the access of the first host to the slave is completed, controlling the second host to access the slave according to the access information of the second host in the cache space. In the embodiment of the invention, the corresponding cache mechanism is added to the host with low arbitration priority in the system, and when the host with high priority completes the access to the slave, the access of the second host to the slave is completed. According to the cache mechanism, the access of the host with the low priority to the slave is realized, so that the access of the host with the low priority cannot be lost, and the access of the specific host to the slave is more fair.

Description

[0001] This application claims the priority of patent application CN202410160758.5, entitled “Multi-host access control method, device, electronic device and storage medium”, filed on February 5, 2024. The entire contents of this application are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a multi-host access control method, device, electronic device and storage medium. Background Art

[0003] In a system-on-chip (SOC), there are usually multiple masters, multiple slaves, and an arbiter. Multiple masters can initiate transmission requests at the same time. After arbitration, the master with a high priority obtains the bus and the authorization signal is pulled high. After decoding, the slave is read and written, and the master with a low priority loses access rights. In some systems, the master with a low priority will never be authorized.

[0004] For example, when multiple hosts can initiate transmission requests at the same time, for example, host 1 and host 2 simultaneously initiate access to slave 1. After arbitration, if host 1 has a higher priority, host 1 acquires the bus and performs read and write access to slave 1 after decoding; host 2 with a lower priority loses access to slave 1. If host 2 has a lower priority, host 2 will not be able to acquire the bus. How to enable each host to access the slave is an urgent problem to be solved. Summary of the invention

[0005] The purpose of some embodiments of the present application is to provide a multi-host access control method, device, electronic device and storage medium. Through the technical solution of the embodiments of the present application, transmission requests sent by multiple hosts are received; the multiple hosts are arbitrated to determine the priority information of each host; the host with the maximum priority information is determined as the first host, and the first host is controlled to access the slave, and the access information of the second host is saved in the cache space corresponding to the second host; when the first host completes the access to the slave, the second host is controlled to access the slave according to the access information of the second host in the cache space. In the embodiments of the present application, a corresponding cache mechanism is added to the host with a low arbitration priority in the system. When the host with a high priority completes the access to the slave, the access of the low priority host to the slave is realized according to the cache mechanism. In this way, the access of the low priority host will not be lost, and it is fairer for a specific host to access the slave.

[0006] In a first aspect, some embodiments of the present application provide a multi-host access control method, including:

[0007] Receive transmission requests sent by multiple hosts;

[0008] Performing arbitration on the multiple hosts to determine priority information of each host;

[0009] Determine the host with the highest priority information as the first host, control the first host to access the slave, and save the access information of the second host in the cache space corresponding to the second host;

[0010] When the first host completes access to the slave, the second host is controlled to access the slave according to the access information of the second host in the cache space.

[0011] Some embodiments of the present application add a corresponding cache mechanism to the host with a low arbitration priority in the system. When the host with a high priority completes the access to the slave, the host with a low priority is able to access the slave according to the cache mechanism. In this way, the access of the low-priority host will not be lost, and access to the slave by a specific host is fairer.

[0012] Optionally, after the first host completes accessing the slave, controlling the second host to access the slave according to the access information of the second host in the cache space includes:

[0013] Obtaining a write pointer and a read pointer in the cache space, wherein the write pointer is determined according to the number of received transfer requests, and the read pointer is determined according to the number of accesses to the cache space;

[0014] After the first host completes the access, the cache controller read pointer starts to increase, and the access information of the second host in the cache space is read out through the read pointer to access the slave;

[0015] When the read pointer increases to be equal to the write pointer, the second host completes access to the slave according to the access information of the second host.

[0016] Some embodiments of the present application judge the write pointer and the read pointer, and control the second host to access the slave according to the access information of the second host in the cache space each time, thereby improving the accuracy of the access control of the low-priority host. When the read pointer and the write pointer are equal, the FIFO becomes empty and the access is completed.

[0017] Optionally, the access information of the second host includes at least a host address and a control signal.

[0018] Some embodiments of the present application implement access of the second host to the slave by storing the access information of the second host in a cache space for subsequent acquisition of the host address and control signal from the cache space.

[0019] Optionally, the first host completes accessing the slave, including:

[0020] receiving a feedback signal sent by the slave;

[0021] It is determined, according to the feedback signal, that the access of the first host to the slave is completed.

[0022] In some embodiments of the present application, after the high-priority host completes access to the slave,

[0023] Optionally, the method further comprises:

[0024] Each time a host is added, a cache space corresponding to the host is added.

[0025] Some embodiments of the present application increase the cache space corresponding to the host in real time according to the number of low-priority hosts, so that the memory space can be effectively utilized and the waste of memory space can be avoided.

[0026] Optionally, when there are multiple cache spaces, the method further includes:

[0027] Performing priority decoding on each cache space respectively to obtain decoding information corresponding to the cache space;

[0028] The cache space is read according to the decoding information.

[0029] Some embodiments of the present application can increase corresponding cache space for multiple hosts in the system and for low-priority hosts. When multiple cache spaces cache information of multiple hosts, priority decoding is required to access the slaves.

[0030] In a second aspect, some embodiments of the present application provide a multi-host access control device, including:

[0031] A receiving module, used for receiving transmission requests sent by multiple hosts;

[0032] An arbitration module, used to perform arbitration processing on the multiple hosts and determine the priority information of each host;

[0033] A determination module, configured to determine the host with the highest priority information as the first host, control the first host to access the slave, and save the access information of the second host in a cache space corresponding to the second host;

[0034] The access module is used to control the second host to access the slave according to the access information of the second host in the cache space when the first host completes access to the slave.

[0035] Some embodiments of the present application add a corresponding cache mechanism to the host with a low arbitration priority in the system. When the host with a high priority completes the access to the slave, the host with a low priority is able to access the slave according to the cache mechanism. In this way, the access of the low-priority host will not be lost, and access to the slave by a specific host is fairer.

[0036] Optionally, the access module is used to:

[0037] Obtaining a write pointer and a read pointer in the cache space, wherein the write pointer is determined according to the number of received transfer requests, and the read pointer is determined according to the number of accesses to the cache space;

[0038] After the first host completes the access, the cache controller read pointer starts to increase, and the access information of the second host in the cache space is read out through the read pointer to access the slave;

[0039] When the read pointer increases to be equal to the write pointer, the second host completes access to the slave according to the access information of the second host.

[0040] Some embodiments of the present application judge the write pointer and the read pointer, and each time a read is performed, the second host is controlled to access the slave machine according to the access information of the second host in the cache space, thereby improving the accuracy of access control of the low-priority host. When the read pointer and the write pointer are equal, the FIFO becomes empty and the access is completed.

[0041] Optionally, the access information of the second host includes at least a host address and a control signal.

[0042] Some embodiments of the present application implement access of the second host to the slave by storing the access information of the second host in a cache space for subsequent acquisition of the host address and control signal from the cache space.

[0043] Optionally, the access module is used to:

[0044] receiving a feedback signal sent by the slave;

[0045] It is determined, according to the feedback signal, that the access of the first host to the slave is completed.

[0046] In some embodiments of the present application, after the high-priority host completes access to the slave,

[0047] Optionally, the access module is used to:

[0048] Each time a host is added, a cache space corresponding to the host is added.

[0049] Some embodiments of the present application increase the cache space corresponding to the host in real time according to the number of low-priority hosts, so that the memory space can be effectively utilized and the waste of memory space can be avoided.

[0050] Optionally, when there are multiple cache spaces, the access module is used to:

[0051] Performing priority decoding on each cache space respectively to obtain decoding information corresponding to the cache space;

[0052] The cache space is read according to the decoding information.

[0053] Some embodiments of the present application can increase corresponding cache space for multiple hosts in the system and for low-priority hosts. When multiple cache spaces cache information of multiple hosts, priority decoding is required to access the slaves.

[0054] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the multi-host access control method as described in any embodiment of the first aspect can be implemented.

[0055] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the multi-host access control method as described in any embodiment of the first aspect.

[0056] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, can implement the multi-host access control method as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A flowchart of a multi-host access control method provided in an embodiment of the present application;

[0059] Figure 2 A flowchart of another multi-host access control method provided in an embodiment of the present application;

[0060] Figure 3 A schematic diagram of a multi-host arbitration cache waveform provided in an embodiment of the present application;

[0061] Figure 4 A schematic diagram of the structure of a multi-host access control device provided in an embodiment of the present application;

[0062] Figure 5 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0064] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0065] In a system-on-chip (SOC), there are usually multiple masters, multiple slaves, and an arbiter. Multiple masters can initiate transmission requests at the same time. After arbitration, the master with a high priority obtains the bus and the authorization signal is pulled high. After decoding, the slave is read and written, and the master with a low priority loses access rights. In some systems, the master with a low priority will never be authorized.

[0066] For example, when multiple hosts can initiate transmission requests at the same time, for example, host 1 and host 2 simultaneously initiate access to slave 1, after arbitration, if host 1 has a higher priority, host 1 obtains the bus and performs read and write access to slave 1 after decoding; host 2 with a lower priority will lose access to slave 1. If the priority of host 2 is low, then host 2 will not be able to obtain the bus. In view of this, some embodiments of the present application provide a multi-host access control method, which includes receiving transmission requests sent by multiple hosts; arbitrating multiple hosts to determine the priority information of each host; determining the host with the highest priority information as the first host, and controlling the first host to access the slave, and saving the access information of the second host in the cache space corresponding to the second host; when the first host completes the access to the slave, the second host is controlled to access the slave according to the access information of the second host in the cache space. In the embodiment of the present application, a corresponding cache mechanism is added to the host with a low arbitration priority in the system. When the host with a high priority completes the access to the slave, the access of the low-priority host to the slave is realized according to the cache mechanism. In this way, the access of the low-priority host will not be lost, and it is fairer for a specific host to access the slave.

[0067] like Figure 1 As shown, an embodiment of the present application provides a multi-host access control method, the method comprising:

[0068] S101, receiving transmission requests sent by multiple hosts;

[0069] Specifically, the embodiments of the present application are applied to system-on-a-chip. System-on-a-chip (SoC or SOC, other translations include chip system, system-on-chip, system on chip) is a part of a computer, or a part of the circuit added, put into a chip. This chip will include digital circuits, analog circuits, mixed signals and radio frequency circuits. The applications included therein are usually called embedded systems.

[0070] The system-on-chip (SOC) includes at least a plurality of hosts, a plurality of slaves and an arbiter. In an embodiment of the present application, a cache module is added to the system-on-chip, and the arbiter receives transmission requests sent by a plurality of hosts.

[0071] S102. Arbitrate multiple hosts to determine the priority of each host. Arbitration refers to which host can obtain access rights to the medium in multi-host mode. The bus system only allows one master node to continue to occupy the bus through arbitration. Therefore, the priority information of each host can be determined through arbitration or a preset algorithm.

[0072] S103, determining the host with the highest priority information as the first host, controlling the first host to access the slave, and saving the access information of the second host in the cache space corresponding to the second host;

[0073] Specifically, after determining the priority of each host, the arbitrator selects the host with the highest priority as the first host, that is, the first host obtains the authorization signal and can access the slave. At the same time, other hosts with lower priorities are selected as second hosts, and the access information of the second host is saved in the cache space corresponding to the second host.

[0074] Exemplarily, if the hosts with low priority include host 2 and host 3, for host 2, the access information of host 2 is stored in the cache space of host 2, and for host 3, the access information of host 3 is stored in the cache space of host 3.

[0075] That is to say, when multiple hosts initiate transmission requests at the same time, a FIFO (First Input First Output) control cache module is added to a specific host with a low priority, and the address and control signal of the low priority host are cached through the FIFO write pointer.

[0076] S104 . When the first host completes access to the slave, control the second host to access the slave according to the access information of the second host in the cache space.

[0077] Specifically, after the first host completes access to the slave, the slave returns a feedback signal of access completion to the FIFO controller, and the FIFO controller of the system-level chip determines the state of the cache space of the second slave. When the FIFO of the cache space is not empty, the second host accesses the slave.

[0078] That is, after the cache space of the second host is in a non-empty state and the FIFO controller receives a completion signal fed back by the slave, the information of the low-priority host in the FIFO cache is read through the read pointer and sent to the slave for access.

[0079] The embodiment of the present application adds a cache module to cache instructions and addresses for a low-priority host after arbitration fails, and then executes the low-priority host access after receiving feedback from the slave.

[0080] Some embodiments of the present application add a corresponding cache mechanism to the host with a low arbitration priority in the system. When the host with a high priority completes the access to the slave, the host with a low priority is able to access the slave according to the cache mechanism. In this way, the access of the low-priority host will not be lost, and access to the slave by a specific host is fairer.

[0081] Another embodiment of the present application further supplements the multi-host access control method provided in the above embodiment.

[0082] Optionally, after the first host completes accessing the slave, controlling the second host to access the slave according to the access information of the second host in the cache space includes:

[0083] Obtaining a write pointer and a read pointer in the cache space, wherein the write pointer is determined according to the number of received transmission requests, and the read pointer is determined according to the number of accesses to the cache space;

[0084] After the first host completes the access, the cache controller read pointer starts to increase, and the access information of the second host in the cache space is read out through the read pointer to access the slave;

[0085] When the read pointer increases to be equal to the write pointer, the second host completes access to the slave according to the access information of the second host.

[0086] For example, for a host, the host will send multiple transfer requests to the arbitrator. When a transfer request is received, the write pointer in the cache space is increased by 1. When n transfer instructions are received, the write pointer in the cache space is set to n, where n is a natural number greater than 0.

[0087] After the high-priority host completes access to the slave, it needs to read the address and control signal in the cache space of the second host. For each access, that is, read once, the read pointer in the cache space is increased by 1. For m reads, the read pointer in the cache space is set to m, where m is a natural number greater than 0.

[0088] Some embodiments of the present application judge the write pointer and the read pointer, and each time a read is performed, the second host is controlled to access the slave machine according to the access information of the second host in the cache space, thereby improving the accuracy of access control of the low-priority host. When the read pointer and the write pointer are equal, the FIFO becomes empty and the access is completed.

[0089] Optionally, the access information of the second host includes at least a host address and a control signal.

[0090] Some embodiments of the present application implement access of the second host to the slave by storing the access information of the second host in a cache space for subsequent acquisition of the host address and control signal from the cache space.

[0091] Optionally, the first host completes access to the slave, including:

[0092] Receive the feedback signal sent by the slave;

[0093] According to the feedback signal, it is determined that the access of the first host to the slave is completed.

[0094] In some embodiments of the present application, after the high-priority host completes access to the slave,

[0095] Optionally, the method further comprises:

[0096] Each time a host is added, a cache space corresponding to the host is added.

[0097] Some embodiments of the present application increase the cache space corresponding to the host in real time according to the number of low-priority hosts, so that the memory space can be effectively utilized and the waste of memory space can be avoided.

[0098] Optionally, when there are multiple cache spaces, the method further includes:

[0099] Priority decoding is performed on each cache space respectively to obtain decoding information corresponding to the cache space;

[0100] The cache space is read according to the decoding information.

[0101] Some embodiments of the present application can increase corresponding cache space for multiple hosts in the system and for low-priority hosts. When multiple cache spaces cache information of multiple hosts, priority decoding is required to access the slaves.

[0102] Specifically, using this cache mechanism, multiple hosts with low polling priority in the system can be cached. Each additional host cache will increase a corresponding FIFO; if there are multiple FIFO cache spaces, it is necessary to increase the priority decoding when reading the FIFO cache space, and read the data of multiple FIFO cache spaces; when multiple hosts need to be cached, it is necessary to consider the balance between resource consumption and system performance. For multiple hosts in the system, low-priority hosts with similar requirements can add corresponding FIFO controllers. When multiple FIFOs cache the information of multiple hosts, priority decoding is required to access the slave.

[0103] like Figure 2 As shown, the multi-host arbitration cache mechanism provided in the embodiment of the present application can cache the instructions and addresses of the low-priority host after arbitration, and execute the cached host access rights after receiving the feedback signal of the device; the specific modules and workflow are as follows:

[0104] Compared with the traditional architecture, a FIFO control cache is added, and the default state of the FIFO is empty. When multiple hosts initiate transmission requests at the same time, after arbitration, the host with a high priority will first obtain the authorization of the bus, and the host with a low priority will not obtain authorization; the result of the arbitration authorization grant signal will also be given to the FIFO control module. When the FIFO control module receives the request of the host and the arbitration result grant is 0, the FIFO write enable is valid, and the FIFO write pointer is increased by 1; at the same time, the address and control signal sent by the unauthorized low-priority host are cached in the FIFO. At this time, since the FIFO read pointer does not change, the FIFO changes from empty to non-empty. When the high-priority host completes the access to the slave device, the slave device will feedback the ready signal to the FIFO controller; at this time, the FIFO read pointer starts to increase by 1, and the address and control signal of the FIFO cache are read at the same time, and the slave is read and written; when the FIFO read pointer and write pointer are equal, the FIFO becomes empty again.

[0105] like Figure 2 In the case where host 1 has a relatively low arbitration priority, if host 1 and other hosts, such as host 0 or host n, initiate a transmission request at the same time, then after arbitration, host 1 will not receive the authorization signal grant, but the system does not want to lose the access of host 1. In this case, the FIFO controller will cache the address and control signal of host 1 in the FIFO; the FIFO changes from empty to non-empty, and waits until the slave completes the transmission. The slave feeds back the completion signal to the FIFO controller. At this time, the FIFO starts to read out the cached information of host 1 and gives it to the slave for access. When the FIFO read and write pointers are equal, the FIFO changes from non-empty to empty, and the FIFO read and write pointers are cleared. Only when the FIFO is non-empty and feedback is received from the slave, will the slave be accessed. For the timing diagram, please refer to Figure 3 .

[0106] The embodiment of the present application adds corresponding cache control to the host with low arbitration priority in the system, so that the access of the low-priority host will not be lost, and the access of a specific host to the slave is more fair;

[0107] It should be noted that for each additional host cache, a corresponding FIFO will be added; if there are multiple FIFOs, it is necessary to increase the priority decoding when reading the FIFO and read the data of multiple FIFOs; when multiple hosts need to cache, it is necessary to consider the balance between resource consumption and system performance.

[0108] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any manner without conflict, and this application is not limited thereto.

[0109] Another embodiment of the present application provides a multi-host access control device, which is used to execute the multi-host access control method provided by the above embodiment.

[0110] like Figure 4 4 is a schematic diagram of the structure of a multi-host access control device provided in an embodiment of the present application. The multi-host access control device includes a receiving module 401, an arbitration module 402, a determination module 403 and an access module 404, wherein:

[0111] The receiving module 401 is used to receive transmission requests sent by multiple hosts;

[0112] The arbitration module 402 is used to perform arbitration on multiple hosts and determine the priority information of each host;

[0113] The determination module 403 is used to determine the host with the highest priority information as the first host, control the first host to access the slave, and save the access information of the second host in the cache space corresponding to the second host;

[0114] The access module 404 is used to control the second host to access the slave according to the access information of the second host in the cache space when the first host completes access to the slave.

[0115] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0116] Some embodiments of the present application add a corresponding cache mechanism to the host with a low arbitration priority in the system. When the host with a high priority completes the access to the slave, the host with a low priority is able to access the slave according to the cache mechanism. In this way, the access of the low-priority host will not be lost, and access to the slave by a specific host is fairer.

[0117] Another embodiment of the present application further supplements the multi-host access control device provided in the above embodiment.

[0118] Optionally, the access module is used to:

[0119] Obtaining a write pointer and a read pointer in the cache space, wherein the write pointer is determined according to the number of received transmission requests, and the read pointer is determined according to the number of accesses to the cache space;

[0120] After the first host completes the access, the cache controller read pointer starts to increase, and the access information of the second host in the cache space is read out through the read pointer to access the slave;

[0121] When the read pointer increases to be equal to the write pointer, the second host completes access to the slave according to the access information of the second host.

[0122] Some embodiments of the present application judge the write pointer and the read pointer, and control the second host to access the slave according to the access information of the second host in the cache space each time, thereby improving the accuracy of the access control of the low-priority host. When the read pointer and the write pointer are equal, the FIFO becomes empty and the access is completed.

[0123] Optionally, the access information of the second host includes at least a host address and a control signal.

[0124] Some embodiments of the present application implement access of the second host to the slave by storing the access information of the second host in a cache space for subsequent acquisition of the host address and control signal from the cache space.

[0125] Optionally, the access module is used to:

[0126] Receive the feedback signal sent by the slave;

[0127] According to the feedback signal, it is determined that the access of the first host to the slave is completed.

[0128] In some embodiments of the present application, after the high-priority host completes access to the slave,

[0129] Optionally, the access module is used to:

[0130] Each time a host is added, a cache space corresponding to the host is added.

[0131] Some embodiments of the present application increase the cache space corresponding to the host in real time according to the number of low-priority hosts, so that the memory space can be effectively utilized and the waste of memory space can be avoided.

[0132] Optionally, in the case where there are multiple cache spaces, the access module is used to:

[0133] Priority decoding is performed on each cache space respectively to obtain decoding information corresponding to the cache space;

[0134] The cache space is read according to the decoding information.

[0135] Some embodiments of the present application can increase corresponding cache space for multiple hosts in the system and for low-priority hosts. When multiple cache spaces cache information of multiple hosts, priority decoding is required to access the slaves.

[0136] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0137] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any manner without conflict, and this application is not limited thereto.

[0138] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the multi-host access control method provided in the above embodiments can be implemented.

[0139] An embodiment of the present application also provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations of the method corresponding to any embodiment of the multi-host access control method provided in the above embodiments.

[0140] like Figure 5 As shown, some embodiments of the present application provide an electronic device 500, which includes: a memory 510, a processor 520, and a computer program stored in the memory 510 and executable on the processor 520, wherein the processor 520 can implement any of the embodiments of the multi-host access control method as described above when reading the program from the memory 510 through a bus 530 and executing the program.

[0141] Processor 520 can process digital signals and can include various computing structures, such as complex instruction set computer structure, reduced instruction set computer structure, or a structure that implements a combination of multiple instruction sets. In some examples, processor 520 can be a microprocessor.

[0142] The memory 510 may be used to store instructions executed by the processor 520 or data related to the execution of instructions. These instructions and / or data may include codes for implementing some or all functions of one or more modules described in the embodiments of the present application. The processor 520 of the disclosed embodiment may be used to execute instructions in the memory 510 to implement the method shown above. The memory 510 includes a dynamic random access memory, a static random access memory, a flash memory, an optical memory, or other memory known to those skilled in the art.

[0143] The above are only embodiments of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0145] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A multi-host access control method, characterized in that: The method comprises: Receive transmission requests sent by multiple hosts; Performing arbitration on the multiple hosts to determine priority information of each host; Determine the host with the highest priority information as the first host, control the first host to access the slave, and save the access information of the second host in the cache space corresponding to the second host; When the first host completes access to the slave, the second host is controlled to access the slave according to the access information of the second host in the cache space.

2. The multi-host access control method according to claim 1, characterized in that: After the first host completes accessing the slave, controlling the second host to access the slave according to the access information of the second host in the cache space includes: Obtaining a write pointer and a read pointer in the cache space, wherein the write pointer is determined according to the number of received transfer requests, and the read pointer is determined according to the number of accesses to the cache space; After the first host completes the access, the cache controller read pointer starts to increase, and the access information of the second host in the cache space is read out through the read pointer to access the slave; When the read pointer increases to be equal to the write pointer, the second host completes access to the slave according to the access information of the second host.

3. The multi-host access control method according to claim 1, characterized in that: The access information of the second host includes at least a host address and a control signal.

4. The multi-host access control method according to claim 1, characterized in that: The first host completes access to the slave, including: The first host no longer issues a request and receives a feedback signal sent by the slave; It is determined, according to the feedback signal, that the access of the first host to the slave is completed.

5. The multi-host access control method according to claim 1, characterized in that: The method further comprises: Each time a host is added, a cache space corresponding to the host is added.

6. The multi-host access control method according to claim 5, characterized in that: In the case where there are multiple cache spaces, the method further includes: Performing priority decoding on each cache space respectively to obtain decoding information corresponding to the cache space; The cache space is read according to the decoding information.

7. A multi-host access control device, characterized in that: The device comprises: A receiving module, used for receiving transmission requests sent by multiple hosts; An arbitration module, used to perform arbitration processing on the multiple hosts and determine the priority information of each host; A determination module, configured to determine the host with the highest priority information as the first host, control the first host to access the slave, and save the access information of the second host in a cache space corresponding to the second host; The access module is used to control the second host to access the slave according to the access information of the second host in the cache space when the first host completes access to the slave.

8. The multi-host access control device according to claim 7, characterized in that: The access module is used to: Obtaining a write pointer and a read pointer in the cache space, wherein the write pointer is determined according to the number of received transfer requests, and the read pointer is determined according to the number of accesses to the cache space; After the first host completes the access, the cache controller read pointer starts to increase, and the access information of the second host in the cache space is read out through the read pointer to access the slave; When the read pointer increases to be equal to the write pointer, the second host completes access to the slave according to the access information of the second host.

9. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the multi-host access control method as described in any one of claims 1 to 6 when executing the program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the program, when executed by a processor, can implement the multi-host access control method described in any one of claims 1 to 6.

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