Computer system and method for accessing data of a computer system

Abstract

The present invention discloses a computer system and a data access method for the computer system, belonging to the field of storage technology. The computer system includes: an external request source that issues read requests and write-back requests; a write-back cache module that receives the read requests and write-back requests issued by the external request source; a Cache module that receives prefetch requests and the write-back requests, and writes the data read by the prefetch requests into the write-back cache module; and a main memory that receives the data updated by the Cache module and performs data updates. The computer system of the present invention ensures that the data blocks in the write-back cache are always the latest, can reduce the write-back waiting time during actual Cache access, perform necessary data updates and synchronization operations in advance, and improve the data processing efficiency of the entire system.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and particularly to a computer system and a data access method for a computer system. Background Art

[0002] In modern computer systems, cache technology is used to improve data access speed and reduce overall system latency. The basic working principle of a cache is to temporarily store frequently used data in a fast and small-capacity storage area so that these data can be obtained more quickly during subsequent accesses. However, when the same data is accessed multiple times before the write-back is completed, to ensure data consistency, further access to this data must be blocked until the write-back ends. Although this method ensures data consistency, it greatly affects the access efficiency of the external request source to the cache, resulting in a decline in the overall system performance. Therefore, there is an urgent need for a computer system and a data access method for a computer system that can both ensure the consistency between the data in the cache and the data in the main memory and significantly improve the cache access efficiency to meet the growing demands of modern computer systems. Summary of the Invention

[0003] The purpose of this application is to overcome the defects of the prior art and provide a computer system and a data access method for a computer system.

[0004] In a first aspect, this application provides a computer system, including:

[0005] An external request source that issues read requests and write-back requests;

[0006] A write-back cache module that receives the read requests and the write-back requests issued by the external request source and temporarily stores the write-back requests;

[0007] A cache module that receives prefetch requests and the write-back requests and writes the data read by the prefetch requests into the write-back cache module;

[0008] A main memory that receives the data updated by the cache module and updates the data.

[0009] Optionally, the write-back cache module includes:

[0010] A write-back cache unit that stores the data read by the prefetch requests from the cache module and the data written back by the write-back requests;

[0011] A write-back cache control logic unit that coordinates the interaction between the write-back cache unit and the cache module and the external request source.

[0012] Optionally, the cache module includes:

[0013] The Cache cache unit stores the data read from the main memory and the updated data in the write-back request;

[0014] The Cache control logic unit coordinates the interaction between the Cache cache unit, the write-back cache module, and the external request source.

[0015] Optionally, the Cache control logic unit includes:

[0016] The prefetch request interface receives and forwards the prefetch request issued by the external request source;

[0017] The write-back request interface receives and forwards the write-back request issued by the external request source;

[0018] The prefetch request cache subunit receives and stores the prefetch request forwarded by the prefetch request interface;

[0019] The write-back cache subunit receives and stores the write-back request forwarded by the write-back request interface;

[0020] The arbitration subunit receives the prefetch request stored in the prefetch request cache subunit and the write-back request stored in the write-back cache subunit, performs arbitration operations, and outputs read enable signals for the prefetch request cache subunit and the write-back cache subunit.

[0021] Optionally, the write-back cache control logic unit includes:

[0022] The read request interface receives and forwards the read request issued by the external request source;

[0023] The read Cache ACK write interface receives the data sent by the Cache control logic unit and inputs the data into the write-back cache unit;

[0024] The read Cache REQ write interface receives the read request forwarded by the prefetch request interface and inputs the read request into the write-back cache unit;

[0025] The write-back interface receives the write-back request forwarded by the write-back request interface and inputs the write-back request into the write-back cache unit;

[0026] The read data interface receives the read request forwarded by the read request interface, reads data from the write-back cache unit, and returns it to the external request source.

[0027] Second aspect, the present application also provides a data access method for a computer system. The data access method for the computer system is executed based on the computer system, and the data access method for the computer system includes the following steps:

[0028] Write frequently used data from the Cache module to the write-back cache module through a prefetch operation;

[0029] The external request source issues a request;

[0030] When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If so, return the data read from the write-back cache unit;

[0031] If not, read data from the Cache module through the prefetch operation and write the data read from the Cache module to the write-back cache module;

[0032] When the request is a write-back request, input the write-back request into the Cache module to perform a write-back operation on the Cache module, and input the write-back request into the write-back cache module to perform a write-back on the write-back cache module.

[0033] Optionally, writing frequently used data from the Cache module to the write-back cache module through a prefetch operation includes:

[0034] Store the prefetch request into the prefetch request cache subunit through the prefetch request interface;

[0035] The arbitration subunit receives the prefetch request from the prefetch request cache subunit and performs an arbitration operation, outputting a read enable signal for the prefetch request cache subunit;

[0036] Input the prefetch request into the Cache module for prefetch operation based on the read enable signal for the prefetch request cache subunit;

[0037] When the Cache module finishes the prefetch operation, output a determination signal indicating the completion of the prefetch operation and write the prefetched data to the write-back cache module.

[0038] Optionally, the "if not, read data from the Cache module through the prefetch operation and write the data read from the Cache module to the write-back cache module" includes:

[0039] When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If not, perform a prefetch operation on the Cache module;

[0040] Store the prefetch request into the prefetch request cache subunit through the prefetch request interface;

[0041] The arbitration subunit receives data from the prefetch request cache subunit, performs an arbitration operation, and outputs a read enable signal for the prefetch request cache subunit;

[0042] Input the prefetch request in the prefetch request cache subunit into the Cache module for prefetch operation based on the read enable signal for the prefetch request cache subunit;

[0043] When the Cache module finishes processing the prefetch operation, output the determination signal indicating the completion of the prefetch operation, and write the prefetched data into the write-back cache module;

[0044] The status of the write-back cache subunit becomes readable, input the read request from the entrance of the prefetch request cache subunit into the write-back cache module, perform a read operation on the write-back cache module, and return the read data.

[0045] Optionally, when the request is a write-back request, input the write-back request into the Cache module, perform a write-back operation on the Cache module, and input the write-back request into the write-back cache module to perform a write-back on the write-back cache module, including:

[0046] When the request is a write-back request, store the write-back request into the write-back cache subunit through the write-back request interface;

[0047] The arbitration subunit receives the write-back request from the write-back cache subunit, performs an arbitration operation, and outputs a read enable signal for the write-back cache subunit;

[0048] Input the write-back request in the write-back cache subunit into the Cache module for write-back based on the read enable signal for the write-back cache subunit, and update the data in the main memory;

[0049] Input the write-back request into the write-back cache unit through the write-back interface to perform a write-back on the write-back cache unit.

[0050] Optionally, the arbitration operation includes: setting the absolute priority of the write-back request.

[0051] The present application provides a computer system and a data access method for the computer system. Through a write-back request cache and a reasonable arbitration mechanism, it can ensure the absolute priority processing of write-back requests, avoiding subsequent access blockages caused by untimely data write-back. By prefetching relevant data into the write-back cache module for temporary storage through a prefetch operation, it can reduce the write-back waiting time during access. Performing read and write operations on the Cache module and simultaneously performing synchronous read and write operations on the write-back cache module can ensure the timely update and consistency of data, and can also avoid unnecessary data update operations, improving the utilization rate of system resources and ensuring data consistency.

[0052] To make the above features and advantages of the invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] To more clearly illustrate the technical solutions in the embodiments of the present application or in related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0054] Figure 1 It is a schematic structural diagram of the computer system provided in an embodiment of the present application.

[0055] Figure 2 It is a schematic internal structure diagram of the write-back cache control logic unit and the Cache control logic unit in the computer system provided in an embodiment of the present application.

[0056] Figure 3 It is a flowchart of the data access method of the computer system provided in an embodiment of the present application.

[0057] Figure 4 It is a flowchart of step S10 in the data access method of the computer system provided in an embodiment of the present application.

[0058] Figure 5 It is a flowchart of step S40 in the data access method of the computer system provided in an embodiment of the present application.

[0059] Figure 6 It is a flowchart of step S50 in the data access method of the computer system provided in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0060] To make the objectives and technical solutions of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions of the embodiments of this application with reference to the accompanying drawings of the embodiments of this application. Apparently, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of this application without creative efforts shall fall within the scope of protection of this application.

[0061] As Figure 1 shown, this application provides a computer system, including: an external request source 10, a write-back cache module 20, a Cache module 30, and a main memory 40. The external request source 10 issues read requests and write-back requests; the write-back cache module 20 receives the read requests and write-back requests issued by the external request source 10; the Cache module 30 receives prefetch requests and write-back requests, and writes the data read by the prefetch requests into the write-back cache module 20; the main memory 40 is used to store all data, receives the data updated by the Cache module 30, and performs data update and replacement; the write-back cache module 20 includes: a write-back cache unit 21 and a write-back cache control logic unit 22. The write-back cache unit 21 is used to store the data read from the Cache module 30 by the prefetch requests and the data written back by the write-back requests; the write-back cache control logic unit 22 is used to coordinate the interaction between the write-back cache unit 21 and the Cache module 30 and the external request source 10; the Cache module 30 includes a Cache cache unit 31 and a Cache control logic unit 32. The Cache cache unit 31 is used to store the data read from the main memory 40 and the data updated in the write-back requests; the Cache control logic unit 32 is used to coordinate the interaction between the Cache cache unit 31 and the write-back cache module 20 and the external request source 10.

[0062] Specifically, the Cache control logic unit 32 receives a prefetch request sent by an external request source and transfers it to the Cache buffer unit 31. The Cache buffer unit 31 performs a prefetch operation. After the prefetch operation is completed, the Cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the prefetch operation to the write-back cache module 20. The write-back cache control logic unit 22 receives the confirmation signal cache ack and writes the data read from the Cache buffer unit 31 into the write-back cache unit 21 for temporary storage. The above prefetch operation is repeated to write frequently used data from the Cache buffer unit 31 into the write-back cache unit 21 for temporary storage. By writing frequently used data from the Cache buffer unit 31 into the write-back cache unit 21 for temporary storage, when subsequent read requests need this data, they can directly obtain it from the write-back cache unit 21, avoiding the delay caused by waiting for the write-back operation to complete when reading from the Cache buffer unit 31 and reducing the access time of subsequent read requests.

[0063] Further, when the external request source 10 sends a read request, the write-back cache control logic unit 22 receives the read request and checks whether there is data readable in the write-back cache unit 21. If so, a read operation is performed on the write-back cache unit 21, and the data read from the write-back cache unit 21 is returned to the external request source 10.

[0064] Further, when the external request source 10 sends a read request, the write-back cache control logic unit 22 receives the read request and checks whether there is data readable in the write-back cache unit 21. If not, a prefetch operation is performed on the Cache module 30. The Cache control logic unit 32 receives the prefetch request and performs a prefetch operation on the Cache buffer unit 31 to read the data stored in the Cache buffer unit 31. After the prefetch operation is completed, the Cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the prefetch operation to the write-back cache module 20. The write-back cache control logic unit 22 receives the confirmation signal cache ack and writes the data read from the Cache buffer unit 31 into the write-back cache unit 21. At this time, the status of the write-back cache unit 21 becomes having data readable, that is, the bitmap of the write-back cache unit 21 becomes high. The write-back cache control logic unit 22 receives the read request sent by the external request source 10, performs a read operation on the write-back cache unit 21, reads the data from the write-back cache unit 21, and returns it to the external request source 10.

[0065] Further, when the external request source 10 issues a write-back request, the Cache control logic unit 32 receives the write-back request and performs a write-back operation on the Cache cache unit 31, writing the write-back data into the Cache cache unit 31 to replace the original stored data and updating the data in the main memory 40. At the same time, the write-back cache control logic unit 22 also receives the write-back request and performs a write-back operation on the write-back cache unit 21 to achieve synchronous data update.

[0066] It should be noted that the prefetch request and the read request are the same request. When there is no data in the write-back cache module 20 before the system is started, it is necessary to first prefetch the data in the Cache module 30 and write it into the write-back cache module 20. At this time, the read request is the prefetch request. When there is data in the write-back cache module 20, the subsequent incoming read requests can directly hit in the write-back cache module 20 and directly read out the data. If not, they can hit in the Cache module 30 through the prefetch request, read out the data, and write the read data into the write-back cache module 20 for temporary storage.

[0067] As an example, please refer to Figure 2 , the Cache control logic unit 32 includes: a prefetch request interface 324 that receives and transfers the prefetch request issued by the external request source 10; a write-back request interface 325 that receives and transfers the write-back request issued by the external request source 10; a prefetch request cache subunit 321 that receives and stores the prefetch request transferred by the prefetch request interface 324; a write-back cache subunit 322 that receives and stores the write-back request transferred by the write-back request interface 325; an arbitration subunit 323 that receives the data stored in the prefetch request cache subunit 321 and the write-back cache subunit 322 and performs an arbitration operation. The arbitration subunit 323 gives absolute priority to the write-back request. The request sources of the arbitration subunit 323 are the non-empty signals of the prefetch request cache subunit 321 and the non-empty signal of the write-back cache subunit 322. The arbitration subunit 323 generates signals as the read enable signal of the prefetch request cache subunit 321 and the read enable signal of the write-back cache subunit 322 respectively, and transfers the prefetch request of the prefetch request cache subunit 321 and the write-back request of the write-back cache subunit 322 to the Cache cache unit 31.

[0068] As an example, the write-back cache control logic unit 22 includes: a read request interface 221 that receives a read request issued by an external request source 10 and forwards it; a read Cache ACK write interface 222 that receives a confirmation signal cache ack issued by the Cache control logic unit 32 and inputs the data pre-read from the Cache cache unit 31 into the write-back cache unit 21; a read Cache REQ write interface 223 that receives the read request forwarded by the pre-read request interface 324 and inputs the read request into the write-back cache unit 21; a write-back interface 224 that receives the write-back request forwarded by the write-back request interface 325 and inputs the write-back request into the write-back cache unit 21; a read data interface 225 that receives the read request forwarded by the read request interface 221, reads data from the write-back cache unit 21, and returns it to the external request source 10.

[0069] Specifically, when the pre-read request interface 324 receives a pre-read request issued by an external request source, it inputs the pre-read request into the pre-read request cache sub-unit 321 for temporary storage and issues a non-empty signal for the pre-read request. The arbitration sub-unit 323 receives the non-empty signal and the pre-read request stored in the pre-read request cache sub-unit 321, performs an arbitration operation. When arbitrating, the write-back request is set to be absolutely prioritized, and requests of the same type are arranged in chronological order. Then, a read enable signal for the pre-read request cache sub-unit 321 is output, and the Cache cache unit 31 performs a pre-read operation. When the pre-read operation is completed, the Cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the pre-read operation to the write-back cache module 20. The read Cache ACK write interface 222 of the write-back cache module 20 receives the confirmation signal cache ack and writes the data pre-read from the Cache cache unit 31 into the write-back cache unit 21 for temporary storage.

[0070] Further, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether there is data readable in the write-back cache unit 21. If so, the read request interface 221 forwards the read request to the read data interface 225. The read data interface 225 receives the read request, reads data from the write-back cache unit 21, and returns it to the external request source 10.

[0071] Further, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether there is data readable in the write-back cache unit 21. If not, a prefetch operation is performed on the Cache module 30. The prefetch request interface 324 receives the prefetch request and inputs the prefetch request into the prefetch request cache sub-unit 321. The prefetch request cache sub-unit 321 receives the prefetch request and outputs a non-empty signal of the prefetch request. The arbitration sub-unit 323 receives the non-empty signal and performs an arbitration operation. When arbitrating, the write-back request is set to have absolute priority, and requests of the same type are arranged in chronological order, and a read enable signal for the prefetch request cache sub-unit 321 is output. The Cache cache unit 31 performs a prefetch operation. When the prefetch operation is completed, the Cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the prefetch operation to the write-back cache module 20. The read Cache ACK write interface 222 of the write-back cache module 20 receives the confirmation signal cache ack and writes the data prefetched from the Cache cache unit 31 into the write-back cache unit 21. At this time, the write-back cache unit 21 becomes readable, that is, the bitmap of the write-back cache unit 21 becomes high. The read request interface 221 conveys the read request to the read data interface 225. The read data interface 225 receives the read request, reads data from the write-back cache unit 21, and returns it to the external request source 10.

[0072] Further, when the external request source 10 issues a write-back request, the write-back request interface 325 receives the write-back request and inputs the write-back request into the write-back cache sub-unit 322. The write-back cache sub-unit 322 receives the write-back request and outputs a write-back request non-empty signal. The arbitration sub-unit 323 receives the non-empty signal and performs an arbitration operation. When arbitrating, the write-back request is set to have absolute priority, and requests of the same type are arranged in chronological order. Then, a read enable signal for the write-back cache sub-unit 322 is output. The Cache cache unit 31 writes the data into the write-back cache sub-unit 322, replaces the original stored data, and updates the data in the main memory 40. At the same time, the write-back interface 224 also receives the write-back request and performs a write-back operation on the write-back cache unit 21 to achieve data update and replacement. Through the prefetch operation, the data that may be needed in the future is prefetched into the write-back cache module 20 in advance, so that the data can be obtained more quickly during subsequent data access, reducing the delay caused by waiting for the data to be loaded from the main memory to the Cache module 30 and improving the overall speed of data access. For read requests, when there is data readable in the write-back cache module 20, the data can be directly read from the write-back cache module 20 and returned to the external request source 10, avoiding unnecessary access to the Cache module 30 and further shortening the data acquisition time. Even if there is no data readable in the write-back cache module 20, the subsequent prefetch operation can quickly replenish the data and maintain an efficient read process. In the scenario of multi-task concurrency and frequent data read and write, this mechanism can effectively reduce the waiting time between tasks and improve the overall throughput of the system. Setting the write-back request to have absolute priority in the arbitration sub-unit 323 ensures that the write-back operation is completed before any read operation, avoiding data inconsistency problems caused by incomplete write-back. The Cache module 30 sends a confirmation signal cache ack indicating the completion of the prefetch operation to the write-back cache module 20. The read Cache ACK write interface 222 receives it and writes the relevant data into the write-back cache unit 21, which enables the data in the write-back cache unit 21 to be updated in a timely manner and kept synchronized with the data in the Cache cache unit 31, further ensuring the consistency of data between different storage levels.

[0073] As an example, the prefetch request may include: a prefetch request enable signal, a prefetch identifier KEY, a prefetch tag TAG, etc.

[0074] As an example, the read request may include: a read request enable signal, a read identifier KEY, a read tag TAG, etc.

[0075] As an example, the write-back request may include: a write-back request enable signal, a write-back identifier KEY, a write-back data Cacheline, a write-back control bit MASK, and other data.

[0076] As an example, the determination signal cache ack for the completion of the prefetch operation may include: a determination signal cacheack enable signal, an ACK_TAG signal, an ACK data signal, etc.

[0077] As an example, the write-back cache unit 21 includes multiple specific random access memories SPEC_RAM, all of which use parametric design, can meet different specifications of the Cache, and for Caches with different delay sizes, the expected depth is configurable, achieving a read-write pipeline, thereby ensuring the consistency of data in the Cache.

[0078] As an example, the write-back cache module 20 may include n specific random access memories SPEC_RAM.

[0079] As an example, the write-back cache module 20 can be built through internal registers, can have 3 write interfaces and 1 read interface, support the storage of data Cacheline, identification KEY, control bit MASK, read requests, write-back request flags, and implement data storage, matching, and replacement.

[0080] As an example, the tag TAG of the read and write request ports of the write-back cache module 20 is the serial number of the specific random access memory SPEC_RAM.

[0081] As an example, the specific random access memory SPEC_RAM can store data, identification KEY, control bit MASK, read requests, write-back requests, etc., support the comparison and replacement of data by the identification KEY, support write-back according to the control bit MASK being high, support the return of the Cache determination signal cache ack data and write it into the specific random access memory SPEC_RAM according to the control bit MASK being low, and the read interface can return data immediately in the current cycle.

[0082] As an example, the prefetch request cache sub-unit 321 is a first-in-first-out FIFO. The depth of the prefetch request cache sub-unit 321 can be set to n, and the size of n can be set according to the access delay of the Cache in different application scenarios, achieving a read-write pipeline, thereby masking the Cache access delay and ensuring that n read requests REQ can be cached simultaneously. When there is data in the prefetch request cache sub-unit 321, that is, there are unprocessed prefetch requests, the arbitration sub-unit 323 receives the non-empty signal of the prefetch request cache sub-unit 321 and performs arbitration operations. When arbitrating, the write-back request is set to have absolute priority, and requests of the same type are arranged in chronological order.

[0083] As an example, the write-back cache sub-unit 322 can be a special first-in-first-out FIFO built using registers, stores data in a first-in-first-out manner, and all cached data is output to the port.

[0084] As an example, the depth of the write-back cache subunit 322 can be 4, and the write-back cache subunit 322 can use the first register REG0, the second register REG1, the third register REG2, and the fourth register REG3 to store and process data.

[0085] As an example, all the data cached by the write-back cache subunit 322 can be output to the port. Since the arbitration subunit 323 at the subsequent stage gives absolute priority to write-back, the depth of the write-back cache subunit 322 can be set relatively small.

[0086] As an example, the arbitration subunit 323 gives absolute priority to write-back, always ensuring that the write-back is completed first before reading, so as to ensure the data consistency inside the Cache.

[0087] As an example, the external request source 10 may include a CPU, a GPU, an I / O device, other hardware accelerators, etc. Among them, the I / O device may include a network interface card, a hard disk controller, etc., and other hardware accelerators may include an encryption / decryption accelerator, a video codec, etc. Its specific type and function depend on the architecture and application scenario of the computer system.

[0088] In the above computer system, through the prefetch request interface 324, the data that may be needed can be read from the Cache cache unit 31 in advance and temporarily stored in the write-back cache unit 21, reducing the access time of subsequent read requests and improving the data access efficiency; through the write-back absolute priority strategy of the arbitration subunit 323, it can ensure that the write-back operation is completed first and then the read operation is performed, preventing data conflicts; the write-back cache unit 21 performs data storage, matching, and replacement, which can improve the access efficiency of the Cache, ensure the data consistency inside the Cache, reduce the performance loss caused by data consistency maintenance, and improve the overall system operation efficiency.

[0089] In another embodiment, please refer to Figure 3 , the present application provides a data access method for a computer system. The data access method for the computer system is executed based on the above computer system, and the data access method for the computer system may include the following steps: S10~S50.

[0090] S10: Write the frequently used data from the Cache module to the write-back cache module through a prefetch operation.

[0091] S20: The external request source issues a request.

[0092] S30: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If so, return the data read from the write-back cache unit.

[0093] S40: If not, read data from the Cache module through a prefetch operation and write the read data into the write-back cache module.

[0094] S50: When the request is a write-back request, input the write-back request into the Cache module to perform a write-back operation on the Cache module, and input the write-back request into the write-back cache module to perform a write-back operation on the write-back cache module.

[0095] In the data access method of the computer system of the present application, frequently used data is prefetched from the Cache module through a prefetch operation and stored in the write-back cache module, which can reduce the latency of subsequent reads of this data, improve the data read speed and the overall system performance, and prepare for subsequent data access operations of the system; when a read request is received, directly read data from the write-back cache module, and when there is no data to read, prefetch and supplement data from the Cache module to improve the data read speed; when a write-back request is received, perform a write-back operation on both the Cache module and the write-back cache module to ensure data update consistency, thereby optimizing the data access performance and data storage consistency of the system, reducing data access latency, and improving the overall response speed and operation efficiency of the system.

[0096] In step S10, please refer to Figure 3 step S10 in

[0097] As an example, please refer to Figure 4 , step S10 may include the following steps: S11~S14.

[0098] S11: Store the prefetch request into the prefetch request cache subunit through the prefetch request interface.

[0099] S12: The arbitration subunit receives data from the prefetch request cache subunit and performs an arbitration operation, outputting a read enable signal for the prefetch request cache subunit.

[0100] S13: Input the prefetch request into the Cache module for a prefetch operation based on the read enable signal for the prefetch request cache subunit.

[0101] S14: When the Cache module finishes the prefetch operation, output a signal indicating the completion of the prefetch operation and write the signal into the write-back cache module.

[0102] Specifically, in step S11, the prefetch request interface 324 receives the prefetch request and inputs it into the prefetch request cache subunit 321, and the prefetch request cache subunit 321 caches the data in the prefetch request.

[0103] As an example, the data cached in the prefetch request cache subunit 321 may include frequently accessed read requests, identification KEYs, tags TAGs, etc.

[0104] Further, in step S12, the arbitration subunit 323 detects a non-empty signal of the prefetch request cache subunit 321, indicating that there is an unprocessed prefetch request in the prefetch request cache subunit 321. The arbitration subunit 323 receives the prefetch request from the prefetch request cache subunit 321 and makes a decision according to the set write-back absolute priority rule, and outputs a read enable signal for the prefetch request cache subunit 321.

[0105] Further, in step S13, after the prefetch request cache subunit 321 receives the read enable signal output by the arbitration subunit 323, the prefetch request cached in the prefetch request cache subunit 321 is input to the Cache cache unit 31 for prefetch operation.

[0106] As an example, the prefetch requests output by the prefetch request cache subunit 321 may include a read request enable signal, a read tag TAG signal, a read identification KEY signal, etc.

[0107] As an example, the read tag TAG can be read from the prefetch request cache subunit 321. This tag TAG is used to identify and locate the data block to be read in the Cache cache unit 31 to ensure that the data can be read accurately.

[0108] Further, in step S14, when the Cache cache unit 31 of the Cache module 30 finishes processing the read operation, the Cache control logic unit 32 delivers the determined signal cache ack for the completed read operation to the read Cache ACK interface 222, and writes the data read from the Cache cache unit 31 into the write-back cache unit 21 in the write-back cache module 20 through the read Cache ACK interface 222.

[0109] Specifically, when the Cache control logic unit 32 returns the determined signal cache ack enabled and the returned tag TAG is consistent with the sequence number NUM of the specific random access memory SPEC_RAM, if the WB flag in the specific random access memory SPEC_RAM is 0 at this time, the read RD flag is set to 1, the valid VLD flag is set to 1, and the write WB flag is set to 0. All the data Cachelines returned by the Cache control logic unit 32 are written into the corresponding data Cachelines in the write-back cache unit 21. And the bitmap at the corresponding position in the write-back cache unit 21 is set to valid, and the bitmap is set to high, indicating that the data Cacheline already exists in the write-back cache unit 21.

[0110] As an example, the determination signal cache ack may include an ACK enable signal, an ACK_TAG signal, an ACK data signal, etc.

[0111] As an example, the determination signal cache ack written to the write-back cache unit 21 may be one clock cycle later than the determination signal cache ack returned by the Cache control logic unit 32.

[0112] In step S20, refer to Figure 3 step S20 in

[0113] As an example, the external request source 10 may issue multiple requests, including n read requests and n write-back requests.

[0114] As an example, the external request source 10 may include a CPU, a GPU, an I / O device, other hardware accelerators, etc. Among them, the I / O device may include a network interface card, a hard disk controller, etc., and other hardware accelerators may include encryption and decryption accelerators, video codecs, etc. Its specific type and function depend on the architecture and application scenario of the computer system.

[0115] In step S30, refer to Figure 3 step S30 in

[0116] As an example, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether the corresponding bitmap in the write-back cache unit 21 in the write-back cache module 20 is high. If so, the read request interface 221 of the write-back cache module 20 receives the read request and passes it to the read data interface 225. The read data interface 225 locates the position of the read request in the write-back cache unit 21 according to the read tag TAG and the identifier KEY of the read request, performs the operation of reading the write-back cache unit 21, and returns the read data.

[0117] As an example, it is necessary to initiate the operation of reading the write-back cache unit 21 when the bitmap of the corresponding write-back cache unit 21 is high. The operation of reading the write-back cache unit 21 needs to carry a tag TAG, and the data of which write-back cache unit 21 is read is matched through the tag TAG. The operation of reading the write-back cache unit 21 supports out-of-order reading, and the reading order is controlled by the tag TAG of the external request source 10.

[0118] Specifically, when the write-back cache unit 21 receives the read request REQ enable signal, and the read tag TAG is the same as the serial number NUM of the specific random access memory SPEC_RAM, and the read identifier KEY is the same as the identifier KEY in the specific random access memory SPEC_RAM, that is, when both the tag TAG and the identifier KEY of the read request match, set the read RD flag to 1, the valid VLD / write WB flag to 0, write the identifier KEY of the read request REQ, and keep other fields unchanged.

[0119] As an example, when the write-back cache unit 21 receives the read request REQ enable signal, and the read tag TAG is the same as the serial number NUM of the specific random access memory SPEC_RAM, but the read identifier KEY is different from the identifier KEY in the specific random access memory SPEC_RAM, that is, when the tag TAG of the read request matches but the identifier KEY does not match, set the read RD flag to 1, the valid VLD / write WB flag to 0, write the identifier KEY of the read request REQ, and keep other fields unchanged.

[0120] Among them, read RD is used to indicate whether there has been a previous read operation on this data. When the read RD flag bit is 1, it means there has been a previous read operation on this data; when the read RD flag bit is 0, it means there has been no previous read operation on this data. Write WB is used to indicate whether there has been a previous write operation on this data. When the write WB flag bit is 1, it means there has been a previous write operation on this data; when the write WB flag bit is 0, it means there has been no previous write operation on this data. Valid VLD is a valid flag bit, used to indicate the validity of the data. When the valid VLD flag bit is 1, it means the relevant data is valid and can be used or processed; when the valid VLD flag bit is 0, it means the data may be invalid or not yet ready. The identifier KEY is used to uniquely identify the data. Each data has a corresponding identifier KEY, and different data can be quickly located and distinguished through the identifier KEY. The control bit MASK is used to control the writing and updating method of the data. It is input by bit, and every 8 bits take the low 1 bit as the control bit MASK signal by byte, combined with other data bits to determine which bytes of data need to be updated and which bytes of data remain unchanged.

[0121] In step S40, please refer to Figure 3 step S40 in, if not, then read data from the Cache module through a prefetch operation, and write the read data into the write-back cache module.

[0122] As an example, please refer to Figure 5 , step S40 may include the following steps: S41~S46.

[0123] S41: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If not, a prefetch operation is performed on the Cache module.

[0124] S42: Store the prefetch request into the prefetch request cache sub-unit through the prefetch request interface.

[0125] S43: The arbitration sub-unit receives the data from the prefetch request cache sub-unit and performs an arbitration operation, outputting a read enable signal for the prefetch request cache sub-unit.

[0126] S44: Input the prefetch request into the Cache module for prefetch operation based on the read enable signal for the prefetch request cache sub-unit.

[0127] S45: When the Cache module finishes the prefetch operation, it outputs a determination signal indicating the completion of the prefetch operation and writes the prefetched data into the write-back cache module.

[0128] S46: The status of the write-back cache module becomes having data readable. The read request is input into the write-back cache module from the entrance of the prefetch request cache sub-unit, a read operation is performed on the write-back cache module, and the read data is returned.

[0129] Specifically, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether the corresponding bitmap in the write-back cache unit 21 of the write-back cache module 20 is high. If not, a prefetch operation is performed on the Cache module 30. The prefetch request interface 324 receives the prefetch request and inputs it into the prefetch request cache subunit 321. The prefetch request cache subunit 321 caches the data in the prefetch request and issues a non-empty signal for the prefetch request. The arbitration subunit 323 detects the non-empty signal of the prefetch request cache subunit 321, indicating that there is an unprocessed prefetch request in the prefetch request cache subunit 321. The arbitration subunit 323 receives the prefetch request from the prefetch request cache subunit 321 and makes a decision according to the set write-back absolute priority rule, and outputs a read enable signal for the prefetch request cache subunit 321. Since the arbitration subunit 323 gives absolute priority to the write-back request, when the non-empty signals of both the prefetch request cache subunit 321 and the write-back cache subunit 322 are detected simultaneously, the arbitration subunit 323 will give priority to processing the write-back request in the write-back cache subunit 322 to ensure that the data can be written back to the Cache module 30 in time to maintain data consistency. Only when the write-back request processing of the Cache module 30 is completed and the write-back cache subunit 322 is empty, will the arbitration subunit 323 process the prefetch request in the prefetch request cache subunit 321, thus realizing the reasonable scheduling of read requests and write-back requests, avoiding problems caused by data competition and inconsistency, and at the same time improving the efficiency of the entire cache system. After receiving the read enable signal output by the arbitration subunit 323, the prefetch request cache subunit 321 inputs the prefetch request cached in the prefetch request cache subunit 321 into the Cache cache unit 31 for prefetch operation. After the Cache cache unit 31 of the Cache module 30 finishes the prefetch operation, the Cache control logic unit 32 conveys the determined signal cache ack for the completed read operation to the read Cache ACK interface 222, and writes the data prefetched from the Cache cache unit 31 into the write-back cache unit 21 in the write-back cache module 20 through the read Cache ACK interface 222. The bitmap of the write-back cache unit 21 becomes high. The read Cache REQ write interface 223 obtains the read request from the entrance of the prefetch request cache subunit 321 and transmits it to the write-back cache unit 21, performs a read operation on the write-back cache unit 21, and then returns the read data to the external request source 10 through the read data interface 225.

[0130] As an example, the data read can be returned in the next cycle when the write-back cache unit 21 performs a read operation.

[0131] As an example, obtaining the read request from the entrance of the prefetch request cache subunit 321 can directly delay the read request by one cycle from the entrance of the prefetch request cache subunit 321 and enter the write-back replacement RAM.

[0132] As an example, the tag TAG of the read operation is read from the prefetch request cache subunit 321, and the tag TAG is incremented by 1 for each read operation, that is, the tag TAG changes from 0 to n - 1 and then flips back to 0 and starts to change again.

[0133] As an example, when the Cache control logic unit 32 returns the enable signal cache ack and the returned tag TAG is the same as the sequence number NUM of the specific random access memory SPEC_RAM, if the WB flag in the specific random access memory SPEC_RAM is 0 at this time, the read RD flag is set to 1, the valid VLD flag is set to 1, and the write WB flag is set to 0, and all the data Cacheline returned by the Cache control logic unit 32 is written into the data Cacheline at the corresponding position of the write-back cache unit 21; if the write WB flag in the specific random access memory SPEC_RAM is 1 at this time, the read RD flag is set to 1, the valid VLD flag is set to 1, the data Cacheline with the control bit MASK equal to 1 remains unchanged, and the fields with the control bit MASK equal to 0 are modified to the data Cacheline returned by the Cache cache unit 31.

[0134] As an example, when the write-back cache unit 21 receives the enable signal REQ of the read request and the read tag TAG is the same as the sequence number NUM of the specific random access memory SPEC_RAM, and the read identifier KEY is the same as the identifier KEY in the specific random access memory SPEC_RAM, that is, both the tag TAG and the identifier KEY of the read request match, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, and the identifier KEY of the read request REQ is written, and other fields remain unchanged.

[0135] As an example, when the write-back cache unit 21 receives the enable signal REQ of the read request and the read tag TAG is the same as the sequence number NUM of the specific random access memory SPEC_RAM, and the read identifier KEY is not the same as the identifier KEY in the specific random access memory SPEC_RAM, that is, the tag TAG of the read request matches but the identifier KEY does not match, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, and the identifier KEY of the read request REQ is written, and other fields remain unchanged.

[0136] In step S50, please refer to Figure 3In step S50, when the request is a write-back request, input the write-back request into the Cache module to perform a write-back operation on the Cache module, and input the write-back request into the write-back cache module to perform a write-back operation on the write-back cache module.

[0137] As an example, please refer to Figure 6 , step S50 may include the following steps: S51 to S56.

[0138] S51: When the request is a write-back request, store the write-back request into the write-back cache subunit through the write-back request interface.

[0139] S52: The arbitration subunit receives the write-back request from the write-back cache subunit and performs an arbitration operation to output a read enable signal for the write-back cache subunit.

[0140] S53: Based on the read enable signal for the write-back cache subunit, input the write-back request in the write-back cache subunit into the Cache module for write-back and update the data in the main memory.

[0141] S54: Input the write-back request into the write-back cache unit through the write-back interface to perform a write-back on the write-back cache unit.

[0142] As an example, when the external request source 10 issues a write-back request, the write-back request interface 325 receives the write-back request and inputs it to the write-back cache subunit 322. The write-back cache subunit 322 receives the write-back request and outputs a write-back request non-empty signal. The arbitration subunit 323 detects the non-empty signal of the write-back cache subunit 322, indicating that there is an unprocessed write-back request in the write-back cache subunit 322. The arbitration subunit 323 receives the write-back request from the write-back cache subunit 322 and makes a decision according to the set write-back absolute priority rule, and outputs a read enable signal for the write-back cache subunit. Since the arbitration subunit 323 has absolute priority for write-back requests, when the non-empty signals of the prefetch request cache subunit 321 and the write-back cache subunit 322 are detected simultaneously, the arbitration subunit 323 will give priority to processing the write-back request in the write-back cache subunit 322 to ensure that the data can be written back to the Cache module 30 in time to maintain data consistency. Only when the write-back request processing of the Cache module 30 is completed and the write-back cache subunit 322 is empty, the arbitration subunit 323 will process the prefetch request in the prefetch request cache subunit 321, thus realizing a reasonable scheduling of read requests and write-back requests, avoiding problems caused by data competition and inconsistency, and at the same time improving the efficiency of the entire cache system. After receiving the read enable signal output by the arbitration subunit 323, the write-back cache subunit 322 inputs the write-back data cached in the write-back cache subunit 322 to the Cache cache unit 31 for write-back operation and updates the data in the main memory 40. At the same time, the write-back request is directly input to the write-back cache unit 21 through the write-back interface 224 at the entrance of the write-back cache subunit 322 for write-back operation on the write-back cache unit 21.

[0143] Specifically, when the write-back cache unit 21 receives a write-back request, and the identifier KEY of the write-back request is consistent with the identifier KEY of the specific random access memory SPEC_RAM, and the read RD is 1, the write WB flag is set to 1; the control bit MASK signal of the write-back interface 224 is input bit by bit, and the low 1 bit is taken for every 8 bits as the control bit MASK signal by byte. The converted byte control bit MASK signal is logically ORed with the control bit MASK signal stored in the control bit MASK register and written into the control bit MASK signal field; the data field is written into the field where the control bit MASK signal is 1, and other fields remain unchanged.

[0144] As an example, the tag of the write operation is generated by internal logic, and the write-back request may include: a write-back enable signal, a write-back identifier KEY signal, a write-back data Cacheline, a write-back control bit MASK signal, etc.

[0145] Further, it is determined whether there are both a read request and a write-back request. If not, the data read in the write-back cache unit 21 is returned after one clock cycle. If so, it is determined whether the hardware has the write-through ability; when the hardware does not have the write-through ability, the data returned by the write-back cache unit 21 is directly output after one clock cycle; when the hardware has the write-through ability, the data in the write-back cache unit 21 is processed for write-back, and the data after write-back is output.

[0146] Specifically, when the write-back request and the read request data return in the same clock cycle and the hardware does not have the write-through function, the data returned by the write-back cache unit 21 is directly output after one clock cycle without being coupled with the write-back data; when the hardware has the write-through function and the write-back identifier KEY matches the identifier KEY in the write-back cache unit 21, the data returned by the write-back cache unit 21 is returned after one clock cycle and combined with the write-back data according to the write-back control bit MASK.

[0147] As an example, when the control bit MASK is 1, it means that the corresponding byte position needs to be updated with the write-back data, which means that these bytes in the new write-back data contain the new data to be retained, and these new data will overwrite the old data in the corresponding byte position in the write-back cache unit 21, thus realizing the retention of the new data. When the control bit MASK is 0, it means that the data in the corresponding byte position in the write-back cache unit 21 should be retained, that is, not updated, which is equivalent to excluding the possible old data in the corresponding position in the write-back data, and the data is returned by bitwise OR, and the operation result is directly output as the RSP data, and this data is the latest data. Thus, in the data processing process, only the parts that need to be updated after confirmation will be changed, while the other parts remain unchanged, thus maintaining the stability and consistency of the data.

[0148] In one embodiment, when the write-back request and the Cache control logic unit 32 return a valid determination signal cache ack in the same clock cycle and the read RD is 1, it means that in the same clock cycle, there is both a data write-back operation in progress, and at the same time the Cache cache unit 31 has completed the read operation and the Cache control logic unit 32 has returned the determination signal cache ack. The valid VLD / write WB flag is set to 1, the control bit MASK field is the logical OR operation of the write-back control bit MASK and the control bit MASK in the specific random access memory SPEC_RAM, the data Cacheline is written into the specific random access memory SPEC_RAM according to the write-back data Cacheline, and the data Cacheline returned by the Cache cache unit 31 is written back according to the write-back control bit MASK.

[0149] In another embodiment, when the write-back request and the read request REQ are valid in the same cycle and the identification KEY of the write-back request is the same as that of the read request REQ, that is, in the same clock cycle, both a write-back request occurs and a read request is generated, and the identification KEY of the data involved in these two requests is the same. Set the read RD and write WB flags to 1, input the identification KEY of the read request REQ into the specific random access memory SPEC_RAM, perform an OR operation on the control bit MASK field of the write-back request and the control bit MASK in the specific random access memory SPEC_RAM, and write back the data Cacheline of the write-back data and the data Cacheline in the specific random access memory SPEC_RAM according to the control bit MASK of the write-back request.

[0150] In yet another embodiment, when the write-back request and the read request REQ are valid in the same cycle and the identification KEY of the write-back request is different from that of the read request REQ, that is, in the same clock cycle, both a write-back request and a read request exist, but the identification KEY of the data Cacheline targeted by these two operations is different. Set the read RD flag to 1, set the valid VLD / write WB flag to 0, input the identification KEY of the read request REQ into the specific random access memory SPEC_RAM, and keep other fields unchanged.

[0151] As an example, the present application has a special design and arrangement such that there is no situation where the read request REQ and the determination signal cache ack returned by the Cache control logic unit 32 are both valid at the same time, that is, the occurrence of the read request and the event of the Cache cache unit 31 returning the determination signal cache ack after completing the read operation do not occur at the same moment.

[0152] It should be understood that although the steps in the flowchart of the accompanying drawings are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0153] In the data access method of the computer system of the present application, by means of prefetching operations and using the arbitration subunit 323 to ensure write-back priority, data errors caused by untimely write-back are effectively avoided, and the accuracy and integrity of the data are maintained; by finely processing the read and written data, the read data and the written-back data are respectively sent to the write-back cache unit 21, and the determination signal cache ack is properly processed and returned to the Cache control logic unit 32, achieving precise control over the data flow and improving the orderliness of data processing; the parameterized design of the control bit MASK of the write-back cache unit 21 can meet different specifications of the Cache, realize read-write-back pipelining, maintain data consistency, further improve the Cache access efficiency, and meet the diverse requirements of the system.

[0154] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0155] Although the present application has been disclosed above by way of embodiments, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field to which the present application pertains may make some modifications and refinements without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to that defined by the appended patent application scope.

Claims

1. A computer system, characterized in that, The computer system includes: An external request source that issues read requests and write-back requests; A write-back cache module that receives the read requests and the write-back requests issued by the external request source, responds to the read requests by returning the stored data to the external request source, and responds to the write-back requests by performing write-back operations; A Cache module that receives prefetch requests and the write-back requests, and writes the data read from the prefetch requests into the write-back cache module; A main memory that receives the data updated by the Cache module and updates the data; The write-back cache module includes: a write-back cache unit that stores the data read from the Cache module by the prefetch requests and the data written back by the write-back requests; a write-back cache control logic unit that coordinates the interaction between the write-back cache unit and the Cache module and the external request source; The write-back cache unit performs data storage, matching, and replacement; The write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If so, it performs a read operation on the write-back cache unit and returns the data read from the write-back cache unit to the external request source. If not, it performs a prefetch operation on the Cache module; the write-back cache control logic unit receives the confirmation signal that the Cache module has completed the prefetch operation and writes the read data into the write-back cache unit; the write-back cache control logic unit receives the write-back request and performs a write-back operation on the write-back cache unit; The write-back cache unit includes a plurality of random access memories; The Cache module includes: a Cache cache unit that stores the data read from the main memory and the data updated in the write-back requests; a Cache control logic unit that coordinates the interaction between the Cache cache unit and the write-back cache module and the external request source; The Cache control logic unit includes: a prefetch request interface that receives the prefetch requests issued by the external request source and forwards them; a write-back request interface that receives the write-back requests issued by the external request source and forwards them; a prefetch request cache sub-unit that receives and stores the prefetch requests forwarded by the prefetch request interface; a write-back cache sub-unit that receives and stores the write-back requests forwarded by the write-back request interface; an arbitration sub-unit that receives the prefetch requests stored in the prefetch request cache sub-unit and the write-back requests stored in the write-back cache sub-unit, and performs an arbitration operation to output read enable signals for the prefetch request cache sub-unit and the write-back cache sub-unit.

2. The computer system according to claim 1, wherein The write-back cache control logic unit includes: A read request interface that receives the read requests issued by the external request source and forwards them; A read Cache ACK write interface that receives the data sent by the Cache control logic unit and inputs the data into the write-back cache unit; A read Cache REQ write interface that receives the read requests forwarded by the prefetch request interface and inputs the read requests into the write-back cache unit; The write-back interface receives the write-back request passed by the write-back request interface and inputs the write-back request into the write-back cache unit; The read data interface receives the read request passed by the read request interface, reads data from the write-back cache unit, and returns it to the external request source.

3. A data access method for a computer system, characterized in that, The data access method of the computer system is executed based on the computer system described in any one of claims 1 to 2, and includes the following steps: Write frequently used data from the Cache module to the write-back cache module through a prefetch operation, including: storing the prefetch request into the prefetch request cache subunit through the prefetch request interface; the arbitration subunit receives the prefetch request from the prefetch request cache subunit and performs an arbitration operation, outputting a read enable signal for the prefetch request cache subunit; based on the read enable signal for the prefetch request cache subunit, input the prefetch request into the Cache module for prefetch operation; when the Cache module finishes processing the prefetch operation, output a determination signal indicating the completion of the prefetch operation, and write the prefetched data into the write-back cache module; The external request source issues a request; When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If so, directly read the data from the write-back cache unit and return it to the external request source; If not, read data from the Cache module through the prefetch operation and write the read data into the write-back cache module; When the request is a write-back request, input the write-back request into the Cache module to perform a write-back operation on the Cache module, and input the write-back request into the write-back cache module to perform a write-back operation on the write-back cache module.

4. The data access method of the computer system according to claim 3, wherein If not, read data from the Cache module through the prefetch operation and write the read data into the write-back cache module, including: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data readable in the write-back cache unit. If not, perform a prefetch operation on the Cache module; Store the prefetch request into the prefetch request cache subunit through the prefetch request interface; The arbitration subunit receives the data from the prefetch request cache subunit and performs an arbitration operation, outputting a read enable signal for the prefetch request cache subunit; Based on the read enable signal for the prefetch request cache subunit, input the prefetch request into the Cache module for prefetch operation; When the Cache module finishes processing the prefetch operation, output a determination signal indicating the completion of the prefetch operation, and write the prefetched data into the write-back cache module; The state of the write-back cache subunit becomes having data readable, input the read request from the prefetch request cache subunit into the write-back cache module, perform a read operation on the write-back cache module, and return the read data.

5. The data access method of the computer system according to claim 3, characterized in that, When the request is a write-back request, input the write-back request into the Cache module, perform a write-back operation on the Cache module, and input the write-back request into the write-back cache module to perform a write-back operation on the write-back cache module, including: When the request is a write-back request, store the write-back request in the write-back cache subunit through the write-back request interface; The arbitration subunit receives the write-back request from the write-back cache subunit, performs an arbitration operation, and outputs a read enable signal for the write-back cache subunit; Based on the read enable signal for the write-back cache subunit, input the write-back request in the write-back cache subunit into the Cache module for write-back, and update the data in the main memory; Input the write-back request into the write-back cache unit through the write-back interface to perform a write-back operation on the write-back cache unit.

6. The data access method of the computer system according to any one of claims 3 to 5, characterized in that The arbitration operation includes: setting the absolute priority of the write-back request.

Images