Chip and chip control method
By introducing arbitrators, adders and comparators into the chip, the priority of components is reasonably set, and the problems of difficult response and delay of low-priority components in the prior art are solved, and the effect of efficient multi-component communication is achieved.
Patent Information
- Application Number
- CN202411772056.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-05-06
AI Technical Summary
In the case of high-frequency requests, low-priority components are difficult to respond or may cause delays.
A chip is designed, including an arbitrator, adder and comparator. The arbitrator configures the initial priority of the component, the adder determines the communication priority based on the initial priority, the comparator sorts the candidate components, and the arbitrator determines the target components based on the sorting results and controls their communication, and reduces the priority of the target components after communication.
By rationally setting components priorities, simplifying circuits and reducing latency, ensuring that multiple components can communicate.
Smart Images
Figure CN119938566A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip control technology, and in particular to a chip and a chip control method. Background Art
[0002] The arbitrator is used to control multiple components to use the bus in sequence when multiple components in the chip send requests, so as to achieve a single response to multiple requests. The existing arbitrators have priority settings for multiple components, including fixed priority and polling priority. Among them, fixed priority is processed in a fixed preset priority order, but under high-frequency requests, low-priority components are difficult to get a response. Polling priority is to poll the requests of each component in a strictly fair order. Although each component will get a response, it will cause delays. Summary of the invention
[0003] In order to solve the above problems, an embodiment of the present invention discloses a chip and a chip control method.
[0004] In a first aspect, an embodiment of the present invention provides a chip, comprising: a plurality of components, an arbitrator, an adder and a comparator;
[0005] The arbitrator is used to configure the initial priorities of the multiple components; input the initial priorities of the multiple components into the adder to obtain the communication priorities of the multiple components; input the communication priorities of the candidate components to be communicated among the multiple components into the comparator to obtain the ranking results of the candidate components; determine the target component from the candidate components according to the ranking results of the candidate components, and control the target component to communicate; after the target component communicates, reduce the initial priority of the target component;
[0006] The adder is used to receive the initial priorities of the multiple components sent by the arbitrator; determine the communication priorities of the multiple components according to the initial priorities of the multiple components; and send the communication priorities of the multiple components to the arbitrator;
[0007] The comparator is used to receive the communication priorities of the candidate components sent by the arbitrator, sort the candidate components, and send the sorting result to the arbitrator.
[0008] Optionally, the arbitrator is used to set the response value corresponding to the component among the multiple components that receives the communication request to 1, and set the response values corresponding to other components to 0; perform an AND operation on the response values of the multiple components and the communication priorities corresponding to the multiple components to obtain an operation result; and determine the component whose operation result is greater than zero as the candidate component to communicate.
[0009] Optionally, the adder is used to obtain preset weights of the multiple components; receive initial priorities of the multiple components sent by the arbitrator; add the initial priorities of the multiple components and the preset weights corresponding to the multiple components to obtain communication priorities of the multiple components; and send the communication priorities of the multiple components to the arbitrator.
[0010] Optionally, the arbitrator is used to set the initial priority of the target component to zero after the target component communicates.
[0011] Optionally, the arbitrator is further configured to increase the initial priorities of other components except the target component after the target component communicates.
[0012] Optionally, the arbitrator is used to increase the initial priority of the component whose initial priority is lower than that of the target component among the other components by a preset value after the target component communicates.
[0013] In a second aspect, an embodiment of the present invention provides a chip control method, the method comprising:
[0014] configuring initial priorities of the plurality of components through an arbitrator, and inputting the initial priorities of the plurality of components into an adder;
[0015] Determining, by the adder, communication priorities of the multiple components according to the initial priorities of the multiple components, and sending the communication priorities of the multiple components to the arbitrator;
[0016] inputting the communication priorities of the candidate components to be communicated among the multiple components into the comparator through the arbitrator;
[0017] sorting the candidate components by the comparator and sending the sorting result to the arbitrator;
[0018] The arbitrator determines a target component from the candidate components according to the ranking results of the candidate components, and controls the target component to communicate; after the target component communicates, the initial priority of the target component is reduced.
[0019] Optionally, inputting the communication priorities of the candidate components to be communicated among the multiple components into the comparator through the arbitrator includes:
[0020] The arbitrator sets the response value corresponding to the component that receives the communication request among the multiple components to 1, and sets the response values corresponding to other components to 0; performs an AND operation on the response values of the multiple components and the communication priorities corresponding to the multiple components to obtain an operation result; determines the component whose operation result is greater than zero as the candidate component to be communicated; and inputs the communication priority of the candidate component to be communicated among the multiple components into the comparator.
[0021] Optionally, determining the communication priorities of the multiple components according to the initial priorities of the multiple components by the adder includes:
[0022] The preset weights of the multiple components are obtained through the adder; the initial priorities of the multiple components sent by the arbitrator are received; the initial priorities of the multiple components are added to the preset weights corresponding to the multiple components to obtain the communication priorities of the multiple components.
[0023] Optionally, after the target component communicates, lowering the initial priority of the target component includes:
[0024] After the target component communicates through the arbitrator, the initial priority of the target component is set to zero.
[0025] Optionally, the method further comprises:
[0026] After the target component communicates, the initial priorities of other components except the target component are increased through the arbitrator.
[0027] Optionally, after the target component communicates with the arbitrator, increasing the initial priorities of other components except the target component includes:
[0028] After the target component communicates through the arbitrator, the initial priority of the component whose initial priority is lower than that of the target component among the other components is increased by a preset value.
[0029] The embodiments of the present invention include the following advantages:
[0030] The chip of the embodiment of the present invention includes: multiple components, an arbitrator, an adder and a comparator; the arbitrator is used to configure the initial priorities of the multiple components; the initial priorities of the multiple components are input into the adder to obtain the communication priorities of the multiple components, so that the priority of each component can be reasonably set by the adder, the circuit can be simplified, and the delay can be reduced; the communication priorities of the candidate components to be communicated among the multiple components are input into the comparator to obtain the sorting results of the candidate components, so that the components can be orderly controlled according to the sorting results; according to the sorting results of the candidate components, the target components are determined from the candidate components, and the target components are controlled to communicate; after the target components communicate, the initial priority of the target components is reduced, so that the priorities of the components can be re-sorted, and the communication of the components can be controlled according to the sorting results, so that multiple components can communicate; the adder is used to determine the communication priorities of the multiple components according to the initial priorities of the multiple components; the comparator is used to receive the communication priorities of the candidate components sent by the arbitrator and sort the candidate components, so that the delay can be reduced while ensuring that multiple components can communicate according to the reasonably set priorities. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0032] Figure 1 is a structural block diagram of a chip according to an embodiment of the present invention;
[0033] Figure 2 is a flowchart of a chip control method according to an embodiment of the present invention;
[0034] Figure 3 is a flowchart of another chip control method according to an embodiment of the present invention;
[0035] Figure 4 It is a logic diagram of a chip control method according to an embodiment of the present invention.
[0036] Description of reference numerals:
[0037] Chip 10 , component 11 , arbiter 12 , adder 13 , comparator 14 . DETAILED DESCRIPTION
[0038] Most existing chips use arbiters and counters to calculate the waiting time of each component in the chip to allocate bus usage rights for the requests of each component. Whenever a component in the chip initiates a request, a comparator is needed to compare whether the waiting time of the component exceeds the preset time to determine the priority of the component, but this method will make it difficult for low-priority components to get a response. Alternatively, the chip uses LFSR (Linear Feedback Shift Register) and an arbitrator to randomly assign fixed bus usage rights to each component, and then adds peripheral circuits to redistribute the originally equally divided rights, but the added peripheral circuits need to introduce new registers to represent the status, which will add area on the basis of the newly added peripheral circuits and cause delays.
[0039] The present invention proposes a chip and a chip control method, the purpose of which is to ensure that each component can communicate without delay when multiple components of the chip send requests. In order to achieve this goal, the embodiment of the present invention reasonably sets the priorities of multiple components through an adder, thereby simplifying the circuit and reducing delay, sorting the priorities of the components through a comparator, and adjusting the priorities of the components after each polling through an arbitrator, thereby ensuring that each component can communicate.
[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0041] Reference Figure 1 , shows a structural block diagram of a chip provided by an embodiment of the present invention, the chip 10 may specifically include: multiple components 11, an arbitrator 12, an adder 13 and a comparator 14;
[0042] The arbitrator 12 is used to configure the initial priorities of the multiple components 11; input the initial priorities of the multiple components 11 into the adder 13 to obtain the communication priorities of the multiple components 11; input the communication priorities of the candidate components to be communicated among the multiple components 11 into the comparator 14 to obtain the ranking results of the candidate components; determine the target component from the candidate components according to the ranking results of the candidate components, and control the target component to communicate; after the target component communicates, reduce the initial priority of the target component;
[0043] In an embodiment of the present invention, a chip may include multiple components, an arbitrator, an adder, and a comparator. The components may read data from a data storage component via a bus of the chip. When multiple components initiate requests at the same time, the bus usage order of the multiple components may be allocated via the arbitrator.
[0044] Specifically, the arbitrator pre-configures initial priorities for multiple components, obtains the communication priorities of multiple components according to the initial priorities through an adder, determines the communication priorities of candidate components to be communicated from multiple components, obtains the ranking results of the candidate components through a comparator, determines the candidate component with the highest ranking as the target component according to the ranking results of the candidate components, and controls the target component to communicate through the bus, that is, reads data from the data storage component. After the target component communicates, the arbitrator can lower the initial priority of the target component, and then the multiple components can be prioritized again to control the components that are not communicating to communicate, so as to ensure that multiple components can communicate.
[0045] The adder 13 is used to receive the initial priorities of the multiple components 11 sent by the arbitrator 12; determine the communication priorities of the multiple components 11 according to the initial priorities of the multiple components 11; and send the communication priorities of the multiple components 11 to the arbitrator 12;
[0046] The comparator 14 is configured to receive the communication priorities of the candidate components sent by the arbitrator 12 , sort the candidate components, and send the sorting result to the arbitrator 12 .
[0047] The chip of the embodiment of the present invention includes: multiple components, an arbitrator, an adder and a comparator; the arbitrator is used to configure the initial priorities of the multiple components; the initial priorities of the multiple components are input into the adder to obtain the communication priorities of the multiple components, so that the priority of each component can be reasonably set by the adder, the circuit can be simplified, and the delay can be reduced; the communication priorities of the candidate components to be communicated among the multiple components are input into the comparator to obtain the sorting results of the candidate components, so that the components can be orderly controlled according to the sorting results; according to the sorting results of the candidate components, the target components are determined from the candidate components, and the target components are controlled to communicate; after the target components communicate, the initial priority of the target components is reduced, so that the priorities of the components can be re-sorted, and the communication of the components can be controlled according to the sorting results, so that multiple components can communicate; the adder is used to determine the communication priorities of the multiple components according to the initial priorities of the multiple components; the comparator is used to receive the communication priorities of the candidate components sent by the arbitrator and sort the candidate components, so that the delay can be reduced while ensuring that multiple components can communicate according to the reasonably set priorities.
[0048] In one embodiment, the arbitrator 12 is used to set the response value corresponding to the component 11 that receives the communication request among the multiple components 11 to 1, and set the response values corresponding to other components 11 to 0; perform an AND operation on the response values of the multiple components 11 and the communication priorities corresponding to the multiple components 11 to obtain an operation result; and determine the component whose operation result is greater than zero as the candidate component to communicate.
[0049] In an embodiment of the present invention, there may be a component among multiple components that does not initiate a communication request, so there is no need to perform priority sorting. The arbitrator may set the response value corresponding to the component that receives the communication request among the multiple components to 1, and the response value corresponding to other components to 0. The response values of the multiple components are ANDed with the communication priorities corresponding to the multiple components to obtain a calculation result, wherein the response value corresponding to the component that initiates the communication request is equal to its corresponding communication priority, and the response value corresponding to the component that does not initiate the communication request is equal to 0. The arbitrator may determine the component whose calculation result is greater than zero as a candidate component to be communicated, so that the candidate component participates in the subsequent priority sorting.
[0050] In one embodiment, the adder 13 is used to obtain the preset weights of the multiple components 11; receive the initial priorities of the multiple components 11 sent by the arbitrator 12; add the initial priorities of the multiple components 11 and the preset weights corresponding to the multiple components 11 to obtain the communication priorities of the multiple components 11; and send the communication priorities of the multiple components 11 to the arbitrator 12.
[0051] In an embodiment of the present invention, the preset weights can be set in advance by a technician according to the performance and requirements of the components. The adder can add the initial priorities of multiple components to the preset weights corresponding to the multiple components to obtain the communication priorities of the multiple components. Setting different preset weights for components can change the response rate of the components. Since the components with the highest priority can use the bus, the response probability of the components can be increased by adding the preset weights to the initial priority of each component. In the embodiment of the present invention, only the number of adders corresponding to the components can be increased to change the bus usage rights of each component, which reduces the use of registers, reduces delays, and makes the circuit simpler, reducing the chip area.
[0052] In one embodiment, the arbitrator 12 is used to set the initial priority of the target component to zero after the target component communicates;
[0053] The arbitrator 12 is further configured to increase the initial priorities of other components except the target component after the target component communicates; specifically, the initial priorities of the components whose initial priorities are lower than the target component among the other components are increased by a preset value.
[0054] In an embodiment of the present invention, after the target component communicates, the arbitrator can set the initial priority of the target component to zero, increase the initial priority of components other than the target component whose initial priority is lower than the target component by a preset value, and then perform the next polling, thereby ensuring that multiple components can communicate according to reasonably set priorities.
[0055] The arbitrator of the embodiment of the present invention is used to configure the initial priorities of multiple components; the initial priorities of multiple components are input into an adder to obtain the communication priorities of the multiple components, so that the priority of each component can be reasonably set by the adder, the circuit can be simplified, and the delay can be reduced; the communication priorities of candidate components to be communicated among the multiple components are input into a comparator to obtain the sorting results of the candidate components, so that the components can be orderly controlled according to the sorting results; according to the sorting results of the candidate components, the target components are determined from the candidate components, and the target components are controlled to communicate; after the target components communicate, the initial priority of the target components is reduced, so that the priorities of the components can be re-sorted, and the communication of the components can be controlled according to the sorting results, so that multiple components can communicate; the adder is used to determine the communication priorities of the multiple components according to the initial priorities of the multiple components; the comparator is used to receive the communication priorities of the candidate components sent by the arbitrator and sort the candidate components, so that the delay can be reduced while ensuring that multiple components can communicate according to the reasonably set priorities.
[0056] Reference Figure 2 , shows a flowchart of a chip control method according to an embodiment of the present invention, and the method may specifically include the following steps:
[0057] Step 201, configuring initial priorities of multiple components through an arbitrator, and inputting the initial priorities of the multiple components into an adder;
[0058] In an embodiment of the present invention, a chip may include multiple components, an arbitrator, an adder, and a comparator. The components may read data from a data storage component via a bus of the chip. The arbitrator may pre-configure initial priorities for multiple components, and when multiple components initiate requests at the same time, the bus usage order of the multiple components may be allocated by the arbitrator.
[0059] Step 202, determining the communication priorities of the multiple components according to the initial priorities of the multiple components by the adder, and sending the communication priorities of the multiple components to the arbitrator;
[0060] In an embodiment of the present invention, the communication priorities of multiple components can be obtained according to the initial priorities through an adder, and the communication priorities of candidate components to be communicated can be determined from the multiple components. Therefore, the priority of each component can be reasonably set through the adder, the use of registers can be reduced, the delay can be reduced, the circuit is simpler, and the chip area is reduced.
[0061] Step 203, inputting the communication priorities of the candidate components to be communicated among the multiple components into a comparator through the arbitrator;
[0062] Step 204, sorting the candidate components by the comparator, and sending the sorting result to the arbitrator;
[0063] Step 205: the arbitrator determines a target component from the candidate components according to the ranking results of the candidate components, and controls the target component to communicate; after the target component communicates, the initial priority of the target component is lowered.
[0064] In the embodiment of the present invention, the communication priority of the candidate components to be communicated can be determined from multiple components by an arbitrator, the ranking result of the candidate components can be obtained by a comparator, and the candidate component with the highest ranking can be determined as the target component according to the ranking result of the candidate components, and the target component can be controlled to communicate through the bus, that is, to read data from the data storage component. After the target component communicates, the initial priority of the target component can be lowered by the arbitrator, and then the multiple components can be prioritized again to control the components that are not communicating to communicate, so as to ensure that multiple components can communicate.
[0065] The embodiment of the present invention can configure the initial priorities of multiple components through an arbitrator; input the initial priorities of multiple components into an adder to obtain the communication priorities of multiple components, so that the priority of each component can be reasonably set through the adder, simplify the circuit, and reduce the delay; input the communication priority of the candidate components to be communicated among the multiple components into a comparator to obtain the sorting results of the candidate components, so that the components can be orderly controlled according to the sorting results; determine the target component from the candidate components according to the sorting results of the candidate components, and control the target component to communicate; after the target component communicates, reduce the initial priority of the target component, so that the priorities of the components can be re-sorted, and the component communication can be controlled according to the sorting results, so that multiple components can communicate according to the reasonably set priorities while reducing the delay.
[0066] Reference Figure 3 , shows a flowchart of another chip control method according to an embodiment of the present invention, and the method may specifically include the following steps:
[0067] Step 301, configuring initial priorities of multiple components through an arbitrator, and inputting the initial priorities of the multiple components into an adder;
[0068] Step 302, determining the communication priorities of the multiple components according to the initial priorities of the multiple components through the adder, and sending the communication priorities of the multiple components to the arbitrator;
[0069] In one embodiment, the step of determining the communication priorities of the multiple components according to the initial priorities of the multiple components by the adder may further include the following sub-steps:
[0070] Sub-step S11, obtaining preset weights of the multiple components through the adder;
[0071] Sub-step S12, receiving the initial priorities of the multiple components sent by the arbitrator;
[0072] Sub-step S13, adding the initial priorities of the multiple components to the preset weights corresponding to the multiple components to obtain the communication priorities of the multiple components.
[0073] In an embodiment of the present invention, the preset weights can be set in advance by a technician according to the performance and requirements of the components. The adder can add the initial priorities of multiple components to the preset weights corresponding to the multiple components to obtain the communication priorities of the multiple components. Setting different preset weights for components can change the response rate of the components. Since the components with the highest priority can use the bus, the response probability of the components can be increased by adding the preset weights to the initial priority of each component. In the embodiment of the present invention, only the number of adders corresponding to the components can be increased to change the bus usage rights of each component, which reduces the use of registers, reduces delays, and makes the circuit simpler, reducing the chip area.
[0074] Step 303, inputting the communication priorities of the candidate components to be communicated among the multiple components into a comparator through the arbitrator;
[0075] In one embodiment, the step of inputting the communication priorities of the candidate components to be communicated among the multiple components into the comparator through the arbitrator may further include the following sub-steps:
[0076] Sub-step S21, setting, by the arbitrator, a response value corresponding to a component among the multiple components that receives the communication request to 1, and setting response values corresponding to other components to 0;
[0077] Sub-step S22, performing an AND operation on the response values of the multiple components and the communication priorities corresponding to the multiple components to obtain an operation result;
[0078] Sub-step S23, determining the component whose operation result is greater than zero as the candidate component to be communicated;
[0079] Sub-step S24: inputting the communication priority of the candidate components to be communicated among the multiple components into the comparator.
[0080] In an embodiment of the present invention, there may be a component among multiple components that does not initiate a communication request, so there is no need to perform priority sorting. The arbitrator may set the response value corresponding to the component that receives the communication request among the multiple components to 1, and the response value corresponding to other components to 0. The response values of the multiple components are ANDed with the communication priorities corresponding to the multiple components to obtain a calculation result, wherein the response value corresponding to the component that initiates the communication request is equal to its corresponding communication priority, and the response value corresponding to the component that does not initiate the communication request is equal to 0. The arbitrator may determine the component whose calculation result is greater than zero as a candidate component to be communicated, and then input the communication priority of the candidate component to be communicated among the multiple components into the comparator, so that the candidate component participates in the subsequent priority sorting.
[0081] Step 304, sorting the candidate components by the comparator, and sending the sorting result to the arbitrator;
[0082] Step 305, the arbitrator determines the target component from the candidate components according to the ranking results of the candidate components, and controls the target component to communicate; after the target component communicates, the initial priority of the target component is lowered, and the initial priority of other components except the target component is increased.
[0083] In one embodiment, the step of lowering the initial priority of the target component and raising the initial priorities of other components except the target component after the target component communicates may further include the following sub-steps:
[0084] Sub-step S31, after the target component communicates with the target component, the arbitrator sets the initial priority of the target component to zero, and increases the initial priority of the components whose initial priority is lower than that of the target component among the other components by a preset value.
[0085] In an embodiment of the present invention, after the target component communicates, the arbitrator can set the initial priority of the target component to zero, increase the initial priority of components other than the target component whose initial priority is lower than the target component by a preset value, and then perform the next polling, thereby ensuring that multiple components can communicate according to reasonably set priorities.
[0086] Reference Figure 4, shows a logic diagram of a chip control method provided by an embodiment of the present invention. In order to enable those skilled in the art to better understand the embodiment of the present invention, the following Figure 4 The embodiments of the present invention are described as follows:
[0087] Among them, 0 to n-1 represent n components. P represents the initial priority of the component, which can be a natural number from 0 to n. X represents the preset weight of the component, which can be a natural number from 0 to n. Y is the adder that adds the initial priority P of the component to the preset weight X of the component to obtain the communication priority, Yi = P i + X i. R represents the response value of the component, where the R value of the candidate component is 1 and the R value of other components is 0, Z i = Yi & R i. Z represents the result of the AND operation of the response value R of the component and the communication priority of the component. G represents the sorting result obtained by the comparator sorting the communication priority of the candidate components, where the G value of the target component is high and can be represented by 1; the G value of other components is low and can be represented by 0.
[0088] "+" indicates that the adder performs addition operations; "and" indicates that the arbitrator performs AND operations; "max" indicates that the comparator performs sorting; "loop" indicates that the arbitrator sets the initial priority of the target component to zero, and increases the initial priority of components other than the target component whose initial priority is lower than the target component by a preset value. In the above characters, the Y value and the Z value are the intermediate values of a single cycle of arbitration, and do not need to be stored in the next arbitration. The P value will be updated through the "loop" process.
[0089] Exemplarily, assuming that the number of components is 8 and each component initiates a communication request, that is, the response value of the component R = [1, 1, 1, 1, 1, 1, 1], then Z is equal to the communication priority of the component Y. Assuming the initial priority P = [111, 110, 101, 100, 011, 010, 001, 000], it means that the polling priority of the component decreases from left to right.
[0090] Assuming that the preset weight X is not introduced, the priority of the component is ultimately determined by P, and the output G is [1, 0, 0, 0, 0, 0, 0], responding to the first component. The polling priority of the next arbitration is processed as follows: the initial priority P of the first component is set to zero, and the initial priorities of other components are less than the initial priority of the first component plus 1. Therefore, the polling priority P' of the next arbitration becomes [000, 111, 110, 101, 100, 011, 010, 001], and G is [0, 1, 0, 0, 0, 0, 0], responding to the second component. By analogy, the third, fourth, ..., eight components will be responded to in order.
[0091] Assume that the preset weight X is introduced, X = [4, 3, 2, 1, 0, 0, 0], and the initial priority P = [7, 6, 5, 4, 3, 2, 1, 0], then Z = [11, 9, 7, 5, 3, 2, 1, 0], the first arbitration responds to the first component, and the P value entering the next polling arbitration is [0, 7, 6, 5, 4, 3, 2, 1]. The next arbitration Z is [4, 10, 8, 6, 4, 3, 2, 1], and the second component is responded to at this time, and the P value becomes [1, 0, 7, 6, 5, 4, 3, 2], entering the next arbitration, and so on. The specific polling process is as follows:
[0092] P = [7, 6, 5, 4, 3, 2, 1, 0], Z = [11, 9, 7, 5, 3, 2, 1, 0], G = [1, 0, 0, 0, 0, 0, 0], responding to the first component;
[0093] P = [0, 7, 6, 5, 4, 3, 2, 1], Z = [4, 10, 8, 6, 4, 3, 2, 1], G = [0, 1, 0, 0, 0, 0, 0], responding to the second component;
[0094] P = [1, 0, 7, 6, 5, 4, 3, 2], Z = [5, 3, 9, 7, 5, 4, 3, 2], G = [0, 0, 1, 0, 0, 0, 0], responding to the third component;
[0095] P = [2, 1, 0, 7, 6, 5, 4, 3], Z = [6, 4, 2, 8, 6, 5, 4, 3], G = [0, 0, 0, 1, 0, 0, 0, 0], responding to the 4th component;
[0096] P = [3, 2, 1, 0, 7, 6, 5, 4], Z = [7, 5, 3, 1, 7, 6, 5, 4], G = [1, 0, 0, 0, 0, 0, 0], responding to the first component;
[0097] P = [0, 3, 2, 1, 7, 6, 5, 4], Z = [4, 6, 4, 2, 7, 6, 5, 4], G = [0, 0, 0, 0, 1, 0, 0, 0], responding to the 5th component;
[0098] P = [1, 4, 3, 2, 0, 7, 6, 5], Z = [5, 7, 5, 3, 0, 7, 6, 5], G = [0, 1, 0, 0, 0, 0, 0], responding to the second component;
[0099] P = [2, 0, 4, 3, 1, 7, 6, 5], Z = [6, 3, 6, 4, 1, 7, 6, 5], G = [0, 0, 0, 0, 1, 0, 0], responding to the 6th component;
[0100] P = [3, 1, 5, 4, 2, 0, 7, 6], Z = [7, 4, 7, 5, 2, 0, 7, 6], G = [1, 0, 0, 0, 0, 0, 0], responding to the first component;
[0101] P = [0, 2, 5, 4, 3, 1, 7, 6], Z = [4, 5, 7, 5, 3, 1, 7, 6], G = [0, 0, 1, 0, 0, 0, 0], responding to the third component;
[0102] P = [1, 3, 0, 5, 4, 2, 7, 6], Z = [5, 6, 2, 6, 4, 2, 7, 6], G = [0, 0, 0, 0, 0, 1, 0], responding to the 7th component.
[0103] Computer calculations show that the response rates of the components with this X value are: [3 / 16, 9 / 64, 27 / 256, 81 / 1024, 81 / 1024, 81 / 1024].
[0104] In the above example, the value of X can be [0,7], because when the difference of X is 7, the maximum value of P is 7, and the component with communication priority Y=0 will not get a response. At this time, the range of P value can also be widened, that is, multiplied by a certain multiple, such as 2, the maximum value of P will become 14, so that more precise response rate adjustment can be achieved, but this will increase the cost.
[0105] The embodiment of the present invention can configure the initial priorities of multiple components through an arbitrator; input the initial priorities of multiple components into an adder to obtain the communication priorities of multiple components, so that the priority of each component can be reasonably set through the adder, simplify the circuit, and reduce the delay; input the communication priority of the candidate components to be communicated among the multiple components into a comparator to obtain the sorting results of the candidate components, so that the components can be orderly controlled according to the sorting results; determine the target component from the candidate components according to the sorting results of the candidate components, and control the target component to communicate; after the target component communicates, reduce the initial priority of the target component, so that the priorities of the components can be re-sorted, and the component communication can be controlled according to the sorting results, so that multiple components can communicate according to the reasonably set priorities while reducing the delay.
[0106] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.
[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0108] Those skilled in the art will appreciate that the embodiments of the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more machine-readable media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0109] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0110] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0112] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0113] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0114] The above is a detailed introduction to a chip and a chip control method provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A chip, characterized in that: include: Multiple components, arbiters, adders, and comparators; The arbitrator is used to configure the initial priorities of the multiple components; Inputting the initial priorities of the multiple components into the adder to obtain the communication priorities of the multiple components; inputting the communication priorities of the candidate components to be communicated among the multiple components into the comparator to obtain the ranking results of the candidate components; determining the target component from the candidate components according to the ranking results of the candidate components, and controlling the target component to communicate; after the target component communicates, lowering the initial priority of the target component; The adder is used to receive the initial priorities of the multiple components sent by the arbitrator; and determine the communication priorities of the multiple components according to the initial priorities of the multiple components; sending the communication priorities of the plurality of components to the arbitrator; The comparator is used to receive the communication priorities of the candidate components sent by the arbitrator, sort the candidate components, and send the sorting result to the arbitrator.
2. The chip according to claim 1, characterized in that: The arbitrator is used to set the response value corresponding to the component that receives the communication request among the multiple components to 1, and set the response values corresponding to other components to 0; perform an AND operation on the response values of the multiple components and the communication priorities corresponding to the multiple components to obtain an operation result; The component whose operation result is greater than zero is determined as the candidate component to be communicated.
3. The chip according to claim 1, characterized in that: The adder is used to obtain the preset weights of the multiple components; receive the initial priorities of the multiple components sent by the arbitrator; add the initial priorities of the multiple components and the preset weights corresponding to the multiple components to obtain the communication priorities of the multiple components; and send the communication priorities of the multiple components to the arbitrator.
4. The chip according to claim 1, characterized in that: The arbitrator is used to set the initial priority of the target component to zero after the target component communicates.
5. The chip according to claim 1, characterized in that: The arbitrator is further configured to increase the initial priorities of other components except the target component after the target component communicates.
6. The chip according to claim 5, characterized in that: The arbitrator is used to increase the initial priority of the component whose initial priority is lower than that of the target component among the other components by a preset value after the target component communicates.
7. A chip control method, characterized in that: The method comprises: configuring initial priorities of the plurality of components through an arbitrator, and inputting the initial priorities of the plurality of components into an adder; Determining, by the adder, communication priorities of the multiple components according to the initial priorities of the multiple components, and sending the communication priorities of the multiple components to the arbitrator; inputting the communication priorities of the candidate components to be communicated among the multiple components into a comparator through the arbitrator; sorting the candidate components by the comparator and sending the sorting result to the arbitrator; The arbitrator determines a target component from the candidate components according to the ranking results of the candidate components, and controls the target component to communicate; after the target component communicates, the initial priority of the target component is reduced.
8. The method according to claim 7, characterized in that The step of inputting the communication priorities of the candidate components to be communicated among the multiple components into the comparator through the arbitrator comprises: The arbitrator sets the response value corresponding to the component that receives the communication request among the multiple components to 1, and sets the response values corresponding to other components to 0; performs an AND operation on the response values of the multiple components and the communication priorities corresponding to the multiple components to obtain an operation result; determines the component whose operation result is greater than zero as the candidate component to be communicated; and inputs the communication priority of the candidate component to be communicated among the multiple components into the comparator.
9. The method according to claim 7, characterized in that: Determining the communication priorities of the multiple components according to the initial priorities of the multiple components by the adder includes: The preset weights of the multiple components are obtained through the adder; the initial priorities of the multiple components sent by the arbitrator are received; the initial priorities of the multiple components are added to the preset weights corresponding to the multiple components to obtain the communication priorities of the multiple components.
10. The method according to claim 7, characterized in that After the target component communicates, lowering the initial priority of the target component includes: After the target component communicates through the arbitrator, the initial priority of the target component is set to zero.
11. The method according to claim 7, characterized in that The method further comprises: After the target component communicates, the initial priorities of other components except the target component are increased through the arbitrator.
12. The method according to claim 11, characterized in that After the target component communicates with the arbitrator, increasing the initial priority of other components except the target component includes: After the target component communicates through the arbitrator, the initial priority of the component whose initial priority is lower than that of the target component among the other components is increased by a preset value.