Slave device, replaceable accessory and communication method

Abstract

The invention provides slave equipment, a replaceable accessory and a communication method, and when the slave equipment detects that a clock line is in a high-level state for a preset first duration, an I2C bus is considered to be in an idle state, and a data line is pulled down to be in a low-level state. When the slave device pulls down the data line to the low-level state, large abnormal fluctuation cannot be generated on the data line, and then it is avoided that the slave device mistakenly recognizes the starting signal. It can be understood that when the data line is pulled down to a low level by the slave device, the host device and the slave device cannot communicate through the I2C bus. In order to avoid influencing normal communication requirements on the I2C bus, a release condition is set, and when a preset release condition is met, the data line is released, so that the data line is recovered to a high-level state, and the host device and the slave device can perform normal communication through the I2C bus.

Description

[0001] This application claims the priority of the Chinese patent application submitted to the State Intellectual Property Office on January 31, 2024, with application number "202410140754.0" and invention name "A chip control method, chip and replaceable accessories", all contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a slave device, a replaceable accessory and a communication method. Background Art

[0003] I2C (Inter-Integrated Circuit) is a serial communication protocol that allows multiple devices to be connected to an I2C bus to achieve communication between multiple devices. The I2C bus consists of a data line (SDA) and a clock line (SCL), where the data line is used to transmit data signals and the clock line is used to transmit clock signals.

[0004] Devices connected to the I2C bus are divided into host devices and slave devices. The host device is used to initiate communication on the I2C bus, and the slave device responds passively. Specifically, when the I2C bus is idle, both the data line and the clock line maintain a high level state. When the host device needs to communicate with the slave device, it can pull the data line from a high level state to a low level state while the clock line remains in a high level state to generate a start signal; when the host device needs to stop communicating with the slave device, it can pull the data line from a low level state to a high level state while the clock line remains in a high level state to generate a stop signal.

[0005] However, in actual applications, there may be some signal interference, which may cause abnormal fluctuations in the data line. For example, when a large voltage drop occurs on the data line, the slave device may mistakenly recognize the start signal.

[0006] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0007] The present application provides a slave device, replaceable accessories and communication method, so as to solve the problem in the prior art that the slave device incorrectly recognizes the start signal due to signal interference.

[0008] In a first aspect, an embodiment of the present application provides a slave device, wherein the slave device is configured to be communicatively connected to a host device at least through a clock line and a data line on a bus, and when the bus is in an idle state, the host device outputs a high level, and the slave device is configured to:

[0009] When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state;

[0010] When a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0011] In a possible implementation, when a preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0012] When it is detected that the clock line switches from a high level state to a low level state, the data line is released so that the data line returns to a high level state.

[0013] In a possible implementation, when a preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0014] When the low level state of the data line continues for a second time period, the data line is released so that the data line returns to a high level state.

[0015] In a possible implementation, when a preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0016] When it is detected that the clock line switches from a high level state to a low level state, or when the low level state of the data line continues for a second period of time, the data line is released so that the data line returns to a high level state.

[0017] In a possible implementation, when a preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0018] Parsing the last instruction sent by the host device;

[0019] If the last instruction is a data line pull-down instruction, then when a preset release condition is met, the data line is released so that the data line returns to a high level state;

[0020] If the last instruction is not a data line pull-down instruction, releasing the data line after a preset delay;

[0021] The data line pull-down instruction includes the second duration, and the preset time is less than the second duration.

[0022] In a possible implementation, if the last instruction is a data line pull-down instruction, then when a preset release condition is met, the data line is released so that the data line is restored to a high level state, including:

[0023] If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction matches the address information of the slave device, then when a preset release condition is met, the data line is released so that the data line is restored to a high level state;

[0024] If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction does not match the address information of the slave device, the data line is released after a preset delay.

[0025] In a possible implementation, after detecting that the clock line is in a high level state for a preset first period of time, pulling the data line down to a low level state includes:

[0026] The timing starts when a stop signal sent by the host device is received, and after the high level state of the clock line continues for a preset first time period, the data line is pulled down to a low level state.

[0027] In a second aspect, an embodiment of the present application provides a slave device, including: an electronic module, wherein the electronic module is configured to:

[0028] The bus is at least connected to the host device through a clock line and a data line on the bus, and when the bus is in an idle state, the host device outputs a high level;

[0029] When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state;

[0030] When a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0031] In a possible implementation, the electronic module includes:

[0032] A control unit, the control unit being configured to: be communicatively connected with a host device at least via a clock line and a data line on a bus, and be outputted by the host device at a high level when the bus is in an idle state;

[0033] The peripheral circuit is configured to: pull the data line down to a low level state after detecting that the clock line is in a high level state for a preset first period of time; and release the data line when a preset release condition is met, so that the data line returns to a high level state.

[0034] In a possible implementation, the peripheral circuit includes:

[0035] A trigger unit, wherein a first end of the trigger unit is electrically connected to the clock line, and the trigger unit is configured to: when the clock line is in a high level state for a preset first time period, the second end of the trigger unit outputs a first control signal; when the clock line switches from a high level state to a low level state, the second end of the trigger unit outputs a second control signal;

[0036] A switch unit, wherein a first end of the switch unit is electrically connected to the data line, a second end of the switch unit is connected to a reference potential, a control end of the switch unit is electrically connected to the second end of the trigger unit, and the switch unit is configured as follows: when the control end of the switch unit receives a first control signal output by the second end of the trigger unit, the switch unit is turned on to pull the data line down to a low level state; when the control end of the switch unit receives a second control signal output by the second end of the trigger unit, the switch unit is turned off, the data line is released, and the data line is restored to a high level state.

[0037] In a possible implementation, the trigger unit includes:

[0038] a first resistor, wherein a first end of the first resistor is electrically connected to the clock line;

[0039] a capacitor, wherein a first end of the capacitor is electrically connected to a second end of the first resistor, and a second end of the capacitor is connected to a reference potential;

[0040] The first end of the first resistor is the first end of the trigger unit, and the first end of the capacitor is the second end of the trigger unit.

[0041] In a possible implementation, the first end of the control unit is electrically connected to the controlled end of the trigger unit, and the control unit is further used to: when the low level state of the data line continues for a second time period, control the first end of the control unit to switch from the first state to the second state;

[0042] The trigger unit is also configured as follows: when the first end of the control unit is in the first state, the controlled end of the trigger unit is in an uncontrolled state, and the trigger unit can implement the trigger function of the switch unit; when the first end of the control unit is in the second state, the controlled end of the trigger unit is in a controlled state, and the trigger unit cannot implement the trigger function of the switch unit, so that the switch unit remains in a disconnected state.

[0043] In a possible implementation, the trigger unit includes:

[0044] a first resistor, wherein a first end of the first resistor is electrically connected to the clock line;

[0045] a second resistor, wherein a first end of the second resistor is electrically connected to a first end of the control unit;

[0046] A capacitor, wherein a first end of the capacitor is electrically connected to a second end of the first resistor and a second end of the second resistor respectively, and a second end of the capacitor is connected to a reference potential;

[0047] The first end of the first resistor is the first end of the trigger unit, the first end of the capacitor is the second end of the trigger unit, and the first end of the second resistor is the controlled end of the trigger unit.

[0048] In a possible implementation, the trigger unit further includes:

[0049] A unidirectional conductive element, wherein a first end of the unidirectional conductive element is electrically connected to the clock line, a second end of the unidirectional conductive element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conductive element is unidirectionally conductive to the first end of the unidirectional conductive element.

[0050] In a possible implementation, the switch unit includes:

[0051] a transistor, wherein a first terminal of the transistor is electrically connected to the data line, a second terminal of the transistor is connected to a reference potential, and a control terminal of the transistor is electrically connected to a first terminal of the capacitor;

[0052] The first end of the transistor is the first end of the switch unit, the second end of the transistor is the second end of the switch unit, and the control end of the transistor is the control end of the switch unit.

[0053] In a possible implementation manner, the switch unit further includes:

[0054] a third resistor, wherein a first end of the third resistor is electrically connected to the data line, and a second end of the third resistor is electrically connected to the first end of the transistor;

[0055] Wherein, the first end of the third resistor is the first end of the switch unit.

[0056] In a third aspect, an embodiment of the present application provides a replaceable accessory, including a slave device described in any one of the first aspect and the second aspect.

[0057] In a fourth aspect, an embodiment of the present application provides a communication method, which is applied to a slave device, wherein the slave device is configured to communicate with a host device at least through a clock line and a data line on a bus, and when the bus is in an idle state, the host device outputs a high level, and the method includes:

[0058] When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state;

[0059] When a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0060] In an embodiment of the present application, when the slave device detects that the clock line is in a high level state for a preset first time length, it is considered that the I2C bus is in an idle state, and the data line is pulled down to a low level state. During the period when the slave device pulls the data line down to a low level state, no large abnormal fluctuations will be generated on the data line, thereby avoiding the slave device from mistakenly identifying the start signal. It is understandable that when the data line is pulled down to a low level by the slave device, the host device and the slave device cannot communicate through the I2C bus. In order to avoid affecting the normal communication requirements on the I2C bus, a release condition is set. When the preset release condition is met, the data line is released, so that the data line is restored to a high level state, and the host device and the slave device can then communicate normally through the I2C bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0062] Figure 1 A structural block diagram of a communication system provided in an embodiment of the present application;

[0063] Figure 2A A timing diagram of a start signal provided in an embodiment of the present application;

[0064] Figure 2B A timing diagram of a stop signal provided in an embodiment of the present application;

[0065] Figure 3 A flow chart of a communication method provided in an embodiment of the present application;

[0066] Figure 4A A timing diagram of an application scenario provided in an embodiment of the present application;

[0067] Figure 4B A timing diagram of another application scenario provided in an embodiment of the present application;

[0068] Figure 5 A flowchart of another communication method provided in an embodiment of the present application;

[0069] Figure 6 A flowchart of another communication method provided in an embodiment of the present application;

[0070] Figure 7 A flowchart of another communication method provided in an embodiment of the present application;

[0071] Figure 8 A structural block diagram of a slave device provided in an embodiment of the present application;

[0072] Fig. 9 A structural block diagram of another slave device provided in an embodiment of the present application;

[0073] Fig.10 A structural block diagram of another slave device provided in an embodiment of the present application;

[0074] Fig.11 A structural block diagram of another slave device provided in an embodiment of the present application;

[0075] Fig.12 A structural block diagram of another slave device provided in an embodiment of the present application;

[0076] Fig.13 A structural block diagram of a replaceable accessory is also provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0078] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0079] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0080] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0081] See also Figure 1 , is a structural block diagram of a communication system provided in an embodiment of the present application. Figure 1 As shown, the communication system includes a host device and multiple slave devices connected to the I2C bus, and the communication between the host device and the slave device can be realized through the I2C bus. Specifically, the I2C bus includes a data line and a clock line, wherein the data line is used to transmit a data signal, and the clock line is used to transmit a clock signal. In addition, in practical applications, the I2C bus may also include a power line and a ground line (not shown in the figure), and the host device can power the slave device through the power line and the ground line.

[0082] It is necessary to add that Figure 1 This is only a possible application scenario shown in the embodiment of the present application, and should not be used as a limitation on the protection scope of the present application. For example, in some application scenarios, there may be only one slave device; or in some application scenarios, there may be multiple host devices; and so on.

[0083] In some possible implementations, the host device is an image forming device. Exemplarily, the image forming device may be: an inkjet printer, a laser printer, a 3D printer, a label printer, a dot matrix printer, etc. Further, the image forming device includes an image forming control unit and an image forming unit, wherein the image forming control unit is used to control the image forming device as a whole, and the image forming unit is used to form an image on a conveyed paper under the control of the image forming control unit based on the image data. The image forming control unit may be a system on chip (SoC), which is a micro system composed of components of multiple systems and is configured to control the imaging processing operation of the image forming device, such as linear correction, noise reduction, bad pixel removal, detail enhancement, etc. of the image data, thereby improving the quality of the image output. The image forming control unit is also used to perform processing operations related to data transmission and reception, command transmission and reception, and engine control of printing images, such as transmitting and receiving data, printing engine control commands, status, etc. through an interface unit (including but not limited to a USB port, a wired network port, a wireless network port, or other interfaces, etc.). Accordingly, the slave device may be a replaceable accessory installed on the image forming device, such as a consumable. Consumables are usually ink cartridges, toner cartridges, toner cartridges, toner cartridges, ribbon cartridges, etc. Consumables can also be other easily damaged components, parts, units (such as paper boxes, etc.) that can be installed in the image forming device and need to be replaced, which also belong to the technical solutions corresponding to the consumables protected by this application.

[0084] In some other possible implementations, the host device may be a computer. Correspondingly, the slave device may be a replaceable accessory of the computer, such as a peripheral device / apparatus of the computer. The peripheral device / apparatus of the computer includes a mouse, a keyboard, a camera, etc., which is not specifically limited in the embodiments of the present application.

[0085] In some other possible implementations, the host device is a mobile terminal (e.g., a mobile phone, a tablet computer, a PDA, etc.). Accordingly, the slave device may be a replaceable accessory of the mobile terminal, such as an accessory or a peripheral device / apparatus of the mobile terminal. The accessories or peripheral devices / apparatus of the mobile terminal include lithium batteries, wearable devices, etc., which are not specifically limited in the embodiments of the present application.

[0086] In addition, the slave device may also refer to a circuit unit installed on a replaceable accessory, where the circuit unit is composed of one or more hardware circuits. In some embodiments, at least part of the one or more hardware circuits includes a processor.

[0087] The host device and the slave device need to be determined in a specific scenario. A host device in one scenario may be a slave device in another scenario. Similarly, a slave device in one scenario may be a host device in another scenario.

[0088] For the consumables of the image forming device, one possible implementation is that the consumables are of a split structure, including a drum box and a developer box that are detachable from each other, wherein the drum box includes a photosensitive drum and a charging roller, and the developer box includes a developer container, a developer roller, and a developer conveying element. Another possible implementation is that the consumables are of an integrated structure, for example, the consumables include a developer container, a developer roller, a developer conveying element, a photosensitive drum, a charging roller, etc.

[0089] Furthermore, the consumables may also include only a shell and a developer containing portion. It is additionally noted that the consumables may also be the aforementioned developer box or drum box. The aforementioned developer containing portion is used to contain developers such as toner, and the developer conveying element is a component such as a powder feeding roller, a powder feeding screw, etc., for stirring and / or conveying toner. Of course, the aforementioned developer box may also include only the aforementioned developer containing portion, which is not limited here. Furthermore, the aforementioned developer box may also include only the aforementioned developer containing portion and the developer conveying element, which is not limited here.

[0090] In one possible implementation, the consumables may also include a powder cartridge and / or an imaging component, and the powder cartridge is used to deliver toner to the imaging component when the toner contained in the imaging component is insufficient so that the image forming device forms an image based on the toner delivered by the imaging component. Wherein, when the consumable is a powder cartridge, the consumable may include only a housing and a developer containing portion, or may include a housing, a developer containing portion, and a developer conveying element, which is not limited in the embodiments of the present application. When the consumable is an imaging component, the consumable may include a housing, a developer containing portion, a developer conveying unit, a charging roller, a photosensitive drum, etc., which is not limited in the embodiments of the present application.

[0091] In the standard I2C protocol, when the I2C bus is idle, the host device outputs a high level, so that both the data line and the clock line remain in a high level state. When the host device needs to communicate with the slave device, it can pull the data line from a high level state to a low level state while the clock line remains in a high level state to generate a start signal, such as Figure 2A As shown; when the host device needs to stop communicating with the slave device, it can pull the data line from a low level state to a high level state while the clock line remains in a high level state to generate a stop signal, such as Figure 2B However, in actual applications, there may be some signal interference, resulting in abnormal fluctuations in the data line. For example, when the I2C bus is idle, both the data line and the clock line maintain a high level state. At this time, if there is a large voltage drop on the data line, the slave device will mistakenly recognize the start signal.

[0092] In view of the above problems, an embodiment of the present application provides a communication method, when the slave device detects that the I2C bus is in an idle state after the first preset time length is continuously maintained in the high level state, the data line is pulled down to a low level state. During the period when the slave device pulls the data line down to the low level state, no large abnormal fluctuations will be generated on the data line, thereby avoiding the slave device from mistakenly identifying the start signal. It can be understood that when the data line is pulled down to a low level by the slave device, the host device and the slave device cannot communicate through the I2C bus. In order to avoid affecting the normal communication requirements on the I2C bus, a release condition is set, and when the preset release condition is met, the data line is released, so that the data line is restored to a high level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0093] See also Figure 3 , is a flow chart of a communication method provided in an embodiment of the present application. The method can be applied to Figure 1 The slave device in the communication system shown is configured to communicate with the host device through at least a clock line and a data line on the bus. When the bus is in an idle state, the host device outputs a high level, so that the clock line and the data line remain in a high level state. Figure 3 As shown, it mainly includes the following steps.

[0094] Step S301: after detecting that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state.

[0095] In actual applications, the CPU of the slave device can usually only operate in a single thread and cannot process two things in parallel at the same time. Therefore, it is necessary to confirm that the current communication is completed after receiving a trigger signal of the communication protocol before starting the judgment on whether the data line needs to be lowered, and then execute step S301.

[0096] like Figure 4A and Figure 4BAs shown, in the standard I2C protocol, after sending a byte of data, the sender releases the data line and waits for the receiver to pull down the data line to send an ACK signal (a low-level data); after completing the reception of a byte of data, the receiver pulls down the data line to send an ACK signal. If the data has been transmitted, the host device will pull up the data line from a low level state to a high level state when the clock line is in a high level state, generate a stop signal, and indicate that the communication is stopped. Therefore, in the embodiment of the present application, the judgment of whether the data line needs to be pulled down can be started only after the slave device receives the stop signal. It can be understood that after the host device sends the stop signal, if the clock line remains in a high level state, it means that the I2C bus enters an idle state. Therefore, in the embodiment of the present application, after receiving the stop signal, the slave device starts to detect the duration of the clock line in the high level state. When the duration of the clock line in the high level state reaches the preset first duration, it is confirmed that the I2C bus enters an idle state, and then the data line is pulled down to a low level state.

[0097] In the embodiment of the present application, the slave device can start timing the first duration immediately after receiving the stop signal, that is, the starting point of the first duration is the moment when the slave device receives the stop signal; or it can delay the first duration for a certain period of time after receiving the stop signal, that is, the starting point of the first duration is the moment when the slave device delays for a certain period of time after receiving the stop signal. It can be understood that taking the moment when the slave device receives the stop signal as the starting point of the first duration can improve the sensitivity of the slave device to judge the idle state of the I2C bus.

[0098] Exemplarily, the first duration may be 3ms, 4ms, etc.; or, the first duration may be represented by the number of cycles of the clock signal, for example, the first duration may be 0.5 cycles or 1 cycle, etc. It is understandable that when the first duration is set to be shorter, the sensitivity of the slave device to the judgment of the idle state of the I2C bus is higher, but misjudgment may occur; when the first duration is set to be longer, the sensitivity of the slave device to the judgment of the idle state of the I2C bus is lower, but the reliability is higher. Therefore, those skilled in the art may set the size of the first duration according to actual needs, and the embodiments of the present application do not impose specific restrictions on this.

[0099] In the embodiment of the present application, after the slave device pulls the data line down to a low level state, no large abnormal fluctuation will occur on the data line, thereby preventing the slave device from erroneously recognizing the start signal.

[0100] Step S302: When a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0101] It is understandable that when the data line is pulled down to a low level by the slave device, the host device and the slave device cannot communicate through the I2C bus. In order to avoid affecting the normal communication on the I2C bus, it is also necessary to set a release condition. When the preset release condition is met, the slave device releases the data line, so that the data line returns to a high level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0102] In a possible implementation, when it is detected that the clock line switches from a high level state to a low level state, the data line is released so that the data line returns to a high level state. That is, in the embodiment of the present application, the release condition is: the clock line switches from a high level state to a low level state. For the sake of convenience, this release condition is referred to as the "first release condition".

[0103] It is understandable that when the host device needs to transmit data, it will restore the clock signal on the clock line, that is, convert the high-level signal on the clock line into a pulse signal that switches between high and low levels. In order to avoid affecting the normal communication on the I2C bus, when the host device restores the clock signal on the clock line, the slave device needs to release the data line immediately. Therefore, the first release condition is set to: the clock line switches from a high-level state to a low-level state. For example, in Figure 4A In the application scenario shown, when the slave device pulls the data line low for a period of time t0, the slave device detects the falling edge of the clock signal, indicating that the first release condition is met, and then releases the data line, so that the data line returns to a high level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0104] In a possible implementation, when the low level state of the data line continues for a second time period, the data line is released so that the data line returns to a high level state. That is, in the embodiment of the present application, the release condition is: the low level state of the data line continues for a second time period. For the sake of convenience, the release condition is referred to as the "second release condition". Figure 4B In the application scenario shown, when the slave device pulls the data line low for time t1, the pulling-down time is equal to the second time, indicating that the second release condition is met, and the data line is released, so that the data line returns to a high level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0105] Specifically, the second duration may be data preset in the slave device, or may be data carried in a data line pull-down instruction sent by the host device to the slave device. The embodiment of "the host device sends a data line pull-down instruction to the slave device" is described in detail below.

[0106] In a possible implementation, when it is detected that the clock line switches from a high level state to a low level state, or when the low level state of the data line continues for a second period of time, the data line is released so that the data line returns to a high level state. That is, the first release condition and the second release condition are set at the same time, and when any of the release conditions is met, the data line is released so that the data line returns to a high level state.

[0107] For example, in Figure 4A In the application scenario shown, the first release condition and the second release condition are set at the same time. When the slave device pulls the data line down for a duration of t0, the slave device detects the falling edge of the clock signal, and the first release condition is met. At this time, since the pull-down duration t0 is less than the second duration, the second release condition is not met. The embodiment of the present application directly releases the data line when the first release condition is met, so that the data line returns to a high level state.

[0108] For example, in Figure 4B In the application scenario shown, the first release condition and the second release condition are set at the same time. When the slave device pulls the data line down for a period of time t1, the pull-down period is equal to the second period, that is, the first release condition is met. At this time, since the slave device has not yet detected the falling edge of the clock signal, the first release condition has not yet been met. The embodiment of the present application directly releases the data line when the second release condition is met, so that the data line returns to a high level state.

[0109] Under normal circumstances, according to the setting of the second time duration, the second release condition is usually met first, that is, the end time of the second time duration is usually earlier than the time when the clock signal is restored, so as to leave sufficient idle time for the data line, so as not to affect the reception of the first instruction by the slave device after the data line is released.

[0110] In summary, in the embodiment of the present application, when the slave device detects that the I2C bus is in an idle state after the first preset time length is continuously maintained in the high level state, the data line is pulled down to a low level state. During the period when the slave device pulls the data line down to the low level state, no large abnormal fluctuation will be generated on the data line, thereby avoiding the slave device from mistakenly identifying the start signal. In addition, in order to avoid affecting the normal communication on the I2C bus, a release condition is set, and when the preset release condition is met, the data line is released, so that the data line is restored to a high level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0111] See also Figure 5 , is a flow chart of another communication method provided in an embodiment of the present application. The method can be applied to Figure 1 The communication system shown in Figure 5 As shown, it mainly includes the following steps.

[0112] Step S501: the host device sends the last instruction to the slave device.

[0113] In a possible implementation, the slave device needs to perform a data line pull-down operation based on the instruction of the host device. The last instruction sent by the host device to the slave device may be a data line pull-down instruction or other instructions. The slave device can determine the type of instruction only after parsing the instruction.

[0114] Step S502: After the slave device detects that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state.

[0115] It is understandable that it takes a certain amount of time, for example, 5ms, for the slave device to parse the instruction. If the slave device determines whether the condition of "the clock line is in a high level state for the first preset time" is met after parsing the last instruction, the response speed of the slave device will be slow. In order to improve the response speed of the slave device, the result of the analysis of the last instruction sent by the slave device to the host device is not considered first. When it is determined that the condition of "the clock line is in a high level state for the first preset time" is met, the data line is directly pulled down to a low level state.

[0116] Step S503: The slave device parses the last instruction sent by the host device.

[0117] Specifically, the slave device parses the last instruction sent by the host device to determine whether the last instruction sent by the host device is a data line pull-down instruction. If the last instruction is a data line pull-down instruction, the second duration is usually included in the last instruction, that is, the second duration is usually included in the data line pull-down instruction. Specifically, the second duration can be represented by the last two bytes of the data line pull-down instruction. For example, when the data line pull-down instruction is 65 31 00 22 in hexadecimal, the last two bytes are 00 22, which is 34 in decimal, and the second duration is 34ms.

[0118] Step S504: If the last instruction is a data line pull-down instruction, then when a preset release condition is met, the slave device releases the data line, so that the data line returns to a high level state.

[0119] Specifically, if the last instruction is a data line pull-down instruction, it means that the host device allows the slave device to execute the data line pull-down operation, then the slave device can keep pulling the data line down, and when the preset release condition is met, the slave device releases the data line, so that the data line returns to a high level state. The specific content of the release condition can be found in the above description, and for the sake of brevity, it will not be repeated here.

[0120] In a possible implementation, the data line pull-down instruction also includes the address information of the target slave device, that is, the host device only allows the target slave device to perform the data line pull-down operation. In this case, after receiving the data line pull-down instruction, the slave device also needs to determine whether the address information in the data line pull-down instruction matches the address information of the slave device itself. It can be understood that if the address information in the data line pull-down instruction matches the address information of the slave device itself, it means that the slave device is the target slave device, and the data line pull-down operation can be performed; if the address information in the data line pull-down instruction does not match the address information of the slave device itself, it means that the slave device is not the target slave device, and the data line pull-down operation cannot be performed.

[0121] Specifically, if the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction matches the address information of the slave device, it means that the host device allows the slave device to perform the data line pull-down operation, then the slave device can keep the data line in the state of pulling down, and when the preset release condition is met, release the data line so that the data line returns to the high level state. If the last instruction is a data line pull-down instruction, but the address information in the data line pull-down instruction does not match the address information of the slave device, it means that the host device does not allow the slave device to perform the data line pull-down operation. Since the slave device has performed the data line pull-down operation in the above step S502, the slave device needs to release the data line immediately at this time, or release the data line after a delay of a period of time.

[0122] For example, in Figure 1 In the application scenario shown, the last instruction sent by the host device is a data line pull-down instruction, and the address information of the target slave device in the data line pull-down instruction is the address information of slave device 2, that is, the host device instructs slave device 2 to perform a data line pull-down operation. It can be understood that all slave devices mounted on the I2C bus can receive the data line pull-down instruction sent by the host device.

[0123] When slave device 2 receives the data line pull low instruction, it determines that the address information in the data line pull low instruction matches the address information of slave device 2, indicating that the host device allows slave device 2 to perform the data line pull low operation. Then slave device 2 can keep the data line pulled low and release the data line when the preset release condition is met.

[0124] When other slave devices, such as slave device 1, receive the data line pull low instruction, it is determined that the address information in the data line pull low instruction matches the address information of slave device 1, indicating that the host device does not allow slave device 1 to perform the data line pull low operation, then slave device 1 releases the data line immediately, or releases the data line after a delay.

[0125] In a possible implementation, the slave device releases the data line after a delay, specifically including: the slave device starts timing after executing the data line pull-down operation, and releases the data line after timing to a preset time, that is, achieving the effect of "releasing the data line after a delay". It should be noted that the preset time should be greater than the time required for the slave device to parse the last instruction.

[0126] Step S505: If the last instruction is not a data line pull-down instruction, the slave device releases the data line.

[0127] Specifically, if the last instruction is not a data line pull-down instruction, it means that the host device does not allow the slave device to execute the data line pull-down operation. Since the slave device has executed the data line pull-down operation in the above step S502, the slave device needs to release the data line immediately or release the data line after a delay.

[0128] It should be noted that in some possible implementations, the slave device may not perform the data line pull-down operation based on the instruction of the host device. That is, when the slave device determines that the condition of "the clock line is in a high level state for a preset first period of time" is met, it directly performs the data line pull-down operation without being restricted by other conditions.

[0129] See also Figure 6 , is a flow chart of another communication method provided in an embodiment of the present application. The method can be applied to Figure 1 The host device, such as Figure 6 As shown, it mainly includes the following steps.

[0130] Step S601: the host device sends a data line pull-down instruction.

[0131] Specifically, the data line pull-down instruction includes the second duration and the address information of the target slave device. The data line pull-down instruction is used to instruct the target slave device to pull the data line down to a low level state for the second duration, wherein the target slave device is any slave device among the at least one slave device.

[0132] It should be pointed out that the specific content of the target slave device pulling down the data line can be found in the above description, and for the sake of brevity, it will not be repeated here.

[0133] Step S602: Detect the duration of the low level state on the data line to obtain a third duration.

[0134] It can be understood that if the target slave device is a legitimate device, it can usually correctly perform the pull-down operation of the data line, that is, it can usually pull the data line down to a low level state according to the instruction of the data line pull-down instruction, and it lasts for the second duration; if the target slave device is an illegal device, it usually cannot correctly perform the pull-down operation of the data line, that is, it usually does not pull the data line down to a low level state according to the instruction of the data line pull-down instruction, and it lasts for the second duration. Based on this principle, the host device can determine whether to pass the authentication of the target slave device by detecting the duration of the low level state on the data line (i.e., the pull-down duration). For ease of explanation, the duration of the low level state detected by the host device on the data line is referred to as the "third duration".

[0135] Step S603: If the third time length matches the second time length, the target slave device is authenticated.

[0136] Specifically, if the third duration matches the second duration, it means that the target slave device correctly executes the data line pull-down operation, and the target slave device is a legal device, and the authentication of the target slave device is passed.

[0137] Step S604: If the third time length does not match the second time length, the target slave device is not authenticated.

[0138] Specifically, if the third duration does not match the second duration, it means that the target slave device does not correctly perform the pull-down operation of the data line, and the target slave device is an illegal device, and the authentication of the target slave device fails.

[0139] In a possible implementation, the data line pull-down instruction may not include the address information of the target slave device, but only include the second duration. It is understandable that after each slave device on the data line receives the data line pull-down instruction, it can perform the data line pull-down operation. It is understandable that if any slave device correctly performs the data line pull-down operation, the third duration detected by the host device on the data line matches the second duration. If the third duration detected by the host device on the communication bus does not match the second duration, it means that all slave devices mounted on the communication bus are illegal devices.

[0140] In the embodiment of the present application, the host device authenticates the slave device based on the duration of the pull-down of the data line, thereby preventing the slave device from mistakenly recognizing the start signal and ensuring the security of the communication process.

[0141] See also Figure 7 , is a flow chart of another communication method provided in an embodiment of the present application. The method can be applied to Figure 1 The host device, such as Figure 7 As shown, it mainly includes the following steps.

[0142] Step S701: the host device sends a data line pull-down instruction.

[0143] Specifically, the data line pull-down instruction includes the second duration and the address information of the target slave device. The data line pull-down instruction is used to instruct the target slave device to pull the data line down to a low level state for the second duration, wherein the target slave device is any slave device among the at least one slave device.

[0144] It should be pointed out that the specific content of the target slave device executing the data line pull-down operation can be found in the above description, and for the sake of brevity, it will not be repeated here.

[0145] Step S702: When the data line is in a low level state, detecting the voltage value on the data line.

[0146] Specifically, since there are voltage divider resistors between the physical installation positions of multiple slave devices on the I2C bus, the voltage values ​​when the slave devices at different physical positions actually pull down the data line are different. Based on this principle, the physical position of the slave device can be determined. Specifically, when the data line is in a low level state, the voltage value on the data line is detected.

[0147] Step S703: Determine the physical location of the target slave device according to the voltage value.

[0148] It can be understood that after the host device sends the data line pull-down instruction, the target slave device performs the data line pull-down operation. Therefore, the voltage value detected by the host device when the data line is in a low level state reflects the physical position of the target slave device. Specifically, a mapping relationship between the voltage value and the physical position may also be provided in the host device, and then after obtaining the voltage value, the physical position of the target slave device can be determined according to the voltage value and the mapping relationship between the voltage value and the physical position.

[0149] In the embodiment of the present application, the host device determines the physical position of the target slave device based on the voltage value of the data line when it is in a low level state, thereby preventing the slave device from mistakenly recognizing the start signal and identifying the physical position of the slave device.

[0150] Corresponding to the above method embodiment, the embodiment of the present application further provides a slave device, which is configured to communicate with the host device through at least a clock line and a data line on the bus. When the bus is in an idle state, the host device outputs a high level so that the clock line and the data line remain in a high level state, and the slave device is configured to execute some or all of the steps executed by the slave device side in the above method embodiment.

[0151] For specific contents involved in the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0152] Corresponding to the above method embodiment, the embodiment of the present application further provides a host device, which is configured to communicate with at least one slave device through at least a clock line and a data line on a bus. When the bus is in an idle state, the host device outputs a high level so that the clock line and the data line remain in a high level state, and the host device is configured to execute some or all of the steps executed by the host device side in the above method embodiment.

[0153] For specific contents involved in the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0154] It is understandable that, in a specific implementation, the control logic in the above method embodiment can be implemented by software in the slave device. In addition, part or all of the control logic in the above method embodiment can also be implemented by designing corresponding hardware circuits. Specifically, the slave device includes an electronic module, which is configured to execute part or all of the steps executed by the slave device side in the above method embodiment.

[0155] For specific contents involved in the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0156] See also Figure 8 , is a structural block diagram of a slave device provided in an embodiment of the present application. Figure 8 As shown, the electronic module of the slave device includes a control unit 810 and peripheral circuits.

[0157] The control unit 810 is configured to communicate with the host device at least through the clock line and the data line on the bus. When the bus is in an idle state, the host device outputs a high level so that the clock line and the data line remain in a high level state. Specifically, the control unit 810 includes an interface module, and the interface module includes four interfaces: VCC, GND, SDA, and CLK. The VCC interface and the GND interface are used to connect the power line to provide power to the slave device; the SDA interface is used to connect the data line, and the CLK is used to connect the clock line to realize the communication connection between the slave device and the host device. Exemplarily, the control unit 810 can be an MCU, FPGA, CPU, DSP, etc., and the embodiments of the present application do not impose specific restrictions on this.

[0158] The peripheral circuit is configured to: pull the data line down to a low level state when detecting that the clock line is in a high level state for a preset first period of time; and release the data line when a preset release condition is met, so that the data line returns to a high level state.

[0159] For specific contents involved in the embodiments of the present application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0160] See also Fig. 9 , is a structural block diagram of another slave device provided in an embodiment of the present application. Fig. 9 As shown, the embodiment of the present application is Figure 8 On the basis of the illustrated embodiment, the peripheral circuit specifically includes a trigger unit 820 and a switch unit 830 .

[0161] The first end 820A of the trigger unit 820 is electrically connected to the clock line, and the trigger unit 820 is configured as follows: when the clock line is in a high-level state for a preset first period of time, the second end 820B of the trigger unit 820 outputs a first control signal; when the clock line switches from a high-level state to a low-level state, the second end 820B of the trigger unit 820 outputs a second control signal.

[0162] The first end 830A of the switch unit 830 is electrically connected to the data line, the second end 830B of the switch unit 830 is connected to a reference potential (for example, ground), and the control end 830C of the switch unit 830 is electrically connected to the second end 820B of the trigger unit 820. The switch unit 830 is configured as follows: when the control end 830C of the switch unit 830 receives a first control signal output by the second end 820B of the trigger unit 820, the switch unit 830 is turned on and the data line is pulled down to a low level state; when the control end 830C of the switch unit 830 receives a second control signal output by the second end 820B of the trigger unit 820, the switch unit 830 is turned off, the data line is released, and the data line is restored to a high level state.

[0163] It can be understood that according to the above configuration of the trigger unit 820 and the switch unit 830, when the trigger unit 820 detects that the clock line is in a high-level state for a preset first period of time, it can output a first control signal to turn on the switch unit 830, thereby pulling the data line down to a low-level state. When the trigger unit 820 detects that the clock line switches from a high-level state to a low-level state (satisfying the first release condition), it can output a second control signal to turn off the switch unit 830, thereby releasing the data line, and the data line returns to a high-level state.

[0164] That is to say, in the embodiment of the present application, the control logic of "when the clock line is in a high-level state for a preset first period of time, the data line is pulled down to a low-level state; when the clock line switches from a high-level state to a low-level state, the data line is released and the data line returns to a high-level state" can be implemented through the trigger unit 820 and the switch unit 830.

[0165] See also Fig.10 , is a structural block diagram of another slave device provided in an embodiment of the present application. Fig.10As shown, in the embodiment of the present application, the trigger unit 820 includes a first resistor R1, a diode D and a capacitor C. The first end of the first resistor R1 is electrically connected to the clock line; the cathode of the diode D is electrically connected to the clock line; the first end of the capacitor C is electrically connected to the second end of the first resistor R1 and the anode of the diode D, respectively, and the second end of the capacitor C is connected to the reference potential. The switch unit 830 includes a third resistor R3 and a transistor T. The first end of the third resistor R3 is electrically connected to the data line; the first end of the transistor T is electrically connected to the second end of the third resistor R3, the second end of the transistor T is connected to the reference potential, and the control end of the transistor T is electrically connected to the first end of the capacitor C.

[0166] In an embodiment of the present application, when the clock line is in a high level state, the first resistor R1 takes power on the clock line and continues to charge the capacitor C. When the duration of the high level state on the clock line reaches the set duration (first duration) required for the capacitor C to be fully charged, the capacitor C is fully charged. At this time, the voltage at the first end of the capacitor C can reach the on-voltage threshold of the transistor T, so that the transistor T is turned on, and the data line is discharged by connecting the reference potential through the third resistor R3 and the transistor T, thereby pulling the data line down to a low level state. When the clock signal on the clock line is restored, a low level signal (satisfying the first release condition) is generated on the clock line, and the capacitor C is discharged to the clock line through the first resistor R1 and the diode D. Since the discharge speed after the diode D is turned on is fast, the voltage at the first end of the capacitor C will be quickly reduced. When the voltage at the first end of the capacitor C is lower than the on-voltage threshold of the transistor T, the transistor T is turned off, thereby releasing the control of the data line, so that the data line is restored to a high level state.

[0167] That is to say, through Fig.10 The circuit structure of the trigger unit 820 and the switch unit 830 shown can realize the control logic of "when the clock line is in a high level state for a preset first time period, the data line is pulled down to a low level state; when the clock line switches from a high level state to a low level state, the data line is released and the data line is restored to a high level state". It should be supplemented that, in the embodiment of the present application, the first end 820A of the trigger unit 820 is "the first end of the first resistor R1 and the negative electrode of the diode D"; the second end 820B of the trigger unit 820 is "the first end of the capacitor C"; the first end 830A of the switch unit 830 is "the first end of the third resistor R3"; the second end 830B of the switch unit 830 is "the second end of the transistor T"; and the control end 830C of the switch unit 830 is "the control end of the transistor T". The first control signal output by the second end 820B of the trigger unit 820 is "the high level signal generated by the first end of the capacitor C"; the second control signal output by the second end 820B of the trigger unit 820 is "the low level signal generated by the first end of the capacitor C".

[0168] In addition, in practical applications, those skilled in the art can modify Fig.10 The circuit structure of the trigger unit 820 and / or the switch unit 830 shown is adaptively adjusted to achieve the same functions as the trigger unit 820 and / or the switch unit 830 in the present application, which should all fall within the protection scope of the present application.

[0169] For example, other unidirectional conducting elements (e.g., transistors) may be used instead of Fig.10 The diode D in the trigger unit 820 shown in FIG. Fig.10 The connection relationship in the circuit shown is: the first end of the unidirectional conductive element is electrically connected to the clock line, the second end of the unidirectional conductive element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conductive element is unidirectionally conductive to the first end of the unidirectional conductive element.

[0170] For example, Fig.10 The unidirectional conductive element (diode D) in the trigger unit 820 shown in the figure is removed. It should be supplemented that, since the discharge speed of the unidirectional conductive element is faster after being turned on, after the unidirectional conductive element is set, when a low-level signal is generated on the clock line, the discharge speed of the capacitor C can be increased, thereby improving the response speed of the trigger unit 820.

[0171] For example, Fig.10 The third resistor R3 in the switch unit 830 shown is removed. It should be supplemented that, when the third resistor R3 in the switch unit 830 is removed, the first end of the transistor T is directly connected to the data line. At this time, the first end of the transistor T is the first end 830A of the switch unit 830. In addition, in the embodiment of the present application, the function of the third resistor R3 is to limit the current to prevent the data line from burning. However, when the reference potential connected to the second end 830B of the switch unit 830 is high (non-grounded), the current flowing through the data line itself will not be too large, and there is no need to worry about burning the data line. Therefore, in some application scenarios, removing the third resistor R3 in the switch unit 830 will not affect the operation of the entire circuit.

[0172] It should be pointed out that the above Fig.10 The adjustment of the trigger unit 820 and the switch unit 830 shown is only an exemplary description of the embodiment of the present application. Those skilled in the art may also adjust the trigger unit 820 and the switch unit 830 according to actual needs. Fig.10 The trigger unit 820 and / or the switch unit 830 shown perform other types of adjustments, which are not specifically limited in the embodiments of the present application.

[0173] Understandably, according to Fig. 9 and Fig.10The circuit structure shown can only release the data line when the first release condition is met (the clock line switches from a high level state to a low level state). As described above, in addition to the first release condition, a second release condition can also be set (the low level state of the data line lasts for a second duration). In order to allow the slave device to release the data line when the second release condition is met, the embodiment of the present application configures the second release condition in the control unit 810, and when the second release condition is met, the trigger unit 820 is intervened through an I / O port on the control unit 810, so that the trigger unit 820 outputs a second control signal, thereby releasing the data line. Detailed description is given below in conjunction with a specific implementation method.

[0174] See also Fig.11 , is a structural block diagram of another slave device provided in an embodiment of the present application. Fig.11 As shown, the embodiment of the present application is Fig. 9 On the basis of the illustrated embodiment, the control unit 810 further includes a first terminal 810A, and the first terminal 810A of the control unit 810 is an I / O port. The trigger unit 820 further includes a controlled terminal 820C, and the controlled terminal 820C of the trigger unit 820 is electrically connected to the first terminal 810A of the control unit 810. It can be understood that the control unit 810 can control the output state of the I / O port (for example, floating state, low level state, etc.), and then the trigger unit 820 can be intervened through the output state of the first terminal 810A of the control unit 810.

[0175] Specifically, the first end 810A of the control unit 810 maintains the first state (for example, floating state) by default. In the first state, the controlled end 810C of the control unit 810 is in an uncontrolled state, and the trigger unit 820 can realize the trigger function of the switch unit 830, that is, it can trigger the switch unit 830 to turn on and pull the data line down to a low level state. Specifically, the trigger unit 820 outputs a first control signal according to its own configuration after detecting that the clock line is in a high level state for a preset first time period, so that the switch unit 830 is turned on and the data line is pulled down to a low level state. In addition, in the uncontrolled state, when the trigger unit 820 detects that the clock line switches from a high level state to a low level state (satisfying the first release condition), it can also output a second control signal, so that the switch unit 830 is disconnected, the data line is released, and the data line is restored to a high level state.

[0176] When the control unit 810 detects that the low level state of the data line continues for a second time period (satisfying the second release condition), the first end 810A of the control unit 810 is switched from the first state to the second state (for example, the low level state). In the second state, the controlled end 810C of the control unit 810 is in a controlled state, and the trigger unit 820 cannot realize the trigger function of the switch unit 830, so that the switch unit 830 remains in the disconnected state. Specifically, the trigger unit 820 is no longer affected by the level state of the clock line, the trigger unit 820 continues to output the second control signal, the switch unit 830 is disconnected, the data line is released, and the data line remains in a high level state. That is to say, in the embodiment of the present application, when any of the first release condition and the second release condition is met, the data line is released, so that the data line is restored to a high level state.

[0177] In the embodiment of the present application, the control logic of "when the clock line is in a high-level state for a preset first period of time, the data line is pulled down to a low-level state; when the clock line switches from a high-level state to a low-level state, or when the low-level state of the data line continues for a second period of time, the data line is released and the data line returns to a high-level state" can be implemented through the control unit 810, the trigger unit 820 and the switch unit 830.

[0178] See also Fig.12 , is a structural block diagram of another slave device provided in an embodiment of the present application. Fig.12 As shown, in the embodiment of the present application, the trigger unit 820 includes a first resistor R1, a diode D, a second resistor R2 and a capacitor C. The first end of the first resistor R1 is electrically connected to the clock line; the cathode of the diode D is electrically connected to the clock line; the first end of the second resistor R2 is electrically connected to the first end of the control unit 810; the first end of the capacitor C is electrically connected to the second end of the first resistor R1, the anode of the diode D and the second end of the second resistor R2, respectively, and the second end of the capacitor C is connected to the reference potential. The switch unit 830 includes a third resistor R3 and a transistor T. The first end of the third resistor R3 is electrically connected to the data line; the first end of the transistor T is electrically connected to the second end of the third resistor R3, the second end of the transistor T is connected to the reference potential, and the control end of the transistor T is electrically connected to the first end of the capacitor C.

[0179] In an embodiment of the present application, the first end 810A of the control unit 810 is kept in a floating state by default. It is understandable that when the first end 810A of the control unit 810 is in a floating state, it will not affect the trigger unit 820. Therefore, when the clock line is in a high level state, the first resistor R1 takes power on the clock line and continues to charge the capacitor C. When the duration of the high level state on the clock line reaches the set duration (first duration) required for the capacitor C to be fully charged, the capacitor C is fully charged. At this time, the voltage at the first end of the capacitor C can reach the turn-on voltage threshold of the transistor T, so that the transistor T is turned on, and the data line is discharged by connecting the reference potential through the third resistor R3 and the transistor T, thereby pulling the data line down to a low level state.

[0180] Thereafter, when the clock signal on the clock line is restored, a low level signal is generated on the clock line (satisfying the first release condition), and the capacitor C discharges to the clock line through the first resistor R1 and the diode D. Since the discharge speed of the diode D is fast after being turned on, the voltage at the first end of the capacitor C will decrease rapidly. When the voltage at the first end of the capacitor C is lower than the turn-on voltage threshold of the transistor T, the transistor T is turned off, thereby releasing the control over the data line, so that the data line is restored to a high level state.

[0181] When the control unit 810 detects that the low level state of the data line lasts for a second time period (satisfying the second release condition), the first terminal 810A of the control unit 810 is switched from a floating state to a low level state. At this time, the voltage at the first terminal of the capacitor C decreases rapidly. When the voltage at the first terminal of the capacitor C is lower than the turn-on voltage threshold of the transistor T, the transistor T is turned off, thereby releasing the control of the data line, so that the data line remains in a high level state.

[0182] That is to say, through Fig.12 The software configuration of the control unit 810 and the circuit structure of the trigger unit 820 and the switch unit 830 shown can realize the control logic of "when the clock line is in a high-level state for a preset first period of time, the data line is pulled down to a low-level state; when the clock line switches from a high-level state to a low-level state, or when the low-level state of the data line continues for a second period of time, the data line is released and the data line returns to a high-level state".

[0183] It should be noted that, in the embodiment of the present application, the first end 820A of the trigger unit 820 is "the first end of the first resistor R1 and the negative electrode of the diode D"; the second end 820B of the trigger unit 820 is "the first end of the capacitor C"; the controlled end 820C of the trigger unit 820 is "the first end of the second resistor R2"; the first end 830A of the switch unit 830 is "the first end of the third resistor R3"; the second end 830B of the switch unit 830 is "the second end of the transistor T"; the control end 830C of the switch unit 830 is "the control end of the transistor T". The first state of the first end 810A of the control unit 810 is "high impedance state"; the second state of the first end 810A of the control unit 810 is "low level state". The first control signal output by the second end 820B of the trigger unit 820 is "the high level signal generated by the first end of the capacitor C"; the second control signal output by the second end 820B of the trigger unit 820 is "the low level signal generated by the first end of the capacitor C".

[0184] In addition, in practical applications, those skilled in the art can modify Fig.12 The circuit structure of the trigger unit 820 and / or the switch unit 830 shown is adaptively adjusted to achieve the same functions as the trigger unit 820 and / or the switch unit 830 in the present application, which should all fall within the protection scope of the present application.

[0185] For example, other unidirectional conducting elements (e.g., transistors) may be used instead of Fig.12 The diode D in the trigger unit 820 shown in FIG. Fig.12 The connection relationship in the circuit shown is: the first end of the unidirectional conductive element is electrically connected to the clock line, the second end of the unidirectional conductive element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conductive element is unidirectionally conductive to the first end of the unidirectional conductive element.

[0186] For example, Fig.12 The unidirectional conductive element (diode D) in the trigger unit 820 shown in the figure is removed. It should be supplemented that, since the discharge speed of the unidirectional conductive element is faster after being turned on, after the unidirectional conductive element is set, when a low-level signal is generated on the clock line, the discharge speed of the capacitor C can be increased, thereby improving the response speed of the trigger unit 820.

[0187] For example, Fig.12The third resistor R3 in the switch unit 830 shown is removed. It should be supplemented that, when the third resistor R3 in the switch unit 830 is removed, the first end of the transistor T is directly connected to the data line. At this time, the first end of the transistor T is the first end 830A of the switch unit 830. In addition, in the embodiment of the present application, the function of the third resistor R3 is to limit the current to prevent the data line from burning. However, when the reference potential connected to the second end 830B of the switch unit 830 is high (non-grounded), the current flowing through the data line itself will not be too large, and there is no need to worry about burning the data line. Therefore, in some application scenarios, removing the third resistor R3 in the switch unit 830 will not affect the operation of the entire circuit.

[0188] It should be pointed out that the above Fig.12 The adjustment of the trigger unit 820 and the switch unit 830 shown is only an exemplary description of the embodiment of the present application. Those skilled in the art may also adjust the trigger unit 820 and the switch unit 830 according to actual needs. Fig.12 The trigger unit 820 and / or the switch unit 830 shown perform other types of adjustments, which are not specifically limited in the embodiments of the present application.

[0189] It should be noted that in Figure 8-Figure 12 In the illustrated embodiment, some contents that are repeated in the above method embodiment are omitted. Figure 8-Figure 12 The specific content of the illustrated embodiment can be found in the description of the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0190] Corresponding to the above embodiment, the embodiment of the present application also provides a replaceable accessory.

[0191] See also Fig.13 , a structural block diagram of a replaceable accessory is also provided for the embodiment of the present application. Fig.13 As shown, the replaceable component 1300 includes a slave device. The specific content of the slave device can be found in the description of the above embodiment, and will not be repeated here for the sake of brevity.

[0192] Corresponding to the above embodiment, the embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein when the program is running, the device where the computer-readable storage medium is located may be controlled to perform some or all of the steps in the above method embodiment. In a specific implementation, the computer-readable storage medium may be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0193] Corresponding to the above-mentioned embodiment, the embodiment of the present application further provides a computer program product, which includes executable instructions. When the executable instructions are executed on a computer, the computer executes some or all of the steps in the above-mentioned method embodiment.

[0194] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0195] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0196] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0197] In several embodiments provided in the present application, any function can be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., and other media that can store program codes.

[0198] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A slave device, the slave device being configured to communicate with a host device at least through a clock line and a data line on a bus, and being outputted a high level by the host device when the bus is in an idle state, characterized in that: The slave device is configured as: When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state; When a preset release condition is met, the data line is released so that the data line returns to a high level state.

2. The slave device according to claim 1, characterized in that: When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: When it is detected that the clock line switches from a high level state to a low level state, the data line is released so that the data line returns to a high level state.

3. The slave device according to claim 1, characterized in that: When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: When the low level state of the data line continues for a second time period, the data line is released so that the data line returns to a high level state.

4. The slave device according to claim 1, characterized in that: When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: When it is detected that the clock line switches from a high level state to a low level state, or when the low level state of the data line continues for a second period of time, the data line is released so that the data line returns to a high level state.

5. The slave device according to claim 3 or 4, characterized in that: When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: Parsing the last instruction sent by the host device; If the last instruction is a data line pull-down instruction, then when a preset release condition is met, the data line is released so that the data line returns to a high level state; If the last instruction is not a data line pull-down instruction, releasing the data line after a preset delay time; The data line pull-down instruction includes the second duration, and the preset time is less than the second duration.

6. The slave device according to claim 5, characterized in that: If the last instruction is a data line pull-down instruction, then when a preset release condition is met, the data line is released so that the data line is restored to a high level state, including: If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction matches the address information of the slave device, then when a preset release condition is met, the data line is released so that the data line is restored to a high level state; If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction does not match the address information of the slave device, the data line is released after a preset delay.

7. The slave device according to claim 1, characterized in that: The step of pulling the data line down to a low level state after detecting that the clock line is in a high level state for a preset first time period comprises: The timing starts when a stop signal sent by the host device is received, and after the high level state of the clock line continues for a preset first time period, the data line is pulled down to a low level state.

8. A slave device, characterized in that: include: An electronic module, the electronic module being configured to: The bus is at least connected to the host device through a clock line and a data line on the bus, and when the bus is in an idle state, the host device outputs a high level; When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state; When a preset release condition is met, the data line is released so that the data line returns to a high level state.

9. The slave device according to claim 8, characterized in that: The electronic module comprises: A control unit, the control unit being configured to: be communicatively connected with a host device at least via a clock line and a data line on a bus, and be outputted by the host device at a high level when the bus is in an idle state; The peripheral circuit is configured to: pull the data line down to a low level state after detecting that the clock line is in a high level state for a preset first period of time; and release the data line when a preset release condition is met, so that the data line returns to a high level state.

10. The slave device according to claim 9, characterized in that: The peripheral circuit comprises: A trigger unit, wherein a first end of the trigger unit is electrically connected to the clock line, and the trigger unit is configured to: when the clock line is in a high level state for a preset first time period, the second end of the trigger unit outputs a first control signal; when the clock line switches from a high level state to a low level state, the second end of the trigger unit outputs a second control signal; A switch unit, wherein a first end of the switch unit is electrically connected to the data line, a second end of the switch unit is connected to a reference potential, a control end of the switch unit is electrically connected to the second end of the trigger unit, and the switch unit is configured as follows: when the control end of the switch unit receives a first control signal output by the second end of the trigger unit, the switch unit is turned on to pull the data line down to a low level state; when the control end of the switch unit receives a second control signal output by the second end of the trigger unit, the switch unit is turned off, the data line is released, and the data line is restored to a high level state.

11. The slave device according to claim 10, characterized in that: The trigger unit comprises: a first resistor, wherein a first end of the first resistor is electrically connected to the clock line; a capacitor, wherein a first end of the capacitor is electrically connected to a second end of the first resistor, and a second end of the capacitor is connected to a reference potential; The first end of the first resistor is the first end of the trigger unit, and the first end of the capacitor is the second end of the trigger unit.

12. The slave device according to claim 10, characterized in that: The first end of the control unit is electrically connected to the controlled end of the trigger unit, and the control unit is further used to: when the low level state of the data line lasts for a second time period, control the first end of the control unit to switch from the first state to the second state; The trigger unit is also configured as follows: when the first end of the control unit is in the first state, the controlled end of the trigger unit is in an uncontrolled state, and the trigger unit can implement the trigger function of the switch unit; when the first end of the control unit is in the second state, the controlled end of the trigger unit is in a controlled state, and the trigger unit cannot implement the trigger function of the switch unit, so that the switch unit remains in a disconnected state.

13. The slave device according to claim 12, characterized in that: The trigger unit comprises: a first resistor, wherein a first end of the first resistor is electrically connected to the clock line; a second resistor, wherein a first end of the second resistor is electrically connected to a first end of the control unit; A capacitor, wherein a first end of the capacitor is electrically connected to a second end of the first resistor and a second end of the second resistor respectively, and a second end of the capacitor is connected to a reference potential; The first end of the first resistor is the first end of the trigger unit, the first end of the capacitor is the second end of the trigger unit, and the first end of the second resistor is the controlled end of the trigger unit.

14. The slave device according to claim 11 or 13, characterized in that: The trigger unit also includes: A unidirectional conductive element, wherein a first end of the unidirectional conductive element is electrically connected to the clock line, a second end of the unidirectional conductive element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conductive element is unidirectionally conductive to the first end of the unidirectional conductive element.

15. The slave device according to claim 11 or 13, characterized in that: The switch unit comprises: a transistor, wherein a first terminal of the transistor is electrically connected to the data line, a second terminal of the transistor is connected to a reference potential, and a control terminal of the transistor is electrically connected to a first terminal of the capacitor; The first end of the transistor is the first end of the switch unit, the second end of the transistor is the second end of the switch unit, and the control end of the transistor is the control end of the switch unit.

16. The slave device according to claim 15, characterized in that: The switch unit further comprises: a third resistor, wherein a first end of the third resistor is electrically connected to the data line, and a second end of the third resistor is electrically connected to the first end of the transistor; Wherein, the first end of the third resistor is the first end of the switch unit.

17. A replaceable accessory, characterized in that: The invention comprises the slave device according to any one of claims 1 to 16.

18. A communication method, applied to a slave device, wherein the slave device is configured to communicate with a host device at least through a clock line and a data line on a bus, and when the bus is in an idle state, the host device outputs a high level, characterized in that: The method comprises: When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state; When a preset release condition is met, the data line is released so that the data line returns to a high level state.

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