Processor identification

Abstract

The invention relates to processor identification. The present description relates to a device comprising: a bus; a peripheral device coupled to the bus, the peripheral device including a first circuit; a processor coupled to the bus and initiating access to the peripheral device, each access including an address phase and a subsequent data phase; and for each processor, a second circuit that delivers an identifier of the processor on the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores an identifier present on the bus during an address phase of the access and then delivers the identifier stored on the bus during a data phase of the access.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French Patent Application No. 2311953, filed on November 3, 2023, entitled “Identification de processeurs”, which is hereby incorporated by reference to the maximum extent permitted by law. Technical Field

[0003] The present description relates generally to electronic circuits and, more particularly, to systems on a chip (SOCs) including multiple processors. Background Art

[0004] Known devices or systems on a chip include multiple processors that are configured to execute the same instruction set. In such devices, the processor is coupled (e.g., connected) to a bus to enable read and / or write access to peripheral devices coupled (e.g., connected) to the bus.

[0005] In some of these known devices, read and / or write access to each peripheral device is subject to the identity of the processor initiating this access. Each processor is then identified by a unique identifier that is different from the identifiers of the other processors. In order to achieve this, each processor is associated with an identification circuit that communicates or delivers the processor's identifier on the bus each time the processor initiates access to the peripheral device via the bus. Thus, when the peripheral device receives an access request, it verifies whether the identifier of the processor initiating this access corresponds to the identifier of the processor that has the authorization to access this peripheral device.

[0006] Thus, it is possible to define compartments within a device, each compartment comprising a processor and all peripherals that the processor is authorized to access.The identifier of each processor (delivered by an identification circuit associated with this processor) is for example called a compartment identifier.

[0007] These known compartmentalized devices have various disadvantages. Summary of the invention

[0008] There is a need to overcome all or some of the disadvantages of the known compartmentalized devices described above.

[0009] For example, it would be desirable to have a compartmentalized device of the type described above, where each processor would be able to obtain its compartment identifier.

[0010] Embodiments overcome all or part of the disadvantages of the known compartmentalized devices described above.

[0011] An embodiment provides a device comprising: a bus; a peripheral device coupled to the bus, the peripheral device comprising a first circuit; a processor coupled to the bus and configured to execute the same instruction set and initiate access to the peripheral device via the bus, each access comprising an address phase and a subsequent data phase; and for each processor, a second circuit associated with the processor and configured to provide an identifier of the processor on the bus during the address phase of each access initiated by the processor, wherein the first circuit is configured to store the identifier present on the bus during the address phase of each read access to the first circuit initiated by one of the processors, and to provide the stored identifier to the bus during the data phase of the access.

[0012] Another embodiment provides a method implemented in a device, the device comprising: a bus; a peripheral device connected to the bus and comprising a first circuit; processors coupled to the bus, executing the same instruction set, each processor being associated with a second circuit and initiating access to the peripheral device via the bus, each access comprising an address phase and a subsequent data phase, the method comprising: initiating a read access to the first circuit using one of the processors, providing an identifier of the processor to the bus during the address phase of the access and using the second circuit associated with the processor initiating the access, storing an identifier present on the bus using the first circuit during the address phase of the access, and providing the stored identifier to the bus using the first circuit and during the data phase of the access.

[0013] According to an embodiment, the peripheral device includes a memory shared between at least two processors among the processors, and a program defined by an instruction sequence of an instruction set is stored in the memory and is accessible by the at least two processors.

[0014] According to an embodiment, the program comprises at least a portion whose execution is subject to an identifier of a processor executing the program.

[0015] According to an embodiment, for each access by one of the processors to one of the peripheral devices other than the first circuit, the device is configured to restrict access to the peripheral device based on an identifier of the processor that has initiated the access.

[0016] According to an embodiment, the first circuit includes a register configured to store, during an address phase of each read access to the first circuit, an identifier present on a bus and corresponding to a processor that has initiated the read access, and to provide, during a data phase of each read access to the first circuit, the identifier stored during the address phase of the read access to the bus.

[0017] According to an embodiment, each identifier corresponds to a different processor.

[0018] According to an embodiment, read and write access to the second circuit is not possible.

[0019] According to an embodiment, the bus is of AMBA type.

[0020] According to an embodiment, the identifier of each processor is hard-coded in the second circuit associated with this processor.

[0021] According to an embodiment, the first circuit is read-only accessible. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0023] Figure 1 Examples of devices to which the described embodiments and variations thereof are applicable are shown in block form;

[0024] Figure 2 An example of an embodiment of the apparatus is shown in block form;

[0025] Figure 3 The flowchart shows the Figure 2 An example of an embodiment of a method implemented in a device of; and

[0026] Figure 4 Shown in the form of a box Figure 2 An example of a detailed embodiment of the circuit of the device. DETAILED DESCRIPTION

[0027] Similar features in the various figures have been denoted by similar reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties.

[0028] For clarity, only those steps and elements that are useful for understanding the embodiments are shown and described in detail.

[0029] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0030] In the following description, when absolute position qualifiers (such as "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as "top", "bottom", "upper", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.) are mentioned, unless otherwise specified, they refer to the orientation of the drawing.

[0031] Unless otherwise specified, the expressions “about”, “approximately”, “substantially” and “around” mean plus or minus 10%, preferably plus or minus 5%.

[0032] Figure 1 An example of a system-on-chip or device 1 to which the described embodiments and variants are applicable is shown in block form.

[0033] The device 1 comprises N processors CPUi, where N is an integer greater than or equal to 2, and i is an integer index ranging from 1 to N. Figure 1 In the example of , N is equal to 2, so the device includes two processors CPU1 and CPU2. The processors CPUi are configured to execute the same instruction set. Preferably, the processors CPUi are exactly the same, but this is not necessary, as long as they can execute the same instruction set.

[0034] Device 1 also includes M peripheral devices Periphj, where M is a positive integer and j is an integer index ranging from 1 to M. Figure 1 In the example of , M is equal to 5, and device 1 includes peripheral devices Periph1, Periph2, Periph3, Periph4, and Periph5. As an example, one of the M peripheral devices (e.g., Figure 1 The peripheral device Periph5 in the example is a memory shared between at least two of the N processors.

[0035] The device 1 also includes a bus BUS having a peripheral device Periphj coupled (eg, connected) thereto and having a processor CPUi coupled (eg, connected) thereto.

[0036] The processor CPUi is a circuit of the device 1 that is configured to initiate read and / or write access to other circuits (e.g., peripheral device Periphj) coupled to the bus BUS. The processor CPUi then plays the role of a "master" circuit. In contrast, the device Periphj cannot initiate read and / or write access to other circuits coupled to the bus BUS. The peripheral device Periphj then plays the role of a "slave" circuit.

[0037] In the device 1, the processor CPUi is configured so that each read or write access to the peripheral device Periphj initiated by the processor CPUi via the bus BUS comprises two successive phases. More specifically, each read or write access to the peripheral device Periphj comprises a first phase (called the address phase) followed by a second phase (called the data phase).

[0038] For example, during the address phase of an access, the processor CPUi initiating this access delivers on the bus BUS the address of the data to which CPUi wishes to write or read, and therefore the address of the peripheral device Periphj it wishes to access, and an indication whether the requested access is a read access or a write access.

[0039] As an example, the bus BUS includes a plurality of conducting lines on which data write or read address bits are simultaneously transmitted in parallel, each address bit being transmitted on a corresponding conducting line.

[0040] As an example, the bus BUS comprises a conducting line on which is transmitted an indication whether an access is a read access or a write access. For example, a bit in a first binary state is transmitted on this conductor to indicate a read access, and a bit in a second binary state is transmitted to indicate a write access.

[0041] By way of example, the bus BUS comprises conductors on which is available a clock signal for clocking the first and second phases of each access.

[0042] As an example, the bus comprises a conducting line on which is transmitted a bit which indicates by a first binary state that the data bit available on the conductor of the bus BUS is valid and can be read and by a second binary state that the data bit available on the conductor of the bus BUS is invalid.

[0043] As an example, each first phase has a duration of one clock signal cycle. For example, in this case, the address bit, the bit indicating the access type (read or write) and the bit indicating, for example, whether the bit on the bus BUS is valid are transmitted simultaneously in parallel.

[0044] For example, during the data phase of access, the data to be read or written is transmitted on the bus. As an example, the bus BUS includes a plurality of lines, and the data bits to be written or read are transmitted simultaneously and in parallel on these lines, and each data bit is transmitted on a corresponding conductive line.

[0045] By way of example, the bus BUS is of the AMBA (Advanced Microcontroller Bus Architecture) type.

[0046] For each processor CPUi, the device 1 also comprises a circuit CIDi associated with the processor CPUi. Figure 1 In the example of FIG. 4 , circuit CID1 is associated with processor CPU1 , and circuit CID2 is associated with processor CPU2 .

[0047] Each circuit CIDi comprises the compartment identifier of the processor with which it is associated.

[0048] As an example, in certain operating stages, such as when the processor CPUi is turned off to implement a low power mode, one or more compartment identifiers of one or more processors (e.g., one or more processors that are turned off) can be delegated to another processor (e.g., a processor that remains turned on). Therefore, the processor CPUi to which the identifiers of one or more compartments of other processors CPUi have been delegated can implement the functions that are usually assigned to these other processors. For example, the processor CPUi that remains turned on can implement the functions that are usually assigned to the processor that has been turned off, which enables this other processor to be kept turned off. This temporary assignment of (one or more) compartment identifiers of one or more other processors to a processor is, for example, referred to as "compartment identifier delegation".

[0049] As an example, in each circuit CIDi, the compartment identifier of the processor CPUi with which the circuit CIDi is associated is hard-coded, ie coded in hardware.

[0050] For example, the compartment identifier of each processor CPUi is determined once in the design of the device 1. In other words, this identifier cannot be changed.

[0051] Preferably, each circuit CIDi is neither a peripheral device Periphj nor a processor CPUi. For example, the circuit CIDi cannot initiate a read or write access to the peripheral device Periphj. In addition, for example, the circuit CIDi cannot be accessed in a read mode or in a write mode.

[0052] For each access (read or write) to a peripheral device Periphj via the bus BUS initiated by its associated processor CPUi, each circuit CIDi is configured to deliver the compartment identifier of this processor CPUi on the bus during the data phase of this access. As an example, the bus BUS comprises a plurality of lines on which are transmitted bits corresponding to (or encoding) the compartment identifier of the processor initiating the access. Thus, the bits of the compartment identifier are transmitted simultaneously in parallel, each bit of the compartment identifier being transmitted on a conductor dedicated to this purpose.

[0053] As already mentioned above, providing each processor CPUi with a compartment identifier enables the device 1 to be compartmentalized. In other words, this enables the definition or selection of the peripheral device(s) Periphj that this processor can access for each processor CPUi.

[0054] As an example, the peripheral device may be accessible to multiple processors CPUi. For example, when the peripheral device Periph5 is a memory, the memory may be accessible to multiple processors, such as Figure 1 In the example, if two processors CPU1 and CPU2 access the memory, then the memory is said to be "shared".

[0055] In order to implement these compartments in device 1, each peripheral device Periphj is configured to, when it receives an access request initiated by processor CPUi, restrict this access (i.e., the implementation of data read or write access in the peripheral device) to the compartment identifier of the processor CPUi that initiated the access during the data phase of this access.

[0056] For example, when the processor CPUi initiates access to the peripheral device Periphj, since the circuit CIDi associated with the processor CPUi supplies the compartment identifier of the processor CPUi to the bus BUS during the address phase of this access, the peripheral device Periphj determines which processor has initiated the access according to the compartment identifier read on the bus BUS during the data phase. Then, the peripheral device Periphj compares this read identifier with the compartment identifier in the list of (one or more) compartment identifiers of all processors CPUi of the device 1 that have access to this peripheral device Periphj. If the read compartment identifier is found in this list, the processor CPUi that initiated the access actually has access to the peripheral device Periphj, and the access continues to the data phase, during which the peripheral device Periphj will supply data (for read access) or receive data (for write access) on the bus.

[0057] As an example, in Figure 1 , peripheral devices Periph1 and Periph2 are accessible only by processor CPU1, peripheral devices Periph3 and Periph4 are accessible only by processor CPU2, and peripheral device Periph5 is accessible by processors CPU1 and CPU2. Therefore, device 1 includes two compartments.

[0058] A disadvantage of the device 1 is that each processor CPUi has no access to its compartment identifier, or in other words, CPUi does not know its identifier.

[0059] In order to overcome this drawback, it is proposed to add a circuit to the peripheral device which, on each read access, stores during the address phase of the access the compartment identifier of the processor initiating the access, and which subsequently supplies to the bus during the data phase of the access the identifier stored during the address phase.

[0060] Preferably, the stored identifier delivered on the bus during the data phase of the access corresponds to the data read during this read access. For example, when the bus includes conductive lines configured to transmit in parallel during the data phase of the access the data bits read or written during this access, then the stored identifier is transmitted on these conductive lines during the data phase.

[0061] Figure 2 An example of an embodiment of an apparatus 2 is shown in block form.

[0062] Device 2 and Figure 1 The present invention is similar to the device 1 of the present invention, and only the differences between the two devices are emphasized here. In other words, unless otherwise indicated, everything pointed out for the device 1 applies to the device 2.

[0063] Compared to the device 1, the device 2 comprises an additional peripheral device CAR in addition to the M peripheral devices Periphj. The circuit CAR is coupled (eg connected) to the bus BUS.

[0064] Preferably, the circuit or peripheral CAR is read-only.

[0065] As an example, a read access to the peripheral device CAR is performed in the same way as a read access to one of the peripheral devices Periphj.

[0066] For each read access to the peripheral device CAR initiated by one of the processors CPUi, the peripheral device CAR is configured to store the compartment identifier of the processor CPUi that has initiated the access. This storage is performed during the data phase of the access, the compartment identifier of the processor CPUi that has initiated the access then being available on the bus BUS. For example, the circuit CAR detects whether a processor has initiated a read access to the circuit CAR by comparing the address of the processor with an address available on the bus BUS during the address phase of the access and by detecting on the bus BUS whether the requested access is a read access.

[0067] Furthermore, the circuit CRA is configured to deliver the stored identifier on the bus BUS during the data phase of this access. More particularly, the circuit CAR is configured to deliver the compartment identifier on the bus BUS during this data phase so that the processor CPUi that has initiated the read access obtains its compartment identifier, or in other words, it can read this compartment identifier.

[0068] For example, the compartment identifier stored by the circuit CAR during the address phase of an access is returned on the bus BUS as a data item transmitted on the bus during the next data phase.

[0069] For example, each time the processor CPUi actively accesses the peripheral device Periphj, during the data phase of the access, the data item to be read or written corresponding to this access is transmitted on the bus BUS, and in the case of a read access to the peripheral device CAR, this data item corresponds to the compartment identifier stored by the circuit CAR during the address phase of this read access.

[0070] Thus, when a processor CPUi wishes to know its compartment identifier, it is sufficient for this processor CPUi to initiate a read access to the circuit CAR so that it receives its compartment identifier in the form of a data item read from the circuit CAR during the data phase of the access.

[0071] The fact that each processor CPUi of the device 1 is able to obtain its compartment identifier has several advantages.

[0072] For example, according to an embodiment, one of the M peripheral devices Periphj, such as peripheral device Periph5, is between at least two processors of device 2 (e.g., between Figure 2 In the example of , a memory shared by processors CPU1 and CPU2 is then possible to store in memory Periph5 a computer program code common to both processors, this program including a part whose execution is constrained by the identifier of the processor executing the program.

[0073] In other words, the code includes one or more parts, each of which can (or must) be executed only by one of the processors CPU1 and CPU2 assigned to this part. Therefore, when one of the processors CPU1 and CPU2 executes the code and reaches such a part of the code, it executes this code part only when its compartment identifier corresponds to the compartment identifier of the processor that has the right to execute this code part. In order to achieve this, the processor executing the code implements read access to the circuit CAR in order to obtain its compartment identifier, and compares its compartment identifier thus obtained with the compartment identifier that constrains the execution of the code part. If the two identifiers are exactly the same, then the processor executes the code part, on the contrary, if the two identifiers are different, then the processor does not execute the code part. The program shared by multiple processors stored in the shared memory is defined, for example, by the instruction sequence of the instruction set shared by these processors.

[0074] As an example, the compartment identifier of the processor CPUi is called "HSR->Attr", which is obtained by this processor CPUi during a read access to the circuit CAR, the compartment identifier of the processor CPU1 is called CPU1_CID, the compartment identifier of the processor CPU2 is called CPU2_CID, the code executable by either processor CPU1 or CPU2 is called P, the first part of the code P is called P1, and the second part of the code P is called P2. For example, consider that the code P has the following form:

[0075] if(HSR->Attr==CPU1_CID){

[0076] P1}

[0077] elsif(HSR->Attr==CPU2_CID){

[0078] P2}.

[0079] When this example of code P is executed by the processor CPU1, the processor CPU1 accesses the circuit CAR in a read mode when it reaches the "if (HSR->Attr==CPU1_CID)" condition and then compares the obtained identifier with the identifier CPU1_CID. Since they are equal, the condition HSR->Attr==CPU1_CID is satisfied and the processor CPU1 executes the code portion P1. Then, when the processor CPU1 reaches the "elsif (HSR->Attr==CPU2_CID)" condition, if it does not store the identifier obtained during the last read access to the circuit CAR, it performs another read access to the circuit CAR, or if it has already stored the identifier obtained during the last read access to the circuit CAR, it directly uses the obtained identifier. The processor then compares the identifier obtained by means of the read access to the circuit CAR with the identifier CPU2_CID. Since they are different, the condition HSR->Attr==CPU2_CID is not satisfied and the processor CPU1 does not execute the portion P2. Similarly, when the code P is executed by the processor CPU2, the processor does not execute the portion P1 but executes the portion P2.

[0080] Restricting the execution of one or more portions of code to the compartment identifier of the processor CPUi executing the code enables this code to be common to multiple processors CPUi, while retaining portions of the code that can only be executed by a given processor. Thus, instead of storing in memory specific code for each processor CPUi, stored in memory is code common to multiple processors, having one or more specificities for at least one of these processors.

[0081] This makes it possible to reduce the size of memory Periph5.

[0082] This also makes it possible to simplify the verification of the code already obtained and its deployment when the code needs to be updated to modify or add functions or code portions specific to one of the processors CPUi.

[0083] Although an example of a code P common to two processors CPU1 and CPU2 is described above, a person skilled in the art can provide a code common to more than two processors based on the functional indications given above.

[0084] In addition, although an example of a code P shared by multiple processors CPUi has been described above, wherein the code P includes a portion specific to each processor CPUi, a person skilled in the art will be able to provide a code shared by multiple processors, the code including at least one portion specific to a given processor, and for each other processor sharing the code, the code may or may not include at least one portion specific to this processor.

[0085] Although an example of code P shared by two processors CPU1 and CPU2 has been described, in which part P1 can only be executed by processor CPU1, and part P2 can only be executed by processor CPU2, in other examples where the device not shown additionally includes processor CPU3, at least one of parts P1 and P2 can be executed by more than one processor. For example, in this case, part P1 can be executed by one or the other of processors CPU1 or CPU3, while part P2 can only be executed by processor CPU2.

[0086] Figure 3 The flowchart shows the Figure 2 An example of an embodiment of a method implemented in a device 2.

[0087] More specifically, Figure 3 An example of an embodiment of a read access to the circuit CAR is illustrated, the steps of the read access to the circuit CAR are as follows: Figure 3 It is indicated by reference numeral 300 in the figure.

[0088] This phase 300 of the read access to the circuit CAR first comprises an address phase 302 (block “Address phase of the read access CAR”). During this address phase 302, the processor CPUi that has initiated the read access supplies the bus BUS with the address of the data item to be read. This address corresponds, for example, to the address of the peripheral device CAR or to the address of a register of the peripheral device CAR. In addition, during this address phase 302, the circuit CIDi of the processor CPUi that has initiated the access supplies the bus BUS with the compartment identifier of this processor CPUi.

[0089] During phase 302, at step 304 (box “Memorize CID”), the circuit CAR stores the compartment identifier present on the bus. For example, the circuit CAR detects that the processor CPUi has initiated a read access to the circuit CAR by means of an address and an indication that the requested access is a read access, this information being present on the bus BUS during the address phase 302. As an example, the compartment identifier present on the bus BUS during the address phase 302 of the read access 300 to the circuit CAR is stored in a register of the circuit CAR.

[0090] The address phase 302 of the read access 300 is followed by a data phase 306 of this access 300 (block “Data phase of read access CAR”).

[0091] During the data phase 306, at a step 308 (block “Provide CIDm”), the circuit CAR supplies to the bus BUS the compartment identifier stored by the circuit CAR at step 304 of the previous address phase 302. The compartment identifier supplied to the bus BUS then corresponds to the data item of the read access 300, i.e. to the data item read from the circuit CAR by the processor CPUi that has initiated the access 300.

[0092] The end of the data phase 306 marks the end of the read access 300 to the circuit CAR.

[0093] Figure 4 Shown in the form of a box Figure 2 An example of a detailed embodiment of the circuit CAR of the device 2 is shown.

[0094] The circuit CAR comprises a register REG. The register REG is configured to store, during the address phase of each read access to the circuit CAR, an identifier of the processor CPUi that has initiated the access, this identifier being supplied to the bus BUS by the circuit CIDi associated with this processor CPUi. The register REG is also configured to supply, during the data phase of each read access to the circuit CAR, to the bus BUS the identifier stored during the previous address phase.

[0095] For example, the register REG includes a plurality of D-type flip-flops 400. For example, each flip-flop 400 includes a data input terminal D configured to receive a bit, an output terminal Q configured to supply a bit stored in the flip-flop 400, and a clock input terminal clk configured to receive a timing signal (e.g., a clock signal of a bus BUS). Then, each flip-flop 400 is configured to store a bit present on its input terminal D at each valid edge of the clock signal received on its input terminal clk and update its output Q accordingly.

[0096] As an example, the circuit CAR comprises a selection or routing circuit 402. The circuit 402 is configured to deliver to the data input of the register REG a compartment identifier CID present on the bus BUS during the address phase of each read access to the circuit CAR, and otherwise a compartment identifier CIDm stored in the register REG.

[0097] As an example, the circuit 402 includes an input terminal I0, an input terminal I1, a selection input terminal S and an output terminal O, which is coupled (preferably connected) to the input terminal of the REG register, for example, to the D input terminal of the flip-flop 400. The input terminal I1 of the circuit 402 is configured, for example, to receive the compartment identifier CID present on the bus BUS during the address phase of each read or write access initiated by the processor CPUi, and the input terminal I0 of the circuit 402 is configured, for example, to receive the output of the register REG, that is, the identifier CIDm stored in the register REG. The input terminal S of the circuit 402 is configured, for example, to receive the binary control signal ctrl. When the signal ctrl is in the first binary state, the circuit 402 couples its input I1 to its output O, or in other words delivers the identifier CID present at its input I1 at its output O, and when the signal ctrl is in the second binary state, the circuit 402 couples its input I0 to its output O, or in other words delivers the stored identifier CIDm present at its input I0 at its output O. The signal ctrl is configured to be in its first binary state during the address phase of each read access to the circuit CAR and to be in its second binary state otherwise.

[0098] As an example, the circuit CAR comprises a circuit 404 configured to deliver a signal ctrl based on a signal available on the bus BUS. For example, the circuit 404 is configured to detect whether the processor CPUi has initiated an access to the circuit CAR based on an address present on the bus BUS and based on an indication of a request for read access present on the bus BUS.

[0099] A person skilled in the art will be able to provide other examples of implementation of the circuit CAR based on the functional indications given above. For example, the circuit 402 can be omitted. In such an example, the data input of the register REG then directly receives the compartment identifier CID present on the bus BUS, and the register REG (e.g., each flip-flop 400) further comprises an activation input, which receives the signal ctrl and is configured to allow updating the register REG only during the active edge of the clock signal of the bus BUS when the signal ctrl is in its first binary state, and if the signal ctrl is in its second binary state, the register REG is not modified or updated.

[0100] Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0101] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A device comprising: bus; a processor coupled to the bus and configured to execute the same instruction set and initiate accesses to peripheral devices via the bus, each access comprising an address phase followed by a data phase; for each processor, a second circuit associated with the processor and configured to provide an identifier of the processor on the bus during an address phase of each access initiated by the processor; as well as A peripheral device coupled to the bus, the peripheral device comprising a first circuit, the first circuit being configured to, upon each read access to the first circuit initiated by one of the processors: storing an identifier present on the bus during an address phase of an access; and The stored identifier is provided to the bus during the data phase of the access.

2. The apparatus according to claim 1, wherein: The peripheral device includes a memory shared between at least two of the processors; and A program comprising a sequence of instructions of an instruction set is stored in the memory and is accessible by the at least two of the processors.

3. The apparatus of claim 2, wherein the program includes at least a portion whose execution is subject to an identifier of a processor executing the program.

4. The device according to claim 1, wherein: For each access by one of the processors to one of the peripheral devices other than the first circuit, the device is configured to restrict access to the peripheral device based on an identifier of the processor that has initiated the access.

5. The apparatus of claim 1 , wherein the first circuit comprises a register configured to: storing, during an address phase of each read access to the first circuit, an identifier present on the bus and corresponding to the processor that has initiated the read access; and During the data phase of each read access to the first circuit, the identifier stored during the address phase of the read access is provided to the bus. The apparatus of claim 1 , wherein each identifier corresponds to a different processor.

7. The device of claim 1, wherein read and write access to the second circuit is not possible.

8. The apparatus of claim 1, wherein the bus is an Advanced Microcontroller Bus Architecture (AMBA) type bus.

9. The apparatus of claim 1, wherein the identifier of each processor is hard-coded in the second circuit associated with the processor.

10. The device of claim 1, wherein the first circuit is read-only accessible.

11. A method implemented in a device, the device comprising a bus, a peripheral device connected to the bus and comprising a first circuit, processors coupled to the bus and executing the same instruction set, each processor being associated with a second circuit and initiating access to the peripheral device via the bus, each access comprising an address phase and a subsequent data phase, the method comprising: Initiating, by one of the processors, a read access to the first circuit; providing an identifier of a processor to the bus during an address phase of the access and using a second circuit associated with the processor initiating the access; storing, by the first circuit, an identifier present on the bus during an address phase of the access; as well as The stored identifier is provided to the bus by the first circuit during a data phase of the access.

12. The method according to claim 11, wherein: The peripheral device includes a memory shared between at least two of the processors; and A program comprising a sequence of instructions of an instruction set is stored in the memory and is accessible by said at least two of said processors.

13. The method of claim 12, wherein the program includes at least a portion whose execution is subject to an identifier of a processor executing the program.

14. The method according to claim 11, wherein: For each access by one of the processors to one of the peripheral devices other than the first circuit, the device is configured to restrict access to the peripheral device based on an identifier of the processor that has initiated the access.

15. The method of claim 11, wherein the first circuit comprises a register configured to: storing during an address phase of each read access to the first circuit an identifier present on the bus and corresponding to the processor that has initiated the read access; and The identifier stored during the address phase of each read access to the first circuit is provided to the bus during the data phase of the read access.

16. The method of claim 11, wherein each identifier corresponds to a different processor.

17. The method of claim 11, wherein read and write access to the second circuit is not possible.

18. The method of claim 11, wherein the bus is an Advanced Microcontroller Bus Architecture (AMBA) type bus.

19. The method of claim 11, wherein the identifier of each processor is hard-coded in the second circuit associated with the processor.

20. The method of claim 11, wherein the first circuit is read-only accessible.

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