Method and device for sampling data and electronic equipment
By outputting the drive clock signal at the chip input and output terminals and connecting it back to the controller to determine the sampling clock signal, the problem that external devices in the prior art provide the IO resources occupied by the along-channel clock and the data sampling speed is solved, and data sampling efficiency is improved while saving IO resources.
Patent Information
- Application Number
- CN202411865920.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-05-06
AI Technical Summary
In the prior art, when performing data sampling, external devices are required to provide a follow-up clock, which leads to IO resources occupied and the data sampling frequency cannot be increased, resulting in a low data sampling speed.
When the drive clock signal is outputted at the chip input and output terminal, it is connected back to the controller, and the portion of its data stage is determined as a sampling clock signal based on the connected drive clock signal, for sampling the target sampled data of the external device.
This method can save IO resources while improving data sampling efficiency, and achieve more efficient data sampling by compensating the path delay of the accompanying clock inside the chip.
Smart Images
Figure CN119938580A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data sampling, and in particular to a method and device for sampling data, and electronic equipment. Background Art
[0002] The FLASH (flash memory) / PSRAM (pseudo-static random access memory) currently on the market are all based on protocols such as xSPI and Hyperbus. When performing a read operation, since the returned data is asynchronous with the host's internal clock, and in order to obtain a higher read frequency, an external device particle is often required to provide a clock as the host's internal sampling clock. For example, in OSPI DDR (double data rate supported by octal serial peripheral interface) mode, the particle needs to provide a DQS clock, and the DDR (double data rate) mode of the Hyperbus protocol requires a RWDS clock. Using an external homologous clock for sampling requires an IO (input and output) resource, but if the internal clock is used for sampling, without a reasonable design, the data sampling frequency cannot be increased, resulting in a low data sampling speed. Summary of the invention
[0003] The present invention provides a method and device for sampling data, and an electronic device, which can improve data sampling efficiency while saving IO resources.
[0004] In one aspect of the present invention, a method for sampling data is provided. The method includes: when a driving clock signal is output from a controller in a chip to an external device via a chip input / output terminal, the driving clock signal is connected back to the controller from the chip input / output terminal; based on the connected driving clock signal, a portion corresponding to a data phase of the driving clock signal is determined as a sampling clock signal; and target sampling data from the external device is sampled according to the sampling clock signal.
[0005] In another aspect of the present invention, a device for sampling data is provided. The device includes an input-output terminal; and a controller, including a clock signal input terminal and a clock signal output terminal, and is configured to: output a driving clock signal through the clock signal output terminal to output the driving clock signal to an external device via the input-output terminal; receive the driving clock signal connected back at the input-output terminal through the clock signal input terminal; determine a portion corresponding to a data phase of the driving clock signal as a sampling clock signal based on the connected driving clock signal; and sample target sampling data from the external device according to the sampling clock signal.
[0006] In another aspect of the present invention, an electronic device is provided, comprising a memory configured to store an executable program and a processor configured to execute the program so that the electronic device performs the above method for sampling data.
[0007] According to the present invention, when the driving clock signal is output from the controller in the chip to the external device via the chip input and output terminals, the driving clock signal is connected back to the controller from the chip input and output terminals, and the part corresponding to its data phase is determined as the sampling clock signal based on the connected driving clock signal, and the target sampling data from the external device is sampled according to the sampling clock signal. In this way, the driving clock signal connected back from the chip input and output terminals can compensate for the path delay of the existing accompanying clock inside the chip. In this way, the driving clock can well replace the existing accompanying clock for data sampling, thereby saving IO resources while improving data sampling efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a flow chart of a method for sampling data according to an embodiment of the present invention; Figure 2 A sampling flow chart of a method for sampling data according to an embodiment of the present invention; Figure 3 A schematic diagram of various clock signals of a method for sampling data according to an embodiment of the present invention; Figure 4 A schematic diagram of the structure of a device for sampling data according to an embodiment of the present invention; Figure 5 FIG. 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0009] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in conjunction with the implementation modes and the accompanying drawings.
[0010] In the existing technology, an external device particle is required to provide a clock as the sampling clock inside the host. Using an external homologous clock for sampling requires an IO resource, but if the internal clock is used for sampling, without a reasonable design, the data sampling frequency cannot be increased, resulting in a low data sampling speed.
[0011] In order to solve at least the above technical problems, the present disclosure provides a method for sampling data. According to the present disclosure, when a driving clock signal is output from a controller in a chip to an external device via a chip input / output terminal, the driving clock signal is connected back to the controller from the chip input / output terminal, and the portion corresponding to its data phase is determined as a sampling clock signal based on the connected driving clock signal, and the target sampling data from the external device is sampled according to the sampling clock signal. In this way, connecting the driving clock signal back from the chip input / output terminal can compensate for the path delay of the existing accompanying clock inside the chip, so that the driving clock can well replace the existing accompanying clock for data sampling, thereby saving IO resources while improving data sampling efficiency.
[0012] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.
[0013] Figure 1 is a flow chart showing a method 100 for sampling data according to an embodiment of the present disclosure. Figure 1 The method 100 includes the following steps 102 to 106.
[0014] In step 102 , when a driving clock signal is output from a controller in a chip to an external device via a chip input / output terminal, the driving clock signal is connected back to the controller from the chip input / output terminal.
[0015] In this way, since a driving clock is output when the controller interacts with an external device, this clock is used to drive the external device to work. During data interaction, the driving clock will flip at a specific frequency and match the instruction structure. Compared with other working clocks inside the IP, this output clock has the characteristics of clear instruction boundaries, which makes it easy to distinguish the part of the clock that represents data, and can more effectively replace the existing on-chip clock.
[0016] In some embodiments, the driving clock signal is sent from the clock signal output terminal of the controller to the chip input / output terminal, and the driving clock signal is output from the chip input / output terminal to an external device. In some embodiments, the driving clock signal received from the chip input / output terminal is received from the clock signal input terminal of the controller.
[0017] In this way, since the path delay of the theoretical accompanying clock includes the delay from the chip input and output terminal (IO_PAD) to the controller inside the chip, the driving clock signal connected back at the chip input and output terminal is received from the clock signal input end of the controller, so that the driving clock and the theoretical accompanying clock can have partially the same clock path delay, and under some environmental conditions, the delays of the rising and falling edges of the clock through IO_PAD may be different, which will cause a clock duty cycle deviation, and this deviation will also indirectly lead to a duty cycle deviation of the accompanying clock. After using the driving clock signal directly returned from IO_PAD, the duty cycle deviation of the clock and the accompanying clock will become consistent, thereby obtaining a clock signal with a duty cycle closer to the theoretical accompanying clock.
[0018] In step 104, a portion corresponding to the data phase of the driving clock signal is determined as a sampling clock signal based on the received driving clock signal.
[0019] In some embodiments, counting is performed based on the received driving clock signal to determine the portion corresponding to the data phase, wherein the driving clock signal includes the data phase and the non-data phase, and the driving clock signal is used to drive the external device to work. In some embodiments, the communication length of the non-data phase is obtained, and counting is performed based on the received driving clock signal, and if the result of the counting reaches the communication length of the non-data phase, the portion after the non-data phase is determined as the portion corresponding to the data phase. In this way, since a specific instruction structure is required when the driving clock interacts with an external device, including a non-data phase and a data phase, the time periods occupied by these phases can be known before transmission, so by counting based on the driving clock signal, the data phase and the non-data phase can be distinguished, and sampling is enabled in the data phase, so that the accompanying clock can be more accurately simulated.
[0020] In some embodiments, the received drive clock signal is phase-corrected to obtain a corrected drive clock signal, and the corrected drive clock signal is counted to determine the portion corresponding to the data phase as the sampling clock signal. In some embodiments, the controller uses an optimized digital signal phase adjustment module to phase-correct the received drive clock signal so that the phase of the received drive clock signal corresponds to the target sampling data. In this way, the phase correction of the drive clock signal by optimizing the digital signal phase adjustment module can compensate for the path delay of the existing accompanying clock outside the chip. After the correction, the drive clock signal is subsequently used to sample the target sampling data of the external device, saving an IO resource.
[0021] In some embodiments, before step 104, the method 100 may further include: continuously superimposing delays on the basis of the received driving clock signal until the data is correctly sampled based on the driving clock signal to obtain a superimposed delay range; and configuring the number of stages of the digital signal phase adjustment module based on the superimposed delay range to obtain the optimized digital signal phase adjustment module. In this way, since the asynchronous module generally designs a digital signal phase adjustment module (delayline) to push the phase of the sampling clock so that the sampling clock can have a suitable setup timing and hold timing when sampling data, this function of the delayline can be directly used to cover the various delays generated by the chip external path. Because the use of the default driving clock signal will sample wrong data, when the function is used for the first time, the software level needs to configure the delayline to perform phase calibration on the clock signal so that the calibrated clock signal can be used to sample external data, thereby solving the problem of the driving clock and the theoretical accompanying clock having the same frequency but different phases, thereby improving the accuracy and efficiency of data sampling.
[0022] In some embodiments, the middle value of the superimposed delay range is selected, and the number of stages of the digital signal phase adjustment module is configured based on the middle value to obtain the optimized digital signal phase adjustment module. In this way, the middle value of the superimposed delay range is selected, and the middle value is used as the final configuration value to optimize the number of stages of the digital signal phase adjustment module, which can effectively resist interference and ensure the optimization effect.
[0023] In step 106, the target sampled data from the external device is sampled according to the sampling clock signal.
[0024] Hereinafter, application scenarios of the method and apparatus for sampling data and the electronic device according to the embodiments of the present invention will be described by way of examples.
[0025] Figure 2 is a flow chart showing a method for sampling data according to an embodiment of the present invention. Figure 2 The method includes the following steps 201 to 205.
[0026] In step 201, in the initial stage, delays are continuously superimposed on the basis of the received driving clock signal until data is correctly sampled based on the driving clock signal to obtain a superimposed delay range; the levels of the delayline module are configured based on the superimposed delay range to obtain an optimized delayline module.
[0027] In some embodiments, configuring the number of delayline modules based on the superimposed delay range to obtain an optimized delayline module includes: selecting an intermediate value of the superimposed delay range, configuring the number of delayline modules based on the intermediate value, and obtaining an optimized delayline module.
[0028] In step 202, when the driving clock signal SFCIO_SCLK_O is output from the controller in the chip to the external device via the chip input / output terminal IO_PAD, the driving clock signal SFCIO_SCLK_I is returned from the chip input / output terminal IO_PAD to the controller.
[0029] Specifically, when the driving clock signal SFCIO_SCLK_O is sent from the clock signal output terminal sclk_o of the controller to the chip input and output terminal IO_PAD, and the driving clock signal SFCIO_SCLK_O is output from the chip input and output terminal IO_PAD to the external device, the driving clock signal SFCIO_SCLK_I connected back at the chip input and output terminal IO_PAD is received from the clock signal input terminal sclk_i of the controller.
[0030] In some embodiments, the external device is a memory device such as FLASH or PSRAM.
[0031] In step 203 , a phase correction is performed on the returned driving clock signal SFCIO_SCLK_I to obtain a corrected driving clock signal SFCIO_SCLK_I.
[0032] Specifically, the controller uses the optimized delayline module to perform phase correction on the received driving clock signal SFCIO_SCLK_I, so that the phase of the received driving clock signal SFCIO_SCLK_I corresponds to the target sampling data.
[0033] In step 204, the corrected driving clock signal SFCIO_SCLK_I is counted to determine the portion corresponding to the data phase as the sampling clock signal SFCIO_SCLK_I. The driving clock signal SFCIO_SCLK_I includes a data phase and a non-data phase, and is used to drive an external device to work.
[0034] Specifically, the communication length of the non-data phase (no data) is obtained and counted based on the received driving clock signal SFCIO_SCLK_I. If the counting result reaches the communication length of the non-data phase, the part after the non-data phase is determined as the part corresponding to the data phase.
[0035] In step 205, target sampled data from an external device is sampled according to the sampling clock signal SFCIO_SCLK_I.
[0036] Figure 3 Schematic diagram of various clock signals showing a method for sampling data according to an embodiment of the present invention. Figure 3 The driving clock signals SFCIO_SCLK_O and SFCIO_SCLK_I have several more non-data phase time periods than the theoretical accompanying clock, and have the same frequency but different phases as the theoretical accompanying clock signal. Therefore, it is necessary to distinguish the data phase signal from the driving clock signal SFCIO_SCLK_I, perform phase correction on it, and use the corrected driving clock signal SFCIO_SCLK_I to sample the target sampling data of the external device. Figure 3 The dq path in the process is the process of sampling the target sampling data from the external device according to the sampling clock signal SFCIO_SCLK_I. Figure 3 The sclk_sample in the above means that the dq on IO_PAD is sampled using the corrected sclk_i.
[0037] According to another aspect of the present invention, Figure 4 4 is a block diagram showing an apparatus 400 for sampling data according to an embodiment of the present invention. Figure 4 The device 400 for sampling data includes an input-output terminal 402 and a controller 404, including a clock signal input terminal sclk_i and a clock signal output terminal sclk_o.
[0038] The controller 404 is configured to output the driving clock signal SFCIO_SCLK_O through the clock signal output terminal sclk_o so as to output the driving clock signal SFCIO_SCLK_O to an external device via the input-output terminal IO_PAD.
[0039] The controller 404 is configured to receive the driving clock signal SFCIO_SCLK_I connected back at the input-output terminal IO_PAD through the clock signal input terminal sclk_i.
[0040] The controller 404 is configured to determine a portion corresponding to a data phase of the driving clock signal SFCIO_SCLK_I as a sampling clock signal SFCIO_SCLK_I based on the received driving clock signal SFCIO_SCLK_I.
[0041] In addition, the controller 404 is configured to sample the target sampled data from the external device according to the sampling clock signal SFCIO_SCLK_I.
[0042] It should be understood that the controller 404 may be further configured to execute the corresponding steps or actions in the method described above, which will not be described in detail herein.
[0043] According to yet another aspect of the present invention, Figure 5 Schematic diagram of an electronic device 500 according to an embodiment of the present invention. Figure 5 The electronic device 500 includes a memory 502 and a processor 504. The memory 502 is configured to store an executable program that can be run on the processor 504. The processor 504 is configured to execute the program so that the electronic device implements the various steps or actions of the method for sampling data as described above.
[0044] In summary, the method and device for sampling data and the electronic device provided by the present invention, when the driving clock signal is output from the controller in the chip via the chip input and output terminals to the external device, the driving clock signal is connected back from the chip input and output terminals to the controller, and the part corresponding to its data phase is determined as the sampling clock signal based on the connected driving clock signal, and the target from the external device is sampled according to the sampling clock signal, so that the driving clock signal connected back from the chip input and output terminals can compensate for the path delay of the existing accompanying clock inside the chip, so that the driving clock can be well replaced by the existing accompanying clock for data sampling, thereby saving IO resources and improving data sampling efficiency. In addition, the delayline module is optimized so that the driving clock signal can be corrected by using the optimized delayline module, which solves the problem that the driving clock and the theoretical accompanying clock have the same frequency but different phases, thereby improving data sampling accuracy and efficiency.
[0045] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A method for sampling data, characterized in that include: When the driving clock signal is output from the controller in the chip to the external device via the chip input / output terminal, the driving clock signal is connected back to the controller from the chip input / output terminal; Determine, based on the received driving clock signal, a portion corresponding to the data phase of the driving clock signal as a sampling clock signal; as well as The target sampling data from the external device is sampled according to the sampling clock signal.
2. The method according to claim 1, characterized in that Determining a portion corresponding to the data phase of the driving clock signal as a sampling clock signal based on the received driving clock signal comprises: Counting based on the received driving clock signal to determine the portion corresponding to the data phase, The driving clock signal includes the data phase and the non-data phase, and the driving clock signal is used to drive the external device to work.
3. The method according to claim 2, characterized in that Counting based on the received driving clock signal to determine the portion corresponding to the data phase comprises: Obtaining the communication length of the non-data phase; Counting based on the received driving clock signal; and If the counting result reaches the communication length of the non-data phase, the portion after the non-data phase is determined as the portion corresponding to the data phase.
4. The method according to claim 1, characterized in that: Determining a portion corresponding to the data phase of the driving clock signal as a sampling clock signal based on the received driving clock signal comprises: Performing phase correction on the received driving clock signal to obtain a corrected driving clock signal; and The corrected driving clock signal is counted to determine the portion corresponding to the data phase as the sampling clock signal.
5. The method according to claim 4, characterized in that Performing phase correction on the returned driving clock signal to obtain a corrected driving clock signal includes: The controller uses an optimized digital signal phase adjustment module to perform phase correction on the received driving clock signal, so that the phase of the received driving clock signal corresponds to the target sampling data.
6. The method according to claim 5, characterized in that Also includes: Continuously superimposing delays on the basis of the received driving clock signal until data is correctly sampled based on the driving clock signal to obtain a superimposed delay range; as well as The number of stages of the digital signal phase adjustment module is configured based on the superimposed delay range to obtain the optimized digital signal phase adjustment module.
7. The method according to claim 6, characterized in that The number of stages of the digital signal phase adjustment module is configured based on the superimposed delay range, so as to obtain the optimized digital signal phase adjustment module, including: Selecting a middle value of the superimposed delay range; and The number of stages of the digital signal phase adjustment module is configured based on the intermediate value to obtain the optimized digital signal phase adjustment module.
8. The method according to claim 1, characterized in that Outputting the driving clock signal from the controller in the chip to the external device via the chip input and output terminals includes: The driving clock signal is sent from the clock signal output end of the controller to the chip input / output terminal, and the driving clock signal is output from the chip input / output terminal to an external device.
9. The method according to claim 1, characterized in that: Connecting the driving clock signal from the chip input / output terminal to the controller includes: The driving clock signal received from the chip input / output terminal is received from the clock signal input end of the controller.
10. A device for sampling data, characterized in that: include: Input and output terminals; as well as The controller includes a clock signal input terminal and a clock signal output terminal, and is configured as follows: Outputting a driving clock signal through the clock signal output terminal to output the driving clock signal to an external device via the input / output terminal; receiving the driving clock signal connected back at the input-output terminal through the clock signal input end; Determine, based on the received driving clock signal, a portion corresponding to the data phase of the driving clock signal as a sampling clock signal; as well as The target sampling data from the external device is sampled according to the sampling clock signal.
11. An electronic device, characterized in that: include: a memory configured to store an executable program; as well as A processor is configured to execute the program so that the electronic device performs the method according to any one of claims 1 to 9.