Chip signal processing method and device and electronic equipment

Abstract

The invention provides a signal processing method and device of a chip and electronic equipment. The method relates to the technical field of signal processing, and comprises the following steps: sampling a first signal received by a first chip to obtain a second signal; the first signal is a signal sent to the first chip by the second chip through the processor interconnection bus; the second chip and the first chip are arranged on the same mainboard, and the first chip is different from the second chip; performing signal superposition on the second signal to obtain simulated eye pattern data of the second signal; determining a critical value of the eye height of the second signal and a critical value of the eye width of the second signal by adjusting the position of a central point included in the simulated eye pattern data; determining the eye height and the eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal; and determining the signal quality of the first signal based on the eye height and the eye width of the second signal. According to the invention, the signal quality of the signal transmitted between the chips can be quantitatively evaluated, and the signal quality can be accurately evaluated.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a chip signal processing method, device and electronic equipment. Background Art

[0002] In the existing chip signal processing method, the method for evaluating the signal quality of the signal transmitted between chips relies on the bit error of data transmission. The bit error is only a result of data transmission and cannot reflect the signal instruction of the real signal during the transmission process. The existing chip signal processing method cannot quantitatively evaluate the signal quality of the signal transmitted between chips, and thus there is a problem that the signal quality cannot be accurately evaluated. Summary of the invention

[0003] The embodiments of the present application provide a chip signal processing method, device and electronic device.

[0004] According to a first aspect of the present application, a chip signal processing method is provided, the method comprising: The present application provides a chip signal processing method, the method comprising: sampling a first signal received by a first chip to obtain a second signal; the first signal is a signal sent by the second chip to the first chip through a processor interconnection bus; the second chip and the first chip are on the same mainboard, and the first chip is different from the second chip; superimposing the second signal to obtain analog eye diagram data of the second signal; determining a critical value of an eye height of the second signal and a critical value of an eye width of the second signal by adjusting a center point position included in the analog eye diagram data; determining an eye height and an eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal; and determining a signal quality of the first signal based on the eye height and the eye width of the second signal.

[0005] According to one embodiment of the present application, the sampling of the first signal received by the first chip to obtain the second signal includes: performing equalization processing on the first signal to obtain the first signal after equalization processing; based on a set encoding method, performing signal branch sampling on the first signal after equalization processing to obtain the second signal; the signal branch sampling characterizes extracting the signal branch of the first signal after equalization processing for sampling according to the set encoding method.

[0006] According to one embodiment of the present application, the signal superposition of the second signal to obtain the analog eye diagram data of the second signal includes: through a set application, the signal superposition of the second signal according to the time dimension and the voltage dimension to obtain the analog eye diagram data of the second signal; the horizontal coordinate axis and the vertical coordinate axis are pre-set in the application, the horizontal coordinate axis represents the time dimension of the second signal, and the vertical coordinate axis represents the voltage dimension of the second signal.

[0007] According to one embodiment of the present application, the critical value of the eye height of the second signal and the critical value of the eye width of the second signal are determined by adjusting the center point position included in the analog eye diagram data, including: adjusting the horizontal center point position in the horizontal coordinate axis based on the timing offset to determine the critical value of the eye width of the second signal; the critical value of the eye width includes a first critical value and a second critical value; adjusting the vertical center point position in the vertical coordinate axis based on the voltage offset to determine the critical value of the eye height of the second signal; the critical value of the eye height includes a third critical value and a fourth critical value; the horizontal center point position is different from the vertical center point position.

[0008] According to one embodiment of the present application, the method of adjusting the horizontal center point position based on the timing offset in the horizontal coordinate axis to determine the critical value of the eye width of the second signal includes: adjusting the horizontal center point position in sequence in a first direction based on the timing offset, and determining the first critical value of the eye width in response to the analog eye diagram data satisfying a set first condition; adjusting the horizontal center point position in sequence in a second direction based on the timing offset, and determining the second critical value of the eye width in response to the analog eye diagram data satisfying a set second condition; the first direction is opposite to the second direction, the first critical value is greater than the second critical value, and the first condition is the same as or different from the second condition.

[0009] According to one embodiment of the present application, the adjusting the vertical center point position based on the voltage offset in the vertical coordinate axis to determine the critical value of the eye height of the second signal includes: sequentially adjusting the vertical center point position in a third direction based on the voltage offset, and determining the third critical value of the eye height in response to the analog eye diagram data satisfying a set third condition; sequentially adjusting the vertical center point position in a fourth direction based on the voltage offset, and determining the fourth critical value of the eye height in response to the analog eye diagram data satisfying a set fourth condition; the third direction is opposite to the fourth direction, the third critical value is greater than the fourth critical value, and the third condition is the same as or different from the fourth condition.

[0010] According to one embodiment of the present application, determining the eye height and eye width of the second signal based on the critical value of the eye height of the second signal and the critical value of the eye width of the second signal includes: subtracting the first critical value from the second critical value to obtain the eye width of the second signal; and subtracting the third critical value from the fourth critical value to obtain the eye height of the second signal.

[0011] According to a second aspect of the present application, a chip signal processing device is provided, the device comprising: a sampling module, used to sample a first signal received by a first chip to obtain a second signal; the first signal is a signal sent by the second chip to the first chip through a processor interconnect bus; the second chip and the first chip are on the same mainboard, and the first chip is different from the second chip; a simulation module, used to perform signal superposition on the second signal to obtain analog eye diagram data of the second signal; an adjustment module, used to determine a critical value of the eye height of the second signal and a critical value of the eye width of the second signal by adjusting the center point position included in the analog eye diagram data; a calculation module, used to determine the eye height and eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal; a determination module, used to determine the signal quality of the first signal based on the eye height and eye width of the second signal.

[0012] According to one embodiment of the present application, the sampling module is used to: perform equalization processing on the first signal to obtain the first signal after equalization processing; based on a set encoding method, perform signal branch sampling on the first signal after equalization processing to obtain the second signal; the signal branch sampling characterization extracts the signal branch of the first signal after equalization processing for sampling according to the set encoding method.

[0013] According to one embodiment of the present application, the simulation module is used to: through a set application, perform signal superposition on the second signal according to the time dimension and the voltage dimension to obtain the simulated eye diagram data of the second signal; the horizontal coordinate axis and the vertical coordinate axis are pre-set in the application, the horizontal coordinate axis represents the time dimension of the second signal, and the vertical coordinate axis represents the voltage dimension of the second signal.

[0014] According to one embodiment of the present application, the adjustment module is used to: adjust the horizontal center point position in the horizontal coordinate axis based on the timing offset to determine the critical value of the eye width of the second signal; the critical value of the eye width includes a first critical value and a second critical value; adjust the vertical center point position in the vertical coordinate axis based on the voltage offset to determine the critical value of the eye height of the second signal; the critical value of the eye height includes a third critical value and a fourth critical value; the horizontal center point position is different from the vertical center point position.

[0015] According to one embodiment of the present application, the adjustment module is used to: sequentially adjust the horizontal center point position in a first direction based on the timing offset, and determine the first critical value of the eye width in response to the simulated eye diagram data satisfying a set first condition; sequentially adjust the horizontal center point position in a second direction based on the timing offset, and determine the second critical value of the eye width in response to the simulated eye diagram data satisfying a set second condition; the first direction is opposite to the second direction, the first critical value is greater than the second critical value, and the first condition is the same as or different from the second condition.

[0016] According to one embodiment of the present application, the adjustment module is used to: sequentially adjust the vertical center point position in a third direction based on the voltage offset, and determine a third critical value of the eye height in response to the analog eye diagram data satisfying a set third condition; sequentially adjust the vertical center point position in a fourth direction based on the voltage offset, and determine a fourth critical value of the eye height in response to the analog eye diagram data satisfying a set fourth condition; the third direction is opposite to the fourth direction, the third critical value is greater than the fourth critical value, and the third condition is the same as or different from the fourth condition.

[0017] According to one embodiment of the present application, the calculation module is used to: subtract the first critical value from the second critical value to obtain the eye width of the second signal; and subtract the third critical value from the fourth critical value to obtain the eye height of the second signal.

[0018] According to a third aspect of the present application, an electronic device is provided, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present application.

[0019] The method of the embodiment of the present application samples the first signal received by the first chip to obtain the second signal; the first signal is a signal sent by the second chip to the first chip through the processor interconnection bus; the second chip and the first chip are on the same motherboard, and the first chip is different from the second chip; the second signal is superimposed to obtain the simulated eye diagram data of the second signal; by adjusting the center point position included in the simulated eye diagram data, the critical value of the eye height of the second signal and the critical value of the eye width of the second signal are determined; the eye height and eye width of the second signal are determined according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal; based on the eye height and eye width of the second signal, the signal quality of the first signal is determined. In this way, the signal quality of the signal transmitted between chips can be quantitatively evaluated, and the signal quality can be accurately evaluated.

[0020] It should be understood that the teachings of the present application are not required to achieve all of the beneficial effects described above, but specific technical solutions can achieve specific technical effects, and other embodiments of the present application can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become readily understood. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, wherein: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0022] Figure 1 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 1 ; Figure 2 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 2 ; Figure 3 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 3 ; Figure 4 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 4 ; Figure 5 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 5 ; Figure 6 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 6 ; Figure 7 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is shown as follows Figure 7 ; Figure 8 An application scenario diagram of the signal processing method of the chip provided in an embodiment of the present application is shown; Fig. 9 Another application scenario diagram of the signal processing method of the chip provided in the embodiment of the present application is shown; Fig.10 An optional schematic diagram of a signal processing device of a chip provided in an embodiment of the present application is shown; Fig.11 An optional schematic diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, features, and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0024] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0027] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0028] DFE (Decision Feedback Equalizer) is used to eliminate inter-signal interference caused by lossy channels through finite impulse response filters, adders, and slicers.

[0029] The processing flow of the signal processing method of the chip provided in the embodiment of the present application is described. Figure 1 , Figure 1 The processing flow diagram of the signal processing method of the chip provided in the embodiment of the present application is as follows Figure 1 , will combine Figure 1 Steps S101-S105 are shown for explanation.

[0030] Step S101, sampling a first signal received by a first chip to obtain a second signal; the first signal is a signal sent by the second chip to the first chip through a processor interconnect bus; the second chip and the first chip are on the same motherboard, and the first chip is different from the second chip.

[0031] In some embodiments, the first chip and the second chip may be located on the same motherboard, and the first chip and the second chip communicate through a processor interconnect bus. The processor (CPU) interconnect bus may include: a high-speed communication bus between chips. The CPU interconnect bus may be used to transmit signals between chips. The motherboard may include a motherboard on a server. The motherboard may be connected to multiple chips, and the embodiment of the present application does not limit the number of chips connected to the motherboard, nor does it limit the specific motherboard. The first chip and the second chip are chips located in different slots in the motherboard. The embodiment of the present application does not limit the specific first chip and the second chip. Sampling may include: extracting discrete sample values ​​from a continuous first signal at set time intervals. The second signal may be used for digital signal processing.

[0032] Step S102: performing signal superposition on the second signal to obtain simulated eye diagram data of the second signal.

[0033] In some embodiments, the simulated eye diagram data may include: graphical data formed by superimposing the second signal multiple times. The simulated eye diagram data may be used to evaluate signal quality.

[0034] Step S103, determining a critical value of an eye height of the second signal and a critical value of an eye width of the second signal by adjusting a center point position included in the simulated eye diagram data.

[0035] In some embodiments, the center point position may include a horizontal center point position and a vertical center point position. The horizontal center point and the vertical center point are not the same center point. The horizontal center point is related to the time dimension of the second signal. The vertical center point is related to the voltage dimension of the second signal. The critical value of the eye width may include: by adjusting the horizontal center point position, determining the error tolerance range of the second signal in time. The critical value of the eye height may include: by adjusting the vertical center point position, determining the error tolerance range of the second signal in voltage.

[0036] Step S104: determining the eye height and the eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal.

[0037] Step S105: determining the signal quality of the first signal based on the eye height and the eye width of the second signal.

[0038] In some embodiments, the eye height may include: the height of the analog eye diagram data in the vertical direction. The eye height may be used to indicate the voltage margin of the second signal. The eye width may include: the width of the analog eye diagram data in the horizontal direction. The eye width may be used to indicate the timing margin of the second signal. The larger the eye height, the larger the amplitude margin of the second signal. The larger the eye width, the larger the timing margin of the second signal. Based on the eye height and eye width of the second signal, its signal quality may be determined by comparing with a preset standard value. If both the eye height and the eye width are greater than or equal to the standard value, it is determined that the signal quality of the first signal is good; if the eye height and the eye width are less than the standard value, it is determined that the signal quality of the first signal is poor. The preset standard value may include the minimum requirements for the eye height and the eye width. The preset standard value may be used to determine whether the first signal can be reliably transmitted in a noise and interference environment.

[0039] As an example, the first chip is processor A, and the second chip is processor B, and the two are connected through a processor interconnect bus. First, processor A receives a first signal sent by processor B. The sampling circuit built into processor A samples the first signal at a sampling frequency of 10Gbps to obtain a second signal. Then, the signal processing module of processor A superimposes the second signal multiple times, aligns the rising edge and the falling edge of the signal each time it is superimposed, and generates simulated eye diagram data. Then, by adjusting the center point position of the simulated eye diagram data, the fault tolerance range of the second signal in voltage and the fault tolerance range of the second signal in time are found, and the critical value of the eye height is determined to be 100mV, and the critical value of the eye width is 50ps. According to the determined critical value of the eye height of 100mV and the critical value of the eye width of 50ps, the actual eye height of the second signal is calculated to be 200mV and the eye width is 100ps. Finally, these eye height and eye width parameters are compared with the preset standard values. If the eye height and eye width are both greater than the standard values, it is considered that the signal quality of the first signal is good. If the eye height and eye width are both less than the standard values, it is considered that the signal quality of the first signal is poor.

[0040] The method of the embodiment of the present application branches the sampling signal inside the chip, encodes and samples the signal, generates analog eye diagram data through an analog oscilloscope inside the chip, and through multiple sampling and superposition, can more clearly display the timing and amplitude characteristics of the signal, determine the eye height and eye width of the signal based on the analog eye diagram data, quantitatively evaluate and directly determine the signal quality, and can intuitively display the timing and amplitude characteristics of the signal, thereby more accurately evaluating the signal quality of the signal transmitted between chips.

[0041] In some embodiments, the processing flow of the signal processing method of the chip is shown as follows: Figure 2 ,like Figure 2 As shown, sampling the first signal received by the first chip to obtain the second signal in step S101 may include: Step S201, performing equalization processing on the first signal to obtain the equalized first signal.

[0042] In this embodiment, the equalization processing may include: AFE (Analog Front End), CTLE (Continuous Time Linear Equalizer), VGA (Variable Gain Amplifier) ​​and DFE. The first signal may be received by the CPU receiving end RX. The first signal after equalization processing may be processed by the CPU.

[0043] Step S202: Based on the set coding mode, signal branch sampling is performed on the first signal after equalization processing to obtain a second signal.

[0044] In some embodiments, the set encoding method may include: referring to the encoding rules predefined in the signal transmission process. The set encoding method can be used to encode and decode the first signal after equalization processing. Signal branch sampling may include extracting the signal branch of the first signal after equalization processing for sampling according to the set encoding method. To obtain signal data for analysis and processing. In the data branch sampling process, when the first signal after equalization processing is extracted, the signal encoding method is 00, 01, 10, 11. The encoding method indicates that every two bits are used as a coding unit. For example, for the binary sequence 00011011, it can be grouped according to every two bits to obtain 00, 01, 10, 11. In the sampling process, the signal is branched and sampled according to these encoding methods, and the corresponding signal branches are extracted. Usually, a high level is represented as a logic "1" and a low level is represented as a logic "0". The encoding methods are 00, 01, 10, 11, which can be mapped to a combination of high and low levels. Specifically as follows: 00 can represent: low level-low level; 01 can represent: low level-high level; 10 can represent: high level-low level; 11 can represent: high level-high level.

[0045] The method of the embodiment of the present application branches the sampling signal inside the chip, encodes and samples the signal after equalization processing, generates analog eye diagram data through an analog oscilloscope inside the chip, and through multiple sampling and superposition, can more clearly display the timing and amplitude characteristics of the signal, determine the eye height and eye width of the signal according to the analog eye diagram data, quantitatively evaluate and directly determine the signal quality, and can intuitively display the timing and amplitude characteristics of the signal, thereby more accurately evaluating the signal quality of the signal transmitted between chips.

[0046] In some embodiments, the processing flow of the signal processing method of the chip is shown as follows: Figure 3 ,like Figure 3 As shown, the signal processing method of the chip may further include: Step S301: superimpose the second signal according to the time dimension and the voltage dimension through a set application program to obtain simulated eye diagram data of the second signal.

[0047] In some embodiments, the second signal can be used to evaluate the signal quality of the first signal. The horizontal coordinate axis and the vertical coordinate axis can be pre-set in the application, the horizontal coordinate axis can represent the time dimension of the second signal, and the vertical coordinate axis can represent the voltage dimension of the second signal. The application can call the function of the analog oscilloscope through the interface of the CPU. The analog oscilloscope is a functional module inside the CPU, which is used to collect and display signals in real time. The analog oscilloscope can collect and process the second signal under the control of the CPU to generate analog eye diagram data of the second signal.

[0048] As an example, the analog oscilloscope function is integrated inside the CPU. By calling the CPU interface, the application first establishes the coordinate axis inside the application. The horizontal coordinate axis is used to represent the time dimension, and the vertical coordinate axis is used to represent the voltage dimension. Then, the signal eye diagram is calibrated: in the horizontal direction, the full-rate (Full-Rate) and half-rate (Half-Rate) sampling operating frequencies are used to calibrate the 0 value of the horizontal coordinate axis; in the vertical direction, through data branch sampling, the 10 and 01 eye diagram data are centered to calibrate the 0 value of the vertical coordinate axis, so that the voltage reference of the signal is centered. Then, the second signal is superimposed according to the time dimension and the voltage dimension to obtain the analog eye diagram data of the second signal, and the analog eye diagram data is displayed in the horizontal coordinate axis and the vertical coordinate axis.

[0049] Step S302: Determine a critical value of an eye height of the second signal and a critical value of an eye width of the second signal by adjusting a center point position included in the simulated eye diagram data.

[0050] The specific description of step S302 is the same as that of step S103 and will not be repeated here.

[0051] The method of the embodiment of the present application branches the sampling signal inside the chip, encodes and samples the signal, and superimposes the second signal according to the time dimension and the voltage dimension through a set application inside the chip to generate analog eye diagram data. Through multiple sampling and superposition, the timing and amplitude characteristics of the signal can be displayed more clearly, the eye height and eye width of the signal can be determined according to the analog eye diagram data, the signal quality can be quantitatively evaluated and directly judged, and the timing and amplitude characteristics of the signal can be intuitively displayed, thereby more accurately evaluating the signal quality of the signal transmitted between chips.

[0052] In some embodiments, the processing flow of the signal processing method of the chip is shown as follows: Figure 4 ,like Figure 4 As shown, in step S103, determining the critical value of the eye height of the second signal and the critical value of the eye width of the second signal by adjusting the center point position included in the simulated eye diagram data may include: Step S401 : adjusting the position of the horizontal center point in the horizontal coordinate axis based on the timing offset to determine a critical value of the eye width of the second signal.

[0053] Step S402 : adjusting the vertical center point position in the vertical coordinate axis based on the voltage offset to determine a critical value of the eye height of the second signal.

[0054] In this embodiment, the critical value of the eye width may include a first critical value and a second critical value. The critical value of the eye height may include a third critical value and a fourth critical value. The horizontal center point position may be different from the vertical center point position. In the eye diagram data, the horizontal center point may be used to represent the center position of the second signal in the time dimension, and the vertical center point may be used to represent the center position of the second signal in the voltage dimension. On the horizontal coordinate axis, the second signal is quantized in the horizontal direction to deflect, and the critical value (margin) of the analog eye diagram data in the time dimension may be determined. On the vertical coordinate axis, the second signal is quantized in the vertical direction to deflect, and the critical value of the analog eye diagram data in the voltage dimension may be determined. The timing offset may include: on the horizontal coordinate axis, the offset of the time reference of the signal relative to the center point position. The voltage offset may include: on the vertical coordinate axis, the offset of the voltage reference of the signal relative to the center point position.

[0055] As an example, the analog oscilloscope samples and superimposes the second signal to generate analog eye diagram data. Then, the horizontal center point position included in the analog eye diagram data is adjusted based on the timing offset in the horizontal coordinate axis, wherein the positive direction of the horizontal coordinate axis is horizontal to the right, and the position of the horizontal center point is adjusted to the left and right respectively by changing the timing offset until the second signal has an error, thereby determining the first critical value and the second critical value of the analog eye diagram data. The first critical value is the right margin of timing, and the second critical value is the left margin of timing. Then, the vertical center point position included in the analog eye diagram data is adjusted based on the voltage offset in the vertical coordinate axis, wherein the positive direction of the vertical coordinate axis is vertically upward, and the position of the vertical center point is adjusted upward and downward respectively by changing the voltage offset until the second signal has an error, thereby determining the third critical value and the fourth critical value of the analog eye diagram data. The third critical value is the upper margin of voltage, and the fourth critical value is the lower margin of voltage.

[0056] The method of the embodiment of the present application, by branching the sampling signal inside the chip, encodes and samples the signal, generates analog eye diagram data through an analog oscilloscope inside the chip, and through multiple sampling and superposition, can more clearly display the timing and amplitude characteristics of the signal, and by adjusting the center point position of the analog eye diagram data, determine the critical values ​​of the eye width and eye height of the second signal in the horizontal and vertical directions respectively. It can accurately determine the timing and amplitude boundaries of the signal, and then determine the eye height and eye width of the signal, quantitatively evaluate and directly determine the signal quality, and can intuitively display the timing and amplitude characteristics of the signal, so as to more accurately evaluate the signal quality of the signal transmitted between chips.

[0057] In some embodiments, the processing flow of the signal processing method of the chip is shown as follows: Figure 5 ,like Figure 5 As shown, the step S401 of adjusting the horizontal center point position in the horizontal coordinate axis based on the timing offset to determine the critical value of the eye width of the second signal may include: Step S501 : adjusting the horizontal center point position in a first direction in sequence based on the timing offset, and determining a first critical value of the eye width in response to the simulated eye diagram data satisfying a set first condition.

[0058] Step S502 , adjusting the horizontal center point position in sequence in a second direction based on the timing offset, and determining a second critical value of the eye width in response to the simulated eye diagram data satisfying a set second condition.

[0059] In this embodiment, the first direction is opposite to the second direction, the first critical value is greater than the second critical value, and the first condition is the same as or different from the second condition. The first direction may be the positive direction of the horizontal coordinate axis, and the second direction may be the negative direction of the horizontal coordinate axis. The first condition may be the set degree of closure of the simulated eye diagram data. The degree of closure of the simulated eye diagram data is used to reflect the degree of interference and distortion of the signal during transmission. When the degree of closure is large, it can be indicated that the interference or distortion of the signal is large. When the degree of closure of the simulated eye diagram data is greater than or equal to the set degree of closure, it is determined that the simulated eye diagram data meets the set first condition. The second condition may be the same as the degree of closure of the simulated eye diagram data set in the first condition, or the second condition may be different from the degree of closure of the simulated eye diagram data set in the first condition. Sequential adjustment may include: gradually changing the position of the horizontal center point according to the set order and step size. For example, starting from the initial position, adjusting +1 or -1 time units each time, and gradually adjusting the position of the horizontal center point until the simulated eye diagram data meets the set condition.

[0060] As an example, the positive direction of the horizontal coordinate axis is horizontally to the right, and the horizontal center point position is adjusted to the right, and the step size of each adjustment is +1 time unit. After each adjustment, it is determined whether the simulated eye diagram data meets the first condition. When the simulated eye diagram data meets the first condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set first condition, and the timing offset value at this time is determined as the first critical value of the eye width. Adjust the horizontal center point position to the left, and the step size of each adjustment is -1 time unit. After each adjustment, it is determined whether the simulated eye diagram data meets the second condition. When the simulated eye diagram data meets the second condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set second condition, and the timing offset value at this time is determined as the second critical value of the eye width.

[0061] The method of the embodiment of the present application, by branching the sampling signal inside the chip, encodes and samples the signal, generates analog eye diagram data through an analog oscilloscope inside the chip, and through multiple sampling and superposition, can more clearly display the timing and amplitude characteristics of the signal, adjust the horizontal center point position based on the timing offset in the horizontal coordinate axis, and determine the critical value of the eye width of the second signal. It can accurately determine the boundary of the signal in the time dimension, and then determine the eye height and eye width of the signal, quantitatively evaluate and directly determine the signal quality, and can intuitively display the timing and amplitude characteristics of the signal, so as to more accurately evaluate the signal quality of the signal transmitted between chips.

[0062] In some embodiments, the processing flow of the signal processing method of the chip is shown as follows: Figure 6 ,like Figure 6 As shown, in step S402, adjusting the vertical center point position in the vertical coordinate axis based on the voltage offset to determine the critical value of the eye height of the second signal may include: Step S601 : adjusting the vertical center point position in sequence in a third direction based on the voltage offset, and determining a third critical value of the eye height in response to the simulated eye diagram data satisfying a set third condition.

[0063] Step S602 , adjusting the vertical center point position in sequence in a fourth direction based on the voltage offset, and determining a fourth critical value of the eye height in response to the simulated eye diagram data satisfying a set fourth condition.

[0064] In this embodiment, the third direction is opposite to the fourth direction, the third critical value is greater than the fourth critical value, and the third condition is the same as or different from the fourth condition. Among them, the third direction can be the positive direction of the vertical coordinate axis, and the fourth direction can be the negative direction of the vertical coordinate axis. The third condition can be the set degree of closure of the simulated eye diagram data. The degree of closure of the simulated eye diagram data is used to reflect the degree of interference and distortion of the signal during transmission. When the degree of closure is large, it can be indicated that the interference or distortion of the signal is large. When the degree of closure of the simulated eye diagram data is greater than or equal to the set degree of closure, it is determined that the simulated eye diagram data meets the set third condition. The fourth condition can be the same as the degree of closure of the simulated eye diagram data set in the third condition, and the fourth condition can also be different from the degree of closure of the simulated eye diagram data set in the third condition. Sequential adjustment can include: gradually changing the position of the vertical center point according to the set order and step size. For example, starting from the initial position, adjusting +1 or -1 voltage units each time, and gradually adjusting the position of the vertical center point until the simulated eye diagram data meets the set condition.

[0065] As an example, the positive direction of the vertical coordinate axis is vertically upward, and the vertical center point position is adjusted upward, and the step size of each adjustment is +1 voltage unit. After each adjustment, it is determined whether the simulated eye diagram data meets the third condition. When the simulated eye diagram data meets the third condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set third condition, and the voltage offset value at this time is determined as the third critical value of the eye height. The vertical center point position is adjusted downward, and the step size of each adjustment is -1 voltage unit. After each adjustment, it is determined whether the simulated eye diagram data meets the fourth condition. When the simulated eye diagram data meets the fourth condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set fourth condition, and the voltage offset value at this time is determined as the fourth critical value of the eye height.

[0066] The method of the embodiment of the present application, by branching the sampling signal inside the chip, encodes and samples the signal, generates analog eye diagram data through an analog oscilloscope inside the chip, and through multiple sampling and superposition, can more clearly display the timing and amplitude characteristics of the signal, adjust the vertical center point position based on the voltage offset in the vertical coordinate axis, and determine the critical value of the eye height of the second signal. It can accurately determine the boundary of the signal in the voltage dimension, and then determine the eye height and eye width of the signal, quantitatively evaluate and directly determine the signal quality, and can intuitively display the timing and amplitude characteristics of the signal, so as to more accurately evaluate the signal quality of the signal transmitted between chips.

[0067] In some embodiments, the processing flow of the signal processing method of the chip is shown as follows: Figure 7 ,like Figure 7 As shown, determining the eye height and the eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal in step S104 may include: Step S701: Subtract the first critical value from the second critical value to obtain the eye width of the second signal.

[0068] Step S702: Subtract the third critical value from the fourth critical value to obtain the eye height of the second signal.

[0069] In this embodiment, the eye width can be determined by the time difference between the right limit and the left limit of the eye width in the simulated eye diagram data. Specifically, eye width=right limit-left limit. The right limit is the first critical value, and the left limit is the second critical value. The eye height can be determined by the voltage difference between the upper limit and the lower limit of the eye height in the simulated eye diagram data. Specifically, the eye height=upper limit-lower limit. The upper limit is the third critical value, and the lower limit is the fourth critical value.

[0070] The method of the embodiment of the present application, by branching the sampling signal inside the chip, encodes and samples the signal, generates analog eye diagram data through an analog oscilloscope inside the chip, and through multiple sampling and superposition, can more clearly display the timing and amplitude characteristics of the signal, and calculate the eye width and eye height of the signal through the critical value of the eye width and the critical value of the eye height. It can provide quantitative evaluation indicators of the signal, can intuitively display the timing and amplitude characteristics of the signal, and thus more accurately evaluate the signal quality of the signal transmitted between chips.

[0071] Figure 8 An application scenario diagram of the signal processing method of the chip provided in an embodiment of the present application is shown.

[0072] refer to Figure 8 An application scenario of the signal processing method of the chip provided in an embodiment of the present application is applied to the signal processing flow of the CPU.

[0073] First, the RX end of the CPU receives the signal sent by other CPUs through the CPU interconnect bus.

[0074] The signal received by the RX end is equalized through the equalization processing module to obtain the equalized signal. Among them, the equalization processing module includes: AFE module, CTLE module, VGA module and DFE module. The AFE module is used to perform preliminary amplification and filtering on the signal to improve the quality of the signal. The CTLE module is used to compensate for the distortion caused by the channel characteristics during the transmission of the signal, and restore the original shape of the signal by adjusting the frequency response of the signal. The VGA module is used to adjust the amplitude of the signal to ensure that the signal maintains a suitable level range during subsequent processing. The DFE module is used to further compensate the signal through a feedback mechanism, eliminate inter-code interference, and improve the reception quality of the signal.

[0075] Based on the set coding mode, the signal after equalization is sampled by signal branches to obtain the signal after branch sampling, and the signal branch sampling does not affect the signal quality of the signal after equalization. The signal branch sampling characterization extracts the signal branches of the signal after equalization for sampling according to the set coding mode.

[0076] Understandably, Figure 8 The application scenarios of the signal processing method of the chip are only some exemplary implementations in the embodiments of the present application. The application scenarios of the signal processing method of the chip in the embodiments of the present application include but are not limited to Figure 8 Application scenarios of the signal processing method of the chip shown.

[0077] Fig. 9 Another application scenario diagram of the signal processing method of the chip provided in an embodiment of the present application is shown.

[0078] refer to Fig. 9 Another application scenario of the signal processing method of the chip provided in the embodiment of the present application is applied to determine the critical value of the eye height and the critical value of the eye width of the signal.

[0079] The timing center point position included in the simulated eye diagram data is adjusted based on the timing offset in the horizontal coordinate axis, wherein the positive direction of the horizontal coordinate axis is horizontally to the right, and the position of the timing center point is adjusted leftward and rightward respectively by changing the timing offset until an error occurs in the second signal, thereby determining a first critical value and a second critical value of the simulated eye diagram data. The first critical value is the right limit of the timing, and the second critical value is the left limit of the timing.

[0080] The positive direction of the horizontal coordinate axis is horizontal to the right. The timing center point position is adjusted to the right, and the step length of each adjustment is +1 time unit. After each adjustment, it is determined whether the simulated eye diagram data meets the first condition. When the simulated eye diagram data meets the first condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set first condition, and the timing offset value at this time is determined as the first critical value of the eye width. Adjust the timing center point position to the left, and the step length of each adjustment is -1 time unit. After each adjustment, it is determined whether the simulated eye diagram data meets the second condition. When the simulated eye diagram data meets the second condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set second condition, and the timing offset value at this time is determined as the second critical value of the eye width.

[0081] Then, the voltage center point position included in the simulated eye diagram data is adjusted based on the voltage offset in the vertical coordinate axis, wherein the positive direction of the vertical coordinate axis is vertically upward, and the voltage center point position is adjusted upward and downward respectively by changing the voltage offset until an error occurs in the signal, thereby determining the third critical value and the fourth critical value of the simulated eye diagram data. The third critical value is the upper limit of the voltage, and the fourth critical value is the lower limit of the voltage.

[0082] The positive direction of the vertical coordinate axis is vertically upward, and the voltage center point position is adjusted upward, and the step length of each adjustment is +1 voltage unit. After each adjustment, it is determined whether the simulated eye diagram data meets the third condition. When the simulated eye diagram data meets the third condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set third condition, and the voltage offset value at this time is determined as the third critical value of the eye height. The voltage center point position is adjusted downward, and the step length of each adjustment is -1 voltage unit. After each adjustment, it is determined whether the simulated eye diagram data meets the fourth condition. When the simulated eye diagram data meets the fourth condition and is greater than or equal to the set closure degree, it is determined that the simulated eye diagram data meets the set fourth condition, and the voltage offset value at this time is determined as the fourth critical value of the eye height.

[0083] Understandably, Fig. 9 The application scenarios of the signal processing method of the chip are only some exemplary implementations in the embodiments of the present application. The application scenarios of the signal processing method of the chip in the embodiments of the present application include but are not limited to Fig. 9 Application scenarios of the signal processing method of the chip shown.

[0084] The following is a description of an exemplary structure of a software module included in the chip signal processing device 90 provided in an embodiment of the present application. In some embodiments, Fig.10 As shown, a chip signal processing device 90 includes: a sampling module 901, which is used to sample a first signal received by a first chip to obtain a second signal; the first signal is a signal sent by the second chip to the first chip through a processor interconnection bus; the second chip and the first chip are on the same mainboard, and the first chip is different from the second chip; a simulation module 902, which is used to perform signal superposition on the second signal to obtain simulated eye diagram data of the second signal; an adjustment module 903, which is used to determine the critical value of the eye height of the second signal and the critical value of the eye width of the second signal by adjusting the center point position included in the simulated eye diagram data; a calculation module 904, which is used to determine the eye height and eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal; a determination module 905, which is used to determine the signal quality of the first signal based on the eye height and eye width of the second signal.

[0085] In some embodiments, the sampling module 901 is used to: perform equalization processing on the first signal to obtain a first signal after equalization processing; based on a set encoding method, perform signal branch sampling on the first signal after equalization processing to obtain the second signal; the signal branch sampling characterization extracts the signal branch of the first signal after equalization processing for sampling according to the set encoding method.

[0086] In some embodiments, the simulation module 902 is used to: through a set application, perform signal superposition on the second signal according to the time dimension and the voltage dimension to obtain simulated eye diagram data of the second signal; the horizontal coordinate axis and the vertical coordinate axis are pre-set in the application, the horizontal coordinate axis represents the time dimension of the second signal, and the vertical coordinate axis represents the voltage dimension of the second signal.

[0087] In some embodiments, the adjustment module 903 is used to: adjust the horizontal center point position in the horizontal coordinate axis based on the timing offset to determine the critical value of the eye width of the second signal; the critical value of the eye width includes a first critical value and a second critical value; adjust the vertical center point position in the vertical coordinate axis based on the voltage offset to determine the critical value of the eye height of the second signal; the critical value of the eye height includes a third critical value and a fourth critical value; the horizontal center point position is different from the vertical center point position.

[0088] In some embodiments, the adjustment module 903 is used to: sequentially adjust the horizontal center point position in a first direction based on the timing offset, and determine the first critical value of the eye width in response to the simulated eye diagram data satisfying a set first condition; sequentially adjust the horizontal center point position in a second direction based on the timing offset, and determine the second critical value of the eye width in response to the simulated eye diagram data satisfying a set second condition; the first direction is opposite to the second direction, the first critical value is greater than the second critical value, and the first condition is the same as or different from the second condition.

[0089] In some embodiments, the adjustment module 903 is used to: sequentially adjust the vertical center point position in a third direction based on the voltage offset, and determine a third critical value of the eye height in response to the analog eye diagram data satisfying a set third condition; sequentially adjust the vertical center point position in a fourth direction based on the voltage offset, and determine a fourth critical value of the eye height in response to the analog eye diagram data satisfying a set fourth condition; the third direction is opposite to the fourth direction, the third critical value is greater than the fourth critical value, and the third condition is the same as or different from the fourth condition.

[0090] In some embodiments, the calculation module 904 is used to: subtract the first critical value from the second critical value to obtain the eye width of the second signal; and subtract the third critical value from the fourth critical value to obtain the eye height of the second signal. It should be noted that the description of the device in the embodiment of the present application is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, so it will not be repeated. Figures 1 to 9 The present invention can be understood by referring to the description of any one of the accompanying drawings.

[0091] According to an embodiment of the present application, the present application also provides an electronic device and a non-transitory computer-readable storage medium.

[0092] Fig.11A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0093] like Fig.11 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a ROM 802 or a computer program loaded from a storage unit 808 into a RAM 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An I / O interface 805 is also connected to the bus 804.

[0094] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0095] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the signal processing method of the chip. For example, in some embodiments, the signal processing method of the chip may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the signal processing method of the chip described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the signal processing method of the chip in any other appropriate manner (e.g., by means of firmware).

[0096] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions / operations specified in the flow chart and / or block diagram. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0098] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0100] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0101] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0102] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0103] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0104] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip signal processing method, characterized in that: The method comprises: Sampling a first signal received by the first chip to obtain a second signal; the first signal is a signal sent by the second chip to the first chip through a processor interconnection bus; the second chip and the first chip are on the same motherboard, and the first chip is different from the second chip; Performing signal superposition on the second signal to obtain simulated eye diagram data of the second signal; Determine a critical value of an eye height of the second signal and a critical value of an eye width of the second signal by adjusting a center point position included in the simulated eye diagram data; determining an eye height and an eye width of the second signal according to a critical value of an eye height of the second signal and a critical value of an eye width of the second signal; The signal quality of the first signal is determined based on the eye height and the eye width of the second signal.

2. The method according to claim 1, characterized in that The step of sampling the first signal received by the first chip to obtain the second signal includes: Performing equalization processing on the first signal to obtain a first signal after equalization processing; Based on a set encoding mode, performing signal branch sampling on the first signal after the equalization processing to obtain the second signal; The signal branch sampling representation extracts the signal branch of the equalized first signal for sampling according to a set encoding method.

3. The method according to claim 1, characterized in that The performing signal superposition on the second signal to obtain simulated eye diagram data of the second signal includes: By using a set application program, signal superposition is performed on the second signal according to a time dimension and a voltage dimension to obtain simulated eye diagram data of the second signal; A horizontal coordinate axis and a vertical coordinate axis are preset in the application, wherein the horizontal coordinate axis represents the time dimension of the second signal, and the vertical coordinate axis represents the voltage dimension of the second signal.

4. The method according to claim 3, characterized in that: The step of determining a critical value of an eye height of the second signal and a critical value of an eye width of the second signal by adjusting a center point position included in the simulated eye diagram data comprises: Adjusting the position of the horizontal center point in the horizontal coordinate axis based on the timing offset to determine a critical value of the eye width of the second signal; the critical value of the eye width includes a first critical value and a second critical value; The vertical center point position is adjusted based on the voltage offset in the vertical coordinate axis to determine a critical value of the eye height of the second signal; the critical value of the eye height includes a third critical value and a fourth critical value; the horizontal center point position is different from the vertical center point position.

5. The method according to claim 4, characterized in that The step of adjusting the horizontal center point position in the horizontal coordinate axis based on the timing offset to determine the critical value of the eye width of the second signal includes: sequentially adjusting the position of the horizontal center point in a first direction based on the timing offset, and determining a first critical value of the eye width in response to the simulated eye diagram data satisfying a set first condition; sequentially adjusting the position of the horizontal center point in a second direction based on the timing offset, and determining a second critical value of the eye width in response to the simulated eye diagram data satisfying a set second condition; The first direction is opposite to the second direction, the first critical value is greater than the second critical value, and the first condition is the same as or different from the second condition.

6. The method according to claim 4, characterized in that The step of adjusting the vertical center point position in the vertical coordinate axis based on the voltage offset to determine the critical value of the eye height of the second signal includes: sequentially adjusting the vertical center point position in a third direction based on the voltage offset, and determining a third critical value of the eye height in response to the simulated eye diagram data satisfying a set third condition; sequentially adjusting the vertical center point position in a fourth direction based on the voltage offset, and determining a fourth critical value of the eye height in response to the simulated eye diagram data satisfying a set fourth condition; The third direction is opposite to the fourth direction, the third critical value is greater than the fourth critical value, and the third condition is the same as or different from the fourth condition.

7. The method according to claim 4, characterized in that The determining the eye height and the eye width of the second signal according to the critical value of the eye height of the second signal and the critical value of the eye width of the second signal comprises: Subtract the first critical value from the second critical value to obtain the eye width of the second signal; The eye height of the second signal is obtained by subtracting the third critical value from the fourth critical value.

8. A chip signal processing device, characterized in that: The device comprises: a sampling module, configured to sample a first signal received by the first chip to obtain a second signal; the first signal is a signal sent by the second chip to the first chip through a processor interconnection bus; the second chip and the first chip are on the same motherboard, and the first chip is different from the second chip; A simulation module, used for performing signal superposition on the second signal to obtain simulated eye diagram data of the second signal; An adjustment module, configured to determine a critical value of an eye height of the second signal and a critical value of an eye width of the second signal by adjusting a center point position included in the simulated eye diagram data; a calculation module, configured to determine an eye height and an eye width of the second signal according to a critical value of an eye height of the second signal and a critical value of an eye width of the second signal; A determination module is used to determine the signal quality of the first signal based on the eye height and the eye width of the second signal.

9. The device according to claim 8, characterized in that The sampling module is used for: Performing equalization processing on the first signal to obtain a first signal after equalization processing; Based on a set encoding mode, performing signal branch sampling on the first signal after the equalization processing to obtain the second signal; The signal branch sampling representation extracts the signal branch of the equalized first signal for sampling according to a set encoding method.

10. The device according to claim 8, characterized in that The simulation module is used to: By using a set application program, signal superposition is performed on the second signal according to a time dimension and a voltage dimension to obtain simulated eye diagram data of the second signal; A horizontal coordinate axis and a vertical coordinate axis are preset in the application, wherein the horizontal coordinate axis represents the time dimension of the second signal, and the vertical coordinate axis represents the voltage dimension of the second signal.

11. The device according to claim 10, characterized in that The adjustment module is used for: Adjusting the position of the horizontal center point in the horizontal coordinate axis based on the timing offset to determine a critical value of the eye width of the second signal; the critical value of the eye width includes a first critical value and a second critical value; The vertical center point position is adjusted based on the voltage offset in the vertical coordinate axis to determine a critical value of the eye height of the second signal; the critical value of the eye height includes a third critical value and a fourth critical value; the horizontal center point position is different from the vertical center point position.

12. The device according to claim 11, characterized in that The adjustment module is used for: sequentially adjusting the position of the horizontal center point in a first direction based on the timing offset, and determining a first critical value of the eye width in response to the simulated eye diagram data satisfying a set first condition; sequentially adjusting the position of the horizontal center point in a second direction based on the timing offset, and determining a second critical value of the eye width in response to the simulated eye diagram data satisfying a set second condition; The first direction is opposite to the second direction, the first critical value is greater than the second critical value, and the first condition is the same as or different from the second condition.

13. The device according to claim 11, characterized in that The adjustment module is used for: sequentially adjusting the vertical center point position in a third direction based on the voltage offset, and determining a third critical value of the eye height in response to the simulated eye diagram data satisfying a set third condition; sequentially adjusting the vertical center point position in a fourth direction based on the voltage offset, and determining a fourth critical value of the eye height in response to the simulated eye diagram data satisfying a set fourth condition; The third direction is opposite to the fourth direction, the third critical value is greater than the fourth critical value, and the third condition is the same as or different from the fourth condition.

14. The device according to claim 11, characterized in that The computing module is used for: Subtract the first critical value from the second critical value to obtain the eye width of the second signal; The eye height of the second signal is obtained by subtracting the third critical value from the fourth critical value.

15. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

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