Modeling method and device for PHY chip supporting 1000BASE-T, equipment and medium

Abstract

The invention discloses a modeling method, device, equipment and medium for a PHY chip supporting 1000BASE-T. In the modeling process of the PHY chip, logic separation processing is performed on a transmission channel used for full duplex communication in the PHY chip to form a first signal channel and a second signal channel which are mutually independent and opposite in signal transmission direction; performing quantization processing on the first sending signal and the second sending signal to obtain a corresponding first discrete floating point signal and a corresponding second discrete floating point signal; and performing multi-stage filtering processing on the first discrete floating point signal and the second discrete floating point signal to obtain a first continuous signal and a second continuous signal. According to the technical scheme, in a 1000BASE-T high-speed transmission and complex interference scene, on the basis of ensuring the integrity and reliability during signal transmission, an accurate modeling effect is provided in the design stage of the PHY chip, so that the performance of the chip in a real environment is predicted more accurately.

Description

Technical Field

[0001] The present invention relates to the field of chip modeling technology, and in particular to a modeling method, device, equipment and medium for a PHY (Port Physical Layer) chip supporting 1000BASE-T (1000 Megabits per Second Baseband Twisted Pair). Background Art

[0002] As one of the mainstream technologies of modern network communication, Gigabit Ethernet is widely used in high-bandwidth data transmission scenarios. The MDI (Media Dependent Interface) of the Gigabit Ethernet PHY chip is an important interface for physical layer data transmission. It supports multiple rate modes, including 10BASE-T, 100BASE-TX and 1000BASE-T. Among them, the 10BASE-T and 100BASE-TX modes only require two pairs of twisted pairs for data transmission. The sending path and the receiving path are independent of each other, realizing relatively simple half-duplex or full-duplex communication.

[0003] In the higher performance 1000BASE-T mode, the MDI interface of the PHY chip needs to use all four pairs of twisted pairs for transmission, and adopts full-duplex transmission. Its notable feature is that the transmission path and the reception path overlap on each pair of twisted pairs, that is, the same pair of cables needs to receive signals while sending signals. This design improves the utilization rate of the line, but also puts higher requirements on signal processing technology.

[0004] In order to achieve bidirectional transmission on a single twisted pair, a hybrid circuit was introduced into the 1000BASE-T design. The main function of the hybrid circuit is to couple the transmit signal and the receive signal in the same pair of cables for transmission, and to avoid mutual interference between the signals through complex echo and crosstalk elimination algorithms. However, this places extremely high demands on the design of the hybrid circuit, especially when dealing with near-end and far-end crosstalk, which can easily lead to the problem of low signal transmission stability caused by the crosstalk phenomenon.

[0005] In order to better analyze and design 1000BASE-T signal processing systems (such as DAC, ADC, mixing circuits, etc.), ADC modeling methods are usually used in related technologies, which are mainly based on specific circuit structures (such as pipeline ADC, successive approximation ADC, etc.). Although these methods are suitable for traditional signal processing needs, they show obvious limitations when facing high-speed signal transmission and complex electromagnetic interference environments. These methods are difficult to meet the judgment requirements for complex signals in terms of accuracy and robustness, especially in Gigabit Ethernet 1000BASE-T scenarios, the ability to reliably restore signals is limited, resulting in rough modeling results.

[0006] In summary, the relevant DAC / ADC modeling methods are difficult to meet the requirements of Gigabit Ethernet 1000BASE-T high-speed transmission, and the insufficient support for signal integrity and reliability leads to rough modeling effects. Summary of the invention

[0007] The main purpose of the present invention is to propose a modeling method, device, equipment and medium for a PHY chip supporting 1000BASE-T, aiming to at least solve the technical problems in the related art such as the rough modeling effect of DAC modeling in a complex signal transmission environment.

[0008] According to a first aspect of the present invention, a modeling method for a PHY chip supporting 1000BASE-T is provided, wherein the PHY chip includes a first bidirectional transmission module and a second bidirectional transmission module, and the modeling method for the PHY chip supporting 1000BASE-T includes:

[0009] In the process of modeling the PHY chip, the transmission channel used for full-duplex communication in the PHY chip is logically separated to form a first signal channel and a second signal channel that are independent of each other and have opposite transmission directions; wherein the first signal channel is used to send the first sending signal of the first bidirectional transmission module to the second bidirectional transmission module, and the second signal channel is used to send the second sending signal of the second bidirectional transmission module to the first bidirectional transmission module;

[0010] quantizing the first transmission signal in the first signal channel and the second transmission signal in the second signal channel to obtain corresponding first discrete floating-point signals and second discrete floating-point signals;

[0011] The first discrete floating point signal transmitted to the second bidirectional transmission module and the second discrete floating point signal transmitted to the first bidirectional transmission module are respectively subjected to multi-stage filtering processing to obtain a first continuous signal and a second continuous signal.

[0012] A second aspect of the present invention provides a modeling device for a PHY chip supporting 1000BASE-T, comprising:

[0013] a logic separation processing module, configured to perform logic separation processing on the transmission channel used for full-duplex communication in the PHY chip during the modeling process of the PHY chip, so as to form a first signal channel and a second signal channel which are independent of each other and have opposite transmission directions; wherein the first signal channel is used to send the first transmission signal of the first bidirectional transmission module to the second bidirectional transmission module, and the second signal channel is used to send the second transmission signal of the second bidirectional transmission module to the first bidirectional transmission module;

[0014] a quantization processing module, configured to perform quantization processing on the first transmission signal in the first signal channel and the second transmission signal in the second signal channel respectively, to obtain corresponding first discrete floating point signals and second discrete floating point signals;

[0015] The multi-stage filtering processing module is used to perform multi-stage filtering on the first discrete floating point signal transmitted to the second bidirectional transmission module and the second discrete floating point signal transmitted to the first bidirectional transmission module to obtain a first continuous signal and a second continuous signal.

[0016] According to a third aspect of the present invention, an electronic device is provided, comprising a memory, a processor and a bus; the bus is used to realize connection and communication between the memory and the processor; the processor is used to execute a computer program stored in the memory; when the processor executes the computer program, the steps in the modeling method of a PHY chip supporting 1000BASE-T according to the first aspect are realized.

[0017] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the modeling method of a PHY chip supporting 1000BASE-T according to the first aspect are implemented.

[0018] The modeling method, device, equipment and medium of the PHY chip supporting 1000BASE-T of the present invention, in the modeling process of the PHY chip, firstly, by logically separating the transmission channel, effectively avoid the interference of the signal in full-duplex communication and ensure the independence of the signal path, and secondly, by introducing quantization processing and multi-stage filtering processing, it is possible to accurately simulate and optimize the signal sending and receiving process, that is, optimize the accuracy of signal modeling, avoid eliminating interference phenomena such as noise, echo and crosstalk. In the 1000BASE-T high-speed transmission and complex interference scenarios, this technical solution is based on the ability to ensure the integrity and reliability of signal transmission, thereby providing an accurate modeling effect in the design stage of the PHY chip, so as to more accurately predict the performance of the chip in a real environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a schematic diagram of the internal structure of data transmission from the MDI interface to the MAC of a Gigabit Ethernet PHY chip in the related art;

[0021] Figure 2 A schematic diagram of the number of bits carried by each signal level when Gigabit Ethernet 1000BASE-T adopts 4D-PAM5 encoding technology in the related art;

[0022] Figure 3 A schematic diagram of a signal transmission route for bidirectional transmission on a single twisted pair in the related art;

[0023] Figure 4 A flow chart of a modeling method for a PHY chip supporting 1000BASE-T provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of a signal transmission route for implementing bidirectional transmission between a first bidirectional transmission module and a second bidirectional transmission module in a PHY chip in an embodiment of the present application;

[0025] Figure 6 This is a schematic diagram of a modeling waveform of a discrete floating-point signal output by a digital-to-analog converter in the Gigabit Ethernet 1000BASE-T mode in an embodiment of the present application:

[0026] Figure 7 It is a schematic diagram of adding a first echo component to the first bidirectional transmission module in an embodiment of the present application;

[0027] Figure 8 Schematic diagram of the comparison of differential signals before and after multi-stage filtering in the embodiment of the present application;

[0028] Fig. 9 A schematic diagram of module connections of a modeling device provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of the internal structural connections of an electronic device provided in an embodiment of the present application.

[0030] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0031] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0032] It should be noted that related terms such as "first", "second", etc. can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present invention, a first component can be referred to as a second component, and the second component can also be referred to as a first component similarly. The term "and / or" refers to any one or more combinations of related items and description items.

[0033] The following is an explanation of Gigabit Ethernet, 1000BASE-T mode, twisted pair, data transceiver system and modeling in related technologies:

[0034] Gigabit Ethernet is one of the key technologies for modern network communications and is widely used in scenarios that require high-speed transmission. Among them, the MDI of the Gigabit Ethernet PHY chip supports multiple rate modes, including 10BASE-T, 100BASE-TX and 1000BASE-T modes. For the 10BASE-T / 100BASE-TX mode, only two pairs of twisted pair cables are used for data transmission, and the sending path and receiving path are separated, that is, the sending and receiving processes are independent of each other; while for the high-speed 1000BASE-T mode, all 4 pairs of wires (full-duplex) are used for data transmission, and the sending path and receiving path overlap, that is, each pair of wires sends signals while receiving signals. Specifically, the internal structure diagram of data transmission from the MDI interface of the Gigabit Ethernet PHY chip to the MAC is shown in the figure. Figure 1 shown.

[0035] Gigabit Ethernet 1000BASE-T uses 4D-PAM5 encoding technology (4D represents 4 transmitters sending on 4 channels DA~DD at the same time, and PAM5 represents 5 levels), and supports a maximum transmission distance of 100 meters. The transmission medium is Category 5 twisted pair, which supports full-duplex transmission of 4 pairs of differential lines. The signal bit rate in each pair of lines is reduced to 1 / 4, that is, the transmission rate of each pair of differential lines is 250Mbps, thereby reducing the cable's signal attenuation. 1000BASE-T uses all 4 pairs of wires in Category 5 twisted pair cables and realizes bidirectional transmission of signals in each pair of wires. It requires crosstalk / echo cancellation technology and Category 5e and higher wiring systems. Specifically, each signal level in 4D-PAM5 encoding represents 2 bits, such as Figure 2 shown.

[0036] The design of bidirectional transmission on a single twisted pair requires the use of a hybrid circuit to separate the transmit path from the receive path, such as Figure 3 As shown in the figure, the mixing circuit is the core part of realizing this bidirectional transmission. It couples the transmit signal and the receive signal in the same pair of cables for transmission without interfering with each other. It needs to eliminate the echo generated by the near-end and far-end mixing circuits, and must also filter out the near-end and far-end crosstalk from the complex signal.

[0037] The modeling of the Gigabit Ethernet 1000BASE-T data transceiver system mainly includes the digital-to-analog conversion circuit, the analog front-end circuit and the analog-to-digital conversion circuit. The common DAC modeling 4D-PAM5 encoding corresponding to the 5 level output formats can be expressed by the combination of TD_P and TD_N as shown in Table 1:

[0038] Table 1

[0039]

[0040] In Table 1, the output format Z is high impedance, 1 and 0 are logic high and low levels.

[0041] When modeling, the ADC input signal is judged to be consistent with the DAC output signal format. The transmission path and reception path of Gigabit Ethernet 1000BASE-T are separated, and the TD_P and TD_N signals of the transmission path are connected to the RD_P and RD_N signals of the reception path respectively. Common ADC modeling methods include modeling based on the specific circuit structure of the ADC, including pipeline ADC, successive approximation ADC and other different types of ADC circuits.

[0042] Based on the above-mentioned related technologies, it can be seen that with the continuous development of semiconductor technology, new DAC and ADC technologies continue to emerge, which put forward higher requirements for signal integrity and transmission quality. The above DAC / ADC modeling methods are difficult to achieve signal effectiveness and reliability transmission. That is, the related DAC / ADC modeling methods are difficult to meet the requirements of Gigabit Ethernet 1000BASE-T high-speed transmission, and there are technical problems such as rough modeling effects due to insufficient support for signal integrity and reliability.

[0043] To solve the above technical problems, please refer to Figure 4 and Figure 5 This embodiment provides a modeling method for a PHY chip supporting 1000BASE-T. The modeling method for a PHY chip supporting 1000BASE-T includes the following steps:

[0044] Step S401 , in the process of modeling the PHY chip, the transmission channel used for full-duplex communication in the PHY chip is logically separated to form a first signal channel 10 and a second signal channel 20 which are independent of each other and have opposite signal transmission directions.

[0045] Specifically, when it is necessary to model the PHY chip, conventional modeling software such as MATLAB is used to open the corresponding software to enter the modeling process of the PHY chip. Since the embodiment of the present application is mainly aimed at modeling the PHY chip in the 1000BASE-T mode, a specific PHY chip modeling environment is set based on the requirements of the 1000BASE-T standard.

[0046] In the established modeling environment under the 1000BASE-T mode, the transmission channel for full-duplex communication in the PHY chip is logically separated to form two independent signal channels with opposite signal transmission directions, namely the first signal channel 10 and the second signal channel 20. This logical separation process is a software-level separation process and does not involve actual physical-level separation processing. Its design is intended to improve the clarity and independence of signal transmission and reduce interference problems such as noise, echo and crosstalk.

[0047] It should be noted that the PHY chip includes a first bidirectional transmission module 100 and a second bidirectional transmission module 200, and the transmission channel for full-duplex communication refers to a transmission channel for bidirectional transmission between the first bidirectional transmission module 100 and the second bidirectional transmission module 200, and the two bidirectional transmission modules are based on the transmission channel to have the ability to send and receive signals at the same time. Through the logical separation operation, the transmission channel is divided into a first signal channel 10 and a second signal channel 20. It should be further explained that the "PHY chip" in the embodiment of the present application refers to a simulated PHY chip that is fictitious in the modeling software according to the actual configuration of the real PHY chip and can be used for simulation testing in the modeling software.

[0048] The first signal channel 10 is used to transmit the first transmission signal of the first bidirectional transmission module 100 to the second bidirectional transmission module 200, that is, the signal is transmitted in only one direction (from the first bidirectional transmission module 100 to the second bidirectional transmission module 200), ensuring that the transmission signal of the first bidirectional transmission module 100 will not be confused with other signals. And the second signal channel 20 is used to transmit the second transmission signal of the second bidirectional transmission module 200 to the first bidirectional transmission module 100. The signal transmission direction of this signal channel (from the second bidirectional transmission module 200 to the first bidirectional transmission module 100) is opposite to the signal transmission direction of the first signal channel 10. The signal is also transmitted in a single direction, ensuring the independence and integrity of the signal.

[0049] Through the above logic separation operation, the twisted pair connection between the first bidirectional transmission module 100 and the second bidirectional transmission module 200 of the PHY chip is functionally decomposed and logically becomes two independent signal paths. The advantages of this design are: eliminating the interference risk of bidirectional signals in the physical channel, ensuring that the signal in each direction can be processed independently, facilitating the subsequent signal quantization and filtering optimization, simplifying the logical relationship of the modeling process, and making the modeling evaluation results closer to the signal transmission characteristics in the real environment.

[0050] In addition, the logic separation design lays the foundation for subsequent signal quantization processing and multi-stage filtering processing. The independent signal path avoids signal interference, so that quantization and filtering operations can be performed on the signals in the first signal channel and the second signal channel respectively, thereby further improving the accuracy of signal modeling.

[0051] Step S402 , quantizing the first transmission signal in the first signal channel and the second transmission signal in the second signal channel to obtain corresponding first discrete floating point signals and second discrete floating point signals.

[0052] Specifically, the first transmission signal in the first signal channel and the second transmission signal in the second signal channel come from the first bidirectional transmission module and the second bidirectional transmission module respectively, and both transmission signals are continuous analog signals.

[0053] In order to convert the discrete signal form that is convenient for digital processing, quantization processing can be performed. The quantization processing can be: first, the first transmission signal and the second transmission signal are uniformly sampled in time, and the continuous time signal is converted into a discrete time signal, that is, the first discrete time signal and the second discrete time signal are obtained. Among them, the sampling frequency must meet the preset sampling theorem to ensure that the signal does not lose important frequency components after sampling, and the sampling value retains the time series information of the signal amplitude, laying the foundation for subsequent quantization. Secondly, the signal amplitude of the first discrete time signal and the second discrete time signal after sampling is quantized, and the continuous amplitude of the signal is mapped to a limited preset floating point number set, and the discretized amplitude data is stored as a standard floating point format (such as single precision 32 bits or double precision 64 bits) to form a first discrete floating point signal and a second discrete floating point signal.

[0054] It should be noted that the quantization processing in the above step S402 is the software-level processing of the PHY chip by the modeling software, rather than the actual processing of the real PHY chip. Because in the modeling process, the main purpose of the quantization processing is to simulate the signal transmission and processing characteristics of the real PHY chip in the simulation environment, so as to predict the performance of the PHY chip and optimize the design in the design stage.

[0055] Step S403: Perform multi-stage filtering on the first discrete floating point signal transmitted to the second bidirectional transmission module and the second discrete floating point signal transmitted to the first bidirectional transmission module to obtain a first continuous signal and a second continuous signal.

[0056] Specifically, multi-stage filtering processing can be performed by cascading multiple filters (such as low-pass filters, high-pass filters, band-pass filters, etc.) to gradually suppress noise, filter interference, and optimize characteristics of the signal. For example, the first layer of filters may mainly eliminate noise, the second layer of filters may process echo signals, and the third layer of filters may be used to suppress signal crosstalk. The above multi-stage filtering processing can filter out discrete noise introduced in the quantization process and random noise generated in the channel, eliminate echo interference caused by signal reflection in the twisted pair channel, process crosstalk caused by adjacent channel signals, ensure the independence of signal transmission direction, restore signal continuity, and convert from discrete floating point signals to continuous analog signals to simulate the real PHY chip signal processing behavior.

[0057] Therefore, the first discrete floating-point signal and the second discrete floating-point signal are respectively restored to the first continuous signal and the second continuous signal after multi-stage filtering, which are used as inputs for subsequent signal analysis to improve the waveform quality of the signal and ensure signal integrity, thereby accurately simulating the performance of the PHY chip in an actual communication environment. This provides a more accurate signal representation for modeling. This process not only simulates the hardware behavior of signal optimization in the PHY chip, but also ensures the accuracy of modeling, laying the foundation for subsequent design optimization and performance verification.

[0058] Through the embodiments of the present application, in the modeling process of the PHY chip, firstly, by logically separating the transmission channel, the interference of the signal in full-duplex communication is effectively avoided, and the independence of the signal path is ensured. Secondly, by introducing quantization processing and multi-stage filtering processing, the signal sending and receiving process can be accurately simulated and optimized, that is, the accuracy of signal modeling is optimized, and interference phenomena such as noise, echo and crosstalk are avoided. In the 1000BASE-T high-speed transmission and complex interference scenarios, this technical solution is based on the ability to ensure the integrity and reliability of signal transmission, thereby providing accurate modeling effects in the design stage of the PHY chip, so as to more accurately predict the performance of the chip in a real environment.

[0059] In an optional implementation manner of the present embodiment, the first bidirectional transmission module and the second bidirectional transmission module are both configured with a digital-to-analog converter DAC, an analog front-end processor AFE and an analog-to-digital converter ADC. After obtaining the first continuous signal and the second continuous signal, it also includes: when the analog front-end processor of the second bidirectional transmission module receives the first continuous signal, the preset first echo component signal is coupled with the first continuous signal, and the obtained first actual transmission signal is transmitted to the analog-to-digital converter of the second bidirectional transmission module; when the analog front-end processor of the first bidirectional transmission module receives the second continuous signal, the preset second echo component signal is coupled with the second continuous signal, and the obtained second actual transmission signal is transmitted to the analog-to-digital converter of the first bidirectional transmission module.

[0060] Specifically, the echo component coupling process of the continuous signal is performed through the analog front-end processor, and then transmitted to the analog-to-digital converter to further simulate the signal interference characteristics in the real communication scenario, that is, the echo cancellation process. This design can achieve high-precision modeling of the echo cancellation of the analog circuit part, improve the accuracy of the modeling, and also provide strong support for the verification of the anti-interference ability of the PHY chip.

[0061] In an optional implementation of this embodiment, the transmission channel includes a twisted pair, and the first bidirectional transmission module 100 and the second bidirectional transmission module 200 are both equipped with a digital-to-analog converter DAC, an analog front-end processor AFE, and an analog-to-digital converter ADC. The transmission channel used for full-duplex communication in the PHY chip is logically separated to form a mutually independent transmission signal channel and a receiving signal channel, specifically including: logically separating the bidirectional communication channel in the twisted pair in the PHY chip to form a mutually independent first signal channel and a second signal channel in the twisted pair.

[0062] In the actual circuit inside the PHY chip, each pair of twisted pairs is connected to a digital-to-analog converter and an analog-to-digital converter, which means that it can both send and receive. When modeling, the 4 pairs of twisted pairs (transmission channels) can be expanded to 8 pairs of twisted pairs (first signal channels and second signal channels), of which 4 pairs are used for sending (first signal channels) and the other 4 pairs are used for receiving (second signal channels), which are used to realize the function of simultaneous sending and receiving in the two bidirectional transmission modules inside the PHY chip in the 1000BASE-T mode. That is, the first signal channel is used to send the first transmission signal sent by the digital-to-analog converter in the first bidirectional transmission module 100 to the analog front-end processor of the second bidirectional transmission module 200, and the second signal channel is used to send the second transmission signal sent by the second bidirectional transmission module 200 to the analog front-end processor of the first bidirectional transmission module 100. After logical separation, the original single physical channel of bidirectional communication is expanded into independent transmission signal channels and reception signal channels, thereby avoiding cross interference of signals on the same physical channel.

[0063] In an optional implementation of this embodiment, the first transmission signal includes a continuous first analog signal obtained after PAM17 modulation processing, and the second transmission signal includes a continuous second analog signal obtained after PAM17 modulation processing. The first transmission signal in the first signal channel and the second transmission signal in the second signal channel are quantized to obtain corresponding first discrete floating-point signals and second discrete floating-point signals, specifically including: quantizing the instantaneous level of the first analog signal in the first signal channel at a preset sampling stage to obtain a first discrete floating-point number corresponding to the preset sampling stage; quantizing the instantaneous level of the second analog signal in the second signal channel at a preset sampling stage to obtain a second discrete floating-point number corresponding to the preset sampling stage.

[0064] Specifically, the first transmission signal and the second transmission signal are modulated by PAM17 (17-level amplitude modulation) to form a continuous first analog signal and a second analog signal, and then quantized to generate a corresponding first discrete floating-point signal and a second discrete floating-point signal. The first discrete floating-point signal and the second discrete floating-point signal are high-precision floating-point numbers that more realistically fit the actual level of the twisted pair (the floating-point modeling waveform of the DAC output in the Gigabit Ethernet 1000BASE-T mode is as follows: Figure 6 This process quantifies the instantaneous level value at the preset sampling stage, providing high-precision discrete signal input for subsequent signal modeling and performance verification.

[0065] In an optional implementation manner of the present embodiment, multi-stage filtering is performed on the first discrete floating-point signal transmitted to the second bidirectional transmission module and the second discrete floating-point signal transmitted to the first bidirectional transmission module to obtain a first continuous signal and a second continuous signal, specifically including: based on a preset digital filter model, multi-stage sampling of the target frequency is performed on the first discrete floating-point signal and the second discrete floating-point signal to obtain corresponding first discrete sampling signals and second discrete sampling signals, and multi-stage filtering is performed on the first discrete sampling signal and the second discrete sampling signal to obtain first continuous signals and second continuous signals.

[0066] For details, please refer to Figure 7 , through the preset digital filter model (2.4G digital filter), on this side of the first bidirectional transmission module 100, the first discrete floating point signal MDI_R_P / N is subjected to multi-stage sampling and multi-stage filtering at the target frequency, and finally generates a high-quality first continuous signal mdi_rx_in. This method effectively optimizes the signal quality, restores the continuous characteristics of the analog signal, and ensures the accuracy and reliability of the modeling, providing solid technical support for the design verification of the PHY chip.

[0067] Among them, the modeling code of digital filter multi-stage sampling includes the following:

[0068] assignfilter_out_P=1*(in_PO*cof0+in_P1*cof1+in_P2*cof2+in_P3*cof3+in_P4*cof4+in_P5*cof5+in_P6*cof6+in_P7*cof7+in_P8*cof8+in_P9*cof9+in_P10*cof 10+in_P11*cof11+in_P12*cof12+in_P13*cof13+in_P14*cof14+in_P15*cof15+in_ P16*cof16+in_P17*cof17+in_P18*cof18+in_P19*cof19+in_P20*cof20+in_P21*co f21+in_P22*cof22+in_P23*cof23+in_P24*cof24+in_P25*cof25+in_P26*cof26+in _P27*cof27+in_P28*cof28+in_P29*cof29+in_P30*cof30+in_P31*cof31+in_P32*co f32+in_P33*cof33+in_P34*cof34+in_P35*cof35+in_P36*cof36+in_P37*cof37

[0069] +in_P38*cof38+in_P39*cof39+in_P40*cof40).

[0070] See also Figure 8 , which shows the comparison of the differential signal output before and after filtering. In 1000BASE-T mode, the floating-point discrete signal output by the DAC reaches the AFE and is converted into a continuous signal through the digital filter. By comparing the waveforms of the differential signal before and after filtering, the optimization effect of the filtering process on signal quality is intuitively reflected.

[0071] In an optional implementation manner of this embodiment, before coupling the preset first echo component signal with the first continuous signal, it also includes: filtering the first transmission signal in the first bidirectional transmission module, and sending the obtained first echo component signal to the analog-to-digital converter in the first bidirectional transmission module through the first internal channel; before coupling the preset second echo component signal with the second continuous signal, it also includes: filtering the second transmission signal in the second bidirectional transmission module, and sending the obtained second echo component signal to the analog-to-digital converter in the second bidirectional transmission module through the second internal channel. The second internal channel is the channel between the analog-to-digital converter in the second bidirectional transmission module and the digital-to-analog converter in the second bidirectional transmission module. The first internal channel is the channel between the analog-to-digital converter in the first bidirectional transmission module and the digital-to-analog converter in the first bidirectional transmission module.

[0072] Please return and continue reading Figure 7 , the first bidirectional transmission module 100 is used as an example to illustrate: the first echo component signal dac_echo_in is obtained by filtering the first transmission signal MDI_T_P / N with a 2.4G digital filter. Specifically, the first echo component signal dac_echo_in is coupled with the received second continuous signal MDI_R_P / N, and the obtained second actual transmission signal AFE_out is transmitted to the analog-to-digital converter of the first bidirectional transmission module 100.

[0073] Among them, the relationship between the second actual transmission signal AFE_out and the first echo component signal dac_echo_in and the second continuous signal MDI_R_P / N is as follows: AFE_out = K (0.5*hybrid_sig_in–0.25*dac_echo_in) + offset, K represents the proportional coefficient of the digital filter, hybrid_sig_in represents the hybrid signal (the signal received through the hybrid circuit of the analog front-end processor AFE), offset represents the offset signal, and AFE_out is calculated by digitally filtering, weighting and offset adjusting hybrid_sig_in and dac_echo_in. That is, this solution adopts the joint technology of echo suppression, digital filtering and signal optimization in the PHY chip, and generates high-quality signal output (AFE_out) by processing the received signal and the echo signal, ensuring reliable communication in the 1000BASE-T high-speed network environment, reducing the bit error rate, and improving the stability and economy of the system.

[0074] In an optional implementation of this embodiment, after the obtained second actual transmission signal is transmitted to the analog-to-digital converter of the first bidirectional transmission module, it also includes: comparing the first actual transmission signal and the second actual transmission signal with the preset expected reference signal respectively to obtain a first comparison result and a second comparison result, outputting a modeling evaluation result according to the first comparison result and the second comparison result, and when the modeling evaluation result does not meet the preset accuracy requirement, it prompts to adjust the first echo component signal and the second echo component signal, and returns to execute the coupling of the preset first echo component signal with the first continuous signal. Specifically, by introducing a comparison link in the modeling process, by comparing the actual transmission signal with the preset reference signal, the modeling accuracy is detected in real time, and the echo component signal is adjusted when the accuracy requirement is not met, so as to continuously optimize the modeling result and realize the dynamic optimization of signal modeling.

[0075] Fig. 9 A modeling device for a PHY chip supporting 1000BASE-T provided by an embodiment of the present invention is shown, comprising:

[0076] The logic separation processing module 901 is used to perform logic separation processing on the transmission channel used for full-duplex communication in the PHY chip during the modeling process of the PHY chip, so as to form a first signal channel and a second signal channel which are independent of each other and have opposite transmission directions; wherein the first signal channel is used to send the first transmission signal of the first bidirectional transmission module to the second bidirectional transmission module, and the second signal channel is used to send the second transmission signal of the second bidirectional transmission module to the first bidirectional transmission module;

[0077] A quantization processing module 902 is used to perform quantization processing on the first transmission signal in the first signal channel and the second transmission signal in the second signal channel respectively to obtain corresponding first discrete floating point signals and second discrete floating point signals;

[0078] The multi-stage filtering processing module 903 is used to perform multi-stage filtering on the first discrete floating point signal transmitted to the second bidirectional transmission module and the second discrete floating point signal transmitted to the first bidirectional transmission module to obtain a first continuous signal and a second continuous signal.

[0079] Through the modeling device for a PHY chip supporting 1000BASE-T of the embodiment of the present application, in the modeling process of the PHY chip, firstly, by logically separating the transmission channel, the interference of the signal in full-duplex communication is effectively avoided to ensure the independence of the signal path. Secondly, by introducing quantization processing and multi-stage filtering processing, the signal sending and receiving process can be accurately simulated and optimized, that is, the accuracy of signal modeling is optimized to avoid eliminating interference phenomena such as noise, echo and crosstalk. In the 1000BASE-T high-speed transmission and complex interference scenarios, this technical solution is based on the ability to ensure the integrity and reliability of signal transmission, thereby providing accurate modeling effects in the design stage of the PHY chip, so as to more accurately predict the performance of the chip in a real environment.

[0080] Fig.10 An electronic device provided by an embodiment of the present invention is shown, and the electronic device can be used to implement the modeling method of a PHY chip for supporting 1000BASE-T in any of the aforementioned embodiments. The electronic device includes:

[0081] Memory 1001, processor 1002, bus 1003, and a computer program stored in memory 1001 and executable on processor 1002, memory 1001 and processor 1002 are connected via bus 1003. When processor 1002 executes the computer program, the modeling method for a PHY chip supporting 1000BASE-T in the aforementioned embodiment is implemented. The number of processors may be one or more.

[0082] The memory 1001 may be a high-speed random access memory (RAM) memory, or a non-volatile memory, such as a disk memory. The memory 1001 is used to store executable program codes, and the processor 1002 is coupled to the memory 1001 .

[0083] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which may be disposed in the electronic device in each of the above embodiments, and the computer-readable storage medium may be a memory.

[0084] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the human body bioelectrical impedance measurement method in the aforementioned embodiment is implemented. Further, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0085] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0086] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0087] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0088] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a readable storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0089] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0090] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A modeling method for a PHY chip supporting 1000BASE-T, characterized in that: The PHY chip includes a first bidirectional transmission module and a second bidirectional transmission module, and the modeling method of the PHY chip for supporting 1000BASE-T includes: In the process of modeling the PHY chip, the transmission channel used for full-duplex communication in the PHY chip is logically separated to form a first signal channel and a second signal channel that are independent of each other and have opposite signal transmission directions; wherein the first signal channel is used to send the first sending signal of the first bidirectional transmission module to the second bidirectional transmission module, and the second signal channel is used to send the second sending signal of the second bidirectional transmission module to the first bidirectional transmission module; quantizing the first transmission signal in the first signal channel and the second transmission signal in the second signal channel to obtain corresponding first discrete floating-point signals and second discrete floating-point signals; The first discrete floating point signal transmitted to the second bidirectional transmission module and the second discrete floating point signal transmitted to the first bidirectional transmission module are respectively subjected to multi-stage filtering processing to obtain a first continuous signal and a second continuous signal.

2. The modeling method for a PHY chip supporting 1000BASE-T as claimed in claim 1, characterized in that: The first bidirectional transmission module and the second bidirectional transmission module are both configured with a digital-to-analog converter, an analog front-end processor and an analog-to-digital converter, and after obtaining the first continuous signal and the second continuous signal, further include: When the analog front-end processor of the second bidirectional transmission module receives the first continuous signal, a preset first echo component signal is coupled with the first continuous signal, and the obtained first actual transmission signal is transmitted to the analog-to-digital converter of the second bidirectional transmission module; When the analog front-end processor of the first bidirectional transmission module receives the second continuous signal, the preset second echo component signal is coupled with the second continuous signal, and the obtained second actual transmission signal is transmitted to the analog-to-digital converter of the first bidirectional transmission module.

3. The modeling method for a PHY chip supporting 1000BASE-T as claimed in claim 1, characterized in that: The transmission channel includes a twisted pair, and the first bidirectional transmission module and the second bidirectional transmission module are both equipped with a digital-to-analog converter, an analog front-end processor and an analog-to-digital converter; The logical separation process of the transmission channel for full-duplex communication in the PHY chip to form a mutually independent transmission signal channel and reception signal channel specifically includes: The bidirectional communication channel in the twisted pair cable in the PHY chip is logically separated to form a first signal channel and a second signal channel that are independent of each other in the twisted pair cable; wherein the first signal channel is used to send the first transmission signal sent by the digital-to-analog converter in the first bidirectional transmission module to the analog front-end processor of the second bidirectional transmission module, and the second signal channel is used to send the second transmission signal sent by the second bidirectional transmission module to the analog front-end processor of the first bidirectional transmission module.

4. The modeling method for a PHY chip supporting 1000BASE-T as claimed in claim 3, characterized in that: The first transmission signal includes a continuous first analog signal obtained after PAM17 modulation processing, and the second transmission signal includes a continuous second analog signal obtained after PAM17 modulation processing; The quantizing process is performed on the first transmission signal in the first signal channel and the second transmission signal in the second signal channel to obtain corresponding first discrete floating point signals and second discrete floating point signals, specifically including: Performing quantization processing based on the instantaneous level of the first analog signal in the first signal channel at a preset sampling stage to obtain a first discrete floating-point number corresponding to the preset sampling stage; A quantization process is performed based on the instantaneous level of the second analog signal in the second signal channel at a preset sampling stage to obtain a second discrete floating-point number corresponding to the preset sampling stage.

5. The modeling method for a PHY chip supporting 1000BASE-T as claimed in claim 4, characterized in that: The step of performing multi-stage filtering on the first discrete floating-point signal transmitted to the second bidirectional transmission module and the second discrete floating-point signal transmitted to the first bidirectional transmission module to obtain a first continuous signal and a second continuous signal specifically includes: Based on a preset digital filter model, the first discrete floating-point signal and the second discrete floating-point signal are respectively subjected to multi-stage sampling processing of a target frequency to obtain corresponding first discrete sampling signals and second discrete sampling signals; The first discrete sampling signal and the second discrete sampling signal are subjected to multi-stage filtering processing to obtain a first continuous signal and a second continuous signal.

6. The modeling method for a PHY chip supporting 1000BASE-T as claimed in claim 2, characterized in that: Before coupling the preset first echo component signal with the first continuous signal, the method further includes: Filtering the first transmission signal in the first bidirectional transmission module, and sending the obtained first echo component signal to the analog-to-digital converter in the first bidirectional transmission module through a first internal channel; wherein the first internal channel is a channel between the analog-to-digital converter in the first bidirectional transmission module and the digital-to-analog converter in the first bidirectional transmission module; Before coupling the preset second echo component signal with the second continuous signal, the method further includes: The second transmission signal in the second bidirectional transmission module is filtered, and the obtained second echo component signal is sent to the analog-to-digital converter in the second bidirectional transmission module through a second internal channel; wherein the second internal channel is a channel between the analog-to-digital converter in the second bidirectional transmission module and the digital-to-analog converter in the second bidirectional transmission module.

7. The modeling method for a PHY chip supporting 1000BASE-T as claimed in claim 2, characterized in that: After transmitting the obtained second actual transmission signal to the analog-to-digital converter of the first bidirectional transmission module, the method further includes: Comparing the first actual transmission signal and the second actual transmission signal with a preset expected reference signal respectively to obtain a first comparison result and a second comparison result; Outputting a modeling evaluation result according to the first comparison result and the second comparison result; When the modeling evaluation result is that the preset accuracy requirement is not met, a prompt is given to adjust the first echo component signal and the second echo component signal, and the step of coupling the preset first echo component signal with the first continuous signal is returned to be executed.

8. A modeling device for a PHY chip supporting 1000BASE-T, characterized in that: include: a logic separation processing module, configured to perform logic separation processing on the transmission channel used for full-duplex communication in the PHY chip during the modeling process of the PHY chip, so as to form a first signal channel and a second signal channel which are independent of each other and have opposite transmission directions; wherein the first signal channel is used to send the first transmission signal of the first bidirectional transmission module to the second bidirectional transmission module, and the second signal channel is used to send the second transmission signal of the second bidirectional transmission module to the first bidirectional transmission module; a quantization processing module, configured to perform quantization processing on the first transmission signal in the first signal channel and the second transmission signal in the second signal channel respectively, to obtain corresponding first discrete floating point signals and second discrete floating point signals; The multi-stage filtering processing module is used to perform multi-stage filtering on the first discrete floating point signal transmitted to the second bidirectional transmission module and the second discrete floating point signal transmitted to the first bidirectional transmission module to obtain a first continuous signal and a second continuous signal.

9. An electronic device, characterized in that: Includes memory, processor and bus; The bus is used to realize the connection and communication between the memory and the processor; The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the method for modeling a PHY chip supporting 1000BASE-T as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the modeling method for a PHY chip supporting 1000BASE-T as described in any one of claims 1 to 7 are implemented.

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