Chip information verification method and device, equipment, medium and program product

Abstract

The invention provides a chip information verification method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of chips, in particular to the technical field of chip design and the technical field of form verification. According to the specific implementation scheme, information matching is carried out on design information of a chip and constraint information of a signal, to-be-verified information used for executing a verification task is obtained, and the to-be-verified information comprises attribute information of a signal path used for transmitting the signal and time sequence constraint information of the signal; based on the task type information of the verification task, performing simplification processing on the to-be-verified information to obtain simplified information; and under the condition that the time sequence constraint information in the simplified information is a constraint condition, performing form verification on the signal path based on the attribute information of the signal path in the simplified information to obtain a verification result.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, in particular to the field of chip design technology and the field of formal verification technology, and specifically to a chip information verification method, device, electronic device, storage medium and program product. Background Art

[0002] The chip manufacturing process includes multiple links, such as functional design, architecture design, circuit design, physical design and manufacturing. In the entire manufacturing process, each link is closely linked, and the previous link is the basis for the success of the next link. Among the multiple links, the verification of the design information of the functional design has become a key influencing factor. Summary of the invention

[0003] The present disclosure provides a chip information verification method, device, electronic device, storage medium and program product.

[0004] According to one aspect of the present disclosure, a chip information verification method is provided, comprising: performing information matching on chip design information and signal constraint information to obtain information to be verified for performing a verification task, wherein the information to be verified includes attribute information of a signal path used to transmit the signal and timing constraint information of the signal; based on task type information of the verification task, simplifying the information to be verified to obtain simplified information; and in a case where the timing constraint information in the simplified information is a constraint condition, formally verifying the signal path based on the attribute information of the signal path in the simplified information to obtain a verification result.

[0005] According to another aspect of the present disclosure, a chip information verification device is provided, including: a matching module, used to match the design information of the chip and the constraint information of the signal to obtain information to be verified for performing a verification task, wherein the above-mentioned information to be verified includes attribute information of the signal path used to transmit the above-mentioned signal and timing constraint information of the above-mentioned signal; a simplification module, used to simplify the above-mentioned information to be verified based on the task type information of the above-mentioned verification task to obtain simplified information; and a verification module, used to perform formal verification on the above-mentioned signal path based on the attribute information of the above-mentioned signal path in the above-mentioned simplified information when the timing constraint information in the above-mentioned simplified information is a constraint condition to obtain a verification result.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described above.

[0007] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method as described above.

[0008] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and the computer program implements the method described above when executed by a processor.

[0009] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0011] Figure 1 A schematic diagram of a multi-cycle path according to an embodiment of the present disclosure is schematically shown;

[0012] Figure 2 An exemplary application scenario diagram in which the chip information verification method and device according to an embodiment of the present disclosure can be applied is schematically shown;

[0013] Figure 3 A flowchart of a chip information verification method according to an embodiment of the present disclosure is schematically shown;

[0014] Figure 4 A schematic diagram of a process of executing formal verification tasks in parallel according to an embodiment of the present disclosure is shown;

[0015] Figure 5A A schematic diagram schematically shows simplified configuration information according to an embodiment of the present disclosure;

[0016] Figure 5B A schematic diagram schematically shows simplified module information according to an embodiment of the present disclosure;

[0017] Figure 5C A schematic diagram schematically shows timing constraint information of a simplified signal according to an embodiment of the present disclosure;

[0018] Fig. 6A The flowchart of the chip information verification method according to the embodiment of the present disclosure is schematically shown;

[0019] Figure 6B A schematic diagram of a chip information verification method according to another embodiment of the present disclosure is shown;

[0020] Figure 7A schematic diagram of a process for generating information to be verified according to another embodiment of the present disclosure is shown;

[0021] Figure 8 A block diagram schematically shows a chip information verification device according to an embodiment of the present disclosure; and

[0022] Fig. 9 A block diagram of an electronic device suitable for implementing a chip information verification method according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0023] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0024] In modern semiconductor design, the increasing complexity and scale of chip architectures have significantly exacerbated the integration challenges of integrated circuits. In chip design, there are multiple design stages. Each design stage needs to be verified to ensure that multiple links with previous and subsequent correlations meet the design specifications and design requirements.

[0025] The chip includes a signal path for transmitting signals, and the signal path may include functional modules and wires. The interface of the functional module can be used as a source node or a target node. The signal transmitted in each signal path may have specific transmission conditions or delay periods. In complex high-frequency chip designs, there are some signal paths whose propagation delay is greater than the clock period, such as multi-cycle paths.

[0026] Figure 1 A schematic diagram of a multi-cycle path according to an embodiment of the present disclosure is schematically shown.

[0027] like Figure 1 As shown, the multi-cycle path 100 may include a signal path between interface A of functional module A and interface B of functional module B. Interface A is used as a source node and interface B is used as a destination node. A signal 101 output by interface A propagates to interface B within N clock cycles.

[0028] Each multi-cycle path can be verified to check whether the signal starting from the source node and arriving at the target node meets the setting of the predetermined clock cycle.

[0029] The completion of a chip generally goes through multiple stages, including design, manufacturing, testing, and packaging. Design includes chip front-end design and chip back-end design. Verification of multi-cycle paths is generally performed in the chip back-end design stage, and simulation verification is often used.

[0030] However, simulation verification of multi-cycle paths in the chip backend design stage generally requires a lot of simulation time and cluster resources. In addition, simulation verification at this stage is usually performed using some experimental cases, which makes it difficult to cover all multi-cycle paths and may cause missed detection. In addition, once a problem is found, it is costly to repair the design information, which will directly affect the time for subsequent chip manufacturing.

[0031] In view of this, the embodiments of the present disclosure provide a chip information verification method, device, electronic device, storage medium and program product. The specific implementation scheme is: information matching is performed on the chip design information and the signal constraint information to obtain information to be verified for performing the verification task, wherein the information to be verified includes the attribute information of the signal path used to transmit the signal and the timing constraint information of the signal. Based on the task type information of the verification task, the information to be verified is simplified to obtain simplified information. In the case where the timing constraint information in the simplified information is a constraint condition, the signal path is formally verified based on the attribute information of the signal path in the simplified information to obtain a verification result.

[0032] Compared with the traditional verification of multi-cycle paths in the chip back-end design stage, the formal verification method provided by the embodiment of the present disclosure can fully cover the verification of multi-cycle paths and avoid ignoring potential errors. In addition, the design information in the chip front-end design stage is verified, which realizes the left shift of formal verification in the chip design process, improves the efficiency of design information correction, and avoids the problem of high repair cost.

[0033] Figure 2 An exemplary application scenario diagram to which the chip information verification method and device according to an embodiment of the present disclosure can be applied is schematically shown.

[0034] It should be noted that Figure 1 What is shown is merely an example of a system architecture to which the embodiments of the present disclosure can be applied, in order to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0035] like Figure 2 As shown, the electronic device 201 may be a device having computing functions and formal verification functions, such as a personal computer, a workstation, a server, etc. The scope of the present disclosure is not limited in this respect.

[0036] The electronic device 201 obtains the design information 202 for describing the chip and the signal constraint information 203 as input. The design information 202 may be the final result of the chip front-end design, and its quality plays a key role in the chip back-end design and even the completion of the final chip. The signal constraint information 203 may include timing constraint information such as the delay period of the signal, but is not limited thereto, and may also include identification information of the interface used to transmit the signal.

[0037] In some embodiments, the design information 202 and the constraint information 203 may be input into the electronic device 201 by a user, may be pre-stored in the electronic device 201, or may be communicatively coupled to other devices to be acquired from the other devices. The scope of the present disclosure is not limited in this respect.

[0038] The electronic device 201 can match the chip design information 202 and the signal constraint information 203 to obtain information to be verified for performing the verification task, wherein the information to be verified includes attribute information of the signal path used to transmit the signal and the timing constraint information of the signal; based on the task type information of the verification task, simplify the information to be verified to obtain simplified information; and when the timing constraint information in the simplified information is a constraint condition, formally verify the signal path based on the attribute information of the signal path in the simplified information to obtain a verification result 204.

[0039] It should be noted that the chip information verification method provided in the embodiment of the present disclosure can generally be executed by the electronic device 201. Correspondingly, the chip information verification device provided in the embodiment of the present disclosure can also be set in the electronic device 201.

[0040] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision, disclosure and application of user personal information involved comply with the provisions of relevant laws and regulations, take necessary confidentiality measures, and do not violate public order and good morals.

[0041] In the technical solution of the present disclosure, the user's authorization or consent is obtained before obtaining or collecting the user's personal information.

[0042] It should be noted that the sequence numbers of the operations in the following method are only used as representations of the operations for the purpose of description, and should not be regarded as representing the execution order of the operations. Unless explicitly stated, the method does not need to be executed completely in the order shown.

[0043] Figure 3 The flowchart of the chip information verification method according to the embodiment of the present disclosure is schematically shown.

[0044] like Figure 3 As shown, the method includes operations S310 to S330.

[0045] In operation S310, information matching is performed on chip design information and signal constraint information to obtain information to be verified for performing a verification task.

[0046] In operation S320, based on the task type information of the verification task, the information to be verified is simplified to obtain simplified information.

[0047] In operation S330, when the timing constraint information in the simplified information is a constraint condition, formal verification is performed on the signal path based on the attribute information of the signal path in the simplified information to obtain a verification result.

[0048] The design information may include the RTL (Register Transfer Level) code of the chip. The design information may be written in a hardware description language used for digital electronic system design. It may also be written in a very high speed integrated circuit hardware description language (VHDL). It may also be written in a hardware description language (Verilog). It should be understood that the design information may also be any other suitable file or document for describing the chip.

[0049] Optionally, the design information may include attribute information of the signal path to be verified, but is not limited to this. The design information may also include other auxiliary information, such as code syntax description information or other annotation information, and may also include other functional information of functional modules other than signal transmission.

[0050] Optionally, the signal path may include a source node, a target node, an intermediate node provided between the source node and the target node, and a wire. Any of the source node, the target node, and the intermediate node may be an interface of a functional module of the chip. The attribute information of the signal path may include module information of the functional module and interface information of the interface of the functional module, as long as it is information used to describe the signal path.

[0051] The signal constraint information may include timing constraint information, but is not limited thereto, and may also include chip rule constraint information and interface information of an interface for transmitting the signal.

[0052] Information matching is performed on the chip design information and the signal constraint information. For example, the identification information of the interface in the design information can be matched with the identification information of the interface in the constraint information. The target constraint information corresponding to the interface is determined from the design information, such as timing constraint information and rule constraint information, etc. The target constraint information is combined with the design information related to the interface to obtain the information to be verified.

[0053] The information to be verified may include property information of a signal path used to transmit a signal and timing constraint information of the signal.

[0054] Simplifying the information to be verified may be to delete redundant information or noise information in the information to be verified to obtain only information related to formal verification as simplified information. However, it is not limited to this, and may also include simplifying and updating part of the information to be verified to make the formal verification simple and effective, and avoid complicating the formal verification process due to the complexity of part of the information.

[0055] Formal Verification (FV) can be called static verification. It uses tools to logically check whether the chip design information meets certain properties. Specifically, it can mathematically prove or verify whether the chip implements the functions described by the design information and obtain verification results.

[0056] There are many types of formal verification, such as multi-cycle path (MCP) verification, false path (FP), etc. Each type of formal verification can be regarded as a verification task, for example, the task type can include a multi-cycle path verification task type or a false path verification task type.

[0057] According to the task type information of the verification task, it can be determined whether to perform multi-cycle path verification or false path verification. Different task types may have different simplified processing methods. The simplified processing method matching the task type information can be used to simplify the information to be verified to obtain simplified information.

[0058] Based on the attribute information of the signal path in the simplified information, the signal path can be formally verified to determine whether the delay of the signal transmitted in the signal path satisfies the constraint condition of the timing constraint information to obtain a verification result. If the verification result indicates that the signal path is normal, the verification is passed. If all signal paths pass the verification, the back-end design and manufacturing of the chip can be performed based on the design information. If the verification result indicates that the signal path is abnormal, the verification fails, and the design information corresponding to the abnormal signal path is corrected so that the design information meets the requirements.

[0059] By using the chip information verification method provided by the embodiment of the present disclosure, the design information of the chip front-end design stage can be verified, which realizes the left shift of formal verification in the chip design process and avoids the problem of high repair time and cost. In addition, by simplifying the information to be verified, the content of redundant information and complex information is reduced, and the efficiency and success rate of formal verification are improved. In addition, the signal path can be fully verified by using the formal verification method to avoid ignoring potential errors.

[0060] In actual application, it is found that in the face of large-scale chip design or a large number of multi-cycle paths, formal verification may become very time-consuming or even impossible to execute successfully.

[0061] Optionally, a parallel formal verification approach may be used to improve the efficiency and success rate of formal verification.

[0062] Figure 4 The flowchart of executing formal verification tasks in parallel according to an embodiment of the present disclosure is schematically shown.

[0063] like Figure 4 As shown, the actual hardware chip function can be described by code such as RTL code to obtain a design information set 410. The chip design information set can be divided based on a predetermined rule to obtain multiple design information, such as design information 1, ..., design information N.

[0064] The predetermined rule may refer to an information division rule. For example, the signal path may be used as an information division rule to divide the design information belonging to the same signal path together. However, it is not limited thereto. The number of signal delay cycles may also be used as an information division rule to divide the design information set of the chip to obtain multiple design information such as the design information of the signal path with a signal delay cycle number of 1, ..., the design information of the signal path with a signal delay cycle number of N, etc.

[0065] Information partitioning rules can also include chip area partitioning rules. For example, the multi-cycle paths inside the IP (Intellectual Property) functional module can be separated from the multi-cycle path information involved in other functional modules in the chip to obtain multiple design information. This can reduce the scale of the signal path that needs to be verified, and avoid the problem of verification failure due to excessive time or excessive memory usage caused by a single verification scale being too large.

[0066] like Figure 4As shown, for multiple design information, constraint information of corresponding signals, such as constraint information 1, ..., constraint information N, can be matched in parallel from constraint information set 420 to obtain multiple information to be verified, such as information to be verified 1, ..., information to be verified N. Parallel simplification processing is performed on each information to be verified to obtain multiple simplified information, such as simplified information 1, ..., simplified information N. Based on the multiple simplified information, formal verification is performed on multiple signal paths in parallel to obtain multiple verification results, such as verification result 1, ..., verification result N.

[0067] Multiple verification results can be combined, for example, verification result 1+…+verification result N, to obtain a verification result corresponding to the design information set. However, this is not limited to this. Multiple verification results can also be fused, for example, verification result 1 is combined with the relevant content in verification result N, and then multiple verification results are combined to obtain a verification result corresponding to the design information set.

[0068] By using the parallel formal verification method provided by the embodiment of the present disclosure, the cluster resources of formal verification can be reasonably utilized to improve the verification efficiency. In addition, taking the formal verification of multi-cycle paths as an example, the design information in the design information set is divided according to the number of delay cycles, so that the boundaries of the design information obtained after the division are clear, and the coupling between the information is avoided, thereby improving the effectiveness and success rate of parallel verification.

[0069] Optionally, the information to be verified can be simplified to solve the problem that formal verification becomes time-consuming or even cannot be successfully performed due to large-scale chip design or a large number of multi-cycle path designs.

[0070] For example, for Figure 3 The operation S320 shown is to simplify the information to be verified to obtain simplified information, which may include simplifying at least one of the following: module information of a functional module, timing constraint information of a signal, and configuration information for formal verification.

[0071] The chip may include a functional module for forming a signal path. The information to be verified may include module information of the functional module, may also include timing constraint information of the signal, and may also include configuration information for performing a formal verification task.

[0072] For example, the module information of a functional module may include relevant information for describing the functional module, such as function, specification, power consumption, identification, etc. The timing constraint information of a signal may include information such as enable delay, offset delay, clock, reset, etc. The configuration information may include operating environment information and expected timing behavior information such as expected effect information or assertions.

[0073] At least one of them can be simplified, and preferably, at least two of them can be simplified, so as to reduce the verification amount of subsequent formal verification by simplifying different types of information at the same time, thereby improving the efficiency and success rate of formal verification.

[0074] The simplification of module information, timing constraint information and configuration information will be explained below respectively.

[0075] According to an optional embodiment of the present disclosure, taking configuration information as an example, simplifying the configuration information may include: based on the application scenario information of the chip, identifying multiple configuration information to obtain an identification result. If the identification result indicates that the target configuration information meets the predetermined simplification condition, deleting the target configuration information.

[0076] Formal verification is a method that uses mathematical models and logical reasoning to prove whether the design information meets the established specifications. Specifically, specific algorithms and model tools can be used to determine whether the timing behavior reflected by the signal path meets the expected timing behavior conditions such as constraints.

[0077] In the case of formal verification, all configuration information, such as operating environment information, can be used to conduct experiments to verify whether the chip corresponding to the design information can be applied to all application scenarios, or to verify whether the chip corresponding to the design information can achieve all functions.

[0078] However, when the chip is actually used, it does not need to be applicable to all application scenarios. On this basis, the operating environment information or assertions in multiple configuration information can be identified based on the application scenario information of the chip to obtain an identification result. If the identification result indicates that the configuration information does not match the application scenario information, it is determined that the configuration information meets the simplification condition and the configuration information can be deleted.

[0079] Figure 5A The figure schematically shows simplified configuration information according to an embodiment of the present disclosure.

[0080] like Figure 5A As shown, the configuration information set for formal verification includes configuration information 1, ..., configuration information N. Based on the application scenario information, configuration information 1 is determined as the target configuration information from the configuration information set, and configuration information 1 is deleted. Configuration information 2, ..., configuration information N are used as part of the simplified information for formal verification.

[0081] The mapping relationship between application scenario information and configuration information can be set in advance. When there is target configuration information in multiple configuration information that does not match the application scenario information of the chip, it is determined that the target configuration information does not need to be applied to subsequent formal verification, and the target configuration information can be deleted to simplify the information to be verified and improve the efficiency of subsequent formal verification.

[0082] According to another optional embodiment of the present disclosure, taking the simplification of module information as an example, the simplification process of the module information may include: determining a target functional module from the signal path based on the module information of the functional module in the signal path, and updating the module information of the target functional module using the predetermined simplified module information to obtain simplified information.

[0083] Optionally, the target functional module may be a module that can be subjected to black box processing, such as a functional module that has been verified, a functional module provided by a third party, etc.

[0084] It should be noted that the module information of the functional module may include identification information of the functional module, functional information of the functional module, and other information such as power consumption and performance of the functional module. For example, the functional module may be composed of multiple functional units, in which case the attribute information of the functional module may also include the attribute information of each of the multiple functional units.

[0085] Figure 5B The figure schematically shows a simplified schematic diagram of module information according to an embodiment of the present disclosure.

[0086] like Figure 5B As shown, information recognition can be performed on design information such as module information of a functional module. When identification information used to characterize a target functional module is identified, the functional module B corresponding to the identification information is used as the target functional module.

[0087] The target functional module may be black-boxed. For example, the module information of the target functional module is updated using the predetermined simplified module information to obtain the module information of the functional module B represented by an ellipse. Specifically, the predetermined simplified module information may only include the identification information of the functional module and the attribute information of the interface, and the internal logic in the target functional module, such as the attribute information of each of the multiple functional units, is omitted.

[0088] By utilizing the simplification of module information provided by the embodiments of the present disclosure, it is possible to simplify the path scale of the signal path to be verified, reduce the verification complexity and difficulty of subsequent formal verification, and thus improve the efficiency and success rate of formal verification.

[0089] According to another optional embodiment of the present disclosure, taking the simplification of timing constraint information as an example, simplifying the timing constraint information of a signal may include: determining a target signal from a plurality of signals based on the setting intention of the signal, and updating an enable clock value in the timing constraint information of the target signal using a predetermined enable clock value.

[0090] When designing a multi-cycle path, the main difference from the single-cycle path design is that the functional module, such as the destination trigger, usually has specific multi-cycle control logic on one side to ensure that the destination trigger only captures data at the specified clock edge to avoid the generation of metastable states in the chip circuit.

[0091] In the case where the clock information transmitted in the signal path is affected by the clock enable, the setting intention of the signal can be determined based on the application scenario information of the chip. Based on the setting intention of the signal, the signal type of the signal is determined. A target signal belonging to a predetermined signal type is determined from multiple signals. For example, an enable signal. The enable clock value of the enable signal can be updated based on the setting intention, for example, the predetermined enable clock value is to represent Enable (valid), for example, set to 1, or Disable (invalid), for example, set to 0. The enable clock value in the timing constraint information of the target signal is updated using the predetermined enable clock value.

[0092] Figure 5C The diagram schematically shows a simplified diagram of timing constraint information of a signal according to an embodiment of the present disclosure.

[0093] like Figure 5C As shown, in the multi-cycle path where interface A of functional module A transmits a signal to interface B1 of functional module B, an enable interface B2 is also provided on functional module B, and an enable clock value of an enable signal input to enable interface B2 can be set to a predetermined enable clock value, such as 1, so that the signal output from source node interface A in the signal path can be propagated to target node interface B1 at any time.

[0094] By simplifying the timing constraint information, the influence of other enabling signals in the signal path can be reduced, thereby improving the verification efficiency and the success rate of the verification analysis.

[0095] The simplified processing of the information to be verified is described in detail above, but the simplified processing is not limited to being applied to the processing of the information to be verified, but can also be applied to the processing of simplified information.

[0096] Fig. 6A The flowchart of the chip information verification method according to the embodiment of the present disclosure is schematically shown.

[0097] like Fig. 6AAs shown, the information to be verified 610 can be simplified to obtain simplified information 620. Based on the simplified information 620, the signal path is formally verified for multi-cycle timing constraints to obtain a verification result 630. It is determined whether the verification result 630 indicates that the signal path is normal. In the case where it is determined that the signal path is normal, the formal verification is terminated. In the case where it is determined that the verification result indicates that there is an abnormality in the signal sub-path, based on the abnormal state information included in the verification result, the simplified sub-information representing the attribute information of the signal sub-path is simplified to obtain updated simplified sub-information, so as to perform formal verification on the updated simplified sub-information.

[0098] Optionally, at least one item of the simplified sub-information may be simplified: module information of a functional module, timing constraint information of a signal, and configuration information for formal verification.

[0099] It should be noted that the method of simplifying the simplified sub-information can be similar to the method of simplifying the verification information. However, it is not limited to this. It is also possible to perform targeted information updates based on the abnormal signal sub-paths characterized by the verification results, without the need to identify the target functional module or the target configuration information.

[0100] For example, based on the abnormal state information included in the verification result, such as abnormal signal wave or abnormal configuration information, the simplified sub-information to be updated is determined, and the simplified sub-information is updated. The updating method may include simplifying the simplified sub-information using predetermined simplified module information or using a predetermined enable clock value. In addition, it may also include deleting the target configuration information in the simplified sub-information.

[0101] According to the embodiments of the present disclosure, the above method can be used to further determine whether the signal path abnormality is caused by non-critical factors or caused by incorrect design information, thereby improving the effectiveness and accuracy of correcting the design information.

[0102] According to an embodiment of the present disclosure, after simplifying the simplified sub-information, formal verification is performed again. If the obtained verification result indicates that the signal sub-path still has an abnormality, the design information can be corrected. However, it is not limited to this. A combination of formal verification and simulation verification can also be used. At the RTL stage, multi-cycle timing verification is performed on the set multi-cycle path, and the cause of the abnormality is further determined by combining simulation verification, thereby improving the effectiveness and accuracy of the corrected design information.

[0103] Figure 6B The flowchart of a chip information verification method according to another embodiment of the present disclosure is schematically shown.

[0104] Figure 6B The flowchart shown is similar to Fig. 6A The difference of the flowchart shown is that, when the verification result indicates that an abnormality exists in the signal subpath, the signal path is simulated and verified based on the simplified information 620 and the reference information included in the verification result 630 to obtain the simulation result 640 .

[0105] However, it is not limited to this. After simplifying the simplified sub-information, formal verification can be performed again. If the obtained verification result indicates that the signal sub-path is still abnormal, the signal path can be simulated and verified based on the simplified information and the reference information included in the verification result to obtain a simulation result. Any method that combines formal verification with simulation verification will suffice.

[0106] The reference information may be directly generated by using a formal verification script after performing formal verification. Based on the simplified information and the reference information, the operation of a real signal path may be simulated in a simulation environment to obtain a simulation result.

[0107] When the simulation result indicates that the signal path is normal, it is determined that the design information corresponding to the simplified information is normal. When the simulation result indicates that the signal path is abnormal, the simplified information can be simplified again based on the simulation result. The simplified processing method can refer to the following example. FIG. 5A to FIG. 5C The updated simplified information is then dynamically simulated and verified again. However, the design information can also be modified based on the simulation results.

[0108] The dual verification method of combining formal verification and simulation verification can improve the verification accuracy of design information and avoid erroneous correction of design information due to verification errors.

[0109] According to an embodiment of the present disclosure, the reference information may include corrected timing constraint information and assertions.

[0110] The following will explain how to use the corrected timing constraint information and assertions for dynamic simulation.

[0111] According to an embodiment of the present disclosure, performing simulation verification based on simplified information and reference information included in the verification result to obtain a simulation result may include: when the corrected timing constraint information included in the reference information is incompatible with a tool used for simulation, performing simulation verification using assertions and simplified information in the reference information to obtain a simulation result. When the corrected timing constraint information is compatible with a tool used for simulation, the corrected timing constraint information and simplified information may be used to perform simulation verification on the signal path to obtain a simulation result.

[0112] Optionally, the corrected timing constraint information and simplified information may be preferentially used to perform simulation verification on the signal path to obtain simulation results. In the case where the corrected timing constraint information included in the reference information is incompatible with the tool used for simulation, the assertions and simplified information in the reference information may be used to perform simulation verification to obtain simulation results.

[0113] The corrected timing constraint information is highly targeted. For example, in a verification process based on formal verification, when the corrected timing constraint information has been reflected in the verification results, the corrected timing constraint information can be directly used to perform simulation verification on the simplified information in a targeted manner, thereby improving the accuracy and effectiveness of the simulation verification while improving the efficiency of the simulation verification.

[0114] It should be noted that the corrected timing constraint information can be used to update the timing constraint information corresponding to the corrected timing constraint information in the simplified information to obtain the updated simplified information. The updated simplified information is used for simulation verification. However, it is not limited to this. Based on the verification result, the corrected timing constraint information can also be directly obtained, and the timing constraint information corresponding to the corrected timing constraint information in the simplified information can be updated to obtain the updated simplified information. In order to use the updated simplified information to re-perform formal verification to determine whether the signal path is normal.

[0115] However, when the verification script of formal verification is incompatible with the verification script of simulation verification, the output corrected timing constraint information is incompatible with the simulation tool, which results in the tool being unable to recognize the corresponding corrected timing constraint information. In this case, assertions can be used for simulation verification.

[0116] For the signal paths with anomalies identified in formal verification, the verification results include a corresponding assertion, which can be combined with the simplified information for simulation verification.

[0117] An assertion can represent that when a signal output by a source node of a functional module changes, for example, from 1 to 0, then in a predetermined clock cycle, a target node of another functional module will detect the changed signal.

[0118] During simulation verification, if any assertion in the simulation regression fails, it means that the specified timing behavior does not hold in the actual situation. You can directly add this assertion in the simulation test environment and check whether this assertion holds through dynamic simulation.

[0119] By utilizing the simulation verification method provided by the embodiment of the present disclosure, assertions and corrected timing constraint information can be combined to help improve the accuracy and effectiveness of simulation results of simulation verification.

[0120] Optionally, for a signal path where early sampling occurs, if the verification result obtained after formal verification indicates that the signal path is abnormal, a detection signal can be inserted into the source node of the signal path before simulation verification to detect whether the detection signal is sampled at a predetermined clock cycle of the target node. If detected, it proves that the signal path is normal, otherwise it indicates that the signal path is abnormal.

[0121] By flexibly adding detection signals, the detection accuracy and efficiency can be improved and false detection problems can be avoided.

[0122] The above describes how to combine formal verification and simulation verification to verify chip information. The following describes how to obtain the information to be verified for formal verification.

[0123] According to the embodiments of the present disclosure, Figure 3 The operation S310 shown, matching the chip design information and the signal constraint information to obtain the information to be verified for performing the verification task, may include: using the constraint information to match and verify the design information to obtain a matching verification result. When the matching verification result indicates that the design information is normal, extracting key information from the design information. The key information includes the attribute information of the signal path. Mapping is established between the constraint information and the key information to generate the information to be verified.

[0124] The constraint information may include identification information of the signal, interface information of the interface used to transmit the signal, timing constraint information of the signal, and the like.

[0125] The design information may include module information of the functional modules, interface information of the interfaces of the functional modules, and the like.

[0126] The interface information of the interface in the constraint information can be used to perform matching verification with the interface information in the design information. If they match, it is determined that the matching verification result indicates that the design information is normal. If they do not match, it is determined that the matching verification result indicates that the design information is abnormal.

[0127] When the matching verification result indicates that the design information is abnormal, the design information or constraint information may be corrected.

[0128] When the matching verification result indicates that the design information is normal, key information in the design information is extracted, including attribute information of the signal path, such as module information of the functional module of the signal path, interface information of the interface, and the like.

[0129] Establishing a mapping between the constraint information and the key information to generate the information to be verified may include combining information other than the key information in the constraint information, such as timing constraint information and rule constraint information, with the key information to generate the information to be verified.

[0130] By utilizing the disclosed embodiments, constraint information and design information are used for matching verification, and then a mapping is established to generate information to be verified. This can not only improve the validity of the information to be verified by utilizing matching verification, but also improve the richness of the information to be verified through mapping, thereby improving the efficiency of subsequent simplification processing and the comprehensiveness of simplification, and avoiding the problem of the comprehensiveness of simplification not being guaranteed due to the simplification processing of a single design information.

[0131] According to the embodiments of the present disclosure, the information to be verified that has established a mapping relationship based on the constraint information and the key information can be directly simplified, but it is not limited to this. The information to be verified that has established a mapping relationship based on the constraint information and the key information can also be used as the initial information to be verified for rule verification.

[0132] Figure 7 The following schematically shows a flow chart of generating information to be verified according to another embodiment of the present disclosure.

[0133] like Figure 7 As shown, mapping the constraint information and the key information to generate the information to be verified may include: using the constraint information 710 to perform matching verification on the design information 720 to obtain a matching verification result. Based on the matching verification result, determine whether the design information is normal. When the matching verification result indicates that the design information is normal, extract the key information 730 in the design information. The key information 730 includes the attribute information of the signal path. Mapping the constraint information 710 and the key information 730 to generate the initial information to be verified 740. Perform rule verification on the initial information to be verified 740 to obtain a rule verification result. Based on the rule verification result, determine whether the design information is normal. When the rule verification result indicates that the design information is normal, generate the information to be verified 750 based on the initial information to be verified 740, for example, use the initial information to be verified as the information to be verified. When the rule verification result indicates that the design information is abnormal, correct the design information and re-perform the rule verification.

[0134] Optionally, the rule verification may be performed using a predetermined specification file as a standard or condition. If the conditions set in the specification file are met, the rule verification is passed; otherwise, the rule verification is not passed and the initial information to be verified needs to be modified.

[0135] By combining the multiple verification methods provided by the embodiments of the present disclosure, different influencing factors can be verified through different verification methods, thereby improving the accuracy and effectiveness of the information to be verified and reducing the waste of resources, costs and time caused by formal verification using invalid information.

[0136] Figure 8 A block diagram of a chip information verification device according to an embodiment of the present disclosure is schematically shown.

[0137] like Figure 8 As shown, the chip information verification device 800 includes: a matching module 810 , a simplification module 820 and a verification module 830 .

[0138] The matching module 810 is used to match the chip design information and the signal constraint information to obtain the information to be verified for performing the verification task, wherein the information to be verified includes the attribute information of the signal path used to transmit the signal and the timing constraint information of the signal.

[0139] The simplification module 820 is used to simplify the information to be verified based on the task type information of the verification task to obtain simplified information.

[0140] The verification module 830 is used to perform formal verification on the signal path based on the attribute information of the signal path in the simplified information when the timing constraint information in the simplified information is a constraint condition to obtain a verification result.

[0141] According to an embodiment of the present disclosure, the chip information verification device further includes: a division module.

[0142] The partitioning module is used to partition the chip design information set according to the number of signal delay cycles to obtain multiple design information.

[0143] According to an embodiment of the present disclosure, a chip includes a functional module for forming a signal path.

[0144] According to an embodiment of the present disclosure, the simplified module includes simplifying at least one of the following:

[0145] Module information of functional modules, timing constraint information of signals, and configuration information for formal verification.

[0146] According to an embodiment of the present disclosure, the chip information verification device further includes: an update module.

[0147] An update module is used to simplify at least one of the following items in the simplified sub-information representing the attribute information of the signal sub-path based on the abnormal status information included in the verification result when the verification result represents the existence of an abnormality in the signal sub-path, so as to obtain updated simplified sub-information so as to perform formal verification on the updated simplified sub-information: module information of the functional module, timing constraint information of the signal, and configuration information used for formal verification.

[0148] According to an embodiment of the present disclosure, the simplification process of the configuration information in the simplification module includes: identifying submodules and deleting submodules.

[0149] The identification submodule is used to identify multiple configuration information based on the application scenario information of the chip to obtain an identification result.

[0150] The deleting submodule is used to delete the target configuration information when the recognition result indicates that the target configuration information meets the predetermined simplification condition.

[0151] According to an embodiment of the present disclosure, the simplified processing of module information in the simplified module includes: a module screening submodule and an information updating submodule.

[0152] The module screening submodule is used to determine a target functional module from the signal path based on the module information of the functional modules in the signal path.

[0153] The updating submodule is used to update the module information of the target functional module using the predetermined simplified module information to obtain simplified information.

[0154] According to an embodiment of the present disclosure, the simplification module simplifies the timing constraint information of the signal, and includes: a signal screening submodule and a signal updating submodule.

[0155] The signal screening submodule is used to determine a target signal from multiple signals based on the setting intention of the signal.

[0156] The signal updating submodule is used to update the enabling clock value in the timing constraint information of the target signal using the predetermined enabling clock value.

[0157] According to an embodiment of the present disclosure, the matching module includes: a matching verification submodule, an extraction submodule and a mapping submodule.

[0158] The matching verification submodule is used to perform matching verification on the design information using the constraint information to obtain a matching verification result.

[0159] The extraction submodule is used to extract key information from the design information when the matching verification result indicates that the design information is normal, wherein the key information includes attribute information of the signal path.

[0160] The mapping submodule is used to establish a mapping between constraint information and key information to generate information to be verified.

[0161] According to an embodiment of the present disclosure, the mapping submodule includes: a mapping unit, a rule verification unit, and a generation unit.

[0162] The mapping unit is used to generate initial information to be verified based on the constraint information and the key information.

[0163] The rule verification unit is used to perform rule verification on the initial information to be verified to obtain a rule verification result.

[0164] The generating unit is used to generate information to be verified based on the initial information to be verified when the rule verification result indicates that the initial information to be verified is normal.

[0165] According to an embodiment of the present disclosure, the chip information verification device further includes: a simulation module.

[0166] The simulation module is used to perform simulation verification on the signal path based on the simplified information and the reference information included in the verification result to obtain the simulation result when the verification result indicates that the signal path is abnormal.

[0167] According to an embodiment of the present disclosure, based on the simplified information and the reference information included in the verification result.

[0168] The simulation module includes: a simulation sub-module.

[0169] The simulation submodule is used to simulate and verify the signal path by using the assertion and simplified information in the reference information to obtain the simulation result when the corrected timing constraint information included in the reference information is incompatible with the tool used for simulation.

[0170] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0171] According to an embodiment of the present disclosure, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method as described above.

[0172] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the method as described above.

[0173] According to an embodiment of the present disclosure, a computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the method as described above.

[0174] Fig. 9A schematic block diagram of an example electronic device 900 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0175] like Fig. 9 As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0176] A number of components in the device 900 are connected to an input / output (I / O) interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0177] The computing unit 901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the various methods and processes described above, such as a chip information verification method. For example, in some embodiments, the chip information verification method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the chip information verification method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the chip information verification method in any other appropriate manner (e.g., by means of firmware).

[0178] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0179] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0180] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0181] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0182] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0183] A computer system may include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises through computer programs running on respective computers and having a client-server relationship to each other. The server may be a cloud server, a server in a distributed system, or a server combined with a blockchain.

[0184] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0185] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A chip information verification method, comprising: Matching chip design information and signal constraint information to obtain information to be verified for performing a verification task, wherein the information to be verified includes attribute information of a signal path for transmitting the signal and timing constraint information of the signal; Based on the task type information of the verification task, simplify the information to be verified to obtain simplified information; and In the case where the timing constraint information in the simplified information is a constraint condition, formal verification is performed on the signal path based on the attribute information of the signal path in the simplified information to obtain a verification result.

2. The method according to claim 1, further comprising: The design information set of the chip is divided according to the number of signal delay cycles to obtain a plurality of the design information.

3. The method according to claim 1 or 2, wherein: The chip includes a functional module for forming the signal path; The simplifying the information to be verified to obtain simplified information includes simplifying at least one of the following: The module information of the functional module, the timing constraint information of the signal, and the configuration information used for formal verification.

4. The method according to any one of claims 1 to 3, further comprising: In the case where the verification result indicates that an abnormality exists in the signal subpath, based on the abnormal state information included in the verification result, at least one of the following items in the simplified sub-information representing the attribute information of the signal subpath is simplified to obtain updated simplified sub-information, so as to perform formal verification on the updated simplified sub-information: Module information of functional modules, timing constraint information of signals, and configuration information for formal verification.

5. The method according to claim 3 or 4, wherein: The configuration information is simplified, including: Based on the application scenario information of the chip, the plurality of configuration information are identified to obtain an identification result; and When the recognition result indicates that the target configuration information meets a predetermined simplification condition, the target configuration information is deleted.

6. The method according to claim 3 or 4, wherein: The module information is simplified, including: Determining a target functional module from the signal path based on the module information of the functional modules in the signal path; The module information of the target functional module is updated using the predetermined simplified module information to obtain the simplified information.

7. The method according to claim 3 or 4, wherein: Simplifying the timing constraint information of the signal, including: determining a target signal from a plurality of the signals based on the setting intention of the signals; and An enable clock value in the timing constraint information of the target signal is updated using a predetermined enable clock value.

8. The method according to any one of claims 1 to 7, wherein: The step of matching the chip design information with the signal constraint information to obtain information to be verified for performing the verification task includes: Using the constraint information to perform matching verification on the design information to obtain a matching verification result; In a case where the matching verification result indicates that the design information is normal, extracting key information from the design information, wherein the key information includes attribute information of the signal path; and A mapping is established between the constraint information and the key information to generate the information to be verified.

9. The method according to claim 8, wherein: The mapping of the constraint information and the key information to generate the information to be verified includes: Based on the constraint information and the key information, generating initial information to be verified; Performing rule verification on the initial information to be verified to obtain a rule verification result; and In a case where the rule verification result indicates that the initial information to be verified is normal, the information to be verified is generated based on the initial information to be verified.

10. The method according to any one of claims 1 to 9, further comprising: In a case where the verification result indicates that an abnormality exists in the signal path, a simulation verification is performed on the signal path based on the simplified information and reference information included in the verification result to obtain a simulation result.

11. The method according to claim 10, wherein: The performing simulation verification on the signal path based on the simplified information and the reference information included in the verification result to obtain the simulation result includes: In the case that the revised timing constraint information included in the reference information is incompatible with the tool used for simulation, the signal path is simulated and verified using the assertions in the reference information and the simplified information to obtain a simulation result.

12. A chip information verification device, comprising: A matching module, used to match the chip design information and the signal constraint information to obtain information to be verified for performing the verification task, wherein the information to be verified includes attribute information of a signal path for transmitting the signal and timing constraint information of the signal; a simplification module, configured to simplify the information to be verified based on the task type information of the verification task to obtain simplified information; and The verification module is used to perform formal verification on the signal path based on the attribute information of the signal path in the simplified information when the timing constraint information in the simplified information is a constraint condition to obtain a verification result.

13. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-11.

15. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 11.

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