Reconfigurable interconnect circuit for multi-core processor, implementation method and chip

Abstract

The application discloses a reconfigurable interconnection circuit for a multi-core processor, an implementation method and a chip, and belongs to the chip technical field. The circuit comprises a multi-master multi-slave routing arbitration structure and an interconnection component. The multi-core processor is connected with the multi-master multi-slave routing arbitration structure. The multi-master multi-slave routing arbitration structure is connected with the embedded FPGA through the interconnection component. The multi-master multi-slave routing arbitration structure is used for identifying and routing arbitration of data transmission between the multi-core processor and the embedded FPGA, and allocating corresponding interconnection resources for the data transmission. The interconnection resources are realized based on the interconnection component. The interconnection component is used for managing and transmitting communication between interfaces connected with the interconnection component. The interfaces are interfaces on the multi-core processor side and / or interfaces on the embedded FPGA side. The application realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA, can reduce the demand for hardware resources, and can reduce the size of a system-level chip.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a reconfigurable interconnection circuit for a multi-core processor, an implementation method and a chip. BACKGROUND

[0002] Single-core processors have performance bottlenecks when processing complex tasks, and multi-core processors have become a solution to improve computing power. Multi-core processors can achieve higher parallel processing capability and stronger computing performance by integrating multiple CPU cores. In the design of a system on chip (SoC), a multi-core processor can be tightly integrated with an embedded field programmable gate array (FPGA) to form a heterogeneous computing platform, in which the multi-core processor is responsible for executing general computing tasks, and the embedded FPGA can be used for specific hardware acceleration tasks. The two work together to improve system performance and efficiency. How to realize the communication and interconnection between the multi-core processor and the embedded FPGA is a problem to be solved. SUMMARY

[0003] The application aims to at least solve one of the technical problems in the related art. To this end, the application provides a reconfigurable interconnection circuit for a multi-core processor, an implementation method and a chip. The circuit dynamically allocates interconnection resources through routing arbitration to form a reconfigurable interconnection circuit, realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA, can reduce the demand for hardware resources, and reduce the size of the system on chip.

[0004] In a first aspect, the application provides a reconfigurable interconnection circuit for a multi-core processor, which includes:

[0005] A multi-master multi-slave routing arbitration structure and an interconnection component, the multi-core processor is connected to the multi-master multi-slave routing arbitration structure, and the multi-master multi-slave routing arbitration structure is connected to the embedded FPGA through the interconnection component,

[0006] The multi-master multi-slave routing arbitration structure is used to identify and route arbitration for data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and to allocate corresponding interconnection resources for the data transmission, the interconnection resources being realized based on the interconnection component;

[0007] The interconnection component is used to manage and transmit communication between interfaces connected by the interconnection component, the interfaces being interfaces on the side of the multi-core processor and / or interfaces on the side of the embedded FPGA;

[0008] The multi-master multi-slave routing arbitration structure or the interconnection component adopts an island type interconnection architecture, and interconnection resources under the island type interconnection architecture include global interconnection resources and local interconnection resources;

[0009] The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes.

[0010] The interconnection channels are composed of a preset number of interconnection line segments and are used to realize signal transmission between logical function blocks.

[0011] The switch boxes include a preset number of programmable switches and are used to realize jump between different interconnection line segments.

[0012] The connection boxes include input connection modules and output connection modules and are used to realize signal transmission between logical function blocks and interconnection channels.

[0013] In the above technical solution, the reconfigurable interconnection circuit for a multi-core processor includes a multi-master multi-slave routing arbitration structure and an interconnection component. The multi-master multi-slave routing arbitration structure is used to identify and arbitrate data transmission between internal or external multi-core processors and embedded FPGAs, and to allocate interconnection resources based on the interconnection component. The interconnection component manages and transmits communication between the interfaces of the multi-core processor and the embedded FPGA. Through dynamic allocation of interconnection resources by routing arbitration, a reconfigurable interconnection circuit is formed, realizing real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA. The demand for hardware resources can be reduced, and the size of the system-on-chip can be reduced. The multi-master multi-slave routing arbitration structure or the interconnection component is an island type interconnection architecture, and the interconnection resources are divided into global interconnection resources and local interconnection resources. The global interconnection resources include interconnection channels and switch boxes, which are used to transmit signals between logical function blocks and control the direction and path of signal transmission through programmable switches in the switch boxes. The local interconnection resources include connection boxes, realizing signal transmission between logical function blocks and interconnection channels. Through connection and expansion of logical function blocks, a complete interconnection circuit function is formed, meeting the interconnection needs of users. Through the island type interconnection architecture, the multi-master multi-slave routing arbitration structure and the interconnection component can be expanded to more processors or peripherals, adapting to different communication needs. Different types of interconnection channels and switch boxes help to more effectively utilize hardware resources, reduce the size of the reconfigurable interconnection circuit for a multi-core processor, and thus reduce the size of the system-on-chip.

[0014] According to one embodiment of the present application, the types of the interconnection component include slave interconnection components, master interconnection components, storage interconnection components, system application interconnection components and control interconnection components.

[0015] The slave interconnection component is used for realizing interconnection between at least one processor in the multi-core processor and the embedded FPGA, the at least one processor serving as a slave, and the embedded FPGA serving as a master.

[0016] The master interconnection component is used for realizing interconnection between at least one processor in the multi-core processor and the embedded FPGA, the at least one processor serving as a master, and the embedded FPGA serving as a slave.

[0017] The storage interconnection component is used for realizing interconnection of storage resources.

[0018] The system application interconnection component is used for realizing interconnection of system-level applications.

[0019] The control interconnection component is used for realizing transmission of control signals.

[0020] In the above technical solution, the interconnection components include the slave interconnection component, the master interconnection component, the storage interconnection component, the system application interconnection component and the control interconnection component, and different types of interconnection components cooperate with each other to realize data transmission and control signal transmission between the multi-core processor and the embedded FPGA or between the multi-core processor and other resources. The processors in the multi-core processor and the programmable logic devices instantiated in the embedded FPGA can be configured as masters or slaves, improving data transmission efficiency. Different types of interconnection components can adapt to different communication requirements, and by dynamically allocating interconnection resources, the demand for hardware resources can be effectively reduced, the size of the reconfigurable interconnection circuit can be reduced, and thus the size of the system-level chip can be reduced.

[0021] According to an embodiment of the present application, the embedded FPGA serving as a master includes at least one programmable logic device instantiated in the embedded FPGA serving as a master.

[0022] In the above technical solution, the embedded FPGA instantiates at least one programmable logic device as a master, and the FPGA serving as a master can communicate and exchange data with other parts of the system-level chip, improving the data processing capability and response speed of the embedded FPGA.

[0023] According to an embodiment of the present application, the embedded FPGA serving as a slave includes at least one programmable logic device instantiated in the embedded FPGA serving as a slave.

[0024] In the above technical solution, the embedded FPGA instantiates at least one programmable logic device as a slave, which can respond to requests from the multi-core processor or other masters, and the embedded FPGA serving as a slave can execute specific tasks or requests initiated by the master, so that the master can effectively use the embedded FPGA.

[0025] According to one embodiment of the present application, the host interconnection component is further configured to implement interconnection between processors in the multi-core processor, at least one processor as a master and at least another processor as a slave.

[0026] In the above technical solution, the host interconnection component supports communication within the multi-core processor, allowing communication between different processors without the need for external devices, improving the efficiency of communication between processors and improving the data processing capability of the multi-core processor.

[0027] According to one embodiment of the present application, the host interconnection component is further configured to implement interconnection between at least one processor in the multi-core processor and an embedded FPGA, at least another processor, at least one programmable logic device instantiated by the embedded FPGA and the at least another processor as a slave, at least one processor in the multi-core processor as a master.

[0028] In the above technical solution, the host interconnection component can be used to implement interconnection between the master and the slave within the multi-core processor, and can also be used to instantiate at least one programmable logic device of the embedded FPGA as a slave, i.e. the host interconnection component can manage communication within the multi-core processor and communication between the multi-core processor and external devices (such as the embedded FPGA), so that the multi-core processor can more effectively use the embedded FPGA and achieve closer cooperation between processors within the multi-core processor.

[0029] According to one embodiment of the present application, the type of interface includes at least one of an AMBA general interface, an AMBA high-performance interface, an AMBA_ACP interface and a CTRL_IO_SIG interface.

[0030] In the above technical solution, the various interface types used in the reconfigurable interconnection circuit for the multi-core processor include at least one of an AMBA general interface, an AMBA high-performance interface, an AMBA_ACP interface and a CTRL_IO_SIG interface, the AMBA general interface supports communication between the multi-core processor and the embedded FPGA in the role of master or slave, the AMBA high-performance interface improves the data transmission rate through FIFO buffering, the ACP interface implements cache coherence and can be used to optimize memory access of the accelerator, and the CTRL_IO_SIG interface is used to transmit control signals. By configuring different interfaces, the interface can be dynamically selected according to the communication requirements, improving the efficiency of data transmission, and the design of multiple interface types and interconnection components makes the reconfigurable interconnection circuit for the multi-core processor adaptable to different communication requirements, effectively reducing the demand for hardware resources and reducing the size of the reconfigurable interconnection circuit for the multi-core processor, thereby reducing the size of the system-on-chip.

[0031] According to one embodiment of the present application, all interfaces on the side of the multi-core processor except the accelerated coherent interface are connected to the multi-master multi-slave routing arbitration structure, and the embedded FPGA is connected through the interconnection component.

[0032] In the above technical solution, all interfaces on the side of the multi-core processor except the accelerated coherent interface are connected to the multi-master multi-slave routing arbitration structure, and the embedded FPGA is connected through the interconnection component, the interconnection resources are dynamically allocated through routing arbitration, a reconfigurable interconnection circuit is formed, the interconnection between the multi-core processor and the embedded FPGA is realized, the demand for hardware resources can be reduced, and the size of the system-on-chip can be reduced, the accelerated coherent interface is not connected to the multi-master multi-slave routing arbitration structure, extra competition and waiting time that may occur are avoided, and the data transmission efficiency between the multi-core processor and the embedded FPGA can be improved.

[0033] According to one embodiment of the present application, the accelerated coherent interface on the side of the multi-core processor is directly connected to a system application interconnection component in the interconnection component, and the system application interconnection component is a coherent control unit in the accelerated processor.

[0034] In the above technical solution, the accelerated coherent interface on the side of the multi-core processor is directly connected to a system application interconnection component in the interconnection component, and the system application interconnection component is a coherent control unit in the accelerated processor, the data transmission path can be simplified, and the data transmission efficiency between the multi-core processor and the embedded FPGA can be improved.

[0035] According to one embodiment of the present application, the interfaces on the side of the embedded FPGA include at least one of a master AMBA general interface, a slave AMBA general interface, a master AMBA high-performance interface, a slave AMBA_ACP interface, and a CTRL_IO_SIG interface.

[0036] The slave interconnection component is connected to the master AMBA general interface, the master interconnection component is connected to the slave AMBA general interface, the storage interconnection component is connected to the master AMBA high-performance interface, the system application interconnection component is connected to the slave AMBA_ACP interface, and the control interconnection component is connected to the CTRL_IO_SIG interface.

[0037] In the technical solution, the slave interconnection component is connected with the host AMBA general interface, the host interconnection component is connected with the slave AMBA general interface, the storage interconnection component is connected with the host AMBA high-performance interface, the system application interconnection component is connected with the slave AMBA_ACP interface, and the control interconnection component is connected with the CTRL_IO_SIG interface. The interface configuration of the embedded FPGA side and the connection mode of the interface with different interconnection components are illustrated, the communication and data transmission between the multi-core processor and the embedded FPGA are realized, and the data transmission requirement in different application scenarios can be met.

[0038] According to an embodiment of the present application, the corresponding interconnection resources are allocated for the data transmission, including: determining the connection relationship of the interconnection line segments in the interconnection component and the jump relationship between the interconnection line segments according to the number of interfaces, the type of interfaces and the circuit application requirement of the multi-master multi-slave routing arbitration structure, and generating a reconfigurable configuration file, which is used to realize the configuration of the conduction or shutdown of the programmable switch in the switch box and the input connection module and the output connection module in the connection box.

[0039] In the technical solution, the connection relationship of the interconnection line segments in the interconnection component and the jump relationship between the interconnection line segments are determined according to the number of interfaces, the type of interfaces and the circuit application requirement of the multi-master multi-slave routing arbitration structure, and a reconfigurable configuration file is generated. The corresponding interconnection resources are allocated for the data transmission according to the reconfigurable configuration file, so that the reconfigurable interconnection circuit for the multi-core processor can adapt to different data transmission requirements, and the flexibility of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0040] According to an embodiment of the present application, the local interconnection resources further include: an input cross interconnection module, which is used to realize the signal interconnection between the logic units and connect the input pins of the logic function block to each logic unit.

[0041] The plurality of logic units constitute the logic function block.

[0042] In the technical solution, the local interconnection resources further include an input cross interconnection module, which can be used to realize the signal interconnection between the logic units and connect the input pins of the logic function block to each logic unit, and can be used to realize the interconnection between the multi-core processor and the embedded FPGA.

[0043] According to an embodiment of the present application, the horizontal channel and the vertical channel of the embedded FPGA side programmable interconnection provide the global interconnection resources, and the global interconnection resources interact with signals through the local interconnection resources and the multi-core processor side interconnection bus.

[0044] The signal output of the multi-core processor side is sent to the interconnection component through the local interconnection resource and is processed by the corresponding logic unit, or the signal output of the multi-core processor side is sent to the adjacent logic unit through the horizontal channel for processing.

[0045] In the technical solution, the horizontal channel and the vertical channel of the embedded FPGA side programmable interconnection provide global interconnection resources, the global interconnection resources interact with signals through the local interconnection resources and the multi-core processor side interconnection bus, the signal output of the multi-core processor side is sent to the interconnection component through the local interconnection resource and is processed by the corresponding logic unit, or is sent to the adjacent logic unit through the horizontal channel for processing, and the interconnection between the multi-core processor and the embedded FPGA is realized through the global interconnection resources and the local interconnection resources, thereby improving the flexibility of the reconfigurable interconnection circuit for the multi-core processor.

[0046] According to an embodiment of the present application, the types of the interconnection line segments include a long interconnection line segment, a short interconnection line segment, a local interconnection line segment and a direct connection line segment, the long interconnection line segment is used to meet the signal path requirement between the logic function blocks far apart, the short interconnection line segment is used to realize the interconnection between the adjacent logic function blocks, and the local interconnection line segment is used to realize the signal sharing and feedback between the logic units in each logic function block.

[0047] In the technical solution, the design of the interconnection line segments adopts a multi-stage combined interconnection system including the long interconnection line segment, the short interconnection line segment, the local interconnection line segment and the direct connection line segment to meet the interconnection requirements of different distances and different complexities, adapt to the layout and signal transmission of different logic function blocks in the multi-master multi-slave routing arbitration structure and the interconnection component, and improve the flexibility of the reconfigurable interconnection circuit for the multi-core processor.

[0048] According to an embodiment of the present application, the interconnection channel is a one-way channel or a two-way channel.

[0049] In the technical solution, the interconnection channel is a one-way channel or a two-way channel, different interconnection channels are selected to adapt to various signal transmission requirements, and the data transmission efficiency of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0050] According to an embodiment of the present application, the switch box is realized in a combination mode of the bidirectional interconnection switch and the unidirectional interconnection switch.

[0051] In the technical solution, the switch box is realized in a combination mode of the bidirectional interconnection switch and the unidirectional interconnection switch, different interconnection switches are selected to adapt to various signal transmission requirements, and the data transmission efficiency of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0052] According to one embodiment of the present application, the topology type of the programmable switch in the switch box comprises at least one of subset interconnection, global interconnection and vertical interconnection.

[0053] In the above technical solution, the topology type of the programmable switch in the switch box comprises at least one of subset interconnection, global interconnection and vertical interconnection, and by reasonably selecting and applying the topology type of the programmable switch in the switch box, the flexibility and scalability of the reconfigurable interconnection circuit for the multi-core processor can be improved.

[0054] According to one embodiment of the present application, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component comprise the number of routing wires that can be connected by the input or output of each logical function block, the number of other routing wires that can be connected by each routing wire, the length of the routing wire segment, the mode of the routing switch, the electrical design of the routing wire and the programmable switch, and the number of routing wire segments of each channel.

[0055] In the above technical solution, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component comprise the number of routing wires that can be connected by the input or output of each logical function block, the number of other routing wires that can be connected by each routing wire, the length of the routing wire segment, the mode of the routing switch, the electrical design of the routing wire and the programmable switch, and the number of routing wire segments of each channel, which together determine the configuration mode of the data transmission path of the reconfigurable interconnection circuit for the multi-core processor, so as to dynamically adjust the routing path according to different data transmission requirements, adapt to different application scenarios, and help to more effectively utilize hardware resources.

[0056] According to one embodiment of the present application, the programmable switch is implemented by using a multiplexer and a tri-state buffer.

[0057] In the above technical solution, the programmable switch is implemented by using a multiplexer and a tri-state buffer, which improves the flexibility and control ability of the programmable switch, can dynamically adjust according to real-time data transmission requirements and routing decisions, and further improves the flexibility of the reconfigurable interconnection circuit for the multi-core processor.

[0058] According to one embodiment of the present application, the multi-master multi-slave routing arbitration structure comprises an AMBA bus matrix, and the AMBA bus matrix is used to connect all AMBA bus interfaces of the multi-core processor.

[0059] In the technical solution, the multi-master multi-slave routing arbitration structure comprises an AMBA bus matrix for connecting all AMBA bus interfaces of the multi-core processor, and all AMBA bus interfaces of the multi-core processor are connected in a centralized manner, thereby improving the data transmission efficiency, optimizing the use of hardware resources, and improving the flexibility of the reconfigurable interconnection circuit for the multi-core processor.

[0060] In a second aspect, the application provides an implementation method of a reconfigurable interconnection circuit for a multi-core processor, which comprises:

[0061] generating a code of the reconfigurable interconnection circuit for the multi-core processor according to the interconnection requirement, the interconnection parameter of the multi-core processor side and the interconnection parameter of the embedded FPGA side;

[0062] generating an FPGA configuration file according to the code;

[0063] downloading the FPGA configuration file into the embedded FPGA to form the reconfigurable interconnection circuit for the multi-core processor.

[0064] In the technical solution, the code of the reconfigurable interconnection circuit for the multi-core processor is generated according to the interconnection requirement, the interconnection parameter of the multi-core processor side and the interconnection parameter of the embedded FPGA side, the code is converted into an FPGA configuration file, the FPGA configuration file is downloaded into the embedded FPGA, the reconfigurable interconnection circuit for the multi-core processor is implemented, the flexibility of implementing the reconfigurable interconnection circuit for the multi-core processor is improved, the reconfigurable interconnection circuit for the multi-core processor can meet different interconnection requirements, and the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor are enhanced.

[0065] According to an embodiment of the application, the interconnection parameter of the multi-core processor side comprises at least one of the following: the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master multi-slave routing arbitration structure, and the interface type of the multi-master multi-slave routing arbitration structure.

[0066] The interconnection parameter of the embedded FPGA side comprises at least one of the following: the number of embedded FPGA masters and slaves, the AMBA bus interface type, the number of interconnection component signals, the interconnection component type, and the number of each interconnection component type.

[0067] In the technical solution, at least one of the following is determined according to the interconnection requirement: the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master multi-slave routing arbitration structure, and the interface type of the multi-master multi-slave routing arbitration structure, and at least one of the following is determined: the number of embedded FPGA masters and slaves, the AMBA bus interface type, the number of interconnection component signals, the interconnection component type, and the number of each interconnection component type. The code of the reconfigurable interconnection circuit for the multi-core processor is generated, the flexibility of implementing the reconfigurable interconnection circuit for the multi-core processor is improved, the reconfigurable interconnection circuit for the multi-core processor can meet different interconnection requirements, and the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor are enhanced.

[0068] According to one embodiment of the present application, the code of the reconfigurable interconnection circuit for the multi-core processor is generated according to the interconnection requirement, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side, and the code generation includes:

[0069] According to the interconnection requirement, the data transmission between the multi-core processor and the embedded FPGA is determined.

[0070] According to the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, the code of the reconfigurable interconnection circuit for the multi-core processor is generated for the data transmission.

[0071] In the technical solution, according to the interconnection requirement, the data transmission between the multi-core processor and the embedded FPGA is determined, according to the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, the code of the reconfigurable interconnection circuit for the multi-core processor is generated for the data transmission, the corresponding reconfigurable interconnection circuit for the multi-core processor is implemented for the data transmission between the multi-core processor and the embedded FPGA, and the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor are enhanced.

[0072] In a third aspect, the present application provides a chip, which includes a multi-core processor and an embedded FPGA, and further includes the reconfigurable interconnection circuit for the multi-core processor according to the first aspect.

[0073] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0074] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0075] Figure 1 is a structural schematic diagram of a reconfigurable interconnection circuit for a multi-core processor provided by some embodiments of the present application;

[0076] Figure 2 is a schematic diagram of interconnection resources under an island interconnection architecture provided by some embodiments of the present application;

[0077] Figure 3 is a schematic diagram of a switch box provided by some embodiments of the present application;

[0078] Figure 4 is a schematic diagram of a connection box provided by some embodiments of the present application;

[0079] Figure 5 is a schematic diagram of configuration of interconnection resources provided by some embodiments of the present application;

[0080] Figure 6 is a structural schematic diagram of an interconnection channel provided by some embodiments of the present application;

[0081] Figure 7 is a schematic diagram of a programmable switch topology provided by some embodiments of the present application;

[0082] Figure 8 is a structural schematic diagram of a bidirectional interconnection switch provided by some embodiments of the present application;

[0083] Figure 9 is a structural schematic diagram of a unidirectional interconnection switch provided by some embodiments of the present application;

[0084] Figure 10 is a schematic diagram of a multi-master multi-slave routing arbitration structure or an interconnection component provided by some embodiments of the present application;

[0085] Figure 11 is a schematic diagram of a programmable switch structure provided by some embodiments of the present application;

[0086] Figure 12 is a schematic diagram of a multiplexer provided by some embodiments of the present application;

[0087] Figure 13 is a schematic diagram of an AMBA bus matrix provided by some embodiments of the present application;

[0088] Figure 14 is a flow schematic diagram of an implementation method of a reconfigurable interconnection circuit for a multi-core processor provided by some embodiments of the present application.

[0089] Legend of Reference Signs:

[0090] 10: reconfigurable interconnection circuit for a multi-core processor;

[0091] 101: multi-master multi-slave routing arbitration structure; 1011: AMBA bus matrix;

[0092] 102: interconnection component; 1021: slave interconnection component; 1022: master interconnection component;

[0093] 1023: storage interconnection component; 1024: system application interconnection component; 1025: control interconnection component. DETAILED DESCRIPTION

[0094] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0095] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and are not limited in number, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the objects before and after are in an "or" relationship.

[0096] With the increasing demand for computing, the performance bottleneck of single-core processors in processing complex tasks has prompted multi-core processors to become a key technology for improving computing power. Multi-core processors can achieve higher parallel processing capability and stronger computing performance by integrating multiple CPU cores. However, the performance of multi-core processors not only depends on the processing capability of the core, but also on the efficiency of inter-core communication, which directly affects the data transmission speed, system delay and overall system performance.

[0097] In a multi-core processor, inter-core communication usually adopts two ways: pipelining and shared memory. In the pipelining mode, data is transmitted between different cores through a private cache area. After CPU0 processes the data, it is transmitted to CPU1, and then CPU1 transmits it to CPU2, and so on. Although this method can achieve continuous processing of tasks, the data transmission across the core cache will cause a long delay. On the other hand, although the inter-core data transmission based on shared memory can be achieved, the clock cycles consumed for accessing the shared memory are much more than those for accessing the private cache, resulting in limited performance.

[0098] In a system on chip (SoC) design, a multi-core processor can be tightly integrated with an embedded field programmable gate array (FPGA) to form a heterogeneous computing platform, where the multi-core processor is responsible for performing general computing tasks, and the embedded FPGA can be used for specific hardware acceleration tasks. The two work together to improve system performance and efficiency. The embedded FPGA can also be referred to as eFPGA. How to realize communication and interconnection between the multi-core processor and the eFPGA is a problem to be solved.

[0099] The multi-core processor-oriented reconfigurable interconnection circuit, implementation method and chip provided by the embodiments of the application will be described in detail below with reference to the accompanying drawings, specific embodiments and application scenarios.

[0100] Figure 1 is a structural schematic diagram of the multi-core processor-oriented reconfigurable interconnection circuit provided by some embodiments of the application. As Figure 1 shown, the multi-core processor-oriented reconfigurable interconnection circuit 10 includes a multi-master multi-slave routing arbitration structure 101 and an interconnection component 102. The multi-core processor is connected to the multi-master multi-slave routing arbitration structure 101. The multi-master multi-slave routing arbitration structure 101 is connected to the embedded FPGA through the interconnection component 102.

[0101] The multi-master multi-slave routing arbitration structure 101 is configured to identify and route arbitrate data transmission between the multi-core processor and the embedded FPGA, and allocate corresponding interconnection resources for the data transmission. The interconnection resources are implemented based on the interconnection component 102.

[0102] The interconnection component 102 is configured to manage and transmit communication between interfaces connected by the interconnection component. The interfaces are interfaces on the multi-core processor side and / or interfaces on the embedded FPGA side.

[0103] The multi-master multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture. The interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources.

[0104] The global interconnection resources include interconnection channels and switch boxes. The local interconnection resources include connection boxes.

[0105] The interconnection channel is composed of a predetermined number of interconnection line segments and is configured to realize signal transmission between logic function blocks.

[0106] The switch box includes a predetermined number of programmable switches and is configured to realize jumping between different interconnection line segments.

[0107] The connection box comprises an input connection module and an output connection module, and is used for realizing signal transmission between a logic function block and an interconnection channel.

[0108] The complete interconnection circuit function required by the user is formed by connecting and extending the functions realized by the plurality of logic function blocks.

[0109] It can be understood that the multi-master multi-slave routing arbitration structure 101 allows a plurality of master devices (such as a plurality of processors) and a plurality of slave devices (such as embedded FPGAs or other devices) to perform data transmission, and identifies, arbitrates and makes routing decisions on the data transmission requests, so that data can be transmitted between devices through a correct path, and interconnection resources realized based on the interconnection component are allocated for data transmission.

[0110] The interconnection component 102 connects the multi-master multi-slave routing arbitration structure 101 and the embedded FPGA, and is used for managing and transmitting communication between interfaces connected by the interconnection component.

[0111] Optionally, the communication between the interfaces can be communication between interfaces on the side of the multi-core processor and interfaces on the side of the embedded FPGA, can be communication between interfaces on the side of the multi-core processor, or can be communication between interfaces on the side of the embedded FPGA.

[0112] The interconnection component 102 realizes the interconnection resources allocated by the multi-master multi-slave routing arbitration structure 101 by managing and transmitting communication between the interfaces connected by the interconnection component, that is, realizes the connection relationship between different interfaces and interconnection line segments and the jump relationship between the interconnection line segments, and can meet different computing requirements and application scenarios.

[0113] The multi-master multi-slave routing arbitration structure 101 identifies, arbitrates and makes routing decisions on data transmission, the interconnection component 102 manages and transmits communication between interfaces connected by the interconnection component based on the routing decisions of the multi-master multi-slave routing arbitration structure 101, realizes corresponding interconnection resources, and the multi-master multi-slave routing arbitration structure 101 and the interconnection component 102 combine to form a reconfigurable interconnection circuit, realizing real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA.

[0114] It should be noted that the identification and routing arbitration of the multi-master multi-slave routing arbitration structure 101 on data transmission are based on an address space, that is, when a data transmission request occurs, the multi-master multi-slave routing arbitration structure determines a data transmission address according to a target address or a source address of the transmission request, further determines a routing path, allocates corresponding interconnection resources, and thus realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA.

[0115] As Figure 1As shown, in the system chip, the multi-master multi-slave routing arbitration structure 101 and the interconnection component 102 play the role of a switch, realizing the communication between the multi-core processor and the embedded FPGA.

[0116] Optionally, the interface communicates based on the Advanced Microcontroller Bus Architecture (AMBA) protocol, which can be referred to as an AMBA interface.

[0117] The AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), and Advanced eXtensible Interface (AXI), which can be used to realize the connection between processors, memories, and peripherals with different performance and power consumption requirements.

[0118] Inside the processor system (the multi-core processor constitutes the processor system), AMBA is used inside the APU to connect the processor core, the SCU, the cache memory or the OCM, and various interconnections inside the FPGA. These connections are in addition to the connections on the CPU-eFPGA boundary.

[0119] In some embodiments, the reconfigurable interconnection circuit for the multi-core processor can include multiple interconnection components 102 with different functions. Some of the interconnection components 102 are directly connected to the embedded FPGA, used for data exchange between the Central Processing Unit (CPU) in the multi-core processor and the embedded FPGA. The central processor can be referred to as a processor. The multi-core processor includes at least one processor. Another part of the interconnection component 102 is used for connection between CPUs or inside the embedded FPGA. The connection between the interconnection components 102 can also be based on the AMBA protocol, so that data can be transmitted between the interconnection components, and the SoC can realize efficient data processing to adapt to various complex computing requirements.

[0120] Figure 2 is a schematic diagram of an interconnection resource under an island type interconnection architecture provided by some embodiments of the present application. As shown in Figure 2As shown, the island-type multi-master multi-slave routing arbitration structure includes interconnection channels, switch boxes, connection boxes, input cross-interconnection modules, and a plurality of logic function blocks (also referred to as logic function modules, or logic clusters), and further includes IP function modules. The IP function module (Intellectual Property Core) refers to a pre-designed and verified integrated circuit design module with specific functions. The logic function block can also be represented as a configurable logic block (Configurable Logic Block, CLB). A plurality of configurable logic blocks constitute programmable logic resources.

[0121] In the island-type interconnection architecture, the multi-master multi-slave routing arbitration structure or interconnection component is divided into a plurality of independent functional units, i.e., "islands". The islands are divided into global interconnection resources and local interconnection resources to support signal transmission and logic control within the SoC.

[0122] The global interconnection resources include interconnection channels and switch boxes (Switch Box, SB). The interconnection channels realize signal transmission between the logic function blocks through preset interconnection lines, and the switch boxes include a preset number of programmable switches, Figure 3 FIG. 1 is a schematic diagram of a switch box according to some embodiments of the present application. The switch box is used to realize switching between different interconnection lines, path selection and switching control between different interconnection lines, thereby managing the direction and routing of signal transmission.

[0123] The interconnection channels are composed of a preset number of regular wiring units. Signal transmission between the logic function blocks is mostly realized through these wiring units, including long interconnection lines and short interconnection lines. The short interconnection lines are used to realize interconnection between adjacent logic function blocks, and the long interconnection lines are used to meet the signal path requirements between logic function blocks that are far apart. The number, direction, length, composition ratio, and distribution of the interconnection channels affect the delay characteristics and signal quality of the circuit, and directly determine the routing rate and resource utilization rate of the embedded FPGA.

[0124] The local interconnection resources include connection boxes (Connection Box, CB), which include input connection modules and output connection modules, and are used to realize signal transmission between the logic function blocks and the interconnection channels, and are also used to realize connection between the interconnection lines and the programmable logic resources. Figure 4 FIG. 2 is a schematic diagram of a connection box according to some embodiments of the present application.

[0125] The interconnection lines in the layout of the chip are actually some horizontal or vertical metal lines, which are bidirectional. However, since all the interconnection lines are connected through the interconnection switches in the SB, the direction of the switch circuit in the interconnection resources determines the direction of the interconnection lines.

[0126] In some embodiments, the local interconnection resource further comprises: an input cross interconnection module, configured to realize signal interconnection between the logic units and connect input pins of the logic function block to the logic units;

[0127] The plurality of logic units constitute the logic function block.

[0128] The input cross interconnection module is configured to realize signal interconnection between the logic units and connect the input pins of the logic function block to the corresponding logic units, which can specifically include allocation and sharing of the input pin connection, cascading between the logic units, feedback of the output signal, and the like.

[0129] In the above technical solution, the reconfigurable interconnection circuit for the multi-core processor includes a multi-master multi-slave routing arbitration structure and an interconnection component. The multi-master multi-slave routing arbitration structure is configured to identify and arbitrate data transmission between the multi-core processor and the embedded FPGA, and to allocate interconnection resources based on the interconnection component. The interconnection component manages and transmits communication between the multi-core processor and the embedded FPGA interface. The interconnection resources are dynamically allocated by routing arbitration to form a reconfigurable interconnection circuit, which realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA. The demand for hardware resources can be reduced, and the size of the system-on-chip can be reduced. The multi-master multi-slave routing arbitration structure or the interconnection component is an island-type interconnection architecture, and the interconnection resources are divided into global interconnection resources and local interconnection resources. The global interconnection resources include interconnection channels and switch boxes, which are configured to transmit signals between logic function blocks and control the direction and path of signal transmission through programmable switches in the switch boxes. The local interconnection resources include connection boxes, which realize signal transmission between the logic function blocks and the interconnection channels. By connecting and expanding the functions of the logic function blocks, a complete application circuit function required by the user can be formed to meet the user's interconnection requirements. The island-type interconnection architecture allows the multi-master multi-slave routing arbitration structure and the interconnection component to be expanded with more processors or peripherals to adapt to different communication requirements. Different types of interconnection channels and switch boxes help to more effectively utilize hardware resources, reduce the size of the reconfigurable interconnection circuit for the multi-core processor, and thus reduce the size of the system-on-chip.

[0130] In an embodiment of the present application, the types of the interconnection component 102 include a slave interconnection component 1021, a master interconnection component 1022, a storage interconnection component 1023, a system application interconnection component 1024, and a control interconnection component 1025, wherein,

[0131] The slave interconnection component 1021 is configured to realize interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor acts as a slave and the embedded FPGA acts as a master.

[0132] The host interconnect component 1022 is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as a host and the embedded FPGA acts as a slave.

[0133] The storage interconnect component 1023 is used to interconnect storage resources;

[0134] The system application interconnection component 1024 is used to realize the interconnection of system-level applications;

[0135] The control interconnection component 1025 is used to transmit control signals.

[0136] like Figure 1 As shown, the slave interconnect component 1021 is used to interconnect at least one CPU in the multi-core processor as a slave and the eFPGA as a master. That is, through the slave interconnect component 1021, the CPU in the multi-core processor can respond to the request of the eFPGA and execute the corresponding task. The master interconnect component 1022 is used to interconnect at least one CPU in the multi-core processor as a master and the eFPGA as a slave. That is, through the master interconnect component 1022, the multi-core processor can control the eFPGA and send instructions and data to it. The storage interconnect component 1023 is used to interconnect storage resources, that is, to manage the access of the multi-core processor and the eFPGA to storage resources (such as memory, hard disk, etc.) and realize data storage and retrieval. The system application interconnect component 1024 is used to interconnect system-level applications, such as for data exchange and communication between different applications. The control interconnect component 1025 is used to transmit control signals and manage the control signals (such as synchronization signals, interrupt signals, etc.) between the multi-core processor and the FPGA to ensure stable operation of the SoC.

[0137] Different types of interconnect components collaborate to enable communication and data transfer between multi-core processors and embedded FPGAs or with other resources, adapting to different computing needs and application scenarios.

[0138] In some embodiments, the embedded FPGA as a host includes at least one programmable logic device instantiated from the embedded FPGA as a host.

[0139] In some embodiments, the embedded FPGA as a slave device includes at least one programmable logic device instantiated from the embedded FPGA as a slave device.

[0140] An eFPGA is an FPGA embedded in a SoC, instantiation refers to creating an instance of a specific hardware design, which can be a logic module, a processor core or any other predefined hardware structure. A programmable logic device refers to a hardware component that can reconfigure its internal logic after manufacturing, in an embedded FPGA, the programmable logic device is usually composed of programmable logic units (such as lookup tables, flip-flops, etc.) and programmable resources (such as switch boxes, wiring resources, etc.).

[0141] In the case of an embedded FPGA as a host, the embedded FPGA instantiates at least one programmable logic device as a host, that is, the FPGA can actively initiate a communication request, control data transmission or logic processing, and the FPGA as a host can directly communicate and exchange data with other parts of the SoC.

[0142] In the case of an embedded FPGA as a slave, the embedded FPGA instantiates at least one programmable logic device as a slave, which responds to requests from a CPU or other host, and the embedded FPGA as a slave can execute specific tasks or requests initiated by the host, so that the host can effectively utilize the embedded FPGA.

[0143] In some embodiments, the host interconnection component 1022 is further configured to implement interconnection between processors in the multi-core processor, at least one processor as a host and at least another processor as a slave.

[0144] It can be understood that the host interconnection component 1022 can be used to implement the interconnection of at least one processor in the multi-core processor as a host and the embedded FPGA as a slave, and can also be used to implement the interconnection of at least one processor in the multi-core processor as a host and at least another processor as a slave, that is, the host interconnection component 1022 can support communication within the multi-core processor, allowing different CPUs to communicate without the need for external other devices, improving the communication efficiency within the multi-core processor, reducing communication delay and improving the processing capability of the SoC.

[0145] In some embodiments, the host interconnection component 1022 is further configured to implement interconnection between at least one processor in the multi-core processor, the embedded FPGA instantiating at least one programmable logic device and at least another processor, the at least one processor in the multi-core processor as a host and the at least another processor as a slave.

[0146] It can be understood that the host interconnection component 1022 can be used to realize the interconnection between the host and the slave inside the multi-core processor, and can also be used to communicate at least one programmable logic device instantiated by the eFPGA as a slave, that is, the host interconnection component can manage the communication inside the multi-core processor and the communication between the multi-core processor and the eFPGA at the same time, so that the multi-core processors and the embedded FPGA can cooperate more closely to meet the corresponding computing requirements and application scenarios.

[0147] In the above technical solution, the interconnection components include slave interconnection components, host interconnection components, storage interconnection components, system application interconnection components, and control interconnection components. Different types of interconnection components cooperate with each other to realize data transmission and control signal transmission between the multi-core processor and the embedded FPGA or other resources. The processors in the multi-core processor and the programmable logic devices instantiated in the embedded FPGA can be configured as hosts or slaves to improve data transmission efficiency. Different types of interconnection components can adapt to different communication requirements. By dynamically allocating interconnection resources, the demand for hardware resources can be effectively reduced, the size of the reconfigurable interconnection circuit can be reduced, and thus the size of the system-on-chip can be reduced.

[0148] In an embodiment of the present application, the types of the interface include at least one of an AMBA general interface, an AMBA high-performance interface, an AMBA_ACP interface, and a CTRL_IO_SIG interface.

[0149] The AMBA general interface is a standardized interface for connecting various components in the multi-core processor and the eFPGA, supporting basic data transmission and communication requirements, and suitable for a variety of different devices and application scenarios. In some embodiments, the AMBA general interface is designed as a 32-bit or 64-bit data bus for low-to-medium speed data communication between the multi-core processor and the eFPGA. The interface is transparent, that is, data is directly transmitted from one device to another without passing through additional buffers. Two AMBA general interfaces are configured to realize bidirectional communication: one interface allows the CPU to control the communication as a host, and the other interface allows the PL (programmable logic device instantiated by the eFPGA) to control the communication as a host. The CPU and the eFPGA can play the role of host or slave as needed in different scenarios, thereby improving the flexibility and communication efficiency of the SoC.

[0150] The AMBA high-performance interface is designed to meet the needs of high-performance computing, providing higher data transmission rate and lower latency. In some embodiments, the AMBA high-performance interface is provided with a FIFO (First-In-First-Out) buffer, allowing batch read and write operations to be performed, thereby further improving the efficiency of data transmission, enabling high-speed data communication between the eFPGA and the multi-core processor, and the data bus width is 32 bits or 64 bits to adapt to different data transmission needs.

[0151] The AMBA_ACP interface is an interface designed for accelerators, supporting cache coherence protocols, allowing accelerators to directly access SoC memory, maintaining cache coherence with processors, and can be used to improve data processing efficiency and reduce latency.

[0152] The CTRL_IO_SIG interface is used to transmit control signals between the multi-core processor and the eFPGA, and can be used to implement synchronization operations and correct data transmission control between SoC components.

[0153] In the above technical solutions, the multiple interface types used in the multi-core processor-oriented reconfigurable interconnection circuit include at least one of the AMBA general-purpose interface, the AMBA high-performance interface, the AMBA_ACP interface, and the CTRL_IO_SIG interface. The AMBA general-purpose interface supports communication between the multi-core processor and the embedded FPGA in master or slave roles, the AMBA high-performance interface improves data transmission rate through FIFO buffering, the ACP interface implements cache coherence and can be used to optimize accelerator memory access, and the CTRL_IO_SIG interface is used to transmit control signals. By configuring different interfaces, the interface can be dynamically selected according to the communication needs, improving the efficiency of data transmission. The design of multiple interface types and interconnection components enables the multi-core processor-oriented reconfigurable interconnection circuit to adapt to different communication needs, effectively reducing the demand for hardware resources and the size of the multi-core processor-oriented reconfigurable interconnection circuit, thereby reducing the size of the system-on-chip.

[0154] In an embodiment of the present application, all interfaces on the multi-core processor side except the accelerator coherence interface are connected to the multi-master multi-slave routing arbitration structure, and the embedded FPGA is connected through the interconnection component.

[0155] The accelerator coherence interface (Accelerator Coherency Port, ACP) is a special interface that can be used for cache coherence access between the multi-core processor and the embedded FPGA, supporting all standard read and write transactions without additional coherence management.

[0156] It can be understood that the ACP interface already has the ability to handle consistent transactions, so it is no longer necessary to perform additional consistency management through the multi-master multi-slave routing arbitration structure, and additional competition and latency that can occur in the multi-master multi-slave routing arbitration structure is avoided, and the data transmission efficiency between the multi-core processor and the embedded FPGA can be improved.

[0157] In the above technical solution, all interfaces of the multi-core processor side except the accelerated consistency interface are connected to the multi-master multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnection component, and the interconnection resources are dynamically allocated through routing arbitration to form a reconfigurable interconnection circuit, realizing the interconnection between the multi-core processor and the embedded FPGA, which can reduce the demand for hardware resources and reduce the size of the system-on-chip, and the accelerated consistency interface is not connected to the multi-master multi-slave routing arbitration structure, avoiding additional competition and latency that can occur, and improving the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0158] In an embodiment of the present application, the accelerated consistency interface on the multi-core processor side is directly connected to a system application interconnection component in the interconnection component, and the system application interconnection component is a consistency control unit in the accelerated processor.

[0159] The consistency control unit (System Coherency Unit, SCU) in the accelerated processor (Accelerated Processing Unit, APU) is used to maintain the cache coherency inside the multi-core processor.

[0160] It can be understood that the accelerated consistency interface is directly connected to the consistency control unit in the accelerated processor, and this connection mode makes the accelerated consistency interface not connected to the multi-master multi-slave routing arbitration structure, but directly connected to the system application interconnection component in the interconnection component, which can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0161] In the above technical solution, the accelerated consistency interface on the multi-core processor side is directly connected to the system application interconnection component in the interconnection component, and this component is the consistency control unit in the accelerated processor, which can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0162] In an embodiment of the present application, the interface on the embedded FPGA side includes at least one of the following: a master AMBA general interface, a slave AMBA general interface, a master AMBA high-performance interface, a slave AMBA_ACP interface, and a CTRL_IO_SIG interface.

[0163] The slave interconnection component is connected with the master AMBA general interface, the master interconnection component is connected with the slave AMBA general interface, the storage interconnection component is connected with the master AMBA high-performance interface, the system application interconnection component is connected with the slave AMBA_ACP interface, and the control interconnection component is connected with the CTRL_IO_SIG interface.

[0164] On the embedded FPGA side, the master AMBA general interface is used for communication when the embedded FPGA is a master and the processor is a slave. The master AMBA high-performance interface is used for high-speed data transmission. The slave AMBA_ACP interface is used for high-speed data transmission supporting cache consistency. The CTRL_IO_SIG interface is used for transmitting control signals and input / output signals.

[0165] The master interconnection component is connected to the slave AMBA general interface, allowing the embedded FPGA to respond to the processor's request as a slave. The storage interconnection component is connected to the master AMBA high-performance interface for high-speed data transmission of storage resources. The system application interconnection component is connected to the slave AMBA_ACP interface for high-speed data transmission of system-level applications. The control interconnection component is connected to the CTRL_IO_SIG interface for transmitting control signals and input / output signals.

[0166] Table 1

[0167]

[0168] Table 1 is an interface description table provided by some embodiments of the present application. As shown in Table 1, in some embodiments, the interface type further includes an AHB_HP interface and an AHB_GP interface. In Table 1, when the interface name starts with M, the processor is the master and the embedded FPGA is the slave. When the interface name starts with S, the processor is the slave and the embedded FPGA is the master.

[0169] The AHB_HP interface realizes a high-bandwidth data path from the FPGA bus master to the OCM and DDR memory, with two read-write communication FIFO buffers. The storage interconnection component connects the high-speed AXI_HP interface with two DDR memory interfaces or OCM. The AXI_HP interface has a 32-bit or 64-bit data master interface, each interface can be programmed independently, and can automatically expand the unaligned 32-bit transmission to 64-bit. The AXI_HP interface also has a programmable write command threshold, supports cross-domain operation under asynchronous clock frequency, and the interface also includes read-write FIFO. The command and communication data FIFO fill level count is visible to the FPGA, allowing the eFPGA to dynamically monitor and manage data.

[0170] The AHB_GP interface is a direct interface, unlike the AHB_HP interface, the AHB_GP interface has no additional buffer, so its performance is mainly limited by the host interface and the slave interconnection, and the AHB_GP interface is more suitable for general rather than high-performance tasks. Each interface of the AHB_GP interface can support multiple peripherals. The AHB_GP interface supports a 32-bit or 64-bit data bus width, has a 12-bit bus interface ID width and a 6-bit slave interface ID width, a host and a slave interface, and each interface can accept 8 read and 8 write operations at a time.

[0171] In the above technical solution, the slave interconnection component is connected with the host AMBA general interface, the host interconnection component is connected with the slave AMBA general interface, the storage interconnection component is connected with the host AMBA high-performance interface, the system application interconnection component is connected with the slave AMBA_ACP interface, and the control interconnection component is connected with the CTRL_IO_SIG interface. The interface configuration on the embedded FPGA side and the connection mode thereof with different interconnection components are illustrated, the communication and data transmission between the multi-core processor and the embedded FPGA are realized, and the data transmission demand in different application scenarios can be met.

[0172] In an embodiment of the present application, the method for allocating the corresponding interconnection resources for the data transmission comprises: determining the connection relationship of the interconnection line segments in the interconnection component and the jump relationship between the interconnection line segments according to the number of interfaces, the type of interfaces and the circuit application demand of the multi-master multi-slave routing arbitration structure, and generating a reconfigurable configuration file, the reconfigurable configuration file being used for realizing the configuration of the conduction or shutdown of the programmable switch in the switch box and the input connection module and the output connection module in the connection box.

[0173] It can be understood that, in the multi-master multi-slave routing arbitration structure, in order to efficiently perform data transmission, the corresponding interconnection resources need to be allocated for the data transmission, and the allocation process is based on the number of interfaces, the type of interfaces and the circuit application demand of the multi-master multi-slave routing arbitration structure. Due to the complexity of the interface logic between the processor and the embedded FPGA, a large number of interfaces and dedicated interconnection resources are needed to realize data transmission. Therefore, in some embodiments, a multi-stage combined interconnection structure is used to design the connection relationship of the interconnection line segments in the interconnection component and the jump relationship between the interconnection line segments.

[0174] The number of interfaces in the multi-master multi-slave routing arbitration structure determines the number of channels that can perform data transmission, and the type of interfaces determines the type of transmitted data. The circuit application demand, i.e., the different demands of different application scenarios for data transmission, including data transmission rate, delay, bandwidth, etc., will directly affect the allocation and configuration of interconnection resources.

[0175] The interconnection line segment is the basis of the interconnection component, which connects different logical function blocks in the interconnection component, forms a data transmission path by determining the connection relationship between the interconnection line segments, and realizes effective data transmission. In the interconnection component, data may need to jump between multiple interconnection line segments, and the jump relationship determines the routing path of the data in the interconnection circuit and how to select the path through the switch box and other interconnection components. After determining the connection relationship of the interconnection line segments in the interconnection component and the jump relationship between the interconnection line segments, a reconfigurable configuration file can be generated.

[0176] Figure 5 is a schematic diagram of configuring interconnection resources provided by some embodiments of the present application. As shown in Figure 5 , the multi-master multi-slave routing arbitration structure or the interconnection component adopts an island type interconnection architecture, and the interconnection resources under the island type interconnection architecture include global interconnection resources and local interconnection resources; the global interconnection resources include an interconnection channel and a switch box, the interconnection channel is composed of a preset number of interconnection line segments, and is used to realize signal transmission between logical function blocks; the switch box includes a preset number of programmable switches, and is used to realize jumping between different interconnection line segments; the local interconnection resources include a connection box, which includes an input connection module and an output connection module, the input connection module and the output connection module are not shown in Figure 5 , and can be realized by programmable switches; the connection box is used to realize signal transmission between the logical function blocks and the interconnection channel. The reconfigurable configuration file is used to realize the configuration of turning on or turning off the programmable switches in the switch box and the input connection module and the output connection module in the connection box.

[0177] In the above technical solution, according to the number of interfaces, the type of interfaces and the circuit application demand of the multi-master multi-slave routing arbitration structure, the connection relationship of the interconnection line segments in the interconnection component and the jump relationship between the interconnection line segments are determined, and a reconfigurable configuration file is generated. According to the reconfigurable configuration file, the corresponding interconnection resources are allocated for data transmission, so that the reconfigurable interconnection circuit for the multi-core processor can adapt to different data transmission demands, and the flexibility of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0178] In an embodiment of the present application, the horizontal channel and the vertical channel of the embedded FPGA side programmable interconnection provide the global interconnection resources, and the global interconnection resources interact with signals through the local interconnection resources and the multi-core processor side interconnection bus;

[0179] The signal output of the multi-core processor side is sent into the interconnection component through the local interconnection resources, and is processed by a corresponding logic unit, or the signal output of the multi-core processor side is sent into an adjacent logic unit through the horizontal channel for processing.

[0180] The embedded FPGA-side programmable interconnects, including horizontal and vertical channels, provide global interconnect resources that allow signals to be transmitted between different logic units. These global interconnect resources include interconnect channels and switch boxes. The interconnect channels are used to transmit signals between logic functional blocks, while the switch boxes contain programmable switches to control the direction and path of signal transmission, thereby enabling flexible signal routing.

[0181] Signal outputs from the multi-core processor can be sent to interconnect components via local interconnect resources, and these signals can also be sent directly to adjacent logic units for processing via horizontal channels, thereby reducing data transmission latency.

[0182] Local interconnect resources include a connection box and an input cross-connect module. The connection box includes input connection modules and output connection modules, used to realize signal transmission between logic function blocks and interconnect channels. The input cross-connect module realizes signal interconnection between logic units. This module can also connect the input pins of the logic function block to each logic unit. It should be noted that multiple logic units constitute a logic function block.

[0183] In the above technical solution, the horizontal and vertical channels of the programmable interconnect on the embedded FPGA side provide global interconnect resources. The global interconnect resources interact with the interconnect bus on the multi-core processor side through local interconnect resources. The signal output on the multi-core processor side is sent to the interconnect component through the local interconnect resources and processed by the corresponding logic unit, or sent to the adjacent logic unit through the horizontal channel for processing. Through the global and local interconnect resources, the interconnection between the multi-core processor and the embedded FPGA is realized, which improves the flexibility of the reconfigurable interconnect circuit for multi-core processors.

[0184] In one embodiment of this application, the interconnection channel is a one-way channel or a two-way channel.

[0185] Figure 6 This is a schematic diagram of the interconnection channel structure provided in some embodiments of this application. For example... Figure 6 As shown in (a), the unidirectional channel uses a unidirectional inverter or buffer at the end of the connection to determine the direction of signal transmission. Signals can only be transmitted from terminals A and C to terminals B and D respectively; the reverse direction is not possible. Figure 6 As shown in (b), at the end of the bidirectional channel connection, the direction of the channel signal transmission is usually selected by a bidirectional selector. The bidirectional selector is often implemented by a buffer or a tri-state buffer. The A and B terminals in the figure can be configured to achieve bidirectional signal transmission.

[0186] In the technical solution, the interconnection channel is a one-way channel or a two-way channel, different interconnection channels are selected to adapt to different data transmission requirements, and the data transmission efficiency of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0187] In an embodiment of the present application, the topology type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection, and vertical interconnection.

[0188] Figure 7 is a programmable switch topology diagram provided by some embodiments of the present application. As shown in Figure 7 The topology type of the programmable switch includes at least one of subset interconnection, global interconnection, and vertical interconnection.

[0189] Subset interconnection means that the programmable switch is configured to connect certain specific circuit elements or modules, thereby forming a smaller, local connection subset. This connection mode is suitable for scenarios where local communication between circuit modules that need to implement specific functions is required.

[0190] Global interconnection means that the programmable switch is configured to allow extensive, global connections between circuit elements or modules. This connection mode is usually used to implement complex circuit functions and system-level integration.

[0191] Vertical interconnection refers to the connection between different levels or different circuit boards, allowing signals to be transmitted between different levels. This connection mode is usually implemented through vias, conductive pillars, or other vertical coupling structures.

[0192] By reasonably selecting and applying the topology type of the programmable switch in the switch box, the jump between different interconnection segments can be achieved, the path selection and jump control between different interconnection segments can be performed, and the direction and routing of signal transmission can be managed.

[0193] In the technical solution, the topology type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection, and vertical interconnection, and by reasonably selecting and applying the topology type of the programmable switch in the switch box, the flexibility and scalability of the reconfigurable interconnection circuit for the multi-core processor can be improved.

[0194] In an embodiment of the present application, the switch box adopts a combination of bidirectional interconnection switches and unidirectional interconnection switches.

[0195] Figure 8 is a structure diagram of a bidirectional interconnection switch provided by some embodiments of the present application. As shown in Figure 8As shown, the horizontal (x) direction interconnection line segment can transmit signals from left to right or from right to left; the vertical (y) direction interconnection line segment can transmit signals from top to bottom or from bottom to top. If the bidirectional interconnection switch is used in the SB as shown in Figure 8 The driven interconnection line segment of the bidirectional interconnection switch is bidirectional.

[0196] Figure 9 is a structural schematic diagram of a unidirectional interconnection switch provided by some embodiments of the present application. As shown in Figure 9 The unidirectional interconnection switch only allows signals to flow in one direction and is suitable for scenarios where signal transmission has a clear direction.

[0197] The combination of the bidirectional interconnection switch and the unidirectional interconnection switch can flexibly configure the transmission path to adapt to different signal transmission requirements.

[0198] In some embodiments, the number of interconnection switches and the jump relationship are set as follows: the connectivity (Fc) between the CLB pin and the wire is set to 10%, that is, among the wires passing through a certain pin of the CLB, 10% of the wires have switches to the input pin, and the number of other interconnection line segments that the interconnection line segment can connect at its end (Fs) is at least 3 and covers the left turn, right turn and forward three directions. The logic function block allows direct data exchange between the input and output of the logic unit, that is, the direct connection signal is increased. By utilizing these flexibilities and considering all options provided by the multi-stage programmable interconnection network, the layout and routing tool can achieve a high routing rate even in the case of low Fc and Fs values.

[0199] In the above technical solution, the switch box is implemented by combining the bidirectional interconnection switch and the unidirectional interconnection switch. By selecting different interconnection switches, various signal transmission requirements can be met, and the data transmission efficiency of the reconfigurable interconnection circuit for multi-core processors is improved.

[0200] In an embodiment of the present application, the types of the interconnection line segments include long interconnection line segments, short interconnection line segments, local interconnection line segments and direct connection line segments. The long interconnection line segments are used to meet the signal path requirements between logic function blocks far apart, the short interconnection line segments are used to realize the interconnection between adjacent logic function blocks, the local interconnection line segments are used to realize the signal sharing and feedback between logic units in each logic function block, and the direct connection line segments are used for signal transmission between adjacent logic function blocks.

[0201] It can be understood that the long interconnection line segment is used to meet the signal path requirement between the logic function blocks far apart, and in the reconfigurable interconnection circuit facing the multi-core processor, the logic function blocks can be distributed at different positions, and the long interconnection line segment can cross a large spatial distance, so that the signal can be accurately transmitted to the target logic function block. The short interconnection line segment is used to realize a large number of signal flows between adjacent logic function blocks and fast interconnection, and since the adjacent logic function blocks are relatively close in space, the short interconnection line segment can reduce the delay and power consumption of signal transmission, thereby improving the efficiency of data transmission. The local interconnection line segment is used to realize signal sharing and feedback between the logic units in each logic function block, and is helpful to enhance the signal processing capability of the logic function block. The direct connection line segment is used for signal transmission between adjacent logic function blocks, and can reduce the delay and power consumption of signal transmission.

[0202] In the embodiment of the present application, the interconnection line segment adopts a multi-stage combined interconnection system, that is, "long line-short line-local interconnection line-direct connection line", and different types of rich interconnection resources are provided to meet the interconnection requirements under different applications, and the user circuit can be efficiently and flexibly implemented.

[0203] Creating a good interconnection architecture involves many complex compromises, including enough programmable switches and interconnection line segments, so that most circuits can be implemented to achieve good routing rate; however, too many interconnection line segments and programmable switches will waste area. Short interconnection line segments are used for connections with a short distance to reduce capacitance and layout area, and long interconnection line segments are used for connections with a long distance to avoid additional delay caused by passing through multiple programmable switches.

[0204] In the above technical solution, the design of the interconnection line segment adopts a multi-stage combined interconnection system, including a long interconnection line segment, a short interconnection line segment, a local interconnection line segment and a direct connection line segment, to meet the interconnection requirements of different distances and different complexities, adapt to the layout and signal transmission of different logic function blocks in the multi-master multi-slave routing arbitration structure and the interconnection component, and improve the flexibility of the reconfigurable interconnection circuit facing the multi-core processor.

[0205] In an embodiment of the present application, the parameters of the multi-master multi-slave routing arbitration structure or the interconnection component include: the number of routing wires that can be connected to the input or output of each logic function block, the number of other routing wires that can be connected to each routing wire, the length of the routing line segment, the mode of the routing switch, the electrical design of the routing wire and the programmable switch, and the number of routing line segments of each channel.

[0206] The number of routing wires that each logical function block can connect to determines how many routing wires the logical function block can connect to, thereby affecting the ability and flexibility of signal transmission. The number of other routing wires that each routing wire can connect to relates to the cross-connection ability between routing wires, affecting the routing selection and traffic management of signals on different paths. The length of the routing wire segment affects the delay of signal transmission and the integrity of the signal, and in physical design, it is directly related to the layout and wiring of the circuit. The mode of the routing switch determines the configuration method of the signal transmission path, including one-way or two-way transmission, and how to select the path through the switch box.

[0207] Figure 10 is a schematic diagram of a multi-master multi-slave routing arbitration structure or interconnection component provided by some embodiments of the present application. For example, the number of routing wires that each logical function block can connect to is 3, the number of other routing wires that each routing wire can connect to is 3, and the number of routing wire segments of each channel is 4. Figure 10

[0208] Figure 11 is a schematic diagram of a programmable switch structure provided by some embodiments of the present application. As shown in Figure 11 , the eFPGA can use transmission tubes controlled by SRAM cells to connect the interconnection wires. Although the transmission tube can bring the smallest area, this structure brings quadratic growth of delay when a large number of transmission tubes are connected in series, which makes this structure slow in implementing large FPGAs.

[0209] In some embodiments, the programmable switch is implemented using a multiplexer and a tri-state buffer. With the increase in area, the delay is reduced, and the eFPGA uses a multiplexer composed of transmission tubes, and the output of the multiplexer is buffered by a tri-state buffer.

[0210] A multiplexer (MUX) is a kind of logic circuit with multiple input lines and an output line, which can select one of multiple inputs as output according to the selection signal. In a reconfigurable interconnection circuit, MUX is used to select the signal path that should be activated.

[0211] Figure 12 is a schematic diagram of a multiplexer provided by some embodiments of the present application. The structure has small transmission tube size and large buffer size, which can balance the area and driving ability, and the structure has superior electrical characteristics, reduces the area, and improves the speed. The multiplexer as shown in Figure 12 can be used as the basic implementation structure of the programmable switch.

[0212] ​A tri-state buffer is a kind of buffer that can be in three states, corresponding to three states of high level, low level and high impedance state (disabled state). The high impedance state allows other parts of the circuit to take over the bus, so that multiple devices can share the same communication path without interfering with each other. In a reconfigurable interconnection circuit, tri-state buffers are used to disable the path when signal transmission is not needed, or to coordinate access when multiple devices share the same bus.

[0213] The programmable switch implemented using the multiplexer and the tri-state buffer improves the flexibility and control capability of the multi-master multi-slave routing arbitration structure or interconnection component, and can be dynamically adjusted according to real-time data transmission requirements and routing decisions.

[0214] In the above technical solution, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component include the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing wire segment, the mode of the routing switch, the electrical design of the routing wire and the programmable switch, and the number of routing wire segments of each channel. These parameters together determine the configuration method of the data transmission path of the reconfigurable interconnection circuit for multi-core processors, which realizes dynamic adjustment of the routing path according to different data transmission requirements, adapts to different application scenarios, and helps to more effectively utilize hardware resources.

[0215] In an embodiment of the present application, the multi-master multi-slave routing arbitration structure includes an AMBA bus matrix 1011, which is used to connect all AMBA bus interfaces of the multi-core processor.

[0216] Figure 13 is a schematic diagram of the AMBA bus matrix provided by some embodiments of the present application, as Figure 13 As shown in the figure, some embodiments of the multi-master multi-slave routing arbitration structure also include an AMBA bus matrix 1011, which is used to connect all AMBA bus interfaces of the multi-core processor. In a multi-core processor, different processors may need to access the same resources, such as memory or peripherals. The AMBA bus matrix provides a shared communication path, and by centrally managing the AMBA bus interfaces, it realizes resource allocation and traffic control, and optimizes the overall performance of the reconfigurable interconnection circuit for multi-core processors.

[0217] In the above technical solution, the multi-master multi-slave routing arbitration structure includes an AMBA bus matrix for connecting all AMBA bus interfaces of the multi-core processor. By centrally connecting all AMBA bus interfaces of the multi-core processor, the efficiency of data transmission is improved, the use of hardware resources is optimized, and the flexibility of the reconfigurable interconnection circuit for multi-core processors is improved.

[0218] Figure 14 is a flowchart of an implementation method of a reconfigurable interconnection circuit for a multi-core processor provided by some embodiments of the present application. As shown in the figure, the implementation method of the reconfigurable interconnection circuit for a multi-core processor includes steps 1410, 1420 and 1430. Figure 14

[0219] Step 1410, according to the interconnection requirement, the interconnection parameter of the multi-core processor side and the interconnection parameter of the embedded FPGA side, generates the code of the reconfigurable interconnection circuit for a multi-core processor;

[0220] The complete interconnection circuit function required by the user is formed by connecting and expanding the functions implemented by multiple logical function blocks. The interconnection requirement reflects the complete interconnection circuit function required by the user, and according to the interconnection requirement, it can be determined which logical function blocks need to be connected and expanded.

[0221] In some embodiments, the interconnection parameter of the multi-core processor side includes at least one of the following: the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master multi-slave routing arbitration structure, the interface type of the multi-master multi-slave routing arbitration structure;

[0222] The interconnection parameter of the embedded FPGA side includes at least one of the following: the number of embedded FPGA masters and slaves, the AMBA bus interface type, the number of interconnection component signals, the interconnection component type, and the number of each interconnection component type.

[0223] In some embodiments, the code of the reconfigurable interconnection circuit for a multi-core processor is generated according to the interconnection requirement, the interconnection parameter of the multi-core processor side and the interconnection parameter of the embedded FPGA side, including:

[0224] According to the interconnection requirement, determine the data transmission between the multi-core processor and the embedded FPGA or inside the multi-core processor;

[0225] According to the interconnection parameter of the multi-core processor side and the interconnection parameter of the embedded FPGA side, generate the code of the reconfigurable interconnection circuit for a multi-core processor for the data transmission.

[0226] ​It can be understood that the code of the reconfigurable interconnection circuit facing the multi-core processor is generated according to at least one of the interconnection requirement, the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master multi-slave routing arbitration structure, the interface type of the multi-master multi-slave routing arbitration structure, at least one of the number of embedded FPGAs masters and slaves, the AMBA bus interface type, the number of interconnection component signals, the interconnection component type and the number of each interconnection component type, so as to enable the generated code to meet the communication and data transmission requirements of the multi-core processor and the embedded FPGA. The structure, function and interconnection relationship of the multi-master multi-slave routing arbitration structure and the interconnection component in the reconfigurable interconnection circuit facing the multi-core processor are defined in detail in the generated code.

[0227] Step 1420, generating an FPGA configuration file according to the code.

[0228] The configuration file of the FPGA is created according to the code generated in step 1410. The configuration file contains information to be downloaded into the embedded FPGA for configuration. The generation of the configuration file may involve code compilation, synthesis and optimization, etc., so that the configuration file can be correctly understood and executed by the embedded FPGA.

[0229] Step 1430, downloading the FPGA configuration file into the embedded FPGA to form the reconfigurable interconnection circuit facing the multi-core processor.

[0230] The FPGA configuration file generated in step 1420 is downloaded into the embedded FPGA, so that it can implement the preset reconfigurable interconnection circuit facing the multi-core processor according to the instructions in the configuration file.

[0231] In the above technical solution, the code of the reconfigurable interconnection circuit facing the multi-core processor is generated according to the interconnection requirement, the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, and the code is converted into an FPGA configuration file. The FPGA configuration file is downloaded into the embedded FPGA to implement the reconfigurable interconnection circuit facing the multi-core processor, improve the flexibility of implementing the reconfigurable interconnection circuit facing the multi-core processor, and enhance the scalability and adaptability of the reconfigurable interconnection circuit facing the multi-core processor.

[0232] The embodiment of the application further provides a chip, which comprises a multi-core processor and an embedded FPGA, and further comprises a reconfigurable interconnection circuit facing the multi-core processor. For understanding of the reconfigurable interconnection circuit facing the multi-core processor, reference can be made to the description in the foregoing embodiments, which will not be repeated here.

[0233] It should be understood that the chip mentioned in the embodiments of the present application can also be referred to as a system-level chip, a system chip, a chip system, or a system-on-chip chip, etc.

[0234] It should be noted that, in this document, the terms "comprise", "comprising", or any other variant thereof are intended to cover non-exclusive inclusions, such that processes, methods, articles, or apparatuses that comprise a list of elements are not limited to those elements, but can also include other elements not expressly listed, or inherent to such processes, methods, articles, or apparatuses. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element. In addition, it should be pointed out that the scope of the methods and apparatuses in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but can also include performing functions in a substantially simultaneous manner or in reverse order, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted, or combined. In addition, the features described with reference to certain examples can be combined in other examples.

[0235] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and the necessary general hardware platform, of course, they can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) execute the methods described in various embodiments of the present application.

[0236] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative, not limiting, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

[0237] In the description of the application, reference has been made to descriptive terms such as "one embodiment", "some embodiments", "an embodiment", "example", "specific example" or "some examples" etc. It is emphasized that each of these terms refers to a specific feature, structure, material or characteristic described in connection with a particular embodiment or example. The descriptive terms are not necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0238] While embodiments of the application have been shown and described, it is to be understood that the application is not limited to the details of the embodiments described, since the scope of the application is defined with respect to the appended claims.

Claims

1. A reconfigurable interconnect circuit for a multi-core processor, comprising: The application relates to a multi-master multi-slave routing arbitration structure and an interconnection component, wherein a multi-core processor is connected to the multi-master multi-slave routing arbitration structure, and the multi-master multi-slave routing arbitration structure is connected to an embedded field programmable gate array (FPGA) through the interconnection component. The multi-master multi-slave routing arbitration structure is used for identifying and routing arbitration of data transmission between the multi-core processor or between the multi-core processor and the embedded FPGA, and the data transmission is allocated with corresponding interconnection resources based on the interconnection component. The interconnection component is used for managing and transmitting communication between interfaces connected to the interconnection component, and the interfaces are interfaces on the multi-core processor side and / or interfaces on the embedded FPGA side. The multi-master multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources. The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes. The interconnection channel is composed of a preset number of interconnection line segments and is used for realizing signal transmission between logic function blocks. The switch box includes a preset number of programmable switches and is used for realizing jump between different interconnection line segments. The connection box includes an input connection module and an output connection module and is used for realizing signal transmission between logic function blocks and the interconnection channel. The types of the interconnection component include slave interconnection components, master interconnection components, storage interconnection components, system application interconnection components and control interconnection components.

2. The reconfigurable interconnect circuit for a multi-core processor according to claim 1, wherein, The slave interconnection component is used for realizing interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor acts as a slave and the embedded FPGA acts as a master. The master interconnection component is used for realizing interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor acts as a master and the embedded FPGA acts as a slave. The storage interconnection component is used for realizing interconnection of storage resources. The system application interconnection component is used for realizing interconnection of system-level applications. The control interconnection component is used for realizing transmission of control signals. The embedded FPGA as a master includes at least one programmable logic device instantiated by the embedded FPGA as a master.

3. The reconfigurable interconnect circuit for a multi-core processor of claim 2, wherein, The embedded FPGA as a slave includes at least one programmable logic device instantiated by the embedded FPGA as a slave.

4. The reconfigurable interconnect circuit for a multi-core processor of claim 2, wherein, The master interconnection component is also used for realizing interconnection between processors in the multi-core processor, wherein at least one processor acts as a master and at least another processor acts as a slave.

5. The reconfigurable interconnect circuit for a multi-core processor of claim 2, wherein, The master interconnection component is also used for realizing interconnection between at least one processor in the multi-core processor and the embedded FPGA and at least another processor, wherein the at least one processor in the multi-core processor acts as a master, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor act as slaves.

6. The reconfigurable interconnect circuit for a multi-core processor of claim 2, wherein, ​ 7. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The types of the interfaces include at least one of an Advanced Microcontroller Bus Architecture (AMBA) general interface, an AMBA high-performance interface, an AMBA_ACP interface and a CTRL_IO_SIG interface.

8. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, All interfaces of the multi-core processor side except the accelerated coherence interface are connected to the multi-master multi-slave routing arbitration structure, and the embedded FPGA is connected to the interconnection assembly.

9. The reconfigurable interconnect circuit for a multi-core processor of claim 2, wherein, The accelerated coherence interface of the multi-core processor side is directly connected to a system application interconnection assembly in the interconnection assembly, and the system application interconnection assembly is a coherence control unit in the accelerated processor.

10. The reconfigurable interconnect circuit for a multi-core processor of claim 2, wherein, The interfaces of the embedded FPGA side include at least one of a master AMBA general interface, a slave AMBA general interface, a master AMBA high-performance interface, a slave AMBA_ACP interface and a CTRL_IO_SIG interface. The slave interconnection assembly is connected to the master AMBA general interface, the master interconnection assembly is connected to the slave AMBA general interface, the storage interconnection assembly is connected to the master AMBA high-performance interface, the system application interconnection assembly is connected to the slave AMBA_ACP interface, and the control interconnection assembly is connected to the CTRL_IO_SIG interface.

11. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The allocation of the interconnection resources for the data transmission includes: determining the connection relationship of the interconnection line segments and the jump relationship between the interconnection line segments in the interconnection assembly according to the number, type and circuit application demand of the interfaces of the multi-master multi-slave routing arbitration structure, and generating a reconfigurable configuration file, which is used for realizing the configuration of the conduction or shutdown of the programmable switches in the switch box and the input connection modules and the output connection modules in the connection box.

12. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The local interconnection resources further include an input cross interconnection module, which is used for realizing the signal interconnection between the logic units and connecting the input pins of the logic function blocks to the logic units. The plurality of logic units constitute the logic function block.

13. The reconfigurable interconnect circuit for a multi-core processor according to any one of claims 1-12, wherein, The horizontal channels and the vertical channels of the programmable interconnection of the embedded FPGA side provide the global interconnection resources, which are used for signal interaction through the local interconnection resources and the interconnection bus of the multi-core processor side. The signal output of the multi-core processor side is sent into the interconnection assembly through the local interconnection resources and is processed by the corresponding logic unit, or the signal output of the multi-core processor side is sent into the adjacent logic unit through the horizontal channel and is processed.

14. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The types of the interconnection line segments include long interconnection line segments, short interconnection line segments, local interconnection line segments and direct connection line segments, the long interconnection line segments are used for meeting the signal path demand between the logic function blocks far away from each other, the short interconnection line segments are used for realizing the interconnection between the adjacent logic function blocks, the local interconnection line segments are used for realizing the signal sharing and feedback between the logic units in each logic function block, and the direct connection line segments are used for the signal transmission between the adjacent logic function blocks.

15. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The interconnection channels are one-way channels or two-way channels.

16. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The switch box adopts a combination of bidirectional interconnection switches and unidirectional interconnection switches.

17. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The topology types of the programmable switches in the switch box include at least one of the following: subset interconnection, global interconnection, and vertical interconnection.

18. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The parameters of the multi-master multi-slave routing arbitration structure or interconnection component include: the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing segment, the mode of the routing switch, the electrical design of the wires and programmable switches, and the number of routing segments for each channel.

19. The reconfigurable interconnect circuit for a multi-core processor of claim 1, wherein, The programmable switch is implemented using a multiplexer and a tri-state buffer.

20. The reconfigurable interconnect circuit for a multi-core processor of any of claims 1-12, 14-19, wherein, The multi-master multi-slave routing arbitration structure includes an AMBA bus matrix, which is used to connect all AMBA bus interfaces of the multi-core processor.

21. A method of implementing a reconfigurable interconnect circuit for a multi-core processor according to any one of claims 1 to 20, characterized by, include: Based on interconnection requirements, interconnection parameters on the multi-core processor side, and interconnection parameters on the embedded FPGA side, the code for the reconfigurable interconnection circuit for the multi-core processor is generated. Generate an FPGA configuration file based on the code; The FPGA configuration file is downloaded to the embedded FPGA to form the reconfigurable interconnect circuit for multi-core processors.

22. The method of claim 21, wherein, The interconnect parameters on the multi-core processor side include at least one of the following: number of CPU cores, data bit width of each CPU, number of CPU master and slave, access address space of each CPU, CPU interface type, number of interfaces of the multi-master multi-slave routing arbitration structure, and interface type of the multi-master multi-slave routing arbitration structure. The interconnect parameters on the embedded FPGA side include at least one of the following: number of embedded FPGA master and slave, AMBA bus interface type, number of interconnect component signals, interconnect component type, and quantity of each type of interconnect component.

23. The method of claim 21, wherein, The step of generating the code for the reconfigurable interconnect circuit for the multi-core processor based on interconnect requirements, interconnect parameters on the multi-core processor side, and interconnect parameters on the embedded FPGA side includes: Based on interconnection requirements, determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA; Based on the interconnect parameters on the multi-core processor side and the interconnect parameters on the embedded FPGA side, code for the reconfigurable interconnect circuit for the multi-core processor is generated for the data transmission.

24. A chip, characterized by It includes multi-core processors and embedded FPGAs, and further includes reconfigurable interconnect circuitry for multi-core processors as claimed in any one of claims 1 to 20.

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