Method for analyzing high-temperature gate offset performance change of p-type gate GaN HEMT device

Abstract

The invention discloses a p-type gate GaN HEMT device high-temperature gate offset performance change analysis method, which comprises the following steps of: firstly, performing parameter acquisition and two-dimensional modeling on a p-type gate GaN HEMT device, and finishing fine grid division; thirdly, constructing an electrical model and optimizing the electrical model; after the consistency of the model and the device manual data is verified, setting the working conditions of the device, including temperature and bias voltage, and introducing a lattice heating model, a trap model, an interface state model, a mobility model and the like, so as to accurately simulate the performance of the device under an actual working condition; then, analyzing the influence of different HTGB stress times on the internal defect density, charge concentration and carrier concentration of the device by introducing a time model; and finally, simulating and analyzing the electrical characteristics of the device after different HTGB stress times, and evaluating the reliability of the device. According to the method, the influence mechanism of the HTGB on the performance degradation of the device is visually displayed, and the change trend of the performance of the device along with time can be evaluated.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a method for analyzing high-temperature gate bias performance changes of a p-type gate GaN HEMT device. Background Art

[0002] As a representative of the third generation of semiconductor materials, gallium nitride (GaN) has attracted more and more attention due to its superior properties such as high electron mobility and high critical electric field. As one of the most common gallium nitride devices, high electron mobility transistor (p-GaN HEMT) devices with p-type gate cap layer are widely used in high temperature, high voltage and high current applications. However, the reliability issues brought by high-power working environment to the devices have gradually become prominent, and it is necessary to analyze the failure mechanism and evaluate their lifespan.

[0003] According to existing experimental research reports, the failure mechanisms of GaN HEMT devices under different working conditions are somewhat different. Under the action of HTGB (High-temperature gate bias), the device threshold voltage (V TH ) drift phenomenon is the most obvious. First, the gate bias stress causes a negative electric center to form in the p-GaN region, causing the threshold voltage to drift positively. Second, high temperature changes the defect density inside the device and significantly reduces the electron concentration in the channel region under the gate, exacerbating the positive drift of the threshold voltage.

[0004] In the development and application of modern power semiconductor devices, high-temperature gate bias (HTGB) testing is an important method for evaluating the reliability of devices in high-temperature environments. HTGB testing is mainly used to analyze the electrical performance and long-term stability of devices under high-temperature gate bias conditions, especially for new wide-bandgap semiconductor devices such as GaN HEMT and SiC MOSFET. These devices may experience threshold voltage drift, increased leakage current and other phenomena under high temperature and high electric field environments, affecting their normal operation and life. At present, traditional HTGB testing methods mainly rely on device reliability experimental means, which is time-consuming and costly. Moreover, in actual operation, these methods are difficult to intuitively display the physical process of device performance changes, and it is also difficult to explain and analyze the specific reasons for the occurrence of the phenomenon. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a method for analyzing the high-temperature gate bias performance changes of a p-type gate GaN HEMT device, so as to accurately simulate the physical process inside the device and reveal the performance changes of the device.

[0006] Technical solution: A method for analyzing the high temperature gate bias performance change of a p-type gate GaN HEMT device, comprising the following steps:

[0007] S1, based on the process structure parameters of a typical p-type gate GaN HEMT device, the device is modeled in two dimensions using software, and the two-dimensional model is meshed to form a meshed device structure that matches the device structure;

[0008] S2, using TCAD software to simulate the electrical model of the gridded device structure and build a device electrical simulation model;

[0009] S3, setting the operating temperature of the device, and using the device electrical simulation model to simulate the influence of different operating temperatures on the electrical characteristics of the device;

[0010] S4, selecting an appropriate simulation operating temperature and setting an electrode bias voltage according to the operating conditions of the device;

[0011] S5, selecting the physical model required for TCAD software simulation;

[0012] S6, adding the time model and setting different HTGB stress times;

[0013] S7, electrical characteristics simulation of the device after different HTGB stress times;

[0014] S8, obtaining the variation of the defect density, charge concentration and carrier concentration inside the device at each time point over time;

[0015] S9, under different HTGB stress times, the device electrical characteristics and internal microscopic physical quantities are compared, the device performance degradation mechanism is analyzed, and its reliability is evaluated.

[0016] Furthermore, when meshing the two-dimensional model, the step size near the 2DEG region is 0.01 μm, and the step size of the remaining regions is 0.1 μm to 0.5 μm.

[0017] Furthermore, in step S5, the required physical models include polarization charge model, lattice heating model, trap and interface state model, carrier generation and recombination model, collision ionization model, mobility model and defect dynamic model; after introducing the lattice heating model, it is necessary to define the position of thermal contact and thermal conductivity.

[0018] Further, in step S6, different HTGB stress times are set, and after each HTGB stress time, a physical quantity distribution file inside the device is output; wherein the time calculation step is adjusted as the HTGB stress time changes, and must be less than the HTGB stress time.

[0019] Compared with the prior art, the present invention has the following significant effects:

[0020] 1. The present invention uses TCAD simulation to construct a device HTGB degradation model, which can accurately simulate the physical processes inside the device, such as current transmission, carrier movement and defect evolution, etc., which helps researchers to reveal the internal mechanism of device performance changes (such as threshold voltage drift, leakage current change), improve device structural parameters with high model accuracy, and optimize device electrical characteristics; on the other hand, TCAD simulation does not need to rely on physical samples, nor does it require a large number of experiments and tests, which can significantly reduce testing costs and time, meeting its urgent needs in the semiconductor industry;

[0021] 2. By introducing the time model, the present invention can dynamically observe the evolution of physical quantities such as the internal trap charge concentration, carrier concentration, and defect density of the device after HTGB over time. This process more intuitively demonstrates the impact mechanism of HTGB on device performance degradation. Finally, by combining the changes of various microscopic physical quantities inside the device with the changes of the device electrical curve over time, the change trend of device performance over time can be evaluated. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a flow chart of the present invention;

[0023] Figure 2 (a) is a schematic diagram of the unit structure of the HEMT device, and (b) is a cell structure diagram used in the simulation;

[0024] Figure 3 (a) is the transfer characteristic diagram of the HEMT device, and (b) is the output and breakdown characteristic diagram of the HEMT device;

[0025] Figure 4 (a) is a schematic diagram of the effect of operating temperature on transfer characteristics, and (b) is a schematic diagram of the effect of operating temperature on output characteristics;

[0026] Figure 5 (a) is the effect of different HTGB stress time on the device transfer characteristics, (b) is a local enlarged view of A; (c) is the effect of different HTGB stress time on the device threshold voltage;

[0027] Figure 6 Schematic diagram of the effect of different HTGB stress time on the acceptor defect ionization density inside the device, where (a) is t = 1×10 0 s, (b) is t = 1 × 10 2 s, (c) is t = 1 × 10 5 s moment, (d) is a comparison of the acceptor defect ionization density in the channel region at different HTGB stress times;

[0028] Figure 7Schematic diagram of the effect of different HTGB stress time on the electron concentration inside the device, where (a) is t = 1×10 0 s, (b) is t = 1 × 10 2 s, (c) is t = 1 × 10 5 s moment, (d) is the comparison of electron concentration in the channel region at different HTGB stress times;

[0029] Figure 8 The influence of different HTGB stress time on the charge concentration inside the device, where (a) is t = 1×10 0 s, (b) is t = 1 × 10 2 s, (c) is t = 1 × 10 5 s, (d) is a comparison of the charge concentration in the channel region at different HTGB stress times. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0031] like Figure 1 As shown, the present invention proposes a method for simulating and analyzing the performance change of a p-type gate GaN HEMT device HTGB, comprising the following steps:

[0032] Step 1: Based on the process structure parameters of a typical p-type gate GaN HEMT device, the device is modeled in two dimensions using software, and the two-dimensional model is meshed to form a meshed device structure that matches the device structure;

[0033] Figure 2 The figure shows the structure of an enhancement mode p-type gate GaN HEMT device. Figure 2 (a) is a schematic diagram of the p-type gate GaN HEMT device unit structure, which includes a 2μm thick GaN buffer layer, a 200nm thick GaN channel layer, a 15nm thick AlGaN barrier layer (Al component is 20%), and a 200nm thick Si3N4 passivation layer. There is a 70nm thick p-type GaN layer between the gate and the AlGaN barrier layer to realize an enhancement mode device. The hole doping concentration in the p-type GaN layer is 2×10 17 cm -3 The gate length is 2μm, the distance between the gate and the source is 2μm, and the distance between the gate and the drain is 6μm. Figure 2(b) is a schematic diagram of the cell structure used when simulating a p-type gate GaN HEMT device. According to the design and process parameters of the p-type gate GaN HEMT device, the GaN HEMT device is modeled in two dimensions using a semiconductor device modeling tool, and then the model is meshed (the specific process is: the 2DEG (two dimensional electron gas) area that has a greater impact on electrical parameters is finely meshed with a step size of 0.01μm or even lower, and the rest of the area is meshed with a step size of 0.1μm-0.5μm), and a gridded device structure is generated to ensure that the grid structure matches the device structure.

[0034] Step 2, using TCAD software to perform electrical model simulation on the gridded device structure to build a device electrical simulation model;

[0035] The grid device structure of the p-type gate GaN HEMT device is electrically simulated using TCAD (Technology Computer Aided Design, referring to semiconductor process simulation and device simulation tools) software, and the SRH (Shockley-Read-Hall) composite model, Auger composite model, and Fermi-Dirac carrier statistical model are introduced to obtain the drain voltage V DS =0.5V when the transfer characteristic curve and gate voltage V GS The output characteristic curves at 1V, 3V, and 5V are respectively, and then the electrical simulation results of the device are compared with the electrical parameters or curves measured in the experiment, and the key process parameters such as the size and concentration of each area of ​​the device are optimized and calibrated, so that the electrical simulation results are finally consistent with those measured in the experiment; the specific steps of optimization and calibration are: the size and doping concentration of each area of ​​the device are changed in a variable manner, and the amplitude of the change of the simulation curve is used to judge whether the effect of the parameter on the device characteristics is relatively large, and the parameters with significant influence are found as the preferred variables for optimization, and then these variables are adjusted to achieve simple and efficient optimization and calibration of the simulation results.

[0036] Figure 3 The figure shows the electrical characteristic curve obtained after electrical optimization of the device structure, where: Figure 3 (a) is a transfer characteristic curve obtained by simulating the electrical characteristics of a p-type gate GaN HEMT device. The threshold voltage V TH About 1.8V; Figure 3 (b) shows the output characteristics and breakdown characteristic curves of the p-type gate GaN HEMT device. The maximum withstand voltage value of the simulated device structure model is 650V, which is consistent with the withstand voltage value provided in the product manual.

[0037] Step 3, setting the operating temperature of the device, and using the device electrical simulation model to simulate the impact of different operating temperatures on the electrical characteristics of the device;

[0038] Since the device may work at different ambient temperatures during application, in this embodiment, it is first necessary to study the effect of high temperature environment on the electrical performance of the device when the gate of the device is not powered. Therefore, based on the device electrical simulation model optimized in step 2, different operating temperatures are set to simulate the effect of various ambient temperatures on the electrical characteristics of the device. Figure 4 The transfer characteristics and output characteristics of the device at 300K, 350K and 400K are shown. Figure 4 It can be seen from the figure that the saturation leakage current of the device decreases significantly with the increase of temperature, and the simulation results are basically consistent with the theoretical expectations. Figure 4 As shown in (a), the transfer characteristic curve of the device moves downward as the temperature increases, and the threshold voltage V TH It decreases slightly with increasing temperature; Figure 4 As shown in (b), when V GS =3V, the saturation I of p-type gate GaN HEMT device at 300K D The saturation leakage current is 7.83A at 400K, and drops to about 3.70A at 400K, less than half of that at 300K. The reason for this phenomenon is that the increase in the operating temperature of the device leads to intensified atomic vibrations in the lattice, which in turn generates more phonons. These phonons scatter with carriers, increasing the scattering probability, causing the carriers to be scattered frequently during movement, thereby reducing their mean free path and ultimately leading to a decrease in mobility. The saturation leakage current is caused by the flow of carriers from the source to the drain. When the mobility of the carriers decreases, at the same bias voltage, the overall mobility of the carriers decreases, reducing the carrier injection at the drain, resulting in a decrease in the saturation leakage current.

[0039] Step 4, according to the working conditions of the device, select the appropriate simulation working temperature and set the electrode bias voltage;

[0040] After determining the effect of operating temperature on the electrical performance of the device, it is necessary to select appropriate simulation operating temperature and device bias voltage to perform HTGB simulation modeling. In this embodiment, the ambient temperature selected is 400K, the drain voltage V D With source voltage V S Set to 0V. According to the device gate rated voltage value provided in the product manual is 5V, the gate voltage V G Set to 5V.

[0041] Step 5, select the physical model required for TCAD software simulation;

[0042] On the basis of step 4, when using TCAD software for HTGB simulation calculation, it is necessary to select a suitable physical model to ensure the accuracy and reliability of the simulation results. The physical models required for HTGB simulation include: polarization charge model, which is used to simulate the polarization effect between the GaN layer and the AlGaN layer of the device; lattice heating model, which is used to simulate the thermal behavior of the device under high temperature conditions; trap and interface state model, which is used to consider the influence of defects and interface states in semiconductor devices on current conduction; carrier generation and recombination model, which is used to describe the generation and recombination process of carriers, thereby affecting the electrical properties of the device; collision ionization model, which is used to carry the collision ionization phenomenon of carriers under high electric fields; mobility model, which is used to describe the mobility of carriers in materials; defect dynamic model, which is used to simulate the influence of the dynamic behavior of defects under different conditions on device performance. (In the simulation process, after introducing the lattice heating model, it is necessary to define the position of thermal contact and set the thermal conductivity to 2500W / K).

[0043] Step 6, add the time model and set different HTGB stress times;

[0044] In step 5, the physical model required for HTGB simulation is first defined. In this step, the time model is introduced to simulate the dynamic evolution of various physical quantities inside the device over time. This process will more intuitively reflect the impact of HTGB on the device performance degradation mechanism. In the simulation process, this implementation selects multiple HTGB stress time points, including 1×10 0 s, 1×10 2 s, 1×10 3 s, 1×10 4 s and 1×10 5 s, and output the device internal physical quantity distribution file after each HTGB stress time, so as to observe the changes of the device internal physical quantities. The time calculation step should be adjusted with the change of HTGB stress time (after defining the end time of high temperature bias stress, the calculation step of the defined time is generally 2-3 orders of magnitude smaller than that time point; for example, if the stress time is 100s, then the time calculation iteration step is generally 1s or less), and must be less than the HTGB stress time.

[0045] Step 7, performing electrical characteristic simulation on the devices obtained after different HTGB stress times, and comparing and analyzing the influence of different stress times on the electrical characteristics of the devices;

[0046] Next, the change of device threshold voltage under different HTGB time is measured, such as Figure 5 As shown in (a), the results show that as the HTGB time increases, the threshold voltage of the device gradually increases, while the saturation drain current (I D ) is gradually reduced. Figure 5As can be seen from (b), the change in threshold voltage is 1 mV at 1 s, and when it reaches 1×10 5 This result indicates that HTGB can cause significant changes in the threshold voltage and saturation leakage current of p-gate GaN HEMT devices, and that an increase in HTGB time may exacerbate this effect.

[0047] Step 8, obtaining the change of defect density, charge concentration and carrier concentration inside the device at each time point over time;

[0048] In order to explain the reasons for the change in the electrical characteristics of the p-type gate GaN HEMT device, this embodiment compares different gate bias stress times (1s, 10 0 s, 1×10 5 s) The impact on the acceptor defect ionization density, electron concentration and charge concentration inside the device, such as Figure 6 , Figure 7 and Figure 8 Specifically, Figure 6 As shown in Figure 1, under the action of long-term high temperature and high electric field, the thermal energy in the material increases, causing more defects or impurity atoms to be excited. As time goes by, the degree of thermal ionization of the acceptor defect gradually increases, resulting in an increase in the ionization density, as shown in Figure 1. Figure 6 As shown in (d) in Figure 7 As shown in Figure 2, the increase in the number of acceptor defects means that more ionized acceptors can bind free electrons, resulting in a gradual decrease in the free electron concentration over time. Figure 7 As shown in (d) in the figure, this is because the acceptor defects consume these electrons by combining with free electrons.

[0049] In addition, if Figure 8 As shown in the figure, due to the positive voltage applied to the gate of the device, more electrons drift to the p-GaN region under the action of the electric field and are captured by the traps in this region, forming negatively charged charges. As the stress time increases, the charge concentration in this region also gradually increases, as shown in the figure below. Figure 8 These results further verify the mechanism of the impact of HTGB process on the performance of power semiconductor devices.

[0050] Step 9, under different HTGB stress times, compare the device electrical characteristics and internal microscopic physical quantities, analyze the device performance degradation mechanism, and evaluate its reliability;

[0051] The change in threshold voltage after different HTGB stress times in step 7 is consistent with the change trend of the internal microscopic parameters of the device observed in step 8. Specifically, the reduction in electron concentration in the channel region of the p-gate GaN HEMT device directly affects the conductivity and current flow ability of the device, resulting in an increase in the threshold voltage. On the other hand, the accumulation of negative charges in the p-GaN region reduces the potential of the channel region under the gate, which means that the device needs to apply a higher gate voltage to reach the on state, thereby increasing the threshold voltage.

Claims

1. A method for analyzing high temperature gate bias performance changes of a p-type gate GaN HEMT device, characterized in that: The steps include: S1, based on the process structure parameters of a typical p-type gate GaN HEMT device, the device is modeled in two dimensions using software, and the two-dimensional model is meshed to form a meshed device structure that matches the device structure; S2, using TCAD software to simulate the electrical model of the gridded device structure and build a device electrical simulation model; S3, setting the operating temperature of the device, and using the device electrical simulation model to simulate the influence of different operating temperatures on the electrical characteristics of the device; S4, selecting an appropriate simulation operating temperature and setting an electrode bias voltage according to the operating conditions of the device; S5, selecting the physical model required for TCAD software simulation; S6, adding the time model and setting different HTGB stress times; S7, electrical characteristics simulation of the device after different HTGB stress times; S8, obtaining the variation of the defect density, charge concentration and carrier concentration inside the device at each time point over time; S9, under different HTGB stress times, the device electrical characteristics and internal microscopic physical quantities are compared, the device performance degradation mechanism is analyzed, and its reliability is evaluated.

2. The method for analyzing high temperature gate bias performance changes of a p-type gate GaN HEMT device according to claim 1, characterized in that: When meshing the two-dimensional model, the step size near the 2DEG region is 0.01 μm, and the step size in the remaining regions is 0.1 μm to 0.5 μm.

3. The method for analyzing high temperature gate bias performance changes of a p-type gate GaN HEMT device according to claim 1, characterized in that: In step S5, the required physical models include polarization charge model, lattice heating model, trap and interface state model, carrier generation and recombination model, collision ionization model, mobility model and defect dynamic model; after introducing the lattice heating model, it is necessary to define the position of thermal contact and thermal conductivity.

4. The method for analyzing high temperature gate bias performance changes of a p-type gate GaN HEMT device according to claim 1, characterized in that: In step S6, different HTGB stress times are set, and after each HTGB stress time, the device internal physical quantity distribution file is output; wherein the time calculation step is adjusted with the change of the HTGB stress time and must be less than the HTGB stress time.

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