Time-dependent breakdown SPICE circuit model and construction and verification method and application thereof

Abstract

The embodiment of the invention relates to the technical field of packaging interconnection reliability analysis, and provides a time-dependent breakdown SPICE circuit model and a construction and verification method and application thereof. According to the embodiment of the invention, the metal conductive filament compact model is adopted to explain related physical phenomena, the SPICE equivalent circuit model is constructed in combination with the resistance degradation model used for describing the resistance degradation phenomenon, the TDDB effect is converted into the change of circuit parameters, the dynamic degradation process of the dielectric layer under the electric field stress is effectively described, and the performance of the dielectric layer is improved. According to the method, device life prediction and modeling of the current and resistance degradation process are achieved, the calculation process is greatly simplified, meanwhile, a process tolerance model used for describing process uncertainty is introduced to construct a time-dependent breakdown SPICE circuit model, calculation efficiency is improved, high modeling precision is kept, the method has remarkable engineering application potential, and the method is suitable for popularization and application. Potential risks can be identified in the evaluation design stage of the dielectric breakdown effect, and the reliability is remarkably improved through optimization design.

Description

Technical Field

[0001] The present disclosure relates to the technical field of package interconnect reliability analysis, and in particular to a time-destruction SPICE circuit model and a construction, verification method and application thereof. Background Art

[0002] With the rapid development of miniaturization of integrated circuit technology and three-dimensional stacking integration technology, the reliability problem of advanced interconnection structures under high-density integration has become increasingly prominent, and the time-dependent dielectric breakdown (TDDB) phenomenon has become a key factor affecting the degradation and failure of interconnection performance. Among them, TDDB refers to the gradual migration of atoms or molecules in dielectric materials under long-term electric field stress to form a conductive path, which leads to an increase in leakage current and ultimately causes dielectric breakdown (Breakdown, BD). The occurrence of BD will cause a sudden change in the electrical properties of the material and cause circuit failure.

[0003] At present, TDDB research mainly focuses on the failure mechanism and model of the dielectric layer, and proposes physical models, statistical models, and empirical models for the TDDB phenomenon. Common models include E, 1 / E, E based on electric field and current. 1 / 2 Models, power law models, fatigue damage models, etc., most of these models focus on qualitatively describing the long-term behavior of dielectric material failure, and cannot fully consider the interaction of multiple influencing factors in complex circuit environments. However, existing models are mainly based on the description of macroscopic physical phenomena or empirical data, lacking a systematic analysis of dielectric failure in circuit systems, especially the performance and impact of TDDB effect at the circuit level, which has not been studied in depth. Summary of the invention

[0004] The present disclosure aims to solve at least one of the problems existing in the prior art and to provide a time-destruction SPICE circuit model and a construction, verification method and application thereof.

[0005] In one aspect of the present disclosure, a method for constructing a time-destruction SPICE circuit model is provided, the method comprising: The compact model of metal conductive filaments and the resistance degradation model are combined into a SPICE equivalent circuit model; The process tolerance model is added to the SPICE equivalent circuit model to obtain a time-dependent breakdown SPICE circuit model.

[0006] Optionally, after a forward voltage is applied to the active electrode of the metal conductive filament compact model, the change in the number of metal atoms in the longitudinal direction in the conductive channel of the metal conductive filament compact model is expressed as: ; After a forward voltage is applied to the active electrode of the metal conductive filament compact model, the change in the number of metal atoms in the lateral direction in the conductive channel of the metal conductive filament compact model is expressed as: ; in, It represents the change of the conductive channel in the longitudinal direction caused by the drift of metal ions, and its value range is [0, 1]; It represents the lateral change of the conductive channel caused by the drift of metal ions, and its value range is [0, 1]; represents the amount of metal ion drift and , represents the drift velocity of metal ions, Indicates the concentration of metal elements; represents the bottom diameter of the conductive channel of the compact model of the metal conductive filament; Indicates time; represents the longitudinal length of the conductive path and ; Represents the length of the conductive filament at time t.

[0007] Optionally, after a forward voltage is applied to the active electrode of the metal conductive filament compact model, the change results of the conductive filaments in the metal conductive filament compact model in the transverse and longitudinal directions are respectively expressed as: ; ; in, represents the resonant frequency; It represents the effective transition distance of ions; represents the potential barrier height; represents the Boltzmann constant; Indicates temperature correction; Indicates temperature; represents the field acceleration factor; represents the applied voltage and ; Indicates the electric field strength; represents the thickness of the dielectric layer in the compact model of the metal conductive filament; represents an intermediate variable and ; Indicates the number of charged ions; Indicates electric charge; Represents the diameter of the conductive filament at time t.

[0008] Optionally, the resistance degradation model in the initial state is It is expressed as: ; in, represents the resistivity of the dielectric layer in the compact model of the metal conductive filament; represents the area of ​​the dielectric layer in the compact model of the metal conductive filament and .

[0009] Optionally, the resistance degradation model is the resistance of the dielectric layer in the metal conductive filament compact model during the degradation process. It is expressed as: ; in, It represents the resistivity of the dielectric layer in the compact model of the metal conductive filaments after the conductive channel in the compact model of the metal conductive filaments is formed.

[0010] Optionally, the resistance degradation model is the resistance at the end of the dielectric layer performance degradation in the metal conductive filament compact model. It is expressed as: ; in, represents the top cross-sectional radius of the conductive channel of the compact model of the metal conductive filament; represents the bottom cross-sectional radius of the conductive channel of the compact metal conductive filament model.

[0011] Optionally, the process tolerance model is expressed as: ; in, represents the power spectrum of the Gaussian autocorrelation function; represents the wave vector and ; represents an imaginary unit; Represents the total number of material structural units into which the dielectric layer in the compact model of metal conductive filaments is divided; Indicates the distance between the upper and lower material structural units in the dielectric layer; Indicates the length of the roughness profile of the line edge; Represents the RMS amplitude of the line edge roughness profile.

[0012] Another aspect of the present disclosure provides a time-dependent breakdown SPICE circuit model, wherein the time-dependent breakdown SPICE circuit model is constructed using the method for constructing the time-dependent breakdown SPICE circuit model described above.

[0013] Another aspect of the present disclosure provides a verification method for a time-destruction SPICE circuit model, the verification method comprising: Conducting experiments on the time-dependent breakdown effect of the gate oxide layer and / or the time-dependent breakdown effect of the TSV blind hole to obtain corresponding gate oxide layer experimental data and / or TSV blind hole experimental data; and / or, conducting simulation on the breakdown effect of the dielectric layer on the surface of chemical mechanical polishing to obtain corresponding simulation data; The time-dependent breakdown SPICE circuit model described above is used to characterize the time-dependent breakdown effect of the gate oxide layer and / or the time-dependent breakdown effect of the TSV blind hole under corresponding experimental conditions, and the corresponding gate oxide layer model simulation data and / or TSV blind hole model simulation data are obtained; and / or, the time-dependent breakdown SPICE circuit model described above is used to characterize the breakdown effect of the dielectric layer on the chemical mechanical polishing surface under corresponding simulation conditions, and the corresponding chemical mechanical polishing surface model simulation data are obtained; Comparing the gate oxide layer experimental data with the gate oxide layer model simulation data, and / or comparing the TSV blind hole experimental data with the TSV blind hole model simulation data, and / or comparing the simulation data with the chemical mechanical polishing surface model simulation data; The time-destruction SPICE circuit model is verified according to the comparison results.

[0014] Another aspect of the present disclosure provides an application of a time-destruction SPICE circuit model, in which the time-destruction SPICE circuit model described above is applied to an equivalent circuit model of a power distribution network and / or through silicon vias to simulate degradation effects of a circuit system.

[0015] Compared with the prior art, the present invention adopts a compact model of metal conductive filaments to explain relevant physical phenomena, and constructs a SPICE equivalent circuit model in combination with a resistance degradation model used to describe resistance degradation phenomena, thereby converting the TDDB effect into changes in circuit parameters, effectively describing the dynamic degradation process of the dielectric layer under electric field stress, and realizing the modeling of device life prediction, current and resistance degradation process, greatly simplifying the calculation process, and introducing a process tolerance model used to describe process uncertainty to construct a time-dependent breakdown SPICE circuit model, which not only improves the calculation efficiency, but also maintains a high modeling accuracy, has significant engineering application potential, can identify potential risks in the evaluation and design stage of the dielectric breakdown effect, and significantly improve its reliability through optimized design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0017] Figure 1A flowchart of a method for constructing a time-destruction SPICE circuit model provided in one embodiment of the present disclosure; Figure 2 A schematic diagram of a compact model of a metal conductive filament provided for another embodiment of the present disclosure; Figure 3 A circuit diagram corresponding to a SPICE equivalent circuit model provided in another embodiment of the present disclosure; Figure 4 Gaussian ACF and LER randomly generated LER profile provided by another embodiment of the present disclosure; Figure 5 A schematic diagram of the TDDB effect of a gate oxide layer provided in another embodiment of the present disclosure; Figure 6 A comparison diagram of simulation results and experimental data of a SPICE circuit model of a gate oxide layer provided in another embodiment of the present disclosure; Figure 7 A comparison diagram of simulation results and experimental data of a SPICE circuit model of a TSV blind via provided in another embodiment of the present disclosure; Figure 8 A schematic diagram of an advanced interconnection on a low dielectric constant substrate and related TDDB effect provided by another embodiment of the present disclosure; Fig. 9 A CMP surface life comparison diagram provided for another embodiment of the present disclosure; Fig.10 A schematic diagram of an equivalent circuit of a 2×2 configured PDN and its unit structure provided in another embodiment of the present disclosure; Fig.11 A schematic diagram of PDN impedance comparison provided by another embodiment of the present disclosure; Fig.12 A schematic diagram comparing the lifespans of PDNs with different dielectric layer thicknesses provided in another embodiment of the present disclosure; Fig.13 A schematic diagram of relative errors between simulation results of a TDDB SPICE model and numerical simulation results provided by another embodiment of the present disclosure; Fig.14 A schematic diagram of the change of PDN impedance over time provided by another embodiment of the present disclosure; Fig.15 A schematic diagram of a signal-ground TSV and an equivalent circuit model corresponding to another embodiment of the present disclosure; Fig.16 A comparison diagram of simulation results of a TDDB SPICE model of TSV and simulation results of a numerical model provided in another embodiment of the present disclosure; Fig.17A comparison diagram of life prediction of TSVs with different dielectric layer thicknesses provided in another embodiment of the present disclosure; Fig.18 A comparison diagram of S parameters at different conductivity change rates provided by another embodiment of the present disclosure; Fig.19 A comparison diagram of S parameters at different frequencies provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. However, it can be understood by those skilled in the art that in each embodiment of the present disclosure, many technical details are proposed in order to enable readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed for protection in the present disclosure can also be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined and referenced with each other without contradiction.

[0019] One embodiment of the present disclosure relates to a method for constructing a time-destruction SPICE circuit model, the process of which is as follows: Figure 1 As shown, it includes step S110 and step S120.

[0020] Step S110, combining the metal conductive filament compact model and the resistance degradation model into a SPICE equivalent circuit model.

[0021] Specifically, SPICE (Simulation Program with Integrated Circuit Emphasis) is a language simulator software used for circuit description and simulation, used to detect the integrity of circuit connections and functions, and used to predict circuit behavior. The SPICE equivalent circuit model is a model used to comprehensively describe the compact model of metal conductive filaments and the resistance degradation model in SPICE software.

[0022] Among them, the compact metal conductive filament model is a model used to describe the behavior of metal conductive filaments. When an external electric field is applied to a dielectric material, the metal atoms in the dielectric material are driven by the electric field. Under the action of the electric field force, they gradually gather along a specific path and form a thin and long conductive channel connecting two electrodes, namely a metal conductive filament (CF). With the formation of metal conductive filaments, the conductivity characteristics of the dielectric material change significantly, the resistance of the dielectric layer decreases significantly, and it presents a low resistance state, triggering a series of electrochemical reactions and physical changes. The compact metal conductive filament model simulates the change of the conductivity characteristics of the dielectric material.

[0023] As the metal conductive filaments in the dielectric material gradually grow, the conductivity of the dielectric material will gradually increase, thereby enhancing the concentration and mobility of metal atoms in the dielectric material, causing the resistance of the dielectric material to gradually decrease. The resistance degradation model simulates this resistance change process of the dielectric material.

[0024] For example, Figure 2 A schematic diagram of the compact model of a metal conductive filament is shown, with a detailed description of the thickness of The growth process of metal conductive filaments, namely metal CF, in the dielectric layer. The upper and lower electrodes of the dielectric layer are the anode and cathode respectively, and the other end of the cathode is connected to the ground terminal (GND). Among them, the material of the anode is metal, and the material of the cathode is metal or semiconductor. In the initial state, the forward voltage applied to the active electrode of the dielectric layer, namely the anode, is In the off state, there are no defects in the dielectric layer and no metal atoms move inside the dielectric layer. In the intermediate state, the forward voltage applied to the anode of the dielectric layer In the on state, an electrochemical reaction occurs at the interface between the anode and the dielectric layer, showing that metal atoms Losing electrons To metal ions Right now , then, the metal ions Under the action of the electric field, it migrates toward the inert electrode, the cathode, and captures electrons near the cathode. Reduction reaction occurs to metal atoms Right now , and finally, the metal atoms Gradually gathered in the dielectric layer, forming a The conductive channel is composed of two stages. In the first stage, a thin conductive filament is formed in the longitudinal direction. In the second stage, the conductive filament continues to grow in the transverse direction, and finally forms a cone-shaped conductive channel between the upper and lower electrodes, namely the anode and the cathode. The conductive channel is the final metal conductive filament, namely the metal CF. After the metal CF is formed, the dielectric layer is in a conductive state.

[0025] Longitudinal length of the conductive path and bottom diameter As an internal state variable, it can be used to describe the changes of the conductive filaments in the compact model of metal conductive filaments in the longitudinal and transverse directions.

[0026] After a positive voltage is applied to the active electrode of the metal conductive filament compact model, the change in the number of metal atoms in the longitudinal direction of the conductive channel of the metal conductive filament compact model is expressed as: .

[0027] After a positive voltage is applied to the active electrode of the metal conductive filament compact model, the metal ions drift into the conductive channel, causing the lateral number of metal atoms in the conductive channel to change. At this time, the lateral change in the number of metal atoms in the conductive channel of the metal conductive filament compact model is expressed as: .

[0028] in, It represents the longitudinal change of the conductive channel caused by the drift of metal ions, and its value range is [0, 1]. It represents the lateral change of the conductive channel caused by the drift of metal ions, and its value range is [0, 1]. represents the amount of metal ion drift and ,in other words, It represents the number of metal ions per unit cross-sectional area that pass through a conductive channel per unit time. Represents the drift velocity of metal ions. Indicates the concentration of metal elements. Represents the bottom diameter of the conductive channel of a compact model of a metallic conductive filament. Indicates time. represents the longitudinal length of the conductive path and . Represents the length of the conductive filament at time t.

[0029] Exemplarily, after a forward voltage is applied to the active electrode of the metal conductive filament compact model, the changes in the conductive filaments in the metal conductive filament compact model in the transverse and longitudinal directions are respectively expressed as: ; .

[0030] in, Indicates the resonant frequency. Represents the effective transition distance of the ion. represents the potential barrier height. represents the Boltzmann constant. Indicates temperature correction. Indicates temperature. Represents the field acceleration factor. represents the applied voltage and . Indicates the electric field strength. Represents the thickness of the dielectric layer in the compact model of metal conductive filaments. represents an intermediate variable and . Indicates the number of charged ions. Represents electric charge. Represents the diameter of the conductive filament at time t.

[0031] For example, Figure 2 As shown, in the initial state, the forward voltage of the anode applied to the dielectric layer of the metal conductive filament compact model is In the off state, there is no movement of metal atoms inside the dielectric layer. At this time, the dielectric layer has excellent insulation performance, low dielectric loss and good transmission characteristics. Therefore, the resistance degradation model in the initial state is It is expressed as: .in, Represents the resistivity of the dielectric layer in the compact model of metal conductive filaments. represents the area of ​​the dielectric layer in the compact model of the metal conductive filament and .

[0032] For example, Figure 2 As shown in the figure, in the intermediate state, i.e., during the growth of the metal CF in the dielectric layer of the compact metal conductive filament model, under the influence of physical fields such as temperature and electric field, defects gradually appear in the dielectric layer and metal atoms migrate. With the continuous accumulation of metal atoms, the size of the metal CF gradually increases, and the resistance, isolation and other properties of the dielectric layer begin to gradually decrease. During the degradation of the dielectric layer performance, the resistance of the dielectric layer is determined by the size of the metal CF. Therefore, the resistance degradation model is the resistance degradation model of the dielectric layer in the compact metal conductive filament model during the degradation of the dielectric layer performance. It is expressed as: .in, It represents the resistivity of the dielectric layer in the metal conductive filament compact model after the conductive channel is formed in the metal conductive filament compact model. In the process of dielectric layer performance degradation, the circuit diagram corresponding to the SPICE equivalent circuit model is as follows Figure 3 shown.

[0033] For example, Figure 2 As shown in the figure, after the dielectric layer of the metal conductive filament compact model has been used for a long time or exposed to an extreme physical field, the metal CF in the dielectric layer is completely formed, and the metal CF electrically connects the anode and the cathode, and the dielectric layer is in a conductive state. At this time, the resistance of the dielectric layer is also determined by the metal CF. Therefore, the resistance degradation model is the resistance at the end of the dielectric layer performance degradation in the metal conductive filament compact model. It is expressed as: .in, The top cross-sectional radius of the conductive channel representing the compact model of the metallic conductive filament. The bottom cross-sectional radius of the conductive channel representing the compact model of the metallic conductive filament.

[0034] Step S120 , adding the process tolerance model to the SPICE equivalent circuit model to obtain a time-dependent breakdown SPICE circuit model.

[0035] Specifically, process structure uncertainty will have a certain impact on the TDDB phenomenon. Therefore, the process tolerance model can use the process tolerance power spectrum density function to characterize the impact of process uncertainty.

[0036] For example, changes in line edge roughness (LER) and line-to-line (L2L) spacing are important factors affecting the performance of nanoscale devices and interconnects, especially in TDDB, which can cause significant performance degradation and reliability issues. Therefore, in order to effectively quantify and evaluate the impact of LER on TDDB reliability, this embodiment develops a Fourier synthesis method based on the power spectral density (PSD) of the Gaussian autocorrelation function (ACF) to simulate and generate LER characteristic curves. In this Fourier synthesis method, the material structure is subdivided into N discrete micro-units, and a random phase is introduced for each unit to ensure the randomness of the simulation and the actual matching. The LER amplitude generated by the random phase is constrained by the power spectral density of the Gaussian ACF to ensure that it conforms to the statistical distribution characteristics of experimental observations. The process tolerance model is used to characterize and model the LER characteristics, and the process tolerance model can be expressed as: .

[0037] in, Represents the power spectrum of the Gaussian autocorrelation function. represents the wave vector and . Represents an imaginary unit. Represents the total number of material structural units into which the dielectric layer in the compact model of metal conductive filaments is divided. Indicates the distance between the upper and lower material structural units in the dielectric layer, and its value should be much smaller than To ensure a reasonable discretization resolution. Indicates the length of the line edge roughness profile. Represents the RMS amplitude of the line edge roughness profile.

[0038] For example, The value range of is usually 20nm to 50nm. =30nm, dx=0.5nm, then the value of dx is much smaller than . Figure 4 It shows that the ideal process thickness of the dielectric layer is 50nm. The Gaussian ACF and LER profiles randomly generated by LER at 0, 0.5, and 2.5 respectively. The x-axis represents the length of the dielectric layer, and the y-axis represents the height of the dielectric layer.

[0039] Compared with the prior art, the method for constructing a time-dependent breakdown SPICE circuit model provided in the embodiments of the present disclosure adopts a compact model of metal conductive filaments to explain relevant physical phenomena, and constructs a SPICE equivalent circuit model in combination with a resistance degradation model used to describe resistance degradation phenomena, thereby converting the TDDB effect into changes in circuit parameters, effectively describing the dynamic degradation process of the dielectric layer under electric field stress, and realizing device life prediction, modeling of current and resistance degradation processes, greatly simplifying the calculation process, and introducing a process tolerance model used to describe process uncertainty to construct a time-dependent breakdown SPICE circuit model, which not only improves the calculation efficiency, but also maintains a high modeling accuracy, has significant engineering application potential, can identify potential risks in the evaluation and design stage of the dielectric breakdown effect, and significantly improve its reliability through optimized design.

[0040] Another embodiment of the present disclosure relates to a time-breakdown SPICE circuit model, which is constructed using the method for constructing a time-breakdown SPICE circuit model described in the above embodiment.

[0041] Compared with the prior art, the time-dependent breakdown SPICE circuit model provided in the embodiments of the present invention adopts a compact model of metal conductive filaments to explain relevant physical phenomena, and combines it with a resistance degradation model used to describe resistance degradation phenomena. The TDDB effect is converted into changes in circuit parameters through a SPICE equivalent circuit model, which effectively describes the dynamic degradation process of the dielectric layer under electric field stress, realizes device life prediction, and modeling of current and resistance degradation processes, greatly simplifies the calculation process, and introduces a process tolerance model used to describe process uncertainty, which not only improves the calculation efficiency, but also maintains a high modeling accuracy. It has significant engineering application potential, can identify potential risks in the evaluation and design stage of dielectric breakdown effects, and significantly improve its reliability through optimized design.

[0042] Another embodiment of the present disclosure relates to a verification method of a time-destruction SPICE circuit model, including: conducting experiments on the time-destruction effect of the gate oxide layer and the time-destruction effect of the TSV blind hole to obtain corresponding gate oxide experimental data and TSV blind hole experimental data. Simulating the breakdown effect of the dielectric layer on the surface of the chemical mechanical polishing (CMP) to obtain corresponding simulation data. Using the time-destruction SPICE circuit model recorded in the above text to characterize the time-destruction effect of the gate oxide layer and the time-destruction effect of the TSV blind hole under the corresponding experimental conditions, the corresponding gate oxide model simulation data and TSV blind hole model simulation data are obtained. Using the time-destruction SPICE circuit model recorded in the above text to characterize the breakdown effect of the dielectric layer on the surface of the chemical mechanical polishing under the corresponding simulation conditions, the corresponding chemical mechanical polishing surface model simulation data is obtained. The gate oxide experimental data is compared with the gate oxide model simulation data, the TSV blind hole experimental data is compared with the TSV blind hole model simulation data, and the simulation data is compared with the chemical mechanical polishing surface model simulation data. The time-destruction SPICE circuit model is verified based on the comparison results.

[0043] The time-destruction SPICE circuit model is verified by using the time-destruction effect of the gate oxide layer.

[0044] Combined Figure 5, when the gate is biased, metal ions gradually migrate in the gate oxide layer. Over time, aging factors such as electric field, temperature and tunnel current cause the metal ions to gradually aggregate, resulting in local high current density. This high current density not only accelerates the gradual migration of metal ions, but also enhances the interaction between them. Finally, a low-resistance CF composed of metal atoms is formed in the gate oxide layer. The self-heating effect caused by the current flowing through the CF causes irreversible thermo-mechanical damage to the gate oxide layer, resulting in hard breakdown. In order to verify the accuracy and performance of the time-dependent breakdown SPICE circuit model, the time-dependent breakdown effect of the gate oxide layer was experimented under different temperature and voltage conditions to obtain the corresponding experimental results, and the time-dependent breakdown effect of the gate oxide layer was simulated using the time-dependent breakdown SPICE circuit model using the parameter values ​​listed in Table 1 to obtain the corresponding simulation results. The experimental data is compared with the simulation results of the time-dependent breakdown SPICE circuit model, and the comparison results are shown in Figure 6. Figure 6 In the figure, the SPICE model is used to refer to the simulation results of the time-breakdown SPICE circuit model, the voltage on the horizontal axis refers to the voltage used in the experimental process and the simulation process, and the life on the vertical axis refers to the life of the gate oxide layer under the corresponding voltage. The comparison results show that the time-breakdown SPICE circuit model has good consistency with the experimental data under the corresponding working environment, which proves the scalability and reliability of the time-breakdown SPICE circuit model.

[0045] Table 1 Parameter information of the time-dependent breakdown SPICE circuit model

[0046] The time-destruction SPICE circuit model is verified by using the time-destruction effect of TSV blind holes.

[0047] Under electrical stress conditions, leakage current will be stimulated in the silicon dioxide insulating layer, which will not only trigger the migration of copper ions in the insulating layer, but also cause copper atoms to gradually accumulate in the insulating layer. As time goes by, the concentration of copper atoms on the dielectric layer continues to accumulate, gradually forming an atomic migration channel. Once the concentration of copper atoms reaches a certain level, a metal conductive filament connecting the two TSVs will be formed. When the leakage current exceeds the breakdown threshold of the silicon dioxide insulating layer, instantaneous breakdown occurs. In order to evaluate the accuracy and performance of the time-dependent breakdown SPICE circuit model, experiments on the time-dependent breakdown effect of TSV blind holes were carried out under various stress conditions to obtain the corresponding experimental data, and the time-dependent breakdown SPICE circuit model was used to simulate the time-dependent breakdown effect of TSV blind holes under the corresponding stress conditions to obtain the corresponding simulation results. The experimental data are compared with the simulation results of the time-dependent breakdown SPICE circuit model. The comparison results are shown in Figure 2. Figure 7 shown. Figure 7In the figure, the SPICE model is used to refer to the simulation results of the time-breakdown SPICE circuit model, the excitation conditions on the horizontal axis refer to the excitation conditions used in the experimental process and the simulation process, and the life on the vertical axis refers to the life of the TSV blind hole under the corresponding excitation conditions. The comparison results show that the maximum relative error between the simulation data and the experimental data is less than 5%, which shows that the time-breakdown SPICE circuit model has high accuracy and reliability. In other words, the time-breakdown SPICE circuit model can characterize the TDDB mechanism in the TSV structure.

[0048] Next, the time-dependent breakdown SPICE circuit model is verified using CMP surface simulation data.

[0049] Over time, the accumulation of copper (Cu) atoms on the CMP surface causes its concentration to reach a certain threshold, forming a leakage current path, such as Figure 8 This leakage current path accelerates the degradation of the dielectric layer, especially the low dielectric constant dielectric layer (low-k dielectric layer), and eventually leads to dielectric breakdown, affecting the overall performance of the chip. The TDDB failure of the CMP surface is mainly attributed to the gradual accumulation of copper atoms on the surface of the dielectric layer, which causes its conductivity to increase over time, which can be described by the following formula: ; .

[0050] in, represents the conductivity between center i and center j. Indicates the initial center spacing. represents the distance between center i and center j, which is the localization radius of the electron at such center. represents the energy barrier between center i and center j. Represents thermal energy. represents the effective transition distance. C represents the normalized concentration. q represents the charge. E represents the electric field intensity. t represents the time. D represents the diffusion coefficient.

[0051] In order to verify the accuracy and effectiveness of the time-destruction SPICE circuit model, based on Figure 8 The CMP surface life was simulated and the corresponding simulation results were obtained. The time-dependent breakdown effect of the CMP surface was simulated using the time-dependent breakdown SPICE circuit model under the corresponding simulation conditions to obtain the corresponding model simulation results. The simulation results were compared with the model simulation results. Fig. 9 shown. Fig. 9 In this paper, SPICE model is used to refer to the simulation results of the time-destruction SPICE circuit model, and FEM model is used to refer to the simulation results based on Figure 8The comparison results show that the simulation results match the model simulation results well, which indicates that the time-destruction SPICE circuit model can predict the TDDB effect of CMP surface with high reliability and accuracy.

[0052] Compared with the prior art, the verification method of the time-breakdown SPICE circuit model provided in the embodiment of the present disclosure verifies the time-breakdown SPICE circuit model provided in the above embodiment, indicating that the time-breakdown SPICE circuit model can predict the TDDB effect of the gate oxide layer, TSV blind hole, and CMP surface with high reliability and high accuracy.

[0053] Another embodiment of the present disclosure relates to an application of a time-breakdown SPICE circuit model, in which the time-breakdown SPICE circuit model described above is applied to an equivalent circuit model of a power distribution network (PDN) and a through silicon via (TSV) to simulate the degradation effect of the circuit system.

[0054] The application of the time-breakdown SPICE circuit model to the power distribution network is described below.

[0055] A PDN equivalent circuit model is constructed, and the failure time of the time-destruction SPICE circuit model and the accuracy of the degradation of the PDN impedance during the simulated degradation process are verified through numerical simulation. Then, the change of the PDN impedance over time is evaluated.

[0056] Specifically, a mesh PDN is usually composed of a power layer and a ground layer. Fig.10 The circuit model of the unit structure of the mesh PDN consists of a resistor R, an inductor L, a capacitor C, and a conductor G. The 2×2 PDN is modeled, the corresponding PDN impedance is calculated according to the circuit model, and the PDN impedance corresponding to the 2×2 PDN is calculated using numerical simulation. The PDN impedance calculated using the circuit model is compared with the PDN impedance calculated using numerical simulation. The comparison results are shown in Figure 2. Fig.11 shown. Fig.11 In the figure, the SPICE model is used to refer to the PDN impedance calculated using the circuit model, and the HFSS model is used to refer to the PDN impedance calculated using numerical simulation. The comparison results show that the two sets of data match well in the [0, 20] GHz range. As the PDN works for a long time, the dielectric gradually degrades and eventually fails.

[0057] A time-dependent breakdown SPICE circuit model of a PDN with V=1V and T=363K, namely a TDDB SPICE model, is constructed. Fig.12The TDDB SPICE model predicted lifetime and the numerical model predicted lifetime corresponding to PDNs with different dielectric layer thicknesses are shown. Fig.12 In this article, SPICE refers to the corresponding data of the TDDB SPICE model, and FEM refers to the corresponding data of the numerical model. Fig.12 As can be seen from the figure, the two sets of data match well, indicating that the TDDB SPICE model can accurately characterize the TDDB effect of the grid PDN. Next, by embedding the developed TDDB SPICE model into the circuit model of the PDN, the TDDB SPICE circuit model of the PDN is obtained. Fig.10 As shown in Figure 1, this can be achieved by updating G in the circuit model of the PDN unit structure to the TDDB SPICE model. The simulation results of the TDDB SPICE model are compared with the results obtained by the numerical simulation model to verify the performance of the established TDDB SPICE model. Fig.13 As shown in the figure, the SPICE model is used to refer to the simulation results of the TDDB SPICE model, and the FEM model is used to refer to the results obtained by numerical simulation. It is observed that when the conductivity change rate G of the dielectric layer is in the range of 1 to 1000, the maximum relative error is no more than 2%. Finally, the TDDB SPICE model and numerical simulation are used to predict the degradation of PDN impedance over time. The change of PDN impedance over time is shown in Fig.14 shown. Fig.14 In FIG. 1 , the SPICE model is used to refer to the simulation results of the TDDB SPICE model, and the FEM model is used to refer to the results obtained by numerical simulation. It is observed that the simulation results of the TDDB SPICE model well characterize the decrease in PDN impedance.

[0058] The application of the time-dependent breakdown SPICE circuit model to through-silicon vias is described below.

[0059] A TSV equivalent circuit model is constructed, and the accuracy of the failure time of the time-dependent breakdown SPICE circuit model and the S-parameter degradation of TSV during the simulated degradation process is verified through numerical simulation. Then, the variation of the S-parameters of TSV over time is evaluated.

[0060] Specifically, the schematic diagram and equivalent circuit model corresponding to the signal-ground TSV are as follows: Fig.15 The left picture and Fig.15 As shown in the right figure in the figure. During long-term operation, ion migration will occur in the dielectric layer, forming a conductive path, causing the dielectric layer to gradually change from a closed state to an open state. Based on the construction method of the time-dependent breakdown SPICE circuit model provided in the above embodiment, the TDDB SPICE model of TSV is constructed, and the stresses such as the bias voltage and temperature of the TSV pair can be regarded as constants. Here, the operating conditions corresponding to the TSV are set to 2 volts and 473K The activation energy of the dielectric layer in the TDDB SPICE model is set to 1.42 eV, and the conductivity gradually increases from the initial value of 10 S / m to 200 S / m over time. The simulation results of the TDDB SPICE model of TSV are compared with those of the numerical model. Fig.16 shown. Fig.16 In the TDDB SPICE model, the SPICE model is used to refer to the simulation results of the TDDB SPICE model of TSV, and the FEM model is used to refer to the simulation results of the numerical model. It is observed that the two sets of data match well. Further, by combining the above TDDB SPICE model with the traditional TSV circuit model, the TDDB SPICE model corresponding to TSV can be obtained. For example, it can be obtained by Fig.15 G sub Replaced with TDDB SPICE model implementation. The TDDB SPICE model corresponding to TSV can not only characterize the real-time characteristics of TSV, but also predict its performance degradation over time. Fig.17 The TDDB SPICE model predicted lifetime and the numerical model predicted lifetime corresponding to TSVs with different dielectric layer thicknesses are shown. Fig.17 In this article, SPICE refers to the corresponding data of the TDDB SPICE model, and FEM refers to the corresponding data of the numerical model. Fig.17 As can be seen from the figure, the two sets of data match well, indicating that the TDDB SPICE model can accurately characterize the TDDB effect of TSV. Similarly, the accuracy of the TDDB SPICE model is first verified, and then its ability to predict overtime degradation is verified. Fig.18 As shown in Figure 1, the S parameters calculated by the TDDB SPICE model are compared with the S parameters obtained by the numerical model at different conductivity change rates. The comparison results show that there is a good consistency between the two sets of data. After that, the TDDB SPICE model is used to predict the overtime degradation phenomenon of the TSV pair. Fig.19 In the figure, the SPICE model is used to refer to the prediction results of the TDDBSPICE model, and the FEM model is used to refer to the results obtained by the numerical model. It is observed that the TDDB SPICE model can predict the degradation of TSV performance over time.

[0061] Compared with the prior art, the application of the time-destruction SPICE circuit model provided by the embodiments of the present disclosure can accurately simulate and highly accurately predict the degradation effects of the power distribution network and the circuit system of the silicon through via.

[0062] Those skilled in the art will appreciate that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for constructing a time-destructive SPICE circuit model, characterized in that: The construction method comprises: The compact model of metal conductive filaments and the resistance degradation model are combined into a SPICE equivalent circuit model; The process tolerance model is added to the SPICE equivalent circuit model to obtain a time-dependent breakdown SPICE circuit model.

2. The construction method according to claim 1, characterized in that: After a forward voltage is applied to the active electrode of the metal conductive filament compact model, the change in the number of metal atoms in the longitudinal direction in the conductive channel of the metal conductive filament compact model is expressed as: ； After a forward voltage is applied to the active electrode of the metal conductive filament compact model, the change in the number of metal atoms in the lateral direction in the conductive channel of the metal conductive filament compact model is expressed as: ； in, It represents the change of the conductive channel in the longitudinal direction caused by the drift of metal ions, and its value range is [0, 1]; It represents the lateral change of the conductive channel caused by the drift of metal ions, and its value range is [0, 1]; represents the amount of metal ion drift and , represents the drift velocity of metal ions, Indicates the concentration of metal elements; represents the bottom diameter of the conductive channel of the compact model of the metal conductive filament; Indicates time; represents the longitudinal length of the conductive path and ; Represents the length of the conductive filament at time t.

3. The construction method according to claim 2, characterized in that: After a forward voltage is applied to the active electrode of the metal conductive filament compact model, the changes of the conductive filaments in the metal conductive filament compact model in the transverse and longitudinal directions are respectively expressed as follows: ； ； in, represents the resonant frequency; It represents the effective transition distance of ions; represents the potential barrier height; represents the Boltzmann constant; Indicates temperature correction; Indicates temperature; represents the field acceleration factor; represents the applied voltage and ; Indicates the electric field strength; represents the thickness of the dielectric layer in the compact model of the metal conductive filament; represents an intermediate variable and ; Indicates the number of charged ions; Indicates electric charge; Represents the diameter of the conductive filament at time t.

4. The construction method according to claim 3, characterized in that: The resistance degradation model is the resistance in the initial state It is expressed as: ； in, represents the resistivity of the dielectric layer in the compact model of the metal conductive filament; represents the area of ​​the dielectric layer in the compact model of the metal conductive filament and .

5. The construction method according to claim 4, characterized in that: The resistance degradation model is the resistance of the dielectric layer in the metal conductive filament compact model during the degradation process. It is expressed as: ； in, It represents the resistivity of the dielectric layer in the compact model of the metal conductive filaments after the conductive channel in the compact model of the metal conductive filaments is formed.

6. The construction method according to claim 5, characterized in that: The resistance degradation model is the resistance at the end of the dielectric layer performance degradation in the metal conductive filament compact model. It is expressed as: ； in, represents the top cross-sectional radius of the conductive channel of the compact model of the metal conductive filament; represents the bottom cross-sectional radius of the conductive channel of the compact metal conductive filament model.

7. The construction method according to claim 6, characterized in that: The process tolerance model is expressed as: ； in, represents the power spectrum of the Gaussian autocorrelation function; represents the wave vector and ; represents an imaginary unit; Represents the total number of material structural units into which the dielectric layer in the compact model of metal conductive filaments is divided; Indicates the distance between the upper and lower material structural units in the dielectric layer; Indicates the length of the roughness profile of the line edge; Represents the RMS amplitude of the line edge roughness profile.

8. A time-dependent breakdown SPICE circuit model, characterized in that: The time-dependent breakdown SPICE circuit model is constructed by using the construction method described in any one of claims 1 to 7.

9. A method for verifying a time-destructive SPICE circuit model, characterized in that: The verification method comprises: Conducting experiments on the time-dependent breakdown effect of the gate oxide layer and / or the time-dependent breakdown effect of the TSV blind hole to obtain corresponding gate oxide layer experimental data and / or TSV blind hole experimental data; and / or, conducting simulation on the breakdown effect of the dielectric layer on the surface of chemical mechanical polishing to obtain corresponding simulation data; The time-dependent breakdown SPICE circuit model of claim 8 is used to characterize the time-dependent breakdown effect of the gate oxide layer and / or the time-dependent breakdown effect of the TSV blind hole under corresponding experimental conditions, and the corresponding gate oxide layer model simulation data and / or TSV blind hole model simulation data are obtained; and / or, the time-dependent breakdown SPICE circuit model of claim 8 is used to characterize the breakdown effect of the dielectric layer on the chemical mechanical polishing surface under corresponding simulation conditions, and the corresponding chemical mechanical polishing surface model simulation data are obtained; Comparing the gate oxide layer experimental data with the gate oxide layer model simulation data, and / or comparing the TSV blind hole experimental data with the TSV blind hole model simulation data, and / or comparing the simulation data with the chemical mechanical polishing surface model simulation data; The time-destruction SPICE circuit model is verified according to the comparison results.

10. An application of a time-breakdown SPICE circuit model, characterized in that: The time-destruction SPICE circuit model of claim 8 is applied to an equivalent circuit model of a power distribution network and / or a through silicon via to simulate the degradation effect of the circuit system.

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