Integrated circuit 3D packaging structure and packaging method thereof

Abstract

The invention discloses an integrated circuit 3D packaging structure and a packaging method thereof, and relates to the technical field of semiconductor packaging, and the packaging method comprises the following steps: obtaining the number of layers of an integrated circuit; according to the number of layers of the integrated circuit, dividing layout positions of modules to obtain a layout model of the integrated circuit; calculating the number of through silicon vias of a chip layer according to the layout model of the integrated circuit; connecting the modules through silicon through holes to obtain a three-dimensional model of the integrated circuit; and evaluating the three-dimensional model of the integrated circuit, and determining the packaging structure of the integrated circuit. The positions of the modules in the chip layer and in the chip layer are divided, the number of the through silicon vias is calculated according to the layout model, the three-dimensional model obtained by connecting the through silicon vias is subjected to wiring, through silicon via and temperature evaluation, the three-dimensional packaging structure of the integrated circuit is determined, the through silicon vias are formed in the modules, meanwhile, wiring and temperature consumption is reduced, and the packaging efficiency is improved. And the performance of the three-dimensional packaging integrated circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to an integrated circuit 3D packaging structure and a packaging method thereof. Background Art

[0002] With the rapid development of modern society, the performance requirements of electronic devices are constantly increasing, and the requirements for integrated circuit packaging technology are getting higher and higher. Traditional two-dimensional integrated circuit packaging technology has problems such as low space utilization, limited electrical performance and insufficient heat dissipation capacity, which restricts the further development and improvement of electronic devices.

[0003] Three-dimensional integrated circuit packaging usually uses silicon through vias to connect vertically stacked chip layers. Three-dimensional integrated circuit packaging has better performance and area than traditional two-dimensional integrated circuit packaging. Therefore, three-dimensional integrated circuit packaging is widely used in various electronic devices.

[0004] The existing three-dimensional integrated circuit packaging is packaged by setting silicon vias outside each module area inside the chip. The method of setting silicon vias outside the module area has problems such as large area, low signal quality and low power integrity, while setting silicon vias inside the module area requires re-layout of the chip layer. Therefore, a three-dimensional integrated circuit packaging method with silicon vias inside the module is needed. Summary of the invention

[0005] The purpose of the present invention is to provide an integrated circuit 3D packaging structure and a packaging method thereof. The present invention divides the position of the module in the chip layer and inside the chip layer, calculates the number of silicon vias according to the layout model, performs routing, silicon via and temperature evaluation on the three-dimensional model obtained by connecting the silicon vias, determines the integrated circuit three-dimensional packaging structure, sets silicon vias inside the module while reducing routing and temperature consumption, and improves the performance of the three-dimensional packaged integrated circuit.

[0006] The purpose of the present invention is achieved by the following technical means: In a first aspect, the present invention provides a packaging method for an integrated circuit 3D packaging structure, comprising the following steps: Get the number of layers of the integrated circuit; Dividing the layout positions of the modules according to the number of levels of the integrated circuit to obtain a layout model of the integrated circuit; Calculating the number of through silicon vias in a chip layer according to a layout model of the integrated circuit; Connect modules to each other through silicon vias to obtain a three-dimensional model of the integrated circuit; The three-dimensional model of the integrated circuit is evaluated to determine the packaging structure of the integrated circuit.

[0007] In some embodiments, dividing the layout positions of the modules according to the number of levels of the integrated circuit to obtain the layout model of the integrated circuit includes the following steps: Initializing the integrated circuit; According to the number of levels of the integrated circuit, the modules are randomly divided into chip layers to obtain an initial layout; According to the initial layout, the layout positions of the modules in the chip layer and the layout positions of the chip layer are adjusted to obtain a layout model of the integrated circuit.

[0008] In some embodiments, the calculating the number of through silicon vias of the chip layer according to the layout model of the integrated circuit comprises the following steps: Obtain the interconnection relationship of the modules and obtain the connection modules; According to the layout model of the integrated circuit, obtaining the layer position of the module and the layer position of the connection module; Calculating the number of through silicon vias of the module according to the layer position of the module and the layer position of the connection module; The number of through silicon vias of the modules is summed to obtain the number of through silicon vias of the chip layer.

[0009] In some embodiments, evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit includes the following steps: Calculating the wiring length of the module according to the three-dimensional model of the integrated circuit; The wiring lengths of the modules are summed to obtain the wiring length of the chip layer. estimating a temperature difference of a chip layer according to the three-dimensional model of the integrated circuit; Obtaining a maximum temperature difference of the integrated circuit according to the temperature difference of the chip layer; The integrated circuit is evaluated according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit, and the packaging structure of the integrated circuit is determined.

[0010] In some embodiments, estimating the temperature difference of the chip layer according to the three-dimensional model of the integrated circuit comprises the following steps: Acquire the interconnection relationship of the chip layer according to the three-dimensional model of the integrated circuit; Calculating the vertical thermal resistance of the chip layer according to the interconnection relationship of the chip layer; Obtaining the through silicon via diameter and the through silicon via height of the chip layer; Calculating the lateral thermal resistance of the through silicon via according to the through silicon via diameter of the chip layer; Calculating the vertical thermal resistance of the through silicon via according to the height of the through silicon via of the chip layer; Calculating the heat of the chip layer according to the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through silicon via, and the vertical thermal resistance of the through silicon via; The temperature difference of the chip layer is estimated according to the heat of the chip layer.

[0011] In some embodiments, the temperature difference of the chip layer is estimated by the following formula: , in, For the The temperature difference of the chip layer, is the thermal resistance of the heat sink, is the number of levels, For the Vertical thermal resistance of the chip layer, is the thermal resistance of the package, For the The heat of the chip layer, is the layer number of the chip layer, .

[0012] In some embodiments, evaluating the integrated circuit according to the wiring length of the chip layer, the number of through silicon vias of the chip layer, and the maximum temperature difference of the integrated circuit to determine the packaging structure of the integrated circuit includes the following steps: Establishing an evaluation function according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit; When the value of the evaluation function is greater than a set threshold, the layout of the modules is repeatedly divided; When the value of the evaluation function is less than a set threshold, determining the packaging structure of the integrated circuit; The evaluation function is expressed as follows: , in, is the evaluation function, is the number of levels, For the The trace length of the layer chip, For the The number of through silicon vias in the layer chip, is the maximum temperature difference of the integrated circuit, is the layer number of the chip layer, is the weight.

[0013] In a second aspect, the present invention provides an integrated circuit 3D packaging structure, and a packaging method using the above-mentioned integrated circuit 3D packaging structure includes: a substrate and a multi-layer chip layer; The chip layer includes a plurality of modules inside, each module includes one or more through silicon vias inside, and the module is electrically connected to one or more modules through the through silicon vias.

[0014] In a third aspect, the present invention provides an electronic device comprising a processor and a memory, wherein the memory is used to store computer program code, and the computer program code comprises computer instructions. When the processor executes the computer instructions, the electronic device executes the above-mentioned packaging method of an integrated circuit 3D packaging structure.

[0015] In a fourth aspect, the present invention provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor executes the above-mentioned packaging method of an integrated circuit 3D packaging structure.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention divides the positions of modules in a chip layer and inside a chip layer, calculates the number of through silicon vias according to a layout model, performs routing, through silicon via and temperature evaluation on a three-dimensional model obtained by connecting the through silicon vias, determines the three-dimensional packaging structure of the integrated circuit, sets through silicon vias inside the module while reducing routing and temperature consumption, and improves the performance of the three-dimensional packaged integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 A schematic diagram of a packaging method for an integrated circuit 3D packaging structure provided in this embodiment; Figure 2 Step S2 provided in this embodiment is to divide the layout positions of the modules according to the number of layers of the integrated circuit to obtain a flow chart of the layout model of the integrated circuit; Figure 3 A schematic flow chart of step S3 provided in this embodiment, calculating the number of through silicon vias of a chip layer according to a layout model of an integrated circuit; Figure 4A schematic flow chart of step S5 provided in this embodiment, evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit; Figure 5 A schematic diagram of a flow chart of estimating the temperature difference of a chip layer according to a three-dimensional model of the integrated circuit in step S53 provided in this embodiment; Figure 6 A schematic flow chart of step S55 provided in this embodiment, evaluating the integrated circuit and determining the packaging structure of the integrated circuit according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit; Figure 7 A schematic diagram of the structure of an electronic device provided in this embodiment. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0022] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] Embodiment 1 This embodiment provides a packaging method for an integrated circuit 3D packaging structure, such as Figure 1 As shown, the following steps are included: S1, obtain the number of layers of the integrated circuit; S2, dividing the layout positions of the modules according to the number of levels of the integrated circuit to obtain a layout model of the integrated circuit; S3, calculating the number of through silicon vias in the chip layer according to the layout model of the integrated circuit; S4, connecting the modules with each other through silicon vias to obtain a three-dimensional model of the integrated circuit; S5, evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit.

[0024] It should be noted that the number of levels of an integrated circuit is the number of chip layers required for integrated circuit packaging, and the through silicon vias are set inside the module and the layout of the module is optimized under the condition of a preset number of chip layers. The layout model of the integrated circuit includes the stacking state of the integrated circuit chip layer and the distribution position of the modules inside each chip layer. In some embodiments, the position of each module can be assigned a position, and a ternary coordinate can be used to represent the position of the module inside the chip layer and the layer number of the chip layer. After the modules in the layout model are connected, the three-dimensional model is evaluated, and it is determined whether to select the three-dimensional model for packaging based on the evaluation results.

[0025] In this embodiment, by dividing the position of the module in the chip layer and inside the chip layer, the number of silicon vias is calculated according to the layout model, the routing, silicon via and temperature evaluation are performed on the three-dimensional model obtained by connecting the silicon vias, and the three-dimensional packaging structure of the integrated circuit is determined. While setting silicon vias inside the module, the routing and temperature consumption are reduced, thereby improving the performance of the three-dimensional packaged integrated circuit.

[0026] In some embodiments, step S2 divides the layout positions of the modules according to the number of layers of the integrated circuit to obtain a layout model of the integrated circuit, such as Figure 2 As shown, the following steps are included: S21, initializing the integrated circuit; S22, randomly dividing the modules into chip layers according to the number of layers of the integrated circuit to obtain an initial layout; S23, adjusting the layout positions of the modules in the chip layer and the layout positions of the chip layer according to the initial layout, to obtain a layout model of the integrated circuit.

[0027] It should be noted that when randomly dividing the modules into chip layers and obtaining the initial layout, the area of ​​the modules needs to be considered to ensure that the area of ​​the chip layer is larger than the sum of the areas of the modules inside the chip layer. After obtaining the initial layout, the modules included in the chip layer are determined. At this time, the positions of the modules inside each chip layer and the positions between chip layers are adjusted, that is, the modules within the layer are moved and the modules between layers are interchanged, to obtain the layout model of the integrated circuit.

[0028] In this embodiment, the initial layout is obtained by randomly dividing the modules, and the modules are moved within the layer and exchanged between layers to obtain a layout model of the integrated circuit, thereby improving the diversity of the integrated circuit module layout.

[0029] In some embodiments, step S3, according to the layout model of the integrated circuit, the number of through silicon vias in the chip layer is calculated, such as Figure 3 As shown, the following steps are included: S31, obtaining the interconnection relationship of the modules and obtaining the connection modules; S32, acquiring the layer position of the module and the layer position of the connection module according to the layout model of the integrated circuit; S33, calculating the number of through silicon vias of the module according to the layer position of the module and the layer position of the connecting module; S34, summing the numbers of TSVs of the modules to obtain the number of TSVs of the chip layer.

[0030] It should be noted that the connection module is a module that is interconnected with a certain module. When the layer position of the module and the layer position of the connection module are located in the same chip layer, it is not necessary to set a silicon through via for electrical connection; when the layer position of the module and the layer position of the connection module are located in different chip layers, an additional silicon through via is required for connection every other chip layer. Specifically, the chip layer includes module A and module B. By obtaining the interconnection relationship of module A, the connection module B and the connection module C are obtained, that is, module B and module C are interconnected with module A; the interconnection relationship of module B is obtained to obtain the connection module A. The layer positions of modules A, B and C are obtained from the layout model, and it is obtained that modules A and B are located in chip layer No. 1, and module C is located in chip layer No. 2. Modules A and B are located in the same chip layer, and there is no need to set a silicon through via. Modules A and C are located in adjacent chip layers, and one silicon through via is required for electrical connection, that is, the number of silicon through vias in the chip layer is 1. In this way, the number of silicon through vias is calculated for each chip layer to obtain the number of silicon through vias for each chip layer.

[0031] In this embodiment, by obtaining the layer position of each module and the layer position of the connecting modules and the connecting modules interconnected therewith, the number of through silicon vias in the chip layer is calculated, providing a data basis for subsequent evaluation and improving the performance of the three-dimensional packaged integrated circuit.

[0032] In some embodiments, step S5, the three-dimensional model of the integrated circuit is evaluated to determine the packaging structure of the integrated circuit, such as Figure 4 As shown, the following steps are included: S51, calculating the wiring length of the module according to the three-dimensional model of the integrated circuit; S52, summing up the wiring lengths of the modules to obtain the wiring length of the chip layer; S53, estimating a temperature difference of a chip layer according to a three-dimensional model of the integrated circuit; S54, obtaining a maximum temperature difference of the integrated circuit according to the temperature difference of the chip layer; S55, evaluating the integrated circuit according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit, and determining the packaging structure of the integrated circuit.

[0033] It should be noted that the trace length of the module refers to the length of the signal line connecting the module to the module on the same chip layer. The trace length of the chip layer is obtained by summing the trace lengths of all modules in the chip layer. The temperature difference of the chip layer is the temperature difference between the chip layer and the ambient temperature. The temperature of the chip layer can be measured by summing the temperature difference between the ambient temperature and the chip layer. The maximum temperature difference of the integrated circuit is obtained by comparing the temperature differences of each chip layer and selecting the maximum temperature difference of the chip layer. The layout is evaluated based on the trace length of the chip layer, the number of through-silicon vias in the chip layer, and the maximum temperature of the integrated circuit chip layer.

[0034] In this embodiment, the wiring length and temperature difference of the chip layer are calculated according to the three-dimensional model of the integrated circuit, providing a data basis for subsequent evaluation and improving the performance of the three-dimensional packaged integrated circuit.

[0035] In some embodiments, in step S53, the temperature difference of the chip layer is estimated based on the three-dimensional model of the integrated circuit, such as Figure 5 As shown, the following steps are included: S531, acquiring the interconnection relationship of the chip layer according to the three-dimensional model of the integrated circuit; S532, calculating the vertical thermal resistance of the chip layer according to the interconnection relationship of the chip layer; S533, obtaining a through silicon via diameter and a through silicon via height of the chip layer; S534, calculating the lateral thermal resistance of the through silicon via according to the through silicon via diameter of the chip layer; S535, calculating the vertical thermal resistance of the through silicon via according to the height of the through silicon via of the chip layer; S536, calculating the heat of the chip layer according to the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through silicon via, and the vertical thermal resistance of the through silicon via; S537, estimating the temperature difference of the chip layer according to the heat of the chip layer.

[0036] In some embodiments, the temperature difference of the chip layer is estimated by the following formula: , in, For the The temperature difference of the chip layer, is the thermal resistance of the heat sink, is the number of levels, For the Vertical thermal resistance of the chip layer, is the thermal resistance of the package, For the The heat of the chip layer, is the layer number of the chip layer, .

[0037] It should be noted that the shape of the through silicon via is cylindrical. When estimating the temperature difference, it is necessary to consider the thermal resistance of the chip layer vertically connected to the chip layer and the vertical thermal resistance of the through silicon via required for the connection. In addition, since the through silicon via is arranged inside the module, the lateral thermal resistance of the through silicon via needs to be considered. Therefore, the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through silicon via and the vertical thermal resistance of the through silicon via are obtained to calculate the heat generated by the chip layer. The vertical thermal resistance of the chip layer and the vertical thermal resistance of the through silicon via can be calculated by conventional calculation methods, which will not be repeated here. The lateral thermal resistance of the through silicon via can be obtained by integrating the through silicon via along the radial direction in the calculation formula of the vertical thermal resistance.

[0038] In this embodiment, the heat of the chip layer is calculated by obtaining the vertical thermal resistance of the chip layer, the lateral thermal resistance of the silicon via and the vertical thermal resistance of the silicon via, so as to estimate the temperature difference of the chip layer, provide a data basis for subsequent evaluation, and improve the performance of the three-dimensional packaged integrated circuit.

[0039] In some embodiments, step S55, the integrated circuit is evaluated based on the wiring length of the chip layer, the number of through silicon vias of the chip layer, and the maximum temperature difference of the integrated circuit to determine the packaging structure of the integrated circuit, such as Figure 6 As shown, the following steps are included: S551, establishing an evaluation function according to the wiring length of the chip layer, the number of through silicon vias of the chip layer, and the maximum temperature difference of the integrated circuit; S552, when the value of the evaluation function is greater than the set threshold, repeatedly dividing the layout of the module; S553, when the value of the evaluation function is less than the set threshold, determining the packaging structure of the integrated circuit; The evaluation function formula is as follows: , in, is the evaluation function, is the number of levels, For the The trace length of the layer chip, For the The number of through silicon vias in the layer chip, is the maximum temperature difference of the integrated circuit, is the layer number of the chip layer, is the weight.

[0040] It should be noted that the calculated routing length of the chip layer, the number of through-silicon vias in the chip layer and the maximum temperature difference of the integrated circuit are input into the evaluation function. When the value output by the evaluation function is less than the set threshold, it means that the layout model meets the optimization requirements of the package design; and when the value output by the evaluation function is greater than the set threshold, it means that there is still room for optimization of the layout model. Repeat steps S2 to S5, divide the layout of the module, form a three-dimensional model and re-evaluate until the value output by the evaluation function is less than the set threshold.

[0041] In this embodiment, by setting an evaluation function, the routing, through silicon via and temperature of the three-dimensional model are evaluated. When the evaluation output is not ideal, the module is re-divided and evaluated. When the evaluation output meets the packaging design requirements, the three-dimensional packaging structure of the integrated circuit is determined, which reduces routing and temperature consumption and improves the performance of the three-dimensional packaged integrated circuit.

[0042] Embodiment 2 This embodiment provides an integrated circuit 3D packaging structure, and uses the above-mentioned packaging method of an integrated circuit 3D packaging structure, including: a substrate and a multi-layer chip layer; The chip layer includes a plurality of modules inside, each module includes one or more through silicon vias inside, and the modules are electrically connected to one or more modules through the through silicon vias.

[0043] In this embodiment, by dividing the position of the module in the chip layer and inside the chip layer, the number of silicon vias is calculated according to the layout model, the routing, silicon via and temperature evaluation are performed on the three-dimensional model obtained by connecting the silicon vias, and the three-dimensional packaging structure of the integrated circuit is determined. While setting silicon vias inside the module, the routing and temperature consumption are reduced, thereby improving the performance of the three-dimensional packaged integrated circuit.

[0044] Embodiment 3 This embodiment provides an electronic device 2, such as Figure 7 As shown, a processor 21 and a memory 22, the memory 22 is used to store computer program codes, the computer program codes include computer instructions, when the processor 21 executes the computer instructions, the electronic device executes the above-mentioned packaging method of an integrated circuit 3D packaging structure.

[0045] The electronic device 2 includes a processor 21, a memory 22, an output device 23, and an input device 24. The processor 21, the memory 22, the output device 23, and the input device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0046] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor 21 may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0047] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory 22 includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), and the memory 22 is used for related instructions and data.

[0048] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0049] This embodiment provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes the above-mentioned packaging method for an integrated circuit 3D packaging structure.

[0050] The above are only specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A packaging method for an integrated circuit 3D packaging structure, characterized in that: The following steps are involved: Get the number of layers of the integrated circuit; Dividing the layout positions of the modules according to the number of levels of the integrated circuit to obtain a layout model of the integrated circuit; Calculating the number of through silicon vias in a chip layer according to a layout model of the integrated circuit; Connect modules to each other through silicon vias to obtain a three-dimensional model of the integrated circuit; The three-dimensional model of the integrated circuit is evaluated to determine the packaging structure of the integrated circuit.

2. The packaging method of an integrated circuit 3D packaging structure according to claim 1, characterized in that: The step of dividing the layout positions of the modules according to the number of layers of the integrated circuit to obtain a layout model of the integrated circuit includes the following steps: Initializing the integrated circuit; According to the number of levels of the integrated circuit, the modules are randomly divided into chip layers to obtain an initial layout; According to the initial layout, the layout positions of the modules in the chip layer and the layout positions of the chip layer are adjusted to obtain a layout model of the integrated circuit.

3. The packaging method of an integrated circuit 3D packaging structure according to claim 1, characterized in that: Calculating the number of through silicon vias in a chip layer according to the layout model of the integrated circuit comprises the following steps: Obtain the interconnection relationship of the modules and obtain the connection modules; According to the layout model of the integrated circuit, obtaining the layer position of the module and the layer position of the connection module; Calculating the number of through silicon vias of the module according to the layer position of the module and the layer position of the connection module; The number of through silicon vias of the modules is summed to obtain the number of through silicon vias of the chip layer.

4. The packaging method of an integrated circuit 3D packaging structure according to claim 1, characterized in that: The step of evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit comprises the following steps: Calculating the wiring length of the module according to the three-dimensional model of the integrated circuit; The wiring lengths of the modules are summed to obtain the wiring length of the chip layer; estimating a temperature difference of a chip layer according to the three-dimensional model of the integrated circuit; Obtaining a maximum temperature difference of the integrated circuit according to the temperature difference of the chip layer; The integrated circuit is evaluated according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit, and the packaging structure of the integrated circuit is determined.

5. The packaging method of the integrated circuit 3D packaging structure according to claim 4, characterized in that: The step of estimating the temperature difference of the chip layer according to the three-dimensional model of the integrated circuit comprises the following steps: Acquire the interconnection relationship of the chip layer according to the three-dimensional model of the integrated circuit; Calculating the vertical thermal resistance of the chip layer according to the interconnection relationship of the chip layer; Obtaining the through silicon via diameter and the through silicon via height of the chip layer; Calculating the lateral thermal resistance of the through silicon via according to the through silicon via diameter of the chip layer; Calculating the vertical thermal resistance of the through silicon via according to the height of the through silicon via of the chip layer; Calculating the heat of the chip layer according to the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through silicon via, and the vertical thermal resistance of the through silicon via; The temperature difference of the chip layer is estimated according to the heat of the chip layer.

6. The packaging method of an integrated circuit 3D packaging structure according to claim 5, characterized in that: The temperature difference of the chip layer is estimated by the following formula: ， in, For the The temperature difference of the chip layer, is the thermal resistance of the heat sink, is the number of levels, For the Vertical thermal resistance of the chip layer, is the thermal resistance of the package, For the The heat of the layer chip, is the layer number of the chip layer, .

7. The packaging method of an integrated circuit 3D packaging structure according to claim 4, characterized in that: The step of evaluating the integrated circuit according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit to determine the packaging structure of the integrated circuit includes the following steps: Establishing an evaluation function according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit; When the value of the evaluation function is greater than a set threshold, the layout of the modules is repeatedly divided; When the value of the evaluation function is less than a set threshold, determining the packaging structure of the integrated circuit; The evaluation function is expressed as follows: ， in, is the evaluation function, is the number of levels, For the The trace length of the layer chip, For the The number of through silicon vias in the layer chip, is the maximum temperature difference of the integrated circuit, is the layer number of the chip layer, is the weight.

8. An integrated circuit 3D packaging structure, using the packaging method of an integrated circuit 3D packaging structure according to any one of claims 1 to 7, characterized in that: include: Substrate and multi-layer chip layers; The chip layer includes a plurality of modules inside, each module includes one or more through silicon vias inside, and the module is electrically connected to one or more modules through the through silicon vias.

9. An electronic device, characterized in that: It includes a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, when the processor executes the computer instructions, the electronic device executes the packaging method of an integrated circuit 3D packaging structure as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a packaging method for an integrated circuit 3D packaging structure as described in any one of claims 1 to 7.

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