Verification method and processing system of integrated circuit

Abstract

The invention provides a verification method and system of an integrated circuit. The integrated circuit is divided into a plurality of modules and a top-layer module used for calling the modules, and the verification method comprises the following steps: aligning the top-layer module and a target module to the same coordinate system based on the layout and wiring information of the target module in the modules and the layout and wiring information of the top-layer module; and based on the aligned target module and the top layer module, module-level voltage drop simulation is operated to obtain a voltage drop simulation result, and the voltage drop simulation result is used for analyzing whether the voltage drop condition meets the standard when the target module is called by the top layer module.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a verification method, a processing system and a computer-readable storage medium for an integrated circuit. Background Art

[0002] Before the design data of an integrated circuit is delivered to a chip manufacturer for production, a series of analysis and verification is usually required to ensure that the design data meets the delivery standards. This series of analysis and verification is collectively referred to as signoff. Signoff helps relevant technical personnel correct loopholes in the design data before tape-out, thereby saving costs.

[0003] Voltage drop (IR drop) refers to the voltage loss caused by the wiring from the power supply voltage and ground voltage to the circuit unit in the integrated circuit. Each unit in the integrated circuit may be affected by the voltage drop, which will slow down the signal propagating to the next unit. When the voltage drop exceeds a certain level, the integrated circuit will fail to function and cannot achieve the required performance. In order for the integrated circuit to work properly, each unit of the integrated circuit needs to have a uniform and stable power supply. Therefore, voltage drop simulation of the integrated circuit design data and analysis and verification based on the simulation results is a key step in the signoff stage. Voltage drop simulation is also called power integrity (PI) simulation. Analysis and verification based on the voltage drop simulation results is to analyze and verify whether the voltage drop in the integrated circuit and the impact of the voltage drop on the power supply meet the signoff standard.

[0004] However, the voltage drop simulation of the integrated circuit can only be performed after all modules are ready, which means that the voltage drop simulation of the integrated circuit can usually only be performed in the late stage of the design cycle, which is not conducive to timely discovery and repair of problems caused by voltage drop in the integrated circuit. Summary of the invention

[0005] In order to solve the problems existing in the above prior art, the present disclosure provides an integrated circuit verification method, a processing system and a computer readable storage medium. According to the solutions of the embodiments of the present disclosure, problems caused by voltage drop in the module of the integrated circuit can be discovered and repaired as early as possible.

[0006] According to one aspect of the present invention, a verification method for an integrated circuit is provided, wherein the integrated circuit is divided into a plurality of modules and a top-level module for calling the plurality of modules, and the verification method comprises:

[0007] Based on the layout and routing information of the target module among the multiple modules and the layout and routing information of the top-level module, aligning the top-level module and the target module to the same coordinate system;

[0008] Based on the aligned target module and the top-level module, a voltage drop simulation is run to obtain a voltage drop simulation result, and the voltage drop simulation result is used to analyze whether the voltage drop condition of the target module meets the standard.

[0009] In some embodiments, after aligning the top-level module and the target module to the same coordinate system, if there is no signal communication path between the top-level module and the target module, relevant units are added to establish a signal path between the top-level module and the target module.

[0010] In some embodiments, the running a voltage drop simulation based on the aligned target module and the top module includes:

[0011] Based on the power ground winding information of each module and the RC parasitic parameter information of the signal line output by the top-level module, the input parameter information of the target module is obtained;

[0012] Based on the input parameter information of the target module, a module-level voltage drop simulation is performed on the target module to obtain a voltage drop simulation result.

[0013] In some embodiments, the running of the module-level voltage drop simulation on the target module includes: collecting key data of the signal value change data under each test case of the target module, and using the key data to run the module-level voltage drop simulation, wherein the collecting of the key data in the signal value change data of the target module includes:

[0014] Obtain power consumption values ​​corresponding to a plurality of simulation windows respectively for the signal value change data under each test case of the target module;

[0015] Determine a simulation window corresponding to a maximum power consumption value in the multiple simulation windows as a key window for signal value change data under each test case of the target module;

[0016] The signal value change data under each test case of the target module is limited according to the key window to obtain the key data of the signal value change data under each test case of the target module.

[0017] In some embodiments, the running a voltage drop simulation based on the aligned target module and the top module includes:

[0018] Align the signal value change data corresponding to the target module and the top-level module under each test case in time, and run module-level power consumption simulation to obtain overall power consumption values ​​corresponding to multiple simulation windows;

[0019] The simulation window corresponding to the maximum power consumption value in the overall power consumption value is used as a key window, and based on the key window, the signal value change data of the target module and the top-level module are limited to obtain the aligned key data of the target module and the top-level module;

[0020] The target module and the top module aligned with the key data are used to run a module-level voltage drop simulation.

[0021] In some embodiments, for the signal value change data under each test case of the target module, obtaining power consumption values ​​corresponding to a plurality of simulation windows respectively includes:

[0022] For the target module, a module-level power consumption simulation is run based on the signal value change data under each test case of the target module to obtain the power consumption value corresponding to the signal value change data under each test case under the multiple simulation windows.

[0023] In some embodiments, aligning the top module and the target module to the same coordinate system includes:

[0024] Select a module containing more units from the top-level module and the target module; and

[0025] The modules containing more units among the top module and the target module are aligned to the coordinate systems of the modules containing fewer units among the top module and the target module.

[0026] In some embodiments, the time widths of the multiple simulation windows are consistent; and / or

[0027] The time difference between every two simulation windows that are adjacent in time sequence is consistent.

[0028] According to a second aspect of the present invention, there is provided a processing system, comprising:

[0029] a processor for executing a verification tool; and

[0030] A storage device provides a running space and a data storage space for the verification tool,

[0031] Wherein, the verification tool is configured to execute any of the verification methods described above.

[0032] According to a third aspect of the present invention, there is provided a computer-readable storage medium having instructions stored thereon, wherein the instructions are executed by one or more processing units to implement any of the verification methods described above.

[0033] According to an embodiment of the present invention, the power consumption of the top-level module is introduced into the voltage drop simulation verification of the target module, so as to discover the voltage drop risk of the target module at an early stage, and the layout and routing of the target module can be corrected before the layout and routing of the target module is finally determined, which helps to alleviate the pressure of the system-level voltage drop simulation verification in the Signoff link. The voltage drop simulation verification of the target module is usually a design with millions of chips, and the time consumed in the voltage drop simulation verification of the target module is relatively short, which can be quickly iterated. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0035] Figure 1 It is a flowchart of integrated circuit design work;

[0036] Figure 2 It is a schematic diagram of the structure of an integrated circuit;

[0037] Figure 3 is a flow chart of a verification method for an integrated circuit according to an embodiment of the present invention;

[0038] Figure 4 yes Figure 3 A flowchart of a specific embodiment of step S120 in FIG.

[0039] Figure 5 A schematic diagram showing steps for obtaining key data for voltage drop simulation according to an embodiment of the present disclosure is shown;

[0040] Figure 6 is a flow chart of running a voltage drop simulation based on an aligned target module and a top module according to the present disclosure;

[0041] Figure 7 A schematic diagram of the structure of a processing system 200 provided according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0042] The present invention is described below based on embodiments, and many specific details of the present invention are described below to make the present invention more clearly understood. However, as those skilled in the art can understand, the present invention may be implemented without following these specific details, that is, the present invention is not limited to these embodiments. In order to avoid confusing the essence of the present invention, well-known methods, processes, procedures, chip devices, and chip circuits are not described in detail.

[0043] The same chip devices are represented by similar reference numerals in various drawings. In addition, it should be understood by those skilled in the art that the drawings provided here are for illustrative purposes and the drawings are not necessarily drawn to scale.

[0044] Before introducing exemplary embodiments of the present application, in order to facilitate those skilled in the art to better understand the present application, some concepts involved in the present application are first explained.

[0045] There are two design ideas for the chip backend: flatten design and hierarchical design. The flattening design method is a bottom-up design idea. This design method will import all the components required in the chip at once, and each component must be fully verified to ensure that the functions of each component are correct. Then all these components are combined to form the entire chip system. When designing, engineers can mobilize any component at will, which means that all components are visible, and there is no so-called black box. In fact, everyone can simply understand it as a complete design that can see all the contents of the chip. The hierarchical design method is a top-down design idea. For the front-end design, it will first analyze the functions to be realized by the entire chip, and then divide (partition) into different functional modules (blocks). When dividing, it only cares about the input and output of each module, without considering how the module is specifically constructed.

[0046] Violation: Violation. The design and verification of integrated circuit system-on-chip is a very time-consuming and complicated process. It takes a few months or even years for a product to go from the initial conception to design, verification, tape-out, testing and finally to mass production. In the design process of integrated circuit system-on-chip, simulation and verification are often required to check whether the designed system-on-chip can be executed as envisioned. Pre-functional simulation and post-timing simulation are required in the design and verification process of integrated circuit system-on-chip. Among them, pre-functional simulation is for register transfer level (RTL) simulation, which mainly verifies the logical function correctness of the designed circuit through simulation, and the simulation speed is fast. Post-timing simulation is based on the netlist composed of basic gate units, and the gate-level circuit delay of the netlist and the connection delay between various gate-level circuits are taken into account for simulation. Post-timing simulation mainly discovers potential design constraints and timing problems through simulation. And because the delay of circuit elements and paths is taken into account in the post-simulation, the simulation speed is slow. It often takes several hours or even days for a post-simulation of an integrated circuit system-on-chip. Compared with pre-simulation, a large number of timing violations will be reported during the post-simulation of the integrated circuit system on chip, which seriously slows down the post-simulation process. The so-called timing violation refers to the violation of the setup time or hold time or other timing constraints, so that the sampling clock cannot correctly collect data. For example, when using a slower (lower frequency) clock signal to sample a faster (higher frequency) cross-clock domain signal, it is generally required that in the receiving clock domain, the faster cross-clock domain signal needs to be maintained for a longer time to ensure that it can be correctly sampled by the slower clock signal.

[0047] Signal value change dump (VCD) data: refers to the simulation waveform data that can characterize the real working flip state of the signal values ​​corresponding to all gate units obtained by simulating the design data of the integrated circuit based on the corresponding real working scene of the chip. As the result data of the front-end simulation output, it can be generated based on the place and route (PR) database. It is precisely because the VCD data contains the signal change information, which is equivalent to recording the information of the entire simulation. Therefore, the simulation can be reproduced based on the VCD data to analyze and verify the power consumption, voltage drop, etc. VCD data is generally stored in a VCD file, which mainly contains header information, pre-definition of variables, and change information of variable values. As an example, a VCD file can be an ASCII file defined based on the IEEE1364 standard (Verilog HDL language standard).

[0048] Figure 1This is a flowchart of integrated circuit design work. Digital integrated circuit design includes two stages: front-end and back-end. There is no clear boundary between the front-end and back-end. Figure 1 The stage above the dotted line is called the front end, and the stage below the dotted line is called the back end. The front end includes multiple stages such as algorithm or hardware architecture design and analysis, RTL implementation, code style checking, functional verification (pre-simulation), logic synthesis, lens timing analysis, consistency verification and timing simulation (post-simulation). Algorithm or hardware architecture design and analysis completes the analysis and modeling of the high-level algorithm or architecture of the digital part of the chip, provides a correct software function model for the hardware, and provides overall design guidance for RTL implementation. RTL (Register Transfer Level) implementation completes the description of the circuit from high-level description (from algorithm or hardware architecture design and analysis) to the description of the circuit based on the transfer between registers in hardware language. Code style checking is used to eliminate problems such as cross-clock domain and Lint in RTL code. Functional verification (pre-simulation) is simulated according to RTL implementation, and errors and vulnerabilities in circuit design under ideal conditions without delay are discovered and corrected through simulation. The main indicator of functional verification is functional coverage. Logic synthesis is to translate the program code obtained in the RTL level design into various components of the actual circuit and the connection relationship between them, and then express them in a table, which is called the gate-level netlist. The logic synthesis stage realizes the mapping of the code to the netlist related to the process library. Static timing analysis, compared with the exhaustive verification method of dynamic simulation, ensures that all paths in the design meet the requirements of the internal timing unit for setup time and hold time from the perspective of static analysis. That is, no matter what the starting point is, the signal can be transmitted to the end point of the path in a timely manner and remain constant within the time period required for the normal operation of the circuit. The next stage is consistency verification. Both the RTL code and the netlist after logic synthesis can be abstracted into two graphs composed of nodes and edges. The consistency verification stage uses a method similar to directly comparing whether the two graphs are consistent to determine whether the netlist generated by logic synthesis is correct. The next stage is timing simulation. Compared with functional simulation, timing simulation replaces the RTL code with a netlist, and then needs to load the standard delay format (SDF) file and the process library model. The purpose of timing simulation is to observe whether the function can still remain correct under the conditions of approximate actual working conditions such as unit and path delays. Compared with pre-functional simulation, timing simulation is also called post-simulation.

[0049] The back-end design of digital integrated circuits is also called physical design, which converts the text in the netlist format into units and connections with physical size and position (placement and routing). In the implementation process, the requirements of area, power consumption, performance, etc. must be met. Figure 1In the figure, the backend shows the four steps of floorplan, cell placement, clock tree synthesis and routing. These four steps are combined together and are also called automatic placement and routing (APR). Of course, the backend also includes some steps that are not shown, such as extracting delay information, running DRC (design rule check) and LVS (consistency check of layout and circuit diagram), etc. And the entire design process is an iterative process. When any step fails to meet the constraints or cannot realize the function, it is necessary to repeat the previous steps or even redesign the RTL code.

[0050] Figure 2 It is a schematic diagram of the structure of an integrated circuit. Figure 2 As shown, in the integrated circuit 200, the modules serving as block level simulation objects include n modules Block1 to Blockn (n is a natural number greater than 1) inside the integrated circuit 200 and a top-level module Top0 that calls these n modules Block1 to Blockn. The top-level module Top0 is used to establish signal relationships between different modules and also includes parts outside the n modules Block1 to Blockn (such as interface units, etc.).

[0051] In the front end of the flattened design, each module Block1~Blockn and the top module can be simulated under different test cases, so as to obtain the VCD data of each module and the top module under multiple test cases (including the simulation waveform information of each related signal). This series of VCD data can be stored in the form of VCD files, that is, each module and the top module can correspond to multiple VCD files (corresponding to different test cases).

[0052] At the back end of the flattened design, power consumption and voltage drop simulation can be performed based on VCD data. For example, the modules Block1 to Blockn and the top-level module are organized together, and the voltage drop simulation is performed on the entire integrated circuit, and the power supply voltage distribution of each module is analyzed based on the simulation results. However, as described in the background technology, this approach is not conducive to early detection and repair of voltage drop problems in a single module.

[0053] In order to find the voltage drop problem in the target module (as an example of a single module), the target module and the top module can be aligned to the same coordinate system, and the voltage drop simulation can be performed on the aligned module combination. In this way, the voltage drop simulation result of the target module is closer to the voltage drop simulation result of the target module in the entire integrated circuit during Sigoff, so that the voltage drop problem of the target module can be analyzed more accurately.

[0054] Figure 3 FIG. 1 is a flow chart of a verification method for an integrated circuit provided by an embodiment of the present disclosure. Figure 3 As shown, the verification method includes the following steps.

[0055] In step S110 , the top-level module is aligned to the same coordinate system based on the layout and routing information of the target module among the multiple modules and the layout and routing information of the top-level module.

[0056] In step S120, a module-level voltage drop simulation is run based on the aligned target module and the top-level module to obtain a voltage drop simulation result, which is used to analyze whether the voltage drop condition of the target module meets the standard when it is called by the top-level module.

[0057] Below Figure 2 This embodiment is described in detail with reference to an example.

[0058] Regarding step S110, refer to Figure 2As shown, in the early stage of the back-end work, it is assumed that the module Block3 has completed the automatic placement and routing (auto placement & route, APR) work and obtained the layout and routing information of Block3. The layout and routing information of Block3 will record the size and position of each unit in Block3, the connection between units, the input and output of Block3 and other information. This information is usually stored in the APR database, and at the same time, the layout and routing information of the layout and routing layer of the entire flattened design is output through the top-level module TOP0. This information usually exists in the form of a text file and contains the power ground winding information of the entire layout and routing layer. After having these two layout and routing information, the two modules are aligned to the same coordinate system. The top-level module TOP0 can be aligned to the coordinate system where Block3 is located, or Block3 can be aligned to the coordinate system of the top-level module TOP0. Preferably, the amount of calculation involved in aligning a module containing a smaller number of units to a coordinate system containing a larger number of units is less than the opposite, so the module containing a smaller number of units is aligned to the coordinate system of the module containing a larger number of units. For example, the top-level module TOP0 is usually aligned to the coordinate system of Block3 instead of the opposite. It should be understood that the units that need to be aligned include not only various devices such as capacitors, resistors, switches, amplifiers, etc., but also units such as pads, pins, and through holes used for communication. For example, in the packaging structure, the top module can be connected to the pad, and the target module is then connected to the pad through pins (bumps) and through holes (Through Silicon Via, TSV for short). Therefore, during the alignment process, the pads, pins, and through holes also need to be aligned to the same coordinate system. In addition, if there is no signal connection between the top module and the target module, it is necessary to add pads, pins, and through holes to establish a signal path between the top module and the target module.

[0059] Regarding step S120, a module-level voltage drop simulation is performed on the aligned target module and the top-level module to obtain a voltage drop simulation result. In the voltage drop simulation of the aligned target module and the top-level module, the current path starts from the input end of the top-level module, passes through the inside of the top-level module and the outside of the target module, reaches the input end of the target module, and then passes through the inside of the target module to reach the output end of the target module. Through this process, the simulation result of the combination of the top-level module and the target module is obtained.

[0060] Figure 4 yes Figure 3 The flowchart of a specific embodiment of step S120 in FIG. specifically includes the following steps.

[0061] In step S1201, based on the power ground wiring information of each module and the RC parasitic parameter information of the signal line output by the top-level module, the input parameter information of the target module is obtained.

[0062] In step S1202 , based on the input parameter information of the target module, a module-level voltage drop simulation is performed on the target module to obtain a voltage drop simulation result.

[0063] Through the chip design tool, the definition files of each module are output through the top-level module. The file of each module includes the power ground winding information of the module, and then the specification files of each module are output. The specification files contain the RC parasitic parameter information of all signal lines. Through the above two types of information, the input parameter information of the target module is generated. The input data information records the signal size and timing constraints of each input end of the target module. Then, based on the input parameter information of the target module, the module-level voltage drop simulation is run on the target module to obtain the voltage drop simulation result.

[0064] In some embodiments, at the front end of the flattened design, the target module is simulated under multiple test cases to obtain multiple VCD data corresponding to the multiple test cases, and then the target module is simulated at the module level based on the VCD data of the target module and the input parameter information of the target module.

[0065] In some embodiments, for the VCD data under each test case of the target module, the power consumption values ​​corresponding to the multiple simulation windows are obtained, and then the simulation window corresponding to the maximum power consumption value in the multiple simulation windows is determined as the key window corresponding to the VCD data, and then the VCD data segment defined by the key window is used as the key data of the VCD data. Then the module-level voltage drop simulation of the target module based on the VCD data of the target module and the input parameter information of the target module is as follows: the module-level voltage drop simulation of the target module is performed based on the key data of the target module and the input parameter information of the target module. Since the voltage loss usually increases with the increase of the power consumption value, the greater the voltage loss, the more severe the corresponding voltage drop situation. Therefore, the VCD data segment defined by the simulation window corresponding to the maximum power consumption value can be used as the key data for voltage drop simulation verification. That is to say, if the result obtained by performing the voltage drop simulation based on the key data meets the standard, it means that the other data of the target module other than the key data in the VCD data can also meet the standard, so there is no need to perform the voltage drop simulation based on the entire VCD data, and only the voltage drop simulation verification based on the key data segment of the VCD data is required.

[0066] Figure 5 The following is a schematic diagram of the steps of obtaining key data for voltage drop simulation according to an embodiment of the present disclosure. The following is an explanation based on a VCD data VCD_j1 under a test case corresponding to a submodule Blockj in the integrated circuit 100. The total simulation time corresponding to the VCD data VCD_j1 is recorded as T VCD_all.

[0067] like Figure 5 As shown, as an example, in the module-level power consumption simulation for the module Blockj, m simulation windows w[1] to w[m] can be set in chronological order, and m power consumption values ​​corresponding to the VCD data segment defined by each simulation window can be obtained respectively, where m is a natural number greater than 1. Among them, the starting time of the first simulation window w[1] corresponds to the starting time of the VCD data VCD_j1, and the ending time tm of the last simulation window w[m] can correspond to the ending time of the VCD data VCD_j1, or it may be before the ending time of the VCD data VCD_j1.

[0068] To facilitate power consumption comparison, the m simulation windows w[1] to w[m] all have the same time width Tw. The time width Tw of each simulation window can be set according to the expected simulation accuracy and simulation running time, for example, it can be set to be less than / equal to 100ns. As a reference example, the time width Tw of each simulation window can be selected as 10ns or 20ns, etc. As another option, the m simulation windows w[1] to w[m] can be incremented in time sequence, that is, the time difference between every two adjacent simulation windows in time sequence is consistent.

[0069] In the disclosed embodiment, for the branch VCD data VCD_j1, the module-level power consumption simulation is run based on the simulation windows w[1] to w[m] respectively, and m corresponding power consumption values ​​(for example, at least including dynamic power consumption values) can be obtained. Afterwards, the maximum power consumption value Pmax among the m power consumption values ​​is determined by comparison, and the VCD data segment VCD_j1[ti-Δts,ti] defined by the simulation window w[i] corresponding to the maximum power consumption value is confirmed, and the simulation window w[i] is used as the key window of the branch VCD data VCD_j1, and the VCD data segment VCD_j1[ti-Δts,ti] is used as the key data of the branch VCD data VCD_j1. Wherein i is an integer greater than / equal to 1 and less than / equal to m.

[0070] Taking each module and the top-level module as an example corresponding to k (k is an integer greater than / equal to 1) test cases (i.e., each module and the top-level module corresponds to k VCD data), the information shown in Table 1 below can be stored in a designated storage space (for example, provided by a memory and / or a register):

[0071] Table 1 Each module and its corresponding VCD data, key window and power consumption value

[0072]

[0073] Based on the embodiment of the present invention, the target module (for example, Block 1 in the table) corresponds to k test cases (k is an integer greater than 0), and key data are selected from the VCD data corresponding to the k test cases to run the voltage drop simulation of the module. Although the voltage drop simulation still needs to be run k times, since only key data is used for voltage drop simulation, the simulation time is greatly shortened, and the memory space required during the simulation process is also greatly reduced.

[0074] Figure 6 The flowchart of running voltage drop simulation based on the aligned target module and top-level module according to the embodiment of the present disclosure includes the following steps.

[0075] In step S1211, the signal value change data corresponding to the target module and the top-level module under each test case are aligned in time, and the module-level power consumption simulation is run to obtain the overall power consumption values ​​corresponding to multiple simulation windows.

[0076] In step S1212, the simulation window corresponding to the maximum power consumption value in the overall power consumption value is used as the key window, and based on the key window, the signal value change data of the target module and the top module are limited to obtain the key data of the aligned target module and the top module.

[0077] In step S1213, the module-level voltage drop simulation is run on the aligned target module and the top-level module using the key data.

[0078] According to an embodiment of the present disclosure, as shown in Reference Table 1, the target module and the top-level module each have k VCD data, these data are aligned in time (start time alignment and / or end time alignment), and are combined in pairs, and module-level power consumption simulation is run based on multiple simulation windows (i.e., the target module and the top-level module are used as new modules for module-level simulation), that is, the overall power consumption value corresponding to the combination of the target module and the top-level module in each simulation window is scanned to obtain the maximum power consumption value in the overall power consumption value by comparison, the simulation window corresponding to the maximum power consumption value is used as the key window, and the signal value change data of the target module and the top-level module are limited based on the key window to obtain the key data of the aligned target module and the top-level module, and the key data is used to run the module-level voltage drop simulation on the aligned target module and the top-level module.

[0079] This embodiment uses the top-level module and the target module as a new module for power consumption analysis, and obtains key data corresponding to the maximum power consumption value of the combined module for voltage drop simulation, thereby accurately analyzing the voltage drop problem existing in the target module.

[0080] Figure 7A schematic diagram of the structure of a processing system 200 provided according to an embodiment of the present disclosure is shown.

[0081] like Figure 7 As shown, the processing system 200 mainly includes a storage device 210 and a processor 220, which is used to perform simulation verification on the design data of the integrated circuit to be verified.

[0082] The storage device 210 is, for example, a storage array, a shared directory, etc., and is used to store the design data of the integrated circuit 100, the database required for simulation, the VCD data corresponding to each module, and the file for specifying the signoff standard, etc., and can also provide the first storage space and / or the second storage space mentioned above. The present disclosure does not limit the specific hardware implementation of the storage device 210, for example, it can be a static random access memory (SRAM), a dynamic random access memory (DRAM), other types of random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory or other memory technology, a read-only compact disk read-only memory (CD-ROM), a digital versatile disk (DVD) or other optical storage, a magnetic cassette, a magnetic tape magnetic disk storage or other magnetic storage device or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

[0083] The processor 220 is coupled to the storage device 210 for communication so as to execute the verification tool 10 based on the information provided by the storage device 210, and the verification tool is configured to execute the simulation method and / or verification method of the integrated circuit described in any embodiment of the present disclosure. The storage device 210 is used to provide the operation space and data storage space of the verification tool 10. The processor 220 can be selected from various general-purpose processors (such as a central processing unit CPU and / or a digital processor), or it can be a dedicated processor for executing the method provided by any embodiment of the present disclosure, or it can be a reasonable combination of a general-purpose processor and a dedicated processor.

[0084] The processing system 200 may also include one or more of various input / output units, communication units (for wired and / or wireless communication, such as for receiving VCD data provided by the front end, accessing the cloud to obtain simulation-related databases, etc.), interface units, power supply units, bus units and other structures.

[0085] In summary, the verification method and processing system provided by the embodiment of the present invention perform module-level voltage drop simulation on the aligned top-level module and target module, and the simulation result is more accurate than the voltage drop simulation of the target module only. Moreover, since the voltage drop simulation is performed at the module level, compared with the voltage drop simulation of the top-level design, the number of circuit units involved is smaller (millions of chips), and the running time is shorter, so it can be iterated quickly, and less memory and hard disk storage space is occupied during operation. In the Signoff stage, since the voltage drop simulation of the top-level design is performed, the test cases run by the module-level voltage drop simulation can be deleted later, which further saves hard disk storage space.

[0086] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0088] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0090] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0091] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0092] Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and can store information by any method or technology. The information can be computer-readable instructions, data structures, program modules or other data.

[0093] A computer readable storage medium may be a tangible device that can store instructions for use by an instruction execution device. A computer readable storage medium may be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media include, but are not limited to, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM), static random access memories (SRAM), portable compact disc read-only memories (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves on which instructions are recorded), and any suitable combination of the foregoing, which can be used to store information that can be accessed by a computing device.

[0094] The computer-readable program instructions for performing the above method can be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages) and conventional process programming languages. The computer-readable program instructions can be executed completely on a computer system as an independent software package, or, partially executed on a first computer and partially executed on a second computer away from the first computer. In the latter case, the remote second computer can be connected to the first computer through any type of network, and the network includes a local area network (LAN) or a wide area network (WAN).

[0095] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0096] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention.

Claims

1. A verification method for an integrated circuit, wherein the integrated circuit is divided into a plurality of modules and a top-level module for calling the plurality of modules, the verification method comprising: Based on the layout and routing information of the target module among the multiple modules and the layout and routing information of the top-level module, aligning the top-level module and the target module to the same coordinate system; Based on the aligned target module and the top-level module, a voltage drop simulation is run to obtain a voltage drop simulation result, and the voltage drop simulation result is used to analyze whether the voltage drop condition of the target module meets the standard.

2. According to the verification method of claim 1, after aligning the top-level module and the target module to the same coordinate system, if there is no signal communication path between the top-level module and the target module, relevant units are added to establish a signal path between the top-level module and the target module.

3. The verification method according to claim 1, wherein: The running of voltage drop simulation based on the aligned target module and the top module includes: Based on the power ground winding information of each module and the RC parasitic parameter information of the signal line output by the top-level module, the input parameter information of the target module is obtained; Based on the input parameter information of the target module, a module-level voltage drop simulation is performed on the target module to obtain a voltage drop simulation result.

4. The verification method according to claim 3, wherein: The running of the module-level voltage drop simulation on the target module includes: collecting key data of the signal value change data under each test case of the target module, and using the key data to run the module-level voltage drop simulation, wherein the collecting of the key data in the signal value change data of the target module includes: Obtain power consumption values ​​corresponding to a plurality of simulation windows respectively for the signal value change data under each test case of the target module; Determine a simulation window corresponding to a maximum power consumption value in the multiple simulation windows as a key window for signal value change data under each test case of the target module; The signal value change data under each test case of the target module is limited according to the key window to obtain the key data of the signal value change data under each test case of the target module.

5. The verification method according to claim 1, wherein: The running of voltage drop simulation based on the aligned target module and the top module includes: Align the signal value change data corresponding to the target module and the top-level module under each test case in time, and run module-level power consumption simulation to obtain overall power consumption values ​​corresponding to multiple simulation windows; The simulation window corresponding to the maximum power consumption value in the overall power consumption value is used as a key window, and based on the key window, the signal value change data of the target module and the top-level module are limited to obtain the aligned key data of the target module and the top-level module; The target module and the top module aligned with the key data are used to run a module-level voltage drop simulation.

6. The verification method according to claim 3, wherein: For the signal value change data under each test case of the target module, obtaining power consumption values ​​corresponding to a plurality of simulation windows respectively includes: For the target module, a module-level power consumption simulation is run based on the signal value change data under each test case of the target module to obtain the power consumption value corresponding to the signal value change data under each test case under the multiple simulation windows.

7. The verification method according to claim 1, wherein: The aligning the top module and the target module to the same coordinate system comprises: Selecting a module containing more units from the top-level module and the target module; and The modules containing more units among the top module and the target module are aligned to the coordinate systems of the modules containing fewer units among the top module and the target module.

8. The verification method according to any one of claims 4 to 6, wherein: The time widths of the multiple simulation windows are consistent; and / or The time difference between every two simulation windows that are adjacent in time sequence is consistent.

9. A processing system, wherein: include: a processor for executing a verification tool; as well as A storage device provides a running space and a data storage space for the verification tool, Wherein, the verification tool is configured to execute the verification method described in any one of claims 1 to 8.

10. A computer-readable storage medium having instructions stored thereon, wherein: The instructions are executed by one or more processing units to implement the verification method according to any one of claims 1 to 8.

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