Clock distribution method and device, computer equipment, storage medium and program product

Abstract

The invention relates to the technical field of integrated circuits, and discloses a clock distribution method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: acquiring a clock distribution condition of each device in a target field programmable gate array; based on the clock distribution condition of each device in the target field-programmable gate array, determining a bounding box corresponding to each clock of the target field-programmable gate array; taking each clock of the target field programmable gate array as a vertex, and constructing an undirected graph based on a bounding box corresponding to each clock; processing the undirected graph through a graph dyeing algorithm, and dyeing each vertex in the undirected graph; and distributing devices in the target field programmable gate array corresponding to the vertexes with the same color to the same clock plane. According to the scheme, the accuracy and effectiveness of clock distribution are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a clock distribution method, device, computer equipment, storage medium and program product. Background Art

[0002] Field Programmable Gate Array (FPGA) can be programmed to implement various complex digital logic functions. On the basis of configurability, it contains more complex clock architecture logic to achieve synchronous operation, control timing, optimize performance and simplify design. In the FPGA clock network architecture, a plane composed of clock wires of the same model is called a clock plane. A clock signal can only be transmitted on the same clock plane and cannot be transmitted across planes. Since the physical structure of the clock network in the field programmable gate array is pre-manufactured and cannot be modified later, the implemented functions cannot be adjusted for different application scenarios. In addition, for high-utilization designs, clock routing resources are usually limited. The clock distribution method for field programmable gate arrays in the related art has been difficult to support large-scale clock structures. It is easy to cause congestion of layout and wiring resources due to unreasonable clock distribution, and the utilization rate of resources is low.

[0003] Therefore, there is an urgent need for a solution that can accurately and effectively distribute clocks. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a clock distribution method, apparatus, computer equipment, storage medium and program product to solve the problem of insufficient accuracy and effectiveness in clock distribution.

[0005] In a first aspect, the present invention provides a clock distribution method, the method comprising:

[0006] Obtaining clock distribution of each device in a target field programmable gate array;

[0007] Based on the clock distribution of each device in the target field programmable gate array, respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array;

[0008] Taking each clock of the target field programmable gate array as a vertex, an undirected graph is constructed based on the bounding boxes corresponding to each clock;

[0009] Processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph;

[0010] The devices in the target field programmable gate array corresponding to the vertices with the same color are respectively allocated to the same clock plane.

[0011] In an optional implementation manner, the acquiring the clock distribution of each device in the target field programmable gate array includes:

[0012] Establishing a grid coordinate system based on a target field programmable gate array;

[0013] The clock of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system are obtained.

[0014] In an optional implementation, the determining, based on the clock distribution of each device in the target field programmable gate array, the bounding boxes corresponding to each clock of the target field programmable gate array respectively include:

[0015] Based on the clocks of the devices in the target field programmable gate array and the coordinates of the devices in the grid coordinate system, a bounding box corresponding to each clock is calculated.

[0016] In an optional implementation, constructing an undirected graph based on bounding boxes corresponding to each clock includes:

[0017] If there is position overlap between the bounding boxes corresponding to any two clocks, an undirected edge is added between the vertices corresponding to the two clocks.

[0018] In an optional implementation, processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph includes:

[0019] Determine the degree of each vertex in an undirected graph;

[0020] Arrange each vertex in descending order according to the degree size to obtain the vertex arrangement order;

[0021] Color each vertex according to the order in which the vertices are arranged.

[0022] In an optional implementation, coloring each vertex according to the vertex arrangement order includes:

[0023] Dye the first vertex in the vertex arrangement order as the first color;

[0024] Determine whether the second-rank vertex is connected to the colored vertex through an undirected edge; if not, color the second-rank vertex with the first color; if so, color the second-rank vertex with the second color;

[0025] Repeat the above steps so that each pair of adjacent vertices connected by undirected edges are colored with different colors until all vertices are colored.

[0026] In a second aspect, the present invention provides a clock distribution device, the device comprising:

[0027] An acquisition module, used to acquire the clock distribution of each device in the target field programmable gate array;

[0028] A bounding box module, for determining the bounding boxes corresponding to the respective clocks of the target field programmable gate array based on the clock distribution of the respective devices in the target field programmable gate array;

[0029] An undirected graph module, used for constructing an undirected graph based on bounding boxes corresponding to each clock, taking each clock of the target field programmable gate array as a vertex;

[0030] A graph coloring module, used for processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph;

[0031] The clock distribution module is used to distribute the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0032] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the clock distribution method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the clock distribution method of the first aspect or any corresponding embodiment thereof.

[0034] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the clock distribution method of the first aspect or any corresponding embodiment thereof.

[0035] The technical solution provided by the present invention may include the following beneficial effects:

[0036] The clock distribution method provided by the present invention first obtains the clock distribution of each device in the target field programmable gate array, then determines the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array, then takes each clock of the target field programmable gate array as a vertex, constructs an undirected graph based on the bounding boxes corresponding to each clock, then processes the undirected graph through a graph coloring algorithm, colors each vertex in the undirected graph, and finally respectively allocates the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane. The above scheme determines the bounding boxes corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock as a vertex and performs graph coloring, and then allocates the clock plane, which can reasonably allocate the clock plane resources occupied by each clock in the target field programmable gate array in a targeted manner, alleviates the layout and wiring resource congestion problem caused by ultra-large-scale clocks, sets the minimum clock plane under the premise of ensuring that there is no clock conflict between the devices corresponding to each clock, improves resource utilization, and ensures the accuracy and effectiveness of clock distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 is a schematic flow chart of a clock distribution method according to an embodiment of the present invention;

[0039] Figure 2 is a flow chart of another clock distribution method according to an embodiment of the present invention;

[0040] Figure 3 is a clock distribution diagram according to an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram of a clock boundary box according to an embodiment of the present invention;

[0042] Figure 5 is an undirected graph according to an embodiment of the present invention;

[0043] Figure 6 is a graph coloring result graph according to an embodiment of the present invention;

[0044] Figure 7 is a diagram of clock plane allocation results according to an embodiment of the present invention;

[0045] Figure 8 is a structural block diagram of a clock distribution device according to an embodiment of the present invention;

[0046] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0048] Field Programmable Gate Array (FPGA) can be programmed to implement various complex digital logic functions. On the basis of configurability, it contains more complex clock architecture logic to achieve synchronous operation, control timing, optimize performance and simplify design. In the FPGA clock network architecture, a plane composed of clock wires of the same model is called a clock plane. A clock signal can only be transmitted on the same clock plane and cannot be transmitted across planes. Since the physical structure of the clock network in the field programmable gate array is pre-manufactured and cannot be modified later, the implemented functions cannot be adjusted for different application scenarios. In addition, for high-utilization designs, clock routing resources are usually limited, and the FPGA layout and wiring methods in related technologies have been difficult to support large-scale clock structures.

[0049] Therefore, an embodiment of the present invention provides a clock distribution method, which determines the bounding box corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, and then constructs an undirected graph with each clock as a vertex and performs graph coloring, and then distributes the clock plane, thereby ensuring the accuracy and effectiveness of clock distribution.

[0050] According to an embodiment of the present invention, a clock distribution method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0051] In this embodiment, a clock distribution method is provided, which can be used for desktop computers, notebook computers, servers, etc. Figure 1is a flow chart of a clock distribution method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0052] Step S101, obtaining the clock distribution of each device in the target field programmable gate array.

[0053] The target field programmable gate array is a field programmable gate array that needs to be clocked by the clock distribution method provided in this embodiment. When clocking the target field programmable gate array, it is first necessary to obtain the clock distribution of each device in the target field programmable gate array. The clock of each device can be obtained by the configuration tool provided by the target field programmable gate array, and the coordinates of each device can be obtained by the layout tool, thereby obtaining the clock distribution of each device.

[0054] Step S102: based on the clock distribution of each device in the target field programmable gate array, determine the boundary boxes corresponding to each clock of the target field programmable gate array respectively.

[0055] Based on the clocks and coordinates of each device in the target field programmable gate array, the devices belonging to the same clock are classified into one category using the clock as the classification standard, and the bounding box of the corresponding clock is determined according to the coordinates of the devices belonging to the same clock. For example, the coordinates of the upper left corner of the coordinates of the devices belonging to the same clock are used as the upper left corner coordinates of the bounding box, and the coordinates of the lower right corner of the coordinates of the devices belonging to the same clock are used as the lower right corner coordinates of the bounding box, and so on, to obtain the bounding boxes corresponding to each clock.

[0056] Step S103 , taking each clock of the target field programmable gate array as a vertex and constructing an undirected graph based on the bounding boxes corresponding to each clock.

[0057] An undirected graph is a set of vertices and edges. In this embodiment, each clock of the target field programmable gate array is set as a vertex of the undirected graph, and a preset rule is used to determine whether there is an undirected edge between each vertex. The undirected edge has no direction, and the relationship between the vertices at both ends of the undirected edge is bidirectional and symmetrical. The preset rule can be set according to actual needs. For example, if the bounding boxes corresponding to two clocks overlap, it indicates that the two clocks may conflict if they are in the same clock plane. Therefore, an undirected edge is added between the vertices corresponding to the two clocks to indicate that the two clocks are not assigned to the same clock plane.

[0058] Step S104, processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph.

[0059] The graph coloring algorithm marks the vertices or edges of the graph with different colors so that the colors of adjacent vertices are different. After the graph coloring algorithm is used to color the vertices of the undirected graph, the vertices at both ends of an undirected edge have different colors and the total number of colors used for coloring is the least, that is, there is no conflict between the bounding boxes corresponding to each clock and the total number of colors used for coloring is the least. Exemplarily, a greedy coloring algorithm, a Welch-Powell algorithm, a backtracking algorithm, or other graph coloring algorithms can be used to color the vertices in the undirected graph.

[0060] Step S105 , respectively assigning devices in the target field programmable gate array corresponding to vertices with the same color to the same clock plane.

[0061] Since there is no conflict between the bounding boxes corresponding to the clocks after coloring the vertices in the undirected graph and the total number of colored colors is the least, the vertices with the same color are grouped together. This can ensure that the number of groupings is the least under the premise that there is no conflict between the bounding boxes corresponding to the clocks, ensure that the number of clock planes required to be set is the least, and realize clock distribution accurately and effectively.

[0062] The clock distribution method provided in this embodiment first obtains the clock distribution of each device in the target field programmable gate array, then determines the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array, then takes each clock of the target field programmable gate array as a vertex, constructs an undirected graph based on the bounding boxes corresponding to each clock, then processes the undirected graph through a graph coloring algorithm, colors each vertex in the undirected graph, and finally allocates the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane. The above scheme determines the bounding boxes corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock as a vertex and performs graph coloring, and then allocates the clock plane, which can reasonably allocate the clock plane resources occupied by each clock in the target field programmable gate array in a targeted manner, alleviate the layout and routing resource congestion problem caused by ultra-large-scale clocks, and sets the minimum clock plane under the premise of ensuring that there is no clock conflict between the devices corresponding to each clock, thereby improving resource utilization and ensuring the accuracy and effectiveness of clock distribution.

[0063] In this embodiment, a clock distribution method is provided, which can be used for desktop computers, notebook computers, servers, etc. Figure 2 is a flow chart of a clock distribution method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0064] Step S201, obtaining the clock distribution of each device in the target field programmable gate array.

[0065] Specifically, the above step S201 includes:

[0066] Step S2011, establishing a grid coordinate system based on the target field programmable gate array.

[0067] A grid coordinate system is established based on the physical structure of the target field programmable gate array so that the position of each device in the target field programmable gate array is determined by the coordinates corresponding to each device in the grid coordinate system. Exemplarily, the grid coordinate system in the layout tool of the target field programmable gate array can be used.

[0068] Step S2012, obtaining the clock of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0069] Each device in the target field programmable gate array includes a clock buffer and other functional devices. The clock buffer includes a global clock buffer, a semi-global clock buffer, a regional clock buffer, an I / O clock buffer, etc. The distribution position and number of the clock buffers determine the propagation range and mode of each clock signal in the target field programmable gate array. Other functional devices rely on the corresponding clock buffers to distribute clock signals. Next, the coordinates of each clock buffer and each functional device in the grid coordinate system, the coverage of each clock buffer and the clock corresponding to each functional device are obtained as the clock distribution of each device in the target field programmable gate array.

[0070] Step S202: based on the clock distribution of each device in the target field programmable gate array, determine the boundary boxes corresponding to each clock of the target field programmable gate array respectively.

[0071] Specifically, based on the clocks of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system, the bounding box corresponding to each clock is calculated. Based on the clocks of each device and the coordinates of each device in the grid coordinate system, the upper left corner coordinates and the lower right corner coordinates of the bounding box corresponding to each clock are determined, and the center point coordinates corresponding to the bounding box are calculated according to the upper left corner coordinates and the lower right corner coordinates, which is convenient for positioning. It is also possible to combine the geometric algorithm to obtain the minimum circumscribed rectangle corresponding to each clock as the bounding box to improve the accuracy of the bounding box.

[0072] Optionally, a clock distribution diagram of each device in the target field programmable gate array can also be obtained. The clock distribution diagram is used to indicate the position of each device in the target field programmable gate array and the corresponding clock, and to distinguish the device corresponding to each clock by different identifications or colors.

[0073] For example, Figure 3 is a clock distribution diagram according to an embodiment of the present invention, such as Figure 3 As shown, taking the case where there are 6 clocks in the target field programmable gate array as an example, 6 colors of dots are used to mark the devices corresponding to each clock. Then, the bounding box corresponding to each clock can be determined based on the clock distribution map, for example, by using a deep learning model with a bounding box prediction function to process the clock distribution map to predict the bounding box corresponding to each clock. Figure 4 is a schematic diagram of a clock boundary box according to an embodiment of the present invention, such as Figure 4 As shown, a rectangular bounding box is filled with a color corresponding to each clock, and the rectangular bounding box is used to indicate the distribution position of the corresponding clock.

[0074] Step S203 , taking each clock of the target field programmable gate array as a vertex and constructing an undirected graph based on the bounding boxes corresponding to each clock.

[0075] Specifically, if there is a position overlap between the bounding boxes corresponding to any two clocks, an undirected edge is added between the vertices corresponding to the two clocks. For example, if there is a position overlap between the bounding box corresponding to the first clock and the bounding box corresponding to the second clock, it indicates that there is a conflict between the first clock and the second clock, and an undirected edge is added between the vertex corresponding to the first clock and the vertex corresponding to the second clock, and so on, and an exhaustive enumeration is performed to determine whether an undirected edge needs to be added between any two clocks in each clock.

[0076] For example, Figure 5 is an undirected graph according to an embodiment of the present invention, such as Figure 5 As shown, among the six clocks, there are undirected edges between the first clock and the third clock, the fourth clock, the fifth clock, and the sixth clock, there are undirected edges between the second clock and the third clock and the fourth clock, there is an undirected edge between the third clock and the sixth clock, and there is an undirected edge between the fourth clock and the fifth clock.

[0077] Step S204, processing the undirected graph by using a graph coloring algorithm to color each vertex in the undirected graph.

[0078] Specifically, the above step S204 includes:

[0079] Step S2041, determining the degree of each vertex in the undirected graph.

[0080] The degree of a vertex is the number of undirected edges connected to the vertex. When coloring each vertex in an undirected graph, first identify each vertex in the undirected graph and the number of undirected edges connected to each vertex.

[0081] Step S2042, arrange the vertices in descending order according to their degree to obtain a vertex arrangement order.

[0082] Coloring the vertices with larger degrees first helps improve coloring efficiency, so first arrange the vertices in descending order of degree, and get the vertex arrangement order to determine the coloring order.

[0083] Step S2043, coloring each vertex according to the vertex arrangement order.

[0084] Specifically, dye the first-order vertex in the vertex arrangement order into the first color, and then determine whether the second-order vertex is connected to the dyed vertex through an undirected edge, that is, whether it is connected to the first-order vertex through an undirected edge. If not, dye the second-order vertex into the first color; if so, dye the second-order vertex into the second color. Next, determine whether the third-order vertex is connected to the first-order vertex through an undirected edge. If not, dye the third-order vertex into the first color; if so, determine whether the third-order vertex is connected to the second-order vertex through an undirected edge. If so, dye the third-order vertex into the third color; if not, dye the third-order vertex into the second color. Repeat the above steps so that each pair of adjacent vertices connected by undirected edges are dyed with different colors until all vertices are dyed. Iterations can also be performed. For example, if there are multiple colors available for a vertex in the above steps, the vertex can be dyed with another color during the iteration time until all vertices are dyed. The total number of colors dyed in this round is counted and compared with the total number of colors dyed in the previous round, until the round with the least total number of dyed colors is selected as the optimal solution, which is the final graph coloring result.

[0085] For example, Figure 6 is a graph coloring result graph according to an embodiment of the present invention, such as Figure 6 As shown, the first vertex and the second vertex are dyed with the first color, the third vertex and the fifth vertex are dyed with the second color, and the fourth vertex and the sixth vertex are dyed with the third color. The final total number of colors is 3, and the dyeing colors between any two vertices connected by an undirected edge are different.

[0086] Step S205 , respectively assigning devices in the target field programmable gate array corresponding to vertices with the same color to the same clock plane.

[0087] There is no conflict in the clocks corresponding to the vertices with the same color, so the devices in the target field programmable gate array corresponding to the vertices with the same color can be allocated to the same clock plane, that is, the devices in the target field programmable gate array corresponding to the clocks without conflict are allocated to the same clock plane, so that clock allocation can be achieved. Since the total number of colors is guaranteed to be the minimum in step S204, the clock planes that need to be set are also the minimum, which ensures the accuracy and effectiveness of clock allocation.

[0088] For example, Figure 7 is a diagram showing the clock plane allocation result according to an embodiment of the present invention. Figure 7 As shown, the devices corresponding to the third clock and the devices corresponding to the fifth clock are allocated to clock plane 1, the devices corresponding to the sixth clock and the devices corresponding to the fourth clock are allocated to clock plane 2, and the devices corresponding to the first clock and the devices corresponding to the second clock are allocated to clock plane 3.

[0089] The clock distribution method provided in this embodiment first obtains the clock distribution of each device in the target field programmable gate array, then determines the bounding boxes corresponding to each clock of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array, then takes each clock of the target field programmable gate array as a vertex, constructs an undirected graph based on the bounding boxes corresponding to each clock, then processes the undirected graph through a graph coloring algorithm, colors each vertex in the undirected graph, and finally allocates the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane. The above scheme determines the bounding boxes corresponding to each clock based on the clock distribution of each device in the target field programmable gate array, then constructs an undirected graph with each clock as a vertex and performs graph coloring, and then allocates the clock plane, which can reasonably allocate the clock plane resources occupied by each clock in the target field programmable gate array in a targeted manner, alleviate the layout and routing resource congestion problem caused by ultra-large-scale clocks, and sets the minimum clock plane under the premise of ensuring that there is no clock conflict between the devices corresponding to each clock, thereby improving resource utilization and ensuring the accuracy and effectiveness of clock distribution.

[0090] In this embodiment, a clock distribution device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0091] This embodiment provides a clock distribution device, such as Figure 8 As shown, including:

[0092] An acquisition module 801 is used to acquire the clock distribution of each device in the target field programmable gate array;

[0093] A bounding box module 802 is used to determine the bounding boxes corresponding to the clocks of the target field programmable gate array based on the clock distribution of each device in the target field programmable gate array;

[0094] An undirected graph module 803, used to construct an undirected graph based on the bounding boxes corresponding to the clocks of the target field programmable gate array and taking the clocks of the target field programmable gate array as vertices;

[0095] A graph coloring module 804, used to process the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph;

[0096] The clock distribution module 805 is used to distribute the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

[0097] In an optional implementation, the acquisition module is further used to: establish a grid coordinate system based on the target field programmable gate array; and acquire the clock of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0098] In an optional implementation, the bounding box module is further used to calculate a bounding box corresponding to each clock based on the clock of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system.

[0099] In an optional implementation, the undirected graph module is further used to: if there is a position overlap between the bounding boxes corresponding to any two clocks, then add an undirected edge between the vertices corresponding to the two clocks.

[0100] In an optional implementation, the graph coloring module is further used to: determine the degree of each vertex in the undirected graph; arrange the vertices in descending order of degree to obtain a vertex arrangement order; and color the vertices according to the vertex arrangement order.

[0101] In an optional embodiment, the graph coloring module is also used to: color the first-ranked vertex in the vertex arrangement order as a first color; determine whether the second-ranked vertex is connected to the colored vertex through an undirected edge; if not, color the second-ranked vertex as the first color; if so, color the second-ranked vertex as a second color; repeat the above steps so that each pair of adjacent vertices connected by undirected edges are colored with different colors until all vertices are colored.

[0102] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0103] The clock distribution device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0104] The embodiment of the present invention also provides a computer device having the above Figure 8 The clock distribution device shown.

[0105] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0106] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0107] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0108] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0109] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0110] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Fig. 9 The example of connecting through bus is taken in the following.

[0111] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0112] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0113] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0114] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations shall all fall within the scope of protection of the present invention.

Claims

1. A clock distribution method, characterized in that: The method comprises: Obtaining clock distribution of each device in a target field programmable gate array; Based on the clock distribution of each device in the target field programmable gate array, respectively determine the bounding boxes corresponding to each clock of the target field programmable gate array; Taking each clock of the target field programmable gate array as a vertex, an undirected graph is constructed based on the bounding boxes corresponding to each clock; Processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph; The devices in the target field programmable gate array corresponding to the vertices with the same color are respectively allocated to the same clock plane.

2. The method according to claim 1, characterized in that The step of obtaining the clock distribution of each device in the target field programmable gate array includes: Establishing a grid coordinate system based on a target field programmable gate array; The clock of each device in the target field programmable gate array and the coordinates of each device in the grid coordinate system are obtained.

3. The method according to claim 2, characterized in that The step of determining the boundary boxes corresponding to the clocks of the target field programmable gate array based on the clock distribution of the devices in the target field programmable gate array comprises: Based on the clocks of the devices in the target field programmable gate array and the coordinates of the devices in the grid coordinate system, a bounding box corresponding to each clock is calculated.

4. The method according to any one of claims 1 to 3, characterized in that: The step of constructing an undirected graph based on the bounding boxes corresponding to the respective clocks includes: If there is position overlap between the bounding boxes corresponding to any two clocks, an undirected edge is added between the vertices corresponding to the two clocks.

5. The method according to claim 4, characterized in that Processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph includes: Determine the degree of each vertex in an undirected graph; Arrange each vertex in descending order according to the degree size to obtain the vertex arrangement order; Color each vertex according to the order in which the vertices are arranged.

6. The method according to claim 5, characterized in that The coloring of each vertex according to the vertex arrangement order comprises: Dye the first vertex in the vertex arrangement order as the first color; Determine whether the second-rank vertex is connected to the colored vertex through an undirected edge; if not, color the second-rank vertex with the first color; if so, color the second-rank vertex with the second color; Repeat the above steps so that each pair of adjacent vertices connected by undirected edges are colored with different colors until all vertices are colored.

7. A clock distribution device, characterized in that: The device comprises: An acquisition module, used to acquire the clock distribution of each device in the target field programmable gate array; A bounding box module, for determining the bounding boxes corresponding to the respective clocks of the target field programmable gate array based on the clock distribution of the respective devices in the target field programmable gate array; An undirected graph module, used for constructing an undirected graph based on bounding boxes corresponding to each clock, taking each clock of the target field programmable gate array as a vertex; A graph coloring module, used for processing the undirected graph by a graph coloring algorithm to color each vertex in the undirected graph; The clock distribution module is used to distribute the devices in the target field programmable gate array corresponding to the vertices with the same color to the same clock plane.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the clock distribution method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the clock distribution method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the clock distribution method according to any one of claims 1 to 6.

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