Assertion generation method for logic system design and related equipment

Abstract

The invention provides an assertion generation method for logic system design and related equipment. According to the method, the information of each clause included in the attribute description document designed by the logic system is identified and determined through the clause structure, so that the situation that the information of different clauses is mixed together to influence the identification of the final SVA is avoided. The operators and the signal information of each piece of clause information are recognized, and compared with direct generation of the SVA, the operators and the signal information of each clause are extracted firstly, so that the recognition accuracy of the current task can be ensured, and then two intermediate parameters, namely the operators and the signal information, are generated; the target assertion (SVA) of the logic system design can be accurately generated by combining the two intermediate parameters, and the efficiency and accuracy of SVA generation are improved.

Description

Technical Field

[0001] The present application relates to the field of computer software technology, and in particular to an assertion generation method and related equipment for logic system design. Background Art

[0002] SVA (SystemVerilog Assertion) is a language used to verify whether a design meets expected behavior. It is mainly used to check whether the behavioral characteristics of a design unit (DUT) meet expectations. It describes the design requirements by writing assertions and verifies whether these assertions hold during simulation to ensure the correctness of the design. SVA is widely used in both formal and simulation verification, especially in logic system design (for example, chip design), where it is used to prove whether requirements and design implementations are consistent.

[0003] In the current related technologies, the generation of logical system design assertions (SVA) is mainly completed manually by engineers. This not only requires high professional ability of engineers, but also the efficiency of manually generating SVA is low. Therefore, how to quickly and accurately generate logical system design assertions is an urgent problem to be solved. Summary of the invention

[0004] In view of this, the purpose of this application is to propose an assertion generation method for logic system design and related equipment to solve or partially solve the above technical problems.

[0005] In a first aspect of the present application, a method for generating assertions for a logic system design is provided, comprising:

[0006] Obtaining a property description document of the logic system design;

[0007] Determining each clause information included in the attribute description document through clause structure recognition;

[0008] Identify operators and signal information of each of the clause information;

[0009] A target assertion of the logic system design is generated based on operators and signal information of each of the clause information.

[0010] In a second aspect of the present application, an electronic device is provided, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to perform the method described in the first aspect.

[0011] According to a third aspect of the present application, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores a set of instructions for an electronic device, wherein the set of instructions is used to enable the electronic device to execute the method described in the first aspect.

[0012] The assertion generation method and related device for logic system design provided by the embodiment of the present application determine the clause information included in the attribute description document of the logic system design through clause structure recognition, so as to avoid mixing the information of different clauses together and affect the recognition of the final SVA. Then, the operator and signal information of each clause information are identified. Compared with directly generating SVA, the operator and signal information of each clause are first extracted to ensure the accuracy of the current task recognition, and then the two intermediate parameters of the operator and signal information are generated. After that, the target assertion (SVA) of the logic system design can be accurately generated by combining the two intermediate parameters together, thereby improving the efficiency and accuracy of SVA generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of the structure of an exemplary electronic device provided in an embodiment of the present application.

[0015] Figure 2 A flowchart of an exemplary method for an assertion generation method for a logic system design provided in an embodiment of the present application.

[0016] Figure 3 A flowchart of an exemplary method of an assertion generation method for another logic system design provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0019] Logical system design (e.g., chip design) can be written in a software programming language (e.g., Java, JavaScript, C, C++, or PHP (Hypertext Preprocessor)) or in a hardware programming language (e.g., Verilog, VHDL, System C, or System Verilog).

[0020] In the current related technologies, the generation of assertions (SVA) of logical system designs is mainly completed manually by engineers. This not only requires high professional ability of engineers, but also the efficiency of manually generating SVA is low. In addition, if the acquired attribute description document of the logical system design is directly input into the trained neural network model, and the neural network model outputs SVA, not only is the requirement for the model high, but also, because the model needs to directly abstract SVA based on the attribute description document, it is difficult to ensure that the model can accurately output the SVA corresponding to the current attribute description document every time.

[0021] Therefore, how to quickly and accurately generate assertions for logic system design is an urgent problem that needs to be solved.

[0022] In view of the above problems, the present application proposes an assertion generation method, electronic device and storage medium for logic system design.

[0023] Figure 1 A schematic diagram of the structure of an exemplary electronic device 100 provided in an embodiment of the present application.

[0024] like Figure 1 As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in the electronic device.

[0025] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0026] The memory 104 may be provided with a database in which data during operation (eg, instruction sets, computer codes, intermediate data, etc.) are stored. The simulation tool used for test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory 104 may include program instructions (e.g., program instructions for implementing the technical solution of the present application) and a database storing operation data (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and database stored in the memory. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0027] The network interface 106 can be configured to provide the electronic device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0028] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0029] The bus 110 can be configured to transmit information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0030] It should be noted that, although the structural architecture of the electronic device 100 only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the structural architecture of the electronic device 100 may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the structural architecture of the electronic device 100 may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0031] In the field of chip design, a design can usually be simulated using a simulation tool, such as the GalaxSim simulation tool produced by Xinhuazhang Technology Co., Ltd.

[0032] Figure 2 A flowchart of an exemplary method for an assertion generation method designed for a logic system according to an embodiment of the present application.

[0033] After the architecture engineer completes the design description file (spec) of the logical system design, the code engineer can write the design code document (design) according to the design description document (spec). At the same time, the design description file (spec) can also be used to generate SVA. In some embodiments, the design description document includes one or more of the design code document and the unfinished code document, that is, when the code engineer has completed the design file (design code file), the corresponding spec can be directly generated through the design file. The specific process may include first matching the signals in the design file with the names in the spec, and then extracting relevant information in the spec with the words with corresponding design signals as keywords, and judging whether there is a property description based on this information; if there is, prop generation is performed. When the code engineer has not completed the design file, the currently written code document can be scanned sentence by sentence to identify whether it can be translated into SVA, and if so, the part of the content is converted into prop. Optionally, both of the above two methods of generating prop can be completed by the semantic large model obtained through training.

[0034] In some embodiments, when prop is generated through unfinished code documentation, in order to improve recognition efficiency and accuracy, RAG (enhanced search generation) can be used to improve the efficiency and accuracy of semantic big model recognition. Specifically, when the semantic big model performs the above-mentioned generation task, the outline of the current logical system design can be obtained through the design description file (spec) and input into the semantic big model together, so that the semantic big model can have a deeper understanding of the context of the task currently being performed.

[0035] In the embodiment of the present application, in order to further improve the accuracy of SVA generation, the property description document (prop) corresponding to the design description file (spec) can be first obtained, and the property description document (prop) includes multiple property description statements. Optionally, in some embodiments, the property description document can be presented in the form of a table, which is not limited to this. After obtaining the property description document (prop) of the logical system design, the property description document (prop) can be split into multiple clauses according to clause structure recognition, for example Figure 2 Clause A to clause N in. Optionally, the process of clause structure recognition can be completed by the second semantic large model obtained through training, and then after obtaining multiple clauses corresponding to the attribute description document, the operator and signal information of each clause can be identified or marked through NER (named entity recognition). Optionally, the process of named entity recognition can be implemented by the first semantic large model obtained through training. In some implementations, operators generally include stability, equality, inequality, transition, GreaterThanOrEqualTo, LessThanOrEqualTo, and other operators. Signal information generally includes signal name, type (variable, parameter (commonly used to define the length of variable vectors), constant), length (scalar, vector), etc. After obtaining the operator and signal information of each clause, the target assertion (SVA) can be generated by assembly. Optionally, after obtaining the operator and signal information of each clause, the target assertion can be generated by the first generated large model obtained through training. In some embodiments, the generated target assertion can be one or more assertions. The specific data of the target assertion is generally less than or equal to the number of all clauses. Figure 2 , assuming that the number of assertions included in the target assertion is m, then m≤n. Optionally, the generated target assertion can be output in the form of a table, where each row in the table corresponds to an assertion. Optionally, the generated target assertion can also be output in the form of code, which is not limited.

[0036] In some embodiments, after the SVA is generated, the generated target assertion can also be verified. The specific verification method includes: first, a target program file including the target assertion is generated through the second generation large model obtained through training, and then the syntax of the SVA in the compiler verification is used to complete the generation of correct syntax by feedback of syntax errors; and / or, using the above-mentioned prediction information, verify whether the grammatically passed SVA contains the annotated signal name, operator and sentence structure, and feedback iteration. Optionally, this step can be completed through the third semantic large model obtained through training, that is, the grammatically passed SVA is input into the third semantic large model, and the third semantic large model is used to determine whether the grammatically passed SVA contains the previously identified signal name, operator and sentence structure. Optionally, in some embodiments, the method for verifying the generated target assertion also includes:

[0037] First, obtain multiple signals in the logic system design that are associated with the target assertion. The logic system design can be a logic system design corresponding to the target assertion generated in the implementation of this application, or a logic system design that is associated with the generated target assertion. For example, it can be a historical logic system design with a similar usage scenario to the logic system design corresponding to the target assertion generated previously, or a historical logic system design before the iterative update of the logic system design corresponding to the target assertion. The specific acquisition of the logic system design can be selected according to actual conditions, and there is no limitation on this. After obtaining multiple signals in the logic system design that are associated with the target assertion, the multiple assertion states of the target assertion in the multiple operating cycles can be determined respectively according to the values ​​of these signals in multiple operating cycles; the assertion state includes assertion success or assertion failure; then verify whether the target assertion is correct according to the multiple assertion states. If the multiple assertion states are all assertion success, it can be determined that the target assertion is correct. If the multiple assertion states include assertion failure, it can be determined that the target assertion is wrong.

[0038] In addition, in some embodiments, manual feedback from users may be used to indicate whether the final generated result is correct.

[0039] It should be noted that the various large models in the embodiments of the present application can be obtained by training the existing large models in the relevant technology, and the specific process of training the model is not limited.

[0040] Figure 3 A flowchart of an exemplary method of another assertion generation method for a logic system design provided in an embodiment of the present application. The method comprises the following steps:

[0041] Step S101, obtaining a property description document of the logic system design.

[0042] Step S102: determining each clause information included in the attribute description document through clause structure recognition.

[0043] Step S103, identifying the operator and signal information of each clause information.

[0044] Step S104: generating a target assertion of the logic system design based on the operators and signal information of each of the clause information.

[0045] In some embodiments, the signal information includes a signal name, a signal type, and a signal length.

[0046] In some embodiments, identifying the operator and signal information of each of the clause information specifically includes:

[0047] The first semantic large model obtained through training recognizes the operators and signal information of each of the clause information.

[0048] In some embodiments, the clause structure identification is used to determine each clause information included in the attribute description document, specifically including:

[0049] The second semantic large model obtained through training is used to perform clause structure recognition to determine each clause information included in the attribute description document.

[0050] In some embodiments, after generating the target assertion of the logic system design based on the operators and signal information of each of the clause information, the method further includes:

[0051] Verify whether the target assertion is correct;

[0052] In response to determining that the target assertion is incorrect, the target assertion is regenerated.

[0053] In some embodiments, verifying whether the target assertion is correct specifically includes:

[0054] The third semantic large model obtained through training identifies the prediction operator and prediction signal information of each clause information corresponding to the target assertion;

[0055] Whether the target assertion is correct is verified based on the prediction operator, the prediction signal information, the operator, and the signal information.

[0056] In some embodiments, verifying whether the target assertion is correct specifically includes:

[0057] Acquire a plurality of signals in the logic system design that are associated with the target assertion;

[0058] Based on the values ​​of the multiple signals in multiple operation cycles, respectively determine multiple assertion states of the target assertion in the multiple operation cycles; the assertion state includes assertion success or assertion failure;

[0059] Verify whether the target assertion is correct based on the multiple assertion states.

[0060] In some embodiments, obtaining the property description document of the logic system design specifically includes:

[0061] Obtaining a design description document of the logic system design; the design description document includes one or more of a design code document and an unfinished code document;

[0062] The property description document is generated through the design description document.

[0063] The embodiment of the present application also provides an assertion generation method for logic system design, which determines the clause information included in the attribute description document of the logic system design through clause structure recognition, so as to avoid mixing the information of different clauses together and affecting the recognition of the final SVA. Then, the operator and signal information of each clause information are identified. Compared with directly generating SVA, first extracting the operator and signal information of each clause can ensure the accuracy of the current task recognition, and then generating the two intermediate parameters of the operator and signal information. After that, the target assertion (SVA) of the logic system design can be accurately generated by combining these two intermediate parameters, thereby improving the efficiency and accuracy of SVA generation. In addition, in some embodiments of the present application, a large language model is introduced on the basis of structured parsing and generation to solve the problem of semantic understanding, effectively improving the accuracy of SVA code statement generation, avoiding the technical problems of lack of structured thinking and poor reasoning ability existing in the simple use of large language models, and avoiding the technical defects of existing compilation technology in understanding and processing natural language (Recursive Descent Parsing, NLP model such as Bert) and being unable to understand semantically ambiguous expressions. The embodiment of the present application also provides an electronic device. The electronic device can be Figure 1 The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device executes the assertion generation method for logic system design as described above.

[0064] The embodiment of the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores a set of computer instructions, and when the set of instructions is executed, the electronic device executes the assertion generation method of the logic system design as described above.

[0065] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0066] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0067] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0068] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0069] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0070] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A method for generating assertions for logic system design, comprising: Obtaining a property description document of the logic system design; Determining each clause information included in the attribute description document through clause structure recognition; Identify operators and signal information of each of the clause information; A target assertion of the logic system design is generated based on operators and signal information of each of the clause information.

2. The method according to claim 1, wherein: The signal information includes signal name, signal type and signal length.

3. The method according to claim 1, wherein: Identify the operators and signal information of each of the clause information, specifically including: The first semantic large model obtained through training recognizes the operators and signal information of each of the clause information.

4. The method according to claim 1, wherein: The clause structure identification is used to determine the clause information included in the attribute description document, specifically including: The second semantic large model obtained through training is used to perform clause structure recognition to determine each clause information included in the attribute description document.

5. The method according to claim 1, wherein: After generating the target assertion of the logic system design based on the operators and signal information of each of the clause information, the method further includes: Verify whether the target assertion is correct; In response to determining that the target assertion is incorrect, the target assertion is regenerated.

6. The method according to claim 5, wherein: Verify whether the target assertion is correct, including: The third semantic large model obtained through training identifies the prediction operator and prediction signal information of each clause information corresponding to the target assertion; Whether the target assertion is correct is verified based on the prediction operator, the prediction signal information, the operator, and the signal information.

7. The method according to claim 5, wherein: Verify whether the target assertion is correct, including: Acquire a plurality of signals in the logic system design that are associated with the target assertion; Based on the values ​​of the multiple signals in multiple operation cycles, respectively determine multiple assertion states of the target assertion in the multiple operation cycles; the assertion state includes assertion success or assertion failure; Verify whether the target assertion is correct based on the multiple assertion states.

8. The method according to claim 1, wherein: Obtain the attribute description document of the logic system design, including: Obtaining a design description document of the logic system design; the design description document includes one or more of a design code document and an unfinished code document; The property description document is generated through the design description document.

9. An electronic device, comprising: a memory for storing a set of instructions; as well as At least one processor is configured to execute the set of instructions to perform the method according to any one of claims 1 to 8.

10. A non-transitory computer-readable storage medium storing a set of instructions for a computer, the set of instructions being used to cause the computer to perform the method of any one of claims 1 to 8 when executed.

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