Electric energy control circuit, read-write circuit and memory

Abstract

The invention provides an electric energy control circuit, a read-write circuit and a memory, and relates to the technical field of memories. The electric energy control circuit comprises a first control circuit, a second control circuit, a sampling feedback circuit and an output selection circuit, the first input end of the first control circuit receives a clock signal, and the second input end receives an electric energy control signal; the control end of the sampling feedback circuit is connected with the output end of the first control circuit, the input end is connected with the output end of a bit line pre-charging circuit or a word line power circuit in the read-write circuit, and the output end is connected with the input end of the second control circuit; the output end of the first control circuit and the output end of the second control circuit are connected with the first input end and the second input end of the output selection circuit respectively, and the third input end of the output selection circuit receives clock signals. And the output end of the output selection circuit is connected with the control end of the bit line pre-charging circuit or the word line power supply circuit. According to the invention, the pre-charging state of the bit line or the power supply state of the word line can be adaptively adjusted.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a power control circuit, a read-write circuit and a memory. Background Art

[0002] With the continuous advancement of contemporary technology, the chip area of ​​memory has become smaller. As an important component of the memory, the read-write unit is directly connected to many modules. The optimization of most modules in the memory will have an impact on it, so the read-write unit often becomes the module with the most complex structure.

[0003] Before the read / write unit reads and writes the storage array in the memory, the bit lines of the storage array are precharged first, and then the word lines of some storage cells in the storage array are controlled to be raised to a high level.

[0004] However, in the prior art, whether it is a precharging circuit for precharging the bit line or a power supply circuit for supplying power to the word line, it can only maintain a precharging state or a power supply state, and cannot flexibly adjust the precharging state or the power supply state. Summary of the invention

[0005] The purpose of the present application is to provide a power control circuit, a read / write circuit and a memory to address the deficiencies in the above-mentioned prior art, so as to realize adaptive adjustment of the pre-charge state of the bit line or the power supply state of the word line.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: In a first aspect, an embodiment of the present application provides a power control circuit, the power control circuit comprising: a first control circuit, a second control circuit, a sampling feedback circuit and an output selection circuit; The first input terminal of the first control circuit is used to receive a preset clock signal, and the second input terminal of the first control circuit is used to receive a preset power control signal, so that the first control circuit generates a first control signal based on the preset power control signal and the preset clock signal; The control end of the sampling feedback circuit is connected to the output end of the first control circuit, the input end of the sampling feedback circuit is used to connect to the output end of the bit line precharge circuit or the word line power supply circuit in the read / write circuit, and the output end of the sampling feedback circuit is connected to the input end of the second control circuit, so that the second control circuit outputs a second control signal based on the sampling feedback signal; The output end of the first control circuit and the output end of the second control circuit are connected to the first input end and the second input end of the output selection circuit respectively, and the third input end of the output selection circuit is used to receive the preset clock signal, so that the output selection circuit outputs the target power control signal based on the preset clock signal, the first control signal and the second control signal; The output end of the output selection circuit is used to connect to the control end of the bit line precharge circuit or the word line power supply circuit to control the bit line precharge circuit or the word line power supply circuit to provide power to the corresponding bit line or word line according to the output target power control signal.

[0007] Optionally, the first control circuit includes: a first NAND gate, a first NOT gate, and a second NOT gate; The first input end of the first NAND gate serves as the first input end of the first control circuit, the input end of the first NOT gate serves as the second input end of the first control circuit, the output end of the first NOT gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate serves as the output end of the first control circuit; When the preset clock signal is at a high level, the first control signal is a negated signal of the preset power control signal.

[0008] Optionally, the second control circuit includes: a voltage-dividing sampling protection circuit and a Schmitt trigger; The input end of the voltage-dividing sampling protection circuit serves as the feedback input end of the second control circuit, the output end of the voltage-dividing sampling protection circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger serves as the output end of the second control circuit.

[0009] Optionally, the voltage-dividing sampling protection circuit comprises: a voltage-dividing sampling circuit, a first switching tube and a protection resistor; The input end of the voltage-dividing sampling circuit serves as the input end of the voltage-dividing sampling protection circuit, the output end of the voltage-dividing sampling circuit is connected to the gate of the first switching tube, one of the source or drain of the first switching tube is used to connect to a preset power supply voltage, the other of the source or drain of the first switching tube is connected to the protection resistor, and the connection point serves as the output end of the voltage-dividing sampling protection circuit.

[0010] Optionally, the output selection circuit includes: a first NOR gate and a second NOR gate; The first input end of the first NOR gate and the first input end of the second NOR gate serve as the first input end and the second input end of the output selection circuit respectively, the second input end of the first NOR gate serves as the third input end of the output selection circuit, the output end of the first NOR gate is connected to the second input end of the second NOR gate, and the output end of the second NOR gate serves as the output end of the output selection circuit.

[0011] Optionally, the sampling feedback circuit includes: a second switch tube; One of the source or the drain of the second switch tube is connected to the bit line end of the bit line precharging circuit or the word line voltage end of the word line power supply circuit, the gate of the second switch tube serves as the control end of the sampling feedback circuit, and the other of the source or the drain of the second switch tube serves as the output end of the sampling feedback circuit.

[0012] Optionally, the sampling feedback circuit includes: a third switch tube and a fourth switch tube; One of the source or drain of the third switch tube is used to connect to the bit line end of the bit line precharging circuit, and one of the source or drain of the fourth switch tube is used to connect to the complementary bit line end of the bit line precharging circuit; The gate of the third switch tube and the gate of the fourth switch tube are connected as the control end of the sampling feedback circuit, and the other of the source or drain of the third switch tube and the other of the source or drain of the fourth switch tube are connected to the output end of the sampling feedback circuit.

[0013] In a second aspect, an embodiment of the present application further provides a read-write circuit, the read-write circuit comprising: a plurality of read-write units, a plurality of bit line precharging circuits, a plurality of word line power supply circuits and a power control circuit; Each read-write unit is used to connect at least one bit line in the storage array, the multiple bit line precharging circuits are also connected to the multiple bit lines in the storage array, the control ends of the multiple bit line precharging circuits are all connected to the power control circuit, and the power control circuit is a circuit as described in any one of the first aspects; the multiple word line power supply circuits are respectively connected to the multiple word lines of the storage array.

[0014] In a third aspect, an embodiment of the present application further provides a read-write circuit, the read-write circuit comprising: a plurality of read-write units, a plurality of bit line precharging circuits, a plurality of word line power supply circuits, and a plurality of power control circuits; Each read / write unit is connected to at least one bit line in the storage array, and the plurality of bit line precharging circuits are respectively connected to a plurality of bit lines in the storage array; The multiple word line power supply circuits are respectively connected to the multiple word lines of the storage array, and the control ends of the multiple word line power supply circuits are respectively connected to the multiple power control circuits, and the multiple power control circuits are circuits as described in any one of the first aspects.

[0015] In a fourth aspect, an embodiment of the present application further provides a memory, which includes a read-write circuit and a storage array as described in the second aspect or the third aspect.

[0016] The beneficial effects of this application are: The power control circuit, read-write circuit and memory provided by the present application, when it is determined that the memory is in a working state based on a preset clock signal, the bit line pre-charging circuit is controlled to pre-charge the bit line according to the target power control signal generated by the preset power control signal, or the word line power supply circuit is controlled to charge the word line; when it is determined that the memory is in a sleep state based on the preset clock signal, the bit line pre-charging circuit is controlled to pre-charge the bit line according to the target power control signal generated by the sampling feedback signal, or the word line power supply circuit is controlled to charge the word line, so as to realize adaptive adjustment of the bit line voltage or the word line voltage. The power control circuit has higher flexibility and can effectively improve the speed of the memory recovering from the sleep state to the working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a circuit diagram of an existing pre-charging circuit; Figure 2 A block diagram of the power control circuit provided in the embodiment of the present application; Figure 3 The circuit of the power control circuit provided in the embodiment of the present application Figure 1 ; Figure 4 The circuit of the power control circuit provided in the embodiment of the present application Figure 2 ; Figure 5 A waveform diagram provided for an embodiment of the present application; Figure 6 The principle frame of the read-write circuit provided in the embodiment of the present application Figure 1 ; Figure 7 The principle frame of the read-write circuit provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0020] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0021] In addition, the terms "first", "third", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0023] Hereinafter, the defects of the prior art will be described by taking the prior art pre-charging circuit as an example.

[0024] For example, Figure 1 It is a circuit diagram of an existing pre-charging circuit, such as Figure 1 As shown, before the read / write unit reads or writes the storage unit, the existing pre-charging circuit has a bit line pre-charging control signal BLPR at a low level, three PMOS tubes IP1, IP2 and IP3 at an on state, the bit line (Bit Line, BL) and the complementary bit line (Bit Line Bar, BLB) are connected, and the power supply VDD is pre-charged at an equal voltage through the balancing tubes IP1 and IP, so that BL and BLB are at an equal voltage high level when the storage unit is performing a read / write operation, and the pre-charging is turned off when the storage unit starts to read or write.

[0025] It can be seen that the bit line pre-charge control signal BLPR in the existing pre-charging circuit has only one gear, and can only control the pre-charging circuit to turn on or off pre-charging when the memory is in the working state. It cannot meet the requirement of how to ensure the voltage of the bit line and the complementary bit line when the memory is in the sleep state. Therefore, it is impossible to quickly restore the voltage of the bit line and the complementary bit line when the memory is restored from the sleep state to the working state.

[0026] Similarly, the existing power supply circuit for supplying power to the word line also has the same problem.

[0027] Based on the above-mentioned defects of the prior art, the present application intends to provide a power control circuit that can be applied to a bit line precharge circuit or a word line power supply circuit in a read / write circuit.

[0028] Figure 2 The principle block diagram of the power control circuit provided in the embodiment of the present application is as follows: Figure 2 As shown, the power control circuit 100 includes: a first control circuit 101 , a second control circuit 102 , a sampling feedback circuit 103 and an output selection circuit 104 .

[0029] The first input terminal of the first control circuit 101 is used to receive a preset clock signal CK, and the second input terminal of the first control circuit 101 is used to receive a preset power control signal Power Control_0, so that the first control circuit 101 generates a first control signal Control based on the preset power control signal Power Control_0 and the preset clock signal CK.

[0030] The control end of the sampling feedback circuit 103 is connected to the output end of the first control circuit 101, the input end of the sampling feedback circuit 103 is used to connect to the output end of the bit line precharge circuit or the word line power supply circuit in the read / write circuit, and the output end of the sampling feedback circuit 103 is connected to the input end of the second control circuit 102, so as to enable the second control circuit 102 to output the second control signal Control_Feedback based on the sampling feedback signal Feedback.

[0031] The output end of the first control circuit 101 and the output end of the second control circuit 102 are respectively connected to the first input end and the second input end of the output selection circuit 104. The third input end of the output selection circuit 104 is used to receive the preset clock signal CK, so that the output selection circuit 104 outputs the target power control signal Power Control_1 based on the preset clock signal CK, the first control signal Control and the second control signal Control_Feedback.

[0032] The output end of the output selection circuit 104 is used to connect to the control end of the bit line precharge circuit or the word line power circuit to control the bit line precharge circuit or the word line power circuit to provide power to the corresponding bit line or word line according to the output target power control signal Power Control_1.

[0033] In this embodiment, the first control circuit 101 generates a first control signal Control based on a preset power control signal Power Control_0 and a preset clock signal CK, and the control logic for generating the first control signal Control is that when the preset clock signal CK is a high-level signal, the first control signal Control is generated according to the preset power control signal Power; when the preset clock signal CK is a low-level signal, the first control signal Control is a fixed low-level signal.

[0034] The second control circuit 102 generates a second control signal Control_Feedback based on the sampling feedback signal Feedback provided by the sampling feedback circuit 103, wherein when the sampling feedback signal Feedback indicates that the bit line voltage of the bit line pre-charging circuit or the word line voltage of the word line power supply circuit is less than a preset voltage value, the second control signal Control_Feedback is a low level signal, and when the sampling feedback signal Feedback indicates that the bit line voltage of the bit line pre-charging circuit or the word line voltage of the word line power supply circuit is full voltage, the second control signal Control_Feedback is a high level signal.

[0035] The preset clock signal CK is also a selection indication signal of the output selection circuit 104, which is used to indicate whether to generate the target power control signal Power Control_1 according to the first control signal Control of the first control circuit 101, or to generate the target power control signal Power Control_1 according to the second control signal Control_Feedback of the second control circuit 102. When the preset clock signal CK is a high-level signal, the first control circuit 101 works, and the output selection circuit 104 generates the target power control signal Power Control_1 according to the first control signal Control. Since the first control circuit 101 generates the first control signal Control according to the preset power control signal Power when the preset clock signal CK is a high-level signal, the output selection circuit 104 generates the target power control signal Power Control_1 according to the preset power control signal PowerControl_0 when the preset clock signal CK is a high-level signal.

[0036] When the preset clock signal CK is a low level signal, the second control circuit 102 is activated, and the output selection circuit 104 generates the target power control signal Power Control_1 according to the second control signal Control_Feedback. Since the second control signal Control_Feedback is generated based on the sampled feedback signal Feedback, when the preset clock signal CK is a low level signal, the output selection circuit 104 generates the target power control signal Power Control_1 according to the pre-sampled feedback signal Feedback.

[0037] The preset clock signal CK is a clock signal obtained by performing a logical operation on the logic clock signal of the memory where the read / write circuit is located and the sleep signal. When the logic clock signal indicates that the memory is in a working state for read / write operations, the preset clock signal CK is a high-level signal. The target power control signal Power Control_1 is generated according to the preset power control signal Power to control whether the bit line pre-charging circuit pre-charges the bit line, or controls whether the word line power supply circuit charges the word line to make the word line reach a high level. When the sleep signal indicates that the memory is in a sleep state and no read or write operations are performed, the preset clock signal CK is a low-level signal, and the target power control signal Power Control_1 is generated according to the feedback control signal Feedback, so that when the voltage of the bit line or word line decreases and is less than the preset voltage value, the bit line pre-charge circuit is re-controlled to pre-charge the bit line, or the word line power supply circuit is controlled to charge the word line. When the voltage of the bit line or word line is full voltage, the bit line pre-charge circuit is controlled to stop pre-charging the bit line, or the word line power supply circuit is controlled to stop charging the word line, to ensure that the line voltage of the bit line or word line is maintained at the level required for the read and write operations, so that the bit line or word line can be quickly awakened when the memory re-enters the working state.

[0038] The power control circuit provided in the above embodiment controls the bit line pre-charging circuit to pre-charge the bit line or controls the word line power supply circuit to charge the word line according to the target power control signal generated by the preset power control signal when the memory is determined to be in the working state based on the preset clock signal; and controls the bit line pre-charging circuit to pre-charge the bit line or controls the word line power supply circuit to charge the word line according to the target power control signal generated by the sampling feedback signal when the memory is determined to be in the sleep state based on the preset clock signal, so as to realize adaptive adjustment of the bit line voltage or the word line voltage. The power control circuit has higher flexibility and can effectively improve the speed of the memory recovering from the sleep state to the working state.

[0039] Figure 3 The circuit of the power control circuit provided in the embodiment of the present application Figure 1 ,like Figure 3As shown, taking the sampling feedback circuit and the second output circuit connected to the bit line precharge circuit in the read / write circuit as an example, the first control circuit 101 may include: a first NAND gate NAND1, a first NOT gate NOT1, and a second NOT gate NOT2.

[0040] The first input end of the first NAND gate NAND1 serves as the first input end of the first control circuit 101, the input end of the first NOT gate NOT1 serves as the second input end of the first control circuit 101, the output end of the first NOT gate NOT1 is connected to the second input end of the first NAND gate NAND1, the output end of the first NAND gate NAND1 is connected to the input end of the second NOT gate NOT2, and the output end of the second NOT gate NOT2 serves as the output end of the first control circuit 101; when the preset clock signal CK is at a high level, the first control signal Control is an inverted signal of the preset power control signal Power Control_0.

[0041] In the present embodiment, the preset power control signal Power Control_0 is the bit line precharge signal BLPRB, the target power control signal Power_Control_1 is PRB_Control, and the working principle of the first control circuit 101 is: when the preset clock signal CK is a high level 1, if the preset power control signal Power Control_0 is a high level 1, a low level 0 is output through the first NOT gate NOT1, the low level 0 and the high level 1 are output through the first NAND gate NAND1, and the high level 1 is output through the second NOT gate NOT2; if the preset power control signal Power Control_0 is a low level 0, a high level 1 is output through the first NOT gate NOT1, the high level 1 and the high level 1 are output through the first NAND gate NAND1, and the low level 0 is output through the second NOT gate NOT2. High level 1, therefore, when the preset clock signal CK is a high level 1, if the preset power control signal Power Control_0 is a high level 1, Control_0 is at a high level 1, and the output of the first control circuit 101 is at a low level. If the preset power control signal PowerControl_0 is at a low level 0, the output of the first control circuit 101 is at a high level 1.

[0042] At this time, since the output selection circuit 104 selects the preset power control signal Power Control_0 as the target power control signal Power Control_1, if the target power control signal Power Control_1 is high level 1, the bit line pre-charging circuit is controlled to pre-charge the bit line. Similarly, if the word line power supply circuit is connected, the word line power supply circuit is controlled to supply power to the word line; if the target power control signal Power Control_1 is low level 0, the bit line pre-charging circuit is controlled to stop pre-charging the bit line. Similarly, if the word line power supply circuit is connected, the word line power supply circuit is controlled to stop supplying power to the word line.

[0043] When the preset clock signal CK is a low level 0, if the preset power control signal Power Control_0 is a high level 1, no matter the preset power control signal Power Control_0 is a high level 1 or a low level 0, the output of the first NAND gate NAND1 is a high level 1, and the output of the second NOT gate NOT2 is a low level 0. Therefore, when the preset clock signal CK is a low level 0, the output of the first control circuit 101 is a low level.

[0044] In one possible implementation, Figure 3 As shown, the second control circuit 102 may include: a voltage-dividing sampling protection circuit 121 and a Schmitt trigger 122 .

[0045] The input end of the voltage-dividing sampling protection circuit 121 serves as the feedback input end of the second control circuit 102 , the output end of the voltage-dividing sampling protection circuit 121 is connected to the input end of the Schmitt trigger 122 , and the output end of the Schmitt trigger 122 serves as the output end of the second control circuit 102 .

[0046] In this embodiment, the input end of the voltage-dividing sampling protection circuit 121 is connected to the output end of the sampling feedback circuit 103 to receive the sampling feedback signal Feedback, and outputs a trigger control signal according to the voltage-dividing signal of the sampling feedback signal Feedback to trigger the Schmitt trigger 122 .

[0047] Among them, the structure of Schmitt trigger 122 is as follows Figure 3 As shown, it is composed of PMOS tubes IP1, IP2, IP3 and NMOS tubes IN1, IN2 and IN3. When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is lower than the preset voltage value, such as 60% of the power supply voltage, the voltage-dividing sampling protection circuit 121 outputs a high-level trigger control signal, and the high-level trigger control signal controls IN1 and IN2 of the Schmitt trigger 122 to be turned on, and the output end of the Schmitt trigger 122 outputs a low-level second control signal Control_Feedback.

[0048] When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage reaches the full voltage, that is, the voltage supply, the voltage-dividing sampling protection circuit 121 outputs a low-level trigger control signal, and the low-level trigger control signal controls IP1 and IP2 of the Schmitt trigger 122 to turn on, and the output end of the Schmitt trigger 122 outputs a high-level second control signal Control_Feedback.

[0049] In some embodiments, Figure 3As shown, the voltage-dividing sampling protection circuit 121 may include: a voltage-dividing sampling circuit, a first switch tube IP0 and a protection resistor R3.

[0050] The input end of the voltage-dividing sampling circuit serves as the input end of the voltage-dividing sampling protection circuit 121, and the output end of the voltage-dividing sampling circuit is connected to the gate of the first switch tube IP0. One of the source or drain of the first switch tube IP0 is used to connect to the preset power supply voltage VDD, and the other of the source or drain of the first switch tube IP0 is connected to the protection resistor R3, and the connection point serves as the output end of the voltage-dividing sampling protection circuit 121.

[0051] In this embodiment, the voltage-dividing sampling circuit is composed of resistors R1 and R2, one end of the resistor R1 serves as the input end of the voltage-dividing sampling protection circuit 121, the other end of the resistor R1 is connected to one end of the resistor R2, the connection point of which is connected to the gate of the first switch tube IP0, and the other end of the resistor R2 is grounded.

[0052] When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is lower than the preset voltage value, after the voltage is divided by the resistors R1 and R2 in the voltage divider sampling circuit, P0P is at a low level, the first switch tube IP0 is controlled to be turned on, the connection point between the first switch tube IP0 and the protection resistor R3 is at a high level, IN1 and IN2 of the Schmitt trigger 122 are controlled to be turned on, and the output end of the Schmitt trigger 122 outputs a low-level second control signal Control_Feedback.

[0053] When the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage reaches the full voltage, after the voltage is divided by the resistors R1 and R2 in the voltage divider sampling circuit, P0P is at a high level, and the first switch tube IP0 is controlled to be turned off. The connection point between the first switch tube IP0 and the protection resistor R3 is at a low level, and IP1 and IP2 of the Schmitt trigger 122 are controlled to be turned on, and the output end of the Schmitt trigger 122 outputs a high-level second control signal Control_Feedback.

[0054] For example, the resistance ratio of the resistors R1 and R2 is 3:7. If the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is lower than 60% of the power supply voltage, P0P is lower than 42% of the power supply voltage, the first switch tube IP0 is turned on, and the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is 100% voltage, P0P is 70% of the high level voltage, and the first switch tube IP0 is turned off.

[0055] In one possible implementation, Figure 3 As shown, the output selection circuit 104 may include: a first NOR gate NOR1 and a second NOR gate NOR2.

[0056] The first input terminal of the first NOR gate NOR1 and the first input terminal of the second NOR gate NOR2 serve as the first input terminal and the second input terminal of the output selection circuit 104 respectively, the second input terminal of the first NOR gate NOR2 serves as the third input terminal of the output selection circuit 104, the output terminal of the first NOR gate NOR1 is connected to the second input terminal of the second NOR gate NOR2, and the output terminal of the second NOR gate NOR2 serves as the output terminal of the output selection circuit 104.

[0057] In this embodiment, if Figure 3 As shown, the first NOR gate NOR1 inputs the preset clock signal CK and the second control signal Control_Feedback respectively, and the second NOR gate NOR2 inputs the first control signal Control and the output signal of the first NOR gate NOR1 respectively.

[0058] The working principle of the output selection circuit 104 is: When the preset clock signal CK is a high level 1, no matter the second control signal Control_Feedback is a high level 1 or a low level 0, the output of the first NOR gate NOR1 is always a low level 0. At this time, if the preset power control signal PowerControl_0 is a low level 0, the output of the first control circuit 101 is a high level 1. After the high level 1 and the low level 0 are NORed, the output of the second NOR gate NOR2 is a low level 0, that is, the preset power control signal Power Control_0 is a low level 0, and the target power control signal Power Control_1 is also a low level 0; if the preset power control signal Power Control_0 is a high level 1, the output of the first control circuit 101 is a low level 0. After the low level 0 and the low level 0 are NORed, the output of the second NOR gate NOR2 is a high level 1, that is, the preset power control signal Power Control_0 is a high level 1, and the target power control signal PowerControl_1 is also a high level 1. Therefore, when the preset clock signal CK is at a high level, the target power control signal Power Control_1 is determined by the preset power control signal Power Control_0 , and the target power control signal Power Control_1 is in phase with the preset power control signal Power Control_0 .

[0059] When the preset clock signal CK is at a low level 0, no matter the preset power control signal Power Control_0 is at a high level 1 or a low level 0, the first control signal Control is at a low level 0. At this time, if the second control signal Control_Feedback is at a low level 0, the first NAND gate NOR1 outputs a high level 1, and the second NAND gate NOR2 outputs a low level 0, that is, the second control signal Control_Feedback is at a low level 0, and the target power control signal Power Control_1 is also at a low level 0; if the second control signal Control_Feedback is at a high level 1, the first NAND gate outputs a low level 0, and the second NAND gate NOR2 outputs a high level 1, that is, the second control signal Control_Feedback is at a high level 1, and the target power control signal Power Control_1 is also at a high level 1. Therefore, when the preset clock signal CK is at a low level, the target power control signal Power Control_1 is determined by the sampling feedback signal Feedback, and the target power control signal Power Control_1 is in phase with the second control signal Control_Feedback.

[0060] It can be seen that when the sampling feedback signal Feedback indicates that the bit line voltage or the word line voltage is less than the preset voltage value, the target power control signal Power Control_1 controls the bit line pre-charging circuit to start pre-charging, or controls the word line power supply circuit to supply power. When the bit line voltage or the word line voltage reaches the full voltage, the target power control signal Power Control_1 controls the bit line pre-charging circuit to turn off pre-charging, or controls the word line power supply circuit to stop supplying power. In this way, the bit line pre-charging circuit will not always pre-charge the bit line, and the word line power supply circuit will not always supply power to the word line. The bit line voltage or the word line voltage will remain within a certain range and can be used in the sleep state.

[0061] Figure 4 The circuit of the power control circuit provided in the embodiment of the present application Figure 2 ,like Figure 4 As shown, taking the sampling feedback circuit and the second output circuit connected to the word line power supply circuit in the read-write circuit as an example, the sampling feedback circuit 103 may include: a second switch tube IP9.

[0062] One of the source or drain of the second switch tube IP9 is connected to the bit line end of the bit line precharging circuit or the word line voltage end of the word line power supply circuit, the gate of the second switch tube IP9 serves as the control end of the sampling feedback circuit 103, and the other of the source or drain of the second switch tube IP9 serves as the output end of the sampling feedback circuit 103.

[0063] In this embodiment, the preset power control signal Power Control_0 is the word line power signal WLPRB, and the target power control signal Power_Control_1 is VWL_Control. If the memory array of the memory includes a bit line BL, the bit line end of the bit line precharging circuit is connected to the bit line BL of the memory array, and the sampling feedback circuit 103 includes a second switch tube IP9, one of the source or the drain of the second switch tube IP9 is connected to the bit line end of the bit line precharging circuit to sample the bit line voltage of the bit line BL, the other of the source or the drain of the second switch tube IP9 is connected to the second control circuit 102 to provide the sampling feedback signal Feedback to the second control circuit 102, and the gate of the second switch tube IP9 is connected to the output end of the first control circuit 101 to control whether the sampling feedback circuit 103 performs sampling according to the first control signal Control.

[0064] Among them, when the preset clock signal CK is a high level 1, when the preset power control signal Power Control_0 is a low level 0, the first control signal Control is a high level 1, the target power control signal Power Control_1 is a low level 0, the target power control signal Power Control_1 controls the bit line pre-charging circuit to pre-charge the bit line BL, the second switch tube IP9 is turned off, and the second switch tube IP9 does not perform sampling during the pre-charging process of the bit line BL; when the preset power control signal PowerControl_0 is a high level 1, the first control signal Control is a low level 0, the target power control signal PowerControl_1 is a high level 1, the target power control signal Power Control_1 controls the bit line pre-charging circuit to stop pre-charging the bit line BL, the second switch tube IP9 is turned on, and the second switch tube IP9 samples the bit line voltage.

[0065] When the preset clock signal CK is at a low level of 0, the first control signal Control is at a low level of 0, and the second switch tube IP9 is always at a low level of 0, and the bit line voltage is continuously sampled, so that when the bit line voltage is too low, the bit line pre-charging circuit is controlled by the second control circuit 102 to pre-charge the bit line, and when the bit line voltage is full voltage, the bit line pre-charging circuit is controlled by the second control circuit 102 to stop pre-charging the bit line.

[0066] Similarly, the storage array of the memory also includes word lines WL, and the word line ends of the word line power supply circuit are connected to the word lines WL of the storage array. The way in which the power control circuit controls the word line power supply circuit to supply power to the word lines WL is the same as the working principle of the bit line pre-charging circuit charging the bit line BL, which will not be repeated again.

[0067] In another possible implementation, if the memory array of the memory includes a bit line BL and a complementary bit line BLB, the bit line end of the bit line precharge circuit is connected to the bit line BL of the memory array, and the complementary bit line end is connected to the complementary bit line BLB of the memory array, such as Figure 3 As shown, the sampling feedback circuit 103 may include: a third switch tube IP7 and a fourth switch tube IP8.

[0068] One of the source or drain of the third switch tube IP7 is used to connect to the bit line end of the bit line precharging circuit, and one of the source or drain of the fourth switch tube IP8 is used to connect to the complementary bit line end of the bit line precharging circuit.

[0069] The gate of the third switch tube IP7 and the gate of the fourth switch tube IP8 are connected as the control end of the sampling feedback circuit 103, and the other of the source or drain of the third switch tube IP7 and the other of the source or drain of the fourth switch tube IP8 are connected to the output end of the sampling feedback circuit 103.

[0070] In this embodiment, when the storage array includes a bit line BL and a complementary bit line BLB, during precharging, the voltages of the bit line BL and the complementary bit line BLB need to be charged to the same voltage, so the bit line precharging circuit includes a bit line end and a complementary bit line end. For this purpose, the sampling feedback circuit 103 needs to set a third switch tube IP7 and a fourth switch tube IP8 to sample the bit line voltage and the complementary bit line voltage, respectively.

[0071] Its working principle is the same as that of the sampling feedback circuit 103 including only the second switch tube IP9, and will not be described in detail here.

[0072] For example, Figure 5 The waveform diagram provided in the embodiment of the present application and the working principle of the power control circuit are not described in detail here.

[0073] Based on the power control circuit provided in the above embodiments, an embodiment of the present application further provides a read-write circuit based on the power control circuit.

[0074] In one possible implementation, Figure 6 The principle frame of the read-write circuit provided in the embodiment of the present application Figure 1 ,like Figure 6 As shown, the read / write circuit may include: multiple read / write units 200, multiple bit line pre-charging circuits 300 (only one bit line pre-charging circuit is shown in the figure), multiple word line power supply circuits 400 (only one word line power supply circuit is shown in the figure) and a power control circuit 100.

[0075] Each read / write unit 200 is used to connect at least one bit line BL in the storage array, and multiple bit line precharging circuits 300 are also connected to multiple bit lines BL in the storage array. The control ends of the multiple bit line precharging circuits 300 are all connected to the power control circuit 100, and the multiple word line power supply circuits 400 are respectively connected to multiple word lines WL of the storage array.

[0076] In this embodiment, the output end of the power control circuit 100 is connected to the control end of multiple bit line precharging circuits 300 to control the multiple bit line precharging circuits 300 to precharge the connected bit lines. The input end of the sampling feedback circuit of the power control circuit 100 is connected to the bit line end and the complementary bit line end of any bit line precharging circuit 300 to sample the bit line voltage and the complementary bit line voltage.

[0077] In another possible implementation, Figure 7 The principle frame of the read-write circuit provided in the embodiment of the present application Figure 2 ,like Figure 7 As shown, the read / write circuit may include: a plurality of read / write units 200 , a plurality of bit line precharging circuits 300 , a plurality of word line power supply circuits 400 , and a plurality of power control circuits 100 .

[0078] Each read / write unit 200 is used to connect at least one bit line BL in the storage array, multiple bit line precharging circuits 300 are also connected to multiple bit lines BL in the storage array, multiple word line power supply circuits 400 are respectively connected to multiple word lines WL of the storage array, and the control ends of the multiple word line power supply circuits 400 are respectively connected to multiple power control circuits 100.

[0079] In this embodiment, the output ends of the multiple power control circuits 100 are respectively connected to the control ends of the multiple word line power circuits 400, so as to control the multiple word line power circuits 400 to supply power to the connected word lines. The input end of the sampling feedback circuit of each power control circuit 100 is connected to the word line end of the corresponding word line power circuit 400 to sample the word line voltage.

[0080] It should be noted that when the read-write circuit reads and writes the storage array, all bit lines can be pre-charged uniformly, so only one power control circuit needs to be set up. However, when reading and writing, only the storage cells whose word lines are set to a high level will perform read and write operations. Therefore, each word line corresponds to a power control circuit.

[0081] Based on the read-write circuit provided in the above embodiment, the embodiment of the present application also provides a memory, including Figure 6 Or Figure 7 The read / write circuit and storage array are shown.

[0082] The storage array is composed of M*N storage cells. The word lines of the storage cells in the same row are connected, the bit lines of the storage cells in the same column are connected, and the complementary bit lines are connected. Each read-write unit in the read-write circuit can be connected to at least one bit line in the storage array.

[0083] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A power control circuit, characterized in that: The electric energy control circuit comprises: a first control circuit, a second control circuit, a sampling feedback circuit and an output selection circuit; The first input terminal of the first control circuit is used to receive a preset clock signal, and the second input terminal of the first control circuit is used to receive a preset power control signal, so that the first control circuit generates a first control signal based on the preset power control signal and the preset clock signal; The control end of the sampling feedback circuit is connected to the output end of the first control circuit, the input end of the sampling feedback circuit is used to connect to the output end of the bit line precharge circuit or the word line power supply circuit in the read / write circuit, and the output end of the sampling feedback circuit is connected to the input end of the second control circuit, so that the second control circuit outputs a second control signal based on the sampling feedback signal; The output end of the first control circuit and the output end of the second control circuit are connected to the first input end and the second input end of the output selection circuit respectively, and the third input end of the output selection circuit is used to receive the preset clock signal, so that the output selection circuit outputs the target power control signal based on the preset clock signal, the first control signal and the second control signal; The output end of the output selection circuit is used to connect to the control end of the bit line precharge circuit or the word line power supply circuit to control the bit line precharge circuit or the word line power supply circuit to provide power to the corresponding bit line or word line according to the output target power control signal.

2. The power control circuit according to claim 1, characterized in that: The first control circuit includes: a first NAND gate, a first NOT gate, and a second NOT gate; The first input end of the first NAND gate serves as the first input end of the first control circuit, the input end of the first NOT gate serves as the second input end of the first control circuit, the output end of the first NOT gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate serves as the output end of the first control circuit; When the preset clock signal is at a high level, the first control signal is a negated signal of the preset power control signal.

3. The power control circuit according to claim 1, characterized in that: The second control circuit includes: a voltage-dividing sampling protection circuit and a Schmitt trigger; The input end of the voltage-dividing sampling protection circuit serves as the feedback input end of the second control circuit, the output end of the voltage-dividing sampling protection circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger serves as the output end of the second control circuit.

4. The power control circuit according to claim 3, characterized in that: The voltage-dividing sampling protection circuit comprises: a voltage-dividing sampling circuit, a first switching tube and a protection resistor; The input end of the voltage-dividing sampling circuit serves as the input end of the voltage-dividing sampling protection circuit, the output end of the voltage-dividing sampling circuit is connected to the gate of the first switching tube, one of the source or drain of the first switching tube is used to connect to a preset power supply voltage, the other of the source or drain of the first switching tube is connected to the protection resistor, and the connection point serves as the output end of the voltage-dividing sampling protection circuit.

5. The power control circuit according to claim 1, characterized in that: The output selection circuit comprises: a first NOR gate and a second NOR gate; The first input end of the first NOR gate and the first input end of the second NOR gate serve as the first input end and the second input end of the output selection circuit respectively, the second input end of the first NOR gate serves as the third input end of the output selection circuit, the output end of the first NOR gate is connected to the second input end of the second NOR gate, and the output end of the second NOR gate serves as the output end of the output selection circuit.

6. The power control circuit according to claim 1, characterized in that: The sampling feedback circuit comprises: a second switch tube; One of the source or the drain of the second switch tube is connected to the bit line end of the bit line precharging circuit or the word line voltage end of the word line power supply circuit, the gate of the second switch tube serves as the control end of the sampling feedback circuit, and the other of the source or the drain of the second switch tube serves as the output end of the sampling feedback circuit.

7. The power control circuit according to claim 1, characterized in that: The sampling feedback circuit comprises: a third switch tube and a fourth switch tube; One of the source or drain of the third switch tube is used to connect to the bit line end of the bit line precharging circuit, and one of the source or drain of the fourth switch tube is used to connect to the complementary bit line end of the bit line precharging circuit; The gate of the third switch tube and the gate of the fourth switch tube are connected as the control end of the sampling feedback circuit, and the other of the source or drain of the third switch tube and the other of the source or drain of the fourth switch tube are connected to the output end of the sampling feedback circuit.

8. A read-write circuit, characterized in that: The read / write circuit comprises: a plurality of read / write units, a plurality of bit line pre-charging circuits, a plurality of word line power supply circuits and a power control circuit; Each read / write unit is used to connect at least one bit line in the storage array, the plurality of bit line precharging circuits are also connected to the plurality of bit lines in the storage array, the control ends of the plurality of bit line precharging circuits are all connected to the power control circuit, and the power control circuit is a circuit as claimed in any one of claims 1 to 7; The plurality of word line power supply circuits are respectively connected to a plurality of word lines of the memory array.

9. A read-write circuit, characterized in that: The read / write circuit comprises: a plurality of read / write units, a plurality of bit line pre-charging circuits, a plurality of word line power supply circuits and a plurality of power control circuits; Each read / write unit is connected to at least one bit line in the storage array, and the plurality of bit line precharging circuits are respectively connected to the plurality of bit lines in the storage array; The multiple word line power supply circuits are respectively connected to the multiple word lines of the storage array, and the control ends of the multiple word line power supply circuits are respectively connected to the multiple power control circuits, and the multiple power control circuits are the circuits as described in any one of claims 1 to 6.

10. A memory, characterized in that: The memory comprises the read / write circuit and the storage array as claimed in claim 8 or 9.

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