Memory device for controlling shielded bit lines

Abstract

A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit, and a control circuit. The memory cell array includes: a plurality of bit lines connected to a plurality of memory cells; and shield bit lines disposed between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line pre-charge voltage and an internal power supply voltage based on a power supply voltage of the memory device. The control circuit is configured to selectively provide a bit line pre-charge voltage or an internal supply voltage to the shielded bit line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0151035 filed on November 3, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor memory device, and more particularly, to a memory device for controlling a shielded bit line. Background Art

[0004] Semiconductor chips are made through semiconductor manufacturing processes and then tested by test equipment in wafer, bare die or packaged states. Through testing, defective components or defective chips are screened out. With the continuous advancement of fine processes, semiconductor chips such as dynamic random access memory (DRAM) are more and more likely to have errors in the manufacturing process. With the high integration of DRAM, in order to achieve high integration of memory cells, vertical channel transistors formed vertically on a semiconductor substrate are introduced instead of planar channel transistors formed horizontally on a semiconductor substrate. In a DRAM including a vertical channel transistor, a shielded bit line can be formed in the memory cell array to reduce coupling noise between the bit lines.

[0005] The memory system may desire to obtain reliability, availability, and serviceability (RAS) functions for DRAM. DRAM can perform a repair operation in which a defective memory cell is detected in a test operation for a memory cell array and the defective memory cell is replaced with a redundant memory cell. In DRAM, when a read operation or a refresh operation is performed, a sense amplifier can sense and amplify the voltage difference between a bit line and a complementary bit line. Due to process variations, temperature, and the like, the semiconductor device forming the sense amplifier may have different characteristics (e.g., threshold voltage). In this way, the sensing margin of the sense amplifier will be reduced, and then the accuracy will be reduced, and the performance of the DRAM will deteriorate. Therefore, a method for improving the stability and accuracy of the sense amplifier by controlling the shielding bit line is needed. Summary of the invention

[0006] The inventive concept provides a memory device for controlling a shielded bit line.

[0007] According to one aspect of the inventive concept, a memory device is provided, comprising: a memory cell array, comprising: a plurality of bit lines connected to a plurality of memory cells; and a shielding bit line arranged between the plurality of bit lines and on the lower portion of the plurality of bit lines; a sense amplifier connected between a first sense drive signal line and a second sense drive signal line and configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells; a voltage generating circuit configured to generate a bit line precharge voltage and an internal power supply voltage based on a power supply voltage of the memory device; and a control circuit configured to selectively provide the bit line precharge voltage or the internal power supply voltage to the shielding bit line. The level of the internal power supply voltage may be greater than the level of the bit line precharge voltage.

[0008] According to one aspect of the present invention, a memory device is provided, including a memory cell array, a voltage generating circuit and a control circuit. The memory cell array includes a normal area and a redundant area, a plurality of bit lines connected to a plurality of memory cells are arranged in the normal area, and a redundant bit line is arranged in the redundant area. Some of the plurality of bit lines include: defective memory cells, which are set as repair cells to be replaced by redundant bit lines. The memory cell array includes: a first shielding bit line, arranged between the first bit lines corresponding to the first repair unit among the plurality of bit lines, and arranged on the lower part of the first bit line; a second shielding bit line, arranged between the second bit lines corresponding to the second repair unit among the plurality of bit lines, and arranged on the lower part of the second bit line; and a third shielding bit line, arranged between the redundant bit lines, and arranged on the lower part of the redundant bit line. The voltage generating circuit is configured to generate a bit line precharge voltage and an internal power supply voltage based on a power supply voltage of the memory device. The control circuit is configured to electrically connect the voltage generating circuit to the first shielded bit line based on the connection of a memory cell selected from among the plurality of memory cells to one of the first bit lines, and selectively provide a bit line precharge voltage or an internal power supply voltage to the first shielded bit line. The level of the internal power supply voltage is greater than the level of the bit line precharge voltage.

[0009] According to one aspect of the present invention, a memory device is provided, including a memory cell array, a voltage generating circuit and a control circuit. The memory cell array includes a plurality of bit lines and shielded bit lines, the plurality of bit lines are connected to a plurality of memory cells, the shielded bit lines are arranged between the plurality of bit lines and on the lower part of the plurality of bit lines, and the shielded bit lines are provided with a plurality of bodies; the voltage generating circuit is configured to: generate a bit line precharge voltage and an internal power supply voltage based on a power supply voltage of the memory device. The control circuit includes a plurality of switches respectively and adaptively electrically connected to the bodies of the plurality of shielded bit lines. The control circuit is configured to: selectively provide a bit line precharge voltage, an internal power supply voltage or a ground voltage to each of the bodies of the plurality of shielded bit lines in response to the plurality of switches being turned on or off; and allow each of the plurality of bodies of the shielded bit lines to be in a floating state. The level of the internal power supply voltage may be greater than the level of the bit line precharge voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a conceptual diagram illustrating a test system for testing a memory device according to an example embodiment;

[0012] Figure 2 is used to illustrate the Figure 1 A diagram of a storage device;

[0013] Figure 3 , Figure 4 , Figure 5 and Figure 6 is a diagram for illustrating a structure of a memory device according to example embodiments;

[0014] Figure 7 is a diagram for describing a circuit diagram of a sense amplifier according to example embodiments;

[0015] Fig. 8A and Figure 8B is a timing diagram for describing the operation of a sense amplifier according to example embodiments;

[0016] Fig.9A and Fig. 9B is a timing diagram for describing the operation of a sense amplifier according to example embodiments;

[0017] Fig. 10A and Fig. 10B is a timing diagram for describing the operation of a sense amplifier according to example embodiments;

[0018] Fig.11 and Fig.12 is a diagram for describing a shielded bit line according to example embodiments; and

[0019] Fig.13 is a block diagram for describing a system of an electronic device including a memory device according to example embodiments. DETAILED DESCRIPTION

[0020] Figure 1 is a conceptual diagram illustrating a test system 10 for testing a memory device 20 according to an example embodiment. Figure 2 is used to illustrate the Figure 1 FIG. 20 is a diagram of a memory device 20 .

[0021] Reference Figure 1 and Figure 2 , a method for testing a memory device 20 by a test device 30 in a test system 10 is shown. The test device 30 may include a test host 32 for testing the memory device 20 as a device under test (DUT). The test host 32 may include a central processing unit (CPU) 34 for controlling hardware, software, and firmware to perform a test operation on the memory device 20. The test host 32 may transmit a test signal from the CPU 34 to the memory device 20, or may output an execution result value for a test signal from the memory device 20 to the CPU 34.

[0022] The test host 32 may be implemented as a test program. The test program may include a test algorithm or mode for performing a test operation. For example, the test host 32 stores specific data in a storage area of ​​the DUT (i.e., the memory cell array 22 of the memory device 20), and reads the data, and then can determine the pass or fail of the test operation based on whether the read data is the same as the specific data. The test host 32 can measure whether the range of variation is within the allowable range by measuring the change in voltage / current / frequency for the memory device 20 under various driving conditions. The test host 32 can test the specific circuit operation of the memory device 20, and specifically, can detect defective memory cells by testing the memory cell array 22.

[0023] The memory device 20 may be implemented as a DRAM, but is not limited thereto. For example, the memory device 20 may correspond to a double data rate synchronous DRAM (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus DRAM (RDRAM), etc. Alternatively, the memory device 20 may be implemented as a static RAM (SRAM), a high bandwidth memory (HBM), or a processor built in memory (PIM).

[0024] In some embodiments, the memory device 20 may be implemented as a nonvolatile memory. For example, the memory device 20 may be implemented as a flash memory or a resistive memory such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc.

[0025] The test host 32 may test the memory device 20 via the channel 13. The channel 13 may include a bus and / or a signal line that physically or electrically connects the test host 32 to the memory device 20. For example, the memory device 20 receives a clock CK via a clock bus, the memory device 20 receives a command and an address CA via a command / address bus, and data DQ may be provided between the test host 32 and the memory device 20 via a data bus. In addition, a test signal may be provided between the test host 32 and the memory device 20 via a test signal line. For simplicity of the drawings, it is shown that the signal is transmitted between the test host 32 and the memory device 20 via one signal line or bus, but each bus may include one or more signal lines through which the signal is provided.

[0026] The test host 32 may provide commands to the memory device 20 to test the memory operation. Non-limiting examples of the commands may include access commands for accessing the memory, such as a read command for performing a read operation and a write command for performing a write operation, a mode register write and read command for performing write and read operations on a mode register, a repair command, etc.

[0027] During the test, when the test host 32 provides a write command and an associated address to the memory device 20, the memory device 20 receives the write command and the associated address, and performs a write operation to write the write data received from the test host 32 to the storage location corresponding to the associated address. The test host 32 provides the write data to the memory device 20 according to the timing associated with the reception of the write command. For example, when the write data is provided from the test host 32 to the memory device 20, the timing may be based on a write latency (WL) value indicating the number of clock cycles after the write command. The test host 32 may program the WL value onto a mode register set (MRS) of the memory device 20. As is well known in the art, the MRS of the memory device 20 may be programmed with information for selecting features for setting various operating modes and / or memory operations. In addition, information for test operations of the memory device 20 may be stored in a test mode register set (TMRS).

[0028] During testing, when a read command and an associated address are provided from the test host 32 to the memory device 20, the memory device 20 receives the read command and the associated address, and may perform a read operation to output the read data from the storage location corresponding to the associated address. The read data may be provided from the memory device 20 to the test host 32 according to a timing associated with the receipt of the read command. For example, when the read data is provided from the memory device 20 to the test host 32, the timing may be based on a read latency (RL) value indicating the number of clock cycles after the read command. The RL value may be set on the memory device 20 by the test host 32. For example, the RL value may be programmed on the MRS of the memory device 20.

[0029] The test host 32 may provide a repair command and a defective address to the memory device 20. The repair command is a command for instructing to store a defective address detected by the memory device 20 in a nonvolatile memory (e.g., a fuse array) in the memory device 20 and to perform a repair operation on the defective address. In response to the repair command, the memory device 20 may perform a repair operation so that a defective word line selected by the defective address is replaced by a redundant word line, or a defective bit line selected by the defective address is replaced by a redundant bit line.

[0030] Memory device 20 may include command decoder 21, memory cell array 22, address buffer 23, control circuit 24, address decoder 25, voltage generation circuit 26, data input / output circuit 27, and sense amplifier 28. In an embodiment, sense amplifier 28 may include a bit line sense amplifier.

[0031] The memory cell array 22 may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC formed at points where the rows and columns intersect each other. Each memory cell MC includes a cell transistor and a cell capacitor. For example, the cell transistor may be implemented as a vertical channel transistor. The gate of the cell transistor is connected to one of the word lines WL arranged along the first direction of the memory cell array 22. One end of the cell transistor is connected to one of the bit lines BL arranged along the second direction intersecting the first direction of the memory cell array 22. The other end of the cell transistor is connected to the cell capacitor. The cell capacitor may store a charge of a capacity corresponding to a data state.

[0032] The memory cell array 22 may include redundant rows and / or redundant columns. When a defect or error occurs in the memory cell MC, the redundant memory cell for repairing the defective memory cell is connected to the redundant row and / or redundant column. During the repair operation, when the row or column including the defective memory cell is replaced with the redundant row or redundant column, the replacement may be performed in units of multiple rows (e.g., two or four word lines) or multiple columns (e.g., four or eight bit lines). For example, when eight bit lines including the defective memory cell are replaced with eight redundant bit lines, it means that the eight bit lines become one repair unit (see Fig.12 The above examples are for understanding only and are not intended to limit the present invention.

[0033] In some embodiments, the memory cell array 22 may include a shielded bit line SBL disposed between the bit lines BL and extending over the lower portion of the bit lines BL. In an embodiment, the shielded bit line SBL may be disposed between the complementary bit lines BLB and extending over the lower portion of the complementary bit lines BLB. The shielded bit line SBL may reduce coupling noise between adjacent bit lines BL and between adjacent complementary bit lines BLB. The shielded bit line SBL may be configured as a main body (see Fig.11 ). In another embodiment, the shielding bit line SBL of the memory cell array 22 may include a plurality of bodies. The shielding bit line SBL may be formed of a plurality of bodies corresponding to (depending on) the repair operation performed on the memory cell array 22. In response to eight bit lines (i.e., an example repair unit), the shielding bit line SBL may include a plurality of bodies integrated for each of the eight bit lines (see Fig.12 The above examples are for understanding only and are not intended to limit the present invention.

[0034] The command decoder 21 may determine the command CMD input thereto with reference to an operand (a variable, field, or value indicating a specific aspect of a command) provided to the memory device 20. The command decoder 21 may be configured to perform an internal operation corresponding to the command CMD. The command CMD may include an activation command, a read command, a write command, a precharge command, a repair command, etc.

[0035] The address buffer 23 may receive an address ADDR provided to the memory device 20. The address ADDR may include a row address addressing a word line WL of the memory cell array 22 and a column address addressing a bit line BL of the memory cell array 22. The address buffer 23 may transfer each of the row address and the column address to the address decoder 25.

[0036] The address decoder 25 may include a row decoder and a column decoder, which select the word line WL and the bit line BL of the memory cell MC to be accessed in response to the received address ADDR. The row decoder may enable or activate the word line WL of the memory cell MC corresponding to the row address by decoding the row address. The column decoder may provide a column select signal for selecting the bit line BL of the memory cell MC corresponding to the column address by decoding the column address.

[0037] The control circuit 24 may generate an internal control signal according to the command CMD from the command decoder 21, and control the shielding bit line SBL and / or the sense amplifier 28. When the sense amplifier 28 senses and amplifies the data state of the memory cell MC, the control circuit 24 may control the sense amplifier 28 to sequentially perform an offset compensation operation, a charge sharing operation, a sensing operation, and a precharge operation. The data sensed and amplified by the sense amplifier 28 may be transmitted to the data input / output circuit 27, which is configured to output the data to an external device of the memory device 20 via a data DQ pad.

[0038] The data input / output circuit 27 may receive data DQ to be written on the memory cell MC from an external device and transfer the data to the memory cell array 22. The data input / output circuit 27 may output the data sensed and amplified by the sense amplifier 28 to the external device as read data via the data DQ pad.

[0039] The voltage generation circuit 26 can generate the bit line precharge voltage VBL and the internal power supply voltage VINTA provided to the sense amplifier 28 based on the power supply voltage VDD of the memory device 20. In some embodiments, the level of the bit line precharge voltage VBL can be set to half of the internal power supply voltage VINTA. Each of the voltages VBL, VINTA generated by the voltage generation circuit 26 can be used in the operation performed by the shielded bit line SBL and / or the sense amplifier 28 according to the control of the control circuit 24.

[0040] Figure 3 , Figure 4 , Figure 5 and Figure 6 is a diagram for illustrating a structure of a memory device 20 according to example embodiments. Figure 4 yes Figure 2 1 is a perspective view of a storage device 20. Figure 5 It shows Figure 4 A cross-sectional view of a cutting plane cut along a line corresponding to the second direction D2 in a perspective view of the memory device shown, and Figure 61 is a cross-sectional view showing a cutting surface cut along a line corresponding to the first direction D1. For the convenience of description, upper / lower surface, upper / lower part, upper / lower, etc. are described based on the directions in the figure. Therefore, even one surface can be referred to as an upper surface and a lower surface according to the directions shown in the figure.

[0041] Reference Figure 2 and Figure 3 , the memory device 20 may include a cell array structure CAS and a core peripheral circuit structure CPS that overlap each other in the third direction D3. The cell array structure CAS may include a memory cell array 22. The core peripheral circuit structure CPS may include a core peripheral circuit including a command decoder 21, an address buffer 23, an address decoder 25, a control circuit 24, a sense amplifier 28, a data input / output circuit 27, and a voltage generation circuit 26. Therefore, the memory device 20 may have a structure in which the memory cell array 22 is arranged on the upper part of the core peripheral circuit, that is, a cell above periphery (COP) structure.

[0042] The cell array structure CAS may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells including vertical channel transistors (VCT). In the cell array structure CAS, a plurality of word lines WL may extend along a first direction D1, and a plurality of bit lines BL may extend along a second direction D2.

[0043] The core peripheral circuit structure CPS may include a semiconductor substrate, and semiconductor devices (such as transistors) and patterns for wiring the semiconductor devices are formed on the semiconductor substrate to form core peripheral circuits. After the core peripheral circuits are formed in the core peripheral circuit structure CPS, a cell array structure CAS including a memory cell array 22 may be formed, and a pattern for electrically connecting word lines WL, bit lines BL, and shielding bit lines SBL of the memory cell array 22 to the core peripheral circuits formed in the core peripheral circuit structure CPS may be formed. For example, a sense amplifier 28, a control circuit 24, and a voltage generating circuit 26 may be arranged on the core peripheral circuit structure CPS.

[0044] Reference Figure 4 , Figure 5 , Figure 6, the core peripheral circuit structure CPS may include: a lower substrate 310; an interlayer insulating layer 315; a plurality of circuit elements 312a, 312b formed on the lower substrate 310; first metal layers 314a, 314b connected to the plurality of circuit elements 312a, 312b, respectively; second metal layers 316a, 316b formed on the first metal layers 314a, 314b; and a metal pattern 318 formed as the uppermost metal layer of the core peripheral circuit structure CPS. In an embodiment, the first metal layers 314a and 314b may be formed of tungsten having a relatively high resistance, and the second metal layers 316a and 316b may be formed of copper having a relatively low resistance.

[0045] In this specification, only the first metal layers 314a and 314b and the second metal layers 316a and 316b are shown and described, but the embodiment is not limited thereto, that is, at least one metal layer may also be formed on the second metal layers 316a and 316b. At least a portion of at least one metal layer formed on the second metal layers 316a and 316b may be formed of aluminum or the like, which has a lower resistance than the resistance of copper included in the second metal layers 316a and 316b. An interlayer insulating layer 315 is arranged on the lower substrate 310 to cover a plurality of circuit elements 312a and 312b, the first metal layers 314a and 314b, and the second metal layers 316a and 316b, and may include an insulating material (such as silicon oxide, silicon nitride, etc.).

[0046] The plurality of circuit elements 312a and 312b may be connected to at least one of the circuit elements constituting the peripheral circuit. For ease of description, the first circuit element 312a may represent a reference Figure 3 The second circuit element 312 b may be one of the plurality of transistors in the sense amplifier 28 , and may represent a transistor constituting the control circuit 24 or the voltage generating circuit 26 .

[0047] In the memory device 20, the bit lines BL may be arranged on the upper substrate 320 to be spaced apart from each other in the first direction D1. The bit lines BL may be spaced apart from each other in the first direction D1, and may extend in a second direction D2 intersecting the first direction D1. The active patterns AP may be alternately arranged on each bit line BL in the second direction D2. The active patterns AP may be spaced apart from each other by a specific distance in the first direction D1. That is, the active patterns AP may be arranged two-dimensionally along the first direction D1 and the second direction D2 intersecting each other. In some embodiments, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of active patterns AP form a plurality of vertical channel transistors.

[0048] Each active pattern AP may have a length in the first direction D1, a width in the second direction D2, and a height in a third direction D3 perpendicular to the upper substrate 320. Each active pattern AP may have a substantially uniform width. Each active pattern AP may have an upper surface and a lower surface facing each other in the third direction D3. For example, the lower surface of the active pattern AP may contact the bit line BL.

[0049] Each active pattern AP may include a source region adjacent to the bit line BL, a drain region adjacent to the contact pattern BC, and a channel region between the source region and the drain region. When the memory device 20 operates, the channel region of the active pattern AP may be controlled by the word line WL and the back gate electrode BG. The active pattern AP may include, for example, single crystal silicon (Si) to improve leakage current characteristics when the memory device 20 operates.

[0050] The back gate electrodes BG may be spaced apart from each other by a certain distance on the bit lines BL in the second direction D2. The back gate electrodes BG may extend across the bit lines BL in the first direction D1.

[0051] Each back gate electrode BG may be arranged between adjacent active patterns AP along the second direction D2. The first active pattern 191 may be arranged on one side of each back gate electrode BG, and the second active pattern 192 may be arranged on the other side of each back gate electrode BG. The height of the back gate electrode BG in the vertical direction may be less than the height of the active pattern AP in the vertical direction.

[0052] When the memory device 20 operates, a negative voltage may be applied to the back gate electrode BG, and the threshold voltage of the vertical channel transistor may be increased. This means that a decrease in the threshold voltage and degradation of the leakage current characteristics due to miniaturization of the vertical channel transistor may be prevented.

[0053] The first insulating pattern 111 may be arranged between the active patterns AP adjacent to each other in the second direction D2. The first insulating pattern 111 may extend in the first direction D1 in parallel with the back gate electrode BG. The back gate insulating layer 113 may be arranged between each back gate electrode BG and the active pattern AP and between the back gate electrode BG and the first insulating pattern 111. The back gate insulating layer 113 may include a vertical portion covering both side surfaces of the back gate electrode BG and a horizontal portion connecting the vertical portions of the back gate insulating layer 113. The horizontal portion of the back gate insulating layer 113 may be closer to the contact pattern BC than the bit line BL and may cover the upper surface of the back gate electrode BG. The back gate capping pattern 115 may be arranged between the bit line BL and the back gate electrode BG. The back gate capping pattern 115 may include an insulating material, and the lower surface of the back gate capping pattern 115 may contact the bit line BL. The back gate capping pattern 115 may be arranged between the vertical portions of the back gate insulating layer 113.

[0054] The word lines WL may extend on the bit lines BL along the first direction D1 and may be alternately arranged along the second direction D2. Among the word lines WL, the first word line 181 may be arranged at one side of the first active pattern 191, and the second word line 182 may be arranged at one side of the second active pattern 192. A portion of the first word line 181 may be arranged between the first active patterns 191 adjacent to each other in the first direction D1, and a portion of the second word line 182 may be arranged between the second active patterns 192 adjacent to each other in the first direction D1.

[0055] The word line WL may be vertically spaced apart from the bit line BL and the contact pattern BC. When viewed vertically, the word line WL may be located between the bit line BL and the contact pattern BC. The word lines WL adjacent to each other may have sidewalls facing each other. The height of the word line WL in the vertical direction may be less than the height of the active pattern AP in the vertical direction. The height of the word line WL in the third direction D3 may be equal to or greater than the height of the back gate electrode BG in the third direction D3.

[0056] The gate insulating layer 160 may be arranged between the word line WL and the active pattern AP. The gate insulating layer 160 may extend in parallel with the word line WL along the first direction D1. The gate insulating layer 160 may cover one side surface of the first active pattern 191 and the other side surface of the second active pattern 192. The gate insulating layer 160 may have a substantially uniform thickness. The second insulating pattern 141 may be arranged between the gate insulating layer 160 and the contact pattern BC. For example, the second insulating pattern 141 may include silicon oxide. The first etch stop layer 131 and the second etch stop layer 133 may be arranged between the active pattern AP and the second insulating pattern 141.

[0057] The word lines WL may be isolated from each other by the third insulating pattern 151 on the gate insulating layer 160. The third insulating pattern 151 may extend along the first direction D1 between the word lines WL. The first capping layer 153 may be arranged between the third insulating pattern 151 and the word line WL. The first capping layer 153 may have a substantially uniform thickness. The third insulating pattern 151 may include a third vertical pattern 151A and a third horizontal pattern 151B.

[0058] The contact pattern BC may be connected to the active pattern AP through the third etch stop layer 210 and the interlayer insulating layer 220. For example, the contact patterns BC may be connected to the drain regions of the active pattern AP, respectively. The lower width of each contact pattern BC may be greater than the upper width. The contact patterns BC adjacent to each other may be isolated by the separation dielectric pattern 230. From a planar perspective, each contact pattern BC may have various shapes, such as circular, elliptical, rectangular, square, hexagonal, etc. A landing pad LP may be arranged on the contact pattern BC.

[0059] The separation dielectric pattern 230 may be arranged between the landing pads LP. When viewed from a plane, the landing pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. The upper surface of the landing pads LP may be substantially coplanar with the upper surface of the separation dielectric pattern 230. The fourth etch stop layer 240 may be formed on the separation dielectric pattern 230.

[0060] The data storage patterns DSP may be arranged on the landing pads LP. The data storage patterns DSP may be electrically connected to the active patterns AP, respectively. The data storage patterns DSP may be arranged in a matrix form along the first direction D1 and the second direction D2. The data storage patterns DSP may overlap the landing pads LP in whole or in part. The data storage patterns DSP may contact the upper surface of the landing pads LP in whole or in part. An upper insulating layer 260 may be provided on the data storage patterns DSP, and the cell contact plugs PLG may pass through the upper insulating layer 260 to be connected to the plate electrode 255.

[0061] In some embodiments, the data storage pattern DSP may be a capacitor and may include a capacitor dielectric layer 253 disposed between the storage electrode 251 and the plate electrode 255. At this time, the storage electrode 251 may directly contact the landing pad LP, and when viewed from a plane, the storage electrode 251 may have various shapes such as a circle, an ellipse, a rectangle, a square, a diamond, a hexagon, etc.

[0062] In some embodiments, the data storage pattern DSP may be a variable resistance pattern that can be switched to two resistance states due to an electric pulse applied to the storage element. For example, the data storage pattern DSP may include, but is not limited to, a phase change material that changes a crystal state according to an amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, an antiferromagnetic material, etc. According to the material layer of the data storage pattern DSP, the memory device 20 may be implemented as a resistive memory, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc.

[0063] The shielding bit line SBL may be arranged between the bit lines BL and throughout the lower part of the bit lines BL. The shielding bit line SBL may reduce the coupling noise between adjacent bit lines BL. For example, the shielding bit line SBL may include a shielding structure formed by a conductive material. The first wire insulating layer 173 may be spaced apart from each other in the first direction D1 and may extend along the second direction D2. The first wire insulating layer 173 may be formed to contact the facing side walls of the adjacent bit lines BL and be isolated from each other in the first direction D1. The second wire insulating layer 325 may be formed to surround the lower surface and side surface of the shielding bit line SBL and fill the space between the shielding bit lines SBL. The substrate through hole (e.g., silicon through hole (TSV)) 322 extends longitudinally along the third direction D3, passes through the upper substrate 320 to reach the metal pattern 318 of the uppermost metal layer formed as the core peripheral circuit structure CPS, and electrically connects the shielding bit line SBL to the element 312b of the control circuit 24.

[0064] Generally, the shielding bit line SBL is provided to reduce coupling noise between the bit lines BL, but the bit line BL and the shielding bit line SBL each include a conductive material, so the capacitance between the bit line BL and the shielding bit line SBL may increase. The capacitance between the bit line BL and the shielding bit line SBL may be used to improve the operating characteristics of the sense amplifier 28. The components and operations of the shielding bit line SBL and the sense amplifier 28 will be described in detail below in conjunction with example embodiments.

[0065] Figure 7 is a diagram for describing a circuit diagram of a sense amplifier according to example embodiments. In the timing diagrams described below, the horizontal axis and the vertical axis represent time and voltage level, respectively, and are not necessarily displayed at a constant scale.

[0066] Reference Figure 2 and Figure 7 , the sense amplifier 28 may include: a P-type sense amplifier circuit 710 including a PMOS transistor, an N-type sense amplifier circuit 720 including an NMOS transistor, an isolation circuit 730, and an offset cancellation circuit 740. For convenience of description, the P-type sense amplifier circuit 710 is referred to as a first sense amplifier circuit, and the terms "P-type sense amplifier circuit 710" and "first sense amplifier circuit" may be used interchangeably. The N-type sense amplifier circuit 720 is referred to as a second sense amplifier circuit, and the terms "N-type sense amplifier circuit 720" and "second sense amplifier circuit" may be used interchangeably. In addition, the mismatch between the threshold voltages of the transistors forming the sense amplifier 28 may be referred to as an offset voltage. The removal of the threshold voltage mismatch may be referred to as compensation of the offset voltage.

[0067] The P-type sense amplifier circuit 710 may include a first PMOS transistor P11 and a second PMOS transistor P12 connected to a first sense drive signal LA line. The first PMOS transistor P11 may be connected between the first sense drive signal LA line and a complementary sense bit line SABLB, and the second PMOS transistor P12 may be connected between the first sense drive signal LA line and the sense bit line SABL. The sense bit line SABL may be connected to the gate of the first PMOS transistor P11, and the complementary sense bit line SABLB may be connected to the gate of the second PMOS transistor P12. The first PMOS transistor P11 and the second PMOS transistor P12 may be designed to have the same size. In some embodiments, the first PMOS transistor P11 and the second PMOS transistor P12 may be designed to have different sizes.

[0068] The N-type sense amplifier circuit 720 may include a first NMOS transistor N11 and a second NMOS transistor N12 connected to a second sense drive signal LAB line. The first NMOS transistor N11 may be connected between the second sense drive signal LAB line and a complementary sense bit line SABLB, and the second NMOS transistor N12 may be connected between the second sense drive signal LAB line and the sense bit line SABL. The bit line BL is connected to the gate of the first NMOS transistor N11, and the complementary bit line BLB is connected to the gate of the second NMOS transistor N12. The first NMOS transistor N11 and the second NMOS transistor N12 may be designed to have the same size. In some embodiments, the first NMOS transistor N11 and the second NMOS transistor N12 may be designed to have different sizes.

[0069] The isolation circuit 730 may include a third NMOS transistor N13 and a fourth NMOS transistor N14 that operate in response to an isolation signal ISO. The third NMOS transistor N13 may be connected between the bit line BL and the sensing bit line SABL, and the fourth NMOS transistor N14 may be connected between the complementary bit line BLB and the complementary sensing bit line SABLB. The third NMOS transistor N13 and the fourth NMOS transistor N14 may be designed to have the same size. In some embodiments, the third NMOS transistor N13 and the fourth NMOS transistor N14 may be designed to have different sizes.

[0070] The offset cancellation circuit 740 may include a fifth NMOS transistor N15 and a sixth NMOS transistor N16 that operate in response to the offset cancellation signal OC. The fifth NMOS transistor N15 may be connected between the bit line BL and the complementary sensing bit line SABLB, and the sixth NMOS transistor N16 may be connected between the complementary bit line BLB and the sensing bit line SABL. The fifth NMOS transistor N15 and the sixth NMOS transistor N16 may be designed to have the same size. In some embodiments, the fifth NMOS transistor N15 and the sixth NMOS transistor N16 may be designed to have different sizes.

[0071] Fig. 8A and Figure 8B is a timing diagram for describing the operation of a sense amplifier according to example embodiments.

[0072] Reference Fig. 8A , an offset compensation operation may be performed between time point T1 and time point T2. The word line WL may be in a disabled state, the third NMOS transistor N13 and the fourth NMOS transistor N14 may be in a cut-off state (sometimes referred to as OFF) due to the isolation signal ISO of a logic low level, and the fifth NMOS transistor N15 and the sixth NMOS transistor N16 may be in a conductive state (sometimes referred to as ON) due to the offset cancellation signal OC of a logic high level. An internal power supply voltage VINTA is provided to the first sensing drive signal LA line, and a ground voltage VSS may be provided to the second sensing drive signal LAB line.

[0073] A precharge operation may be performed before time point T1. Performing a precharge operation means that the bit line BL, the complementary bit line BLB, the sensing bit line SABL, and the complementary sensing bit line SABLB are connected via one node and are balanced to the same voltage level due to the isolation signal ISO and the offset cancellation signal OC having a logic high level. For example, the bit line BL, the complementary bit line BLB, the sensing bit line SABL, and the complementary sensing bit line SABLB may be balanced to a bit line precharge voltage VBL provided to the balanced drive signal line by the balancing circuit. During the precharge operation, the shielding bit line SBL adjacent to the bit line BL may be provided with a bit line precharge voltage VBL.

[0074] Between time point T1 and time point T2, the bit line BL and the complementary sensing bit line SABLB may be connected to each other, and the complementary bit line BLB and the sensing bit line SABL may be connected to each other via the fifth transistor N15 and the sixth NMOS transistor N16 turned on by the offset cancellation signal OC of the logic high level. Since the first PMOS transistor P11 and the second PMOS transistor P12 and the first NMOS transistor N11 and the second NMOS transistor N12 connect the first sensing drive signal LA line to the internal power supply voltage VINTA, and connect the second sensing drive signal LAB line to the ground voltage VSS, there may be a specific voltage difference between the bit line BL and the complementary sensing bit line SABLB and between the complementary bit line BLB and the sensing bit line SABL. For ease of description, it is assumed that the bit line BL increases a specific level compared to the complementary bit line BLB, and the complementary sensing bit line SABLB increases a specific level relative to the sensing bit line SABL.

[0075] In some embodiments, in the offset compensation operation between the time point T1 and the time point T2, the internal power supply voltage VINTA may be provided to the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified. Fig. 8A As shown. Since the bit line BL is coupled through the shielding bit line SBL to which the internal power supply voltage VINTA is provided, the voltage levels of the bit line BL and the complementary sensing bit line SABLB can be increased. The rise in the voltage levels of the bit line BL and the complementary sensing bit line SABLB can promote the difference between the specific voltages between the bit line BL and the complementary bit line BLB and between the sensing bit line SABL and the complementary sensing bit line SABLB.

[0076] In some embodiments, due to some problems of the semiconductor manufacturing process, the transistors of the sense amplifier 28 may have slower operating characteristics. Due to the slower operating characteristics of the transistors, the offset compensation operation of the sense amplifier 28 may become slower. In order not to reduce the speed of the offset compensation operation, the internal power supply voltage VINTA may be provided to the shielded bit line SBL. Providing the internal power supply voltage VINTA to all the shielded bit lines SBL in the memory cell array 22 may cause undesirable power consumption that exceeds the specifications of the low-power memory device 20. In order to optimize power consumption, the internal power supply voltage VINTA may be provided only to some of the multiple bodies included in the shielded bit line SBL that are related to the sense amplifier 28 with lower operating characteristics.

[0077] In some embodiments, when the memory device 20 operates in a high temperature environment, it is necessary to reduce the operating speed of the memory device 20. In the offset compensation operation between the time point T1 and the time point T2, the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with a ground voltage VSS. Figure 8BAs shown. Since the bit line BL is coupled through the shielding bit line SBL of the ground voltage VSS, the voltage levels of the bit line BL and the complementary sensing bit line SABLB can be reduced. The reduction of the voltage levels of the bit line BL and the complementary sensing bit line SABLB can slow down the difference between the specific voltages between the bit line BL and the complementary bit line BLB and between the sensing bit line SABL and the complementary sensing bit line SABLB. Conversely, when the memory device 20 operates in a low temperature environment, the internal power supply voltage VINTA can be provided to the shielding bit line SBL to accelerate the offset compensation operation of the sense amplifier 28, as shown. Fig. 8A shown.

[0078] In the present embodiment, the bit line BL increases a specific level compared to the complementary bit line BLB, and therefore, it is assumed that the bit line BL and the complementary bit line BLB have a first voltage difference △Va. In addition, the complementary sensing bit line SABLB increases a specific level compared to the sensing bit line SABL, and therefore, it is assumed that the complementary sensing bit line SABLB and the sensing bit line SABL have a first voltage difference △Va. The above example is only used to understand the present embodiment and does not limit the inventive concept. The first voltage difference △Va can be understood as a first offset voltage according to the difference between the threshold voltages of the first PMOS transistor P11 and the second PMOS transistor P12 and the difference between the threshold voltages of the first NMOS transistor N11 and the second NMOS transistor N12. This means that the bit line BL and the complementary bit line BLB are configured to have a difference as large as the first offset voltage, and thus the offset noise caused by the difference between the threshold voltages of the first PMOS transistor P11 and the second PMOS transistor P12 and the difference between the threshold voltages of the first NMOS transistor N11 and the second NMOS transistor N12 is eliminated. That is, the sense amplifier 28 can compensate for the offset voltage.

[0079] In some embodiments, during the offset compensation operation, it can be considered that there is a first voltage difference ΔVa between the bit line BL and the complementary bit line BLB, and the first voltage difference ΔVa represents a voltage difference caused by the timing of some signals (e.g., the isolation signal ISO, the first sensing drive signal LA, and the second sensing drive signal LAB). The above examples are for understanding only and are not intended to limit the inventive concept.

[0080] Reference Figure 8B , the bit line BL drops a certain level compared to the complementary bit line BLB, and therefore, it is assumed that the bit line BL and the complementary bit line BLB have a second voltage difference △Va'. In addition, the complementary sensing bit line SABLB drops a certain level compared to the sensing bit line SABL, and it is assumed that the complementary sensing bit line SABLB and the sensing bit line SABL have a second voltage difference △Va'. The second voltage difference △Va' may be less than the first voltage difference △Va.

[0081] The purpose and significance of the voltage difference between the bit line BL and the complementary bit line BLB is to remove the offset noise caused by the difference between the threshold voltages of the transistors P11 and P12 of the P-type sense amplifier circuit 710 and the difference between the threshold voltages of the transistors N11 and N12 of the N-type sense amplifier circuit 720, which is important for the sensing and amplification operations of the sense amplifier 28. Therefore, the sensing operation of the sense amplifier 28 can ensure reliability and accuracy.

[0082] The charge sharing operation may be performed between time point T2 and time point T3. At time point T2, the offset cancellation signal OC may be converted to a logic low level, and then, the fifth NMOS transistor N15 and the sixth NMOS transistor N16 become cut-off states, the bit line precharge voltage VBL is provided to the first sensing drive signal and the second sensing drive signal (LA and LAB) lines, and the word line WL is activated or enabled. Charge sharing occurs between the cell capacitor and the bit line BL of the memory cell MC connected to the activated word line WL. When data "1" is stored in the memory cell MC, the voltage level of the bit line BL will rise by a specific level during the charge sharing operation. In another embodiment, when data "0" is stored in the memory cell MC, the voltage level of the bit line BL will drop by a specific level during the charge sharing operation.

[0083] The sensing operation may be performed between time point T3 and time point T5. At time point T3, the internal power supply voltage VINTA is provided to the first sensing drive signal LA line, and the ground voltage VSS may be provided to the second sensing drive signal LAB line. Based on the voltage difference between the sensing bit line SABL and the complementary sensing bit line SABLB, the complementary bit line SABL may increase to the internal power supply voltage VINTA level, and the complementary sensing bit line SABLB may drop to the ground voltage VSS level. Time point T3 may be referred to as a sampling time point for the sensing operation.

[0084] At time point T4, the isolation signal ISO is turned into a logic high level, and then the third NMOS transistor N13 and the fourth NMOS transistor N14 become turned on. The sensing bit line SABL and the bit line BL can be connected to each other, and the complementary sensing bit line SABLB and the complementary bit line BLB can be connected to each other. The bit line BL can be increased to the voltage level of the sensing bit line SABL, and the amount of charge corresponding to the voltage level of the bit line BL can be restored in the cell capacitor of the memory cell MC. At time point T5, the word line WL can be deactivated, and the first bit line voltage VBL can be provided to the first sensing drive signal and the second sensing drive signal (LA and LAB) line.

[0085] At time point T5, a precharge operation may be performed. A bit line precharge voltage VBL is provided to the first sensing drive signal LA line and the second sensing drive signal LAB line, and since the isolation signal ISO and the offset cancellation signal OC have a logic high level, the bit line BL, the complementary bit line BLB, the sensing bit line SABL and the complementary sensing bit line SABLB are connected via one node, and each line may be precharged by the bit line precharge voltage VBL provided to the balancing drive signal line by the balancing circuit.

[0086] exist Fig. 8A and Figure 8B In the embodiment, from time point T1 to time point T2, the offset compensation operation related to the internal power supply voltage VINTA and the ground voltage VSS provided to the shielding bit line SBL is performed by the sense amplifier 28. From time point T2 to time point T3, a charge sharing operation is performed, from time point T3 to time point T5, a sensing operation is performed, and a precharge operation is performed at time point T5. The above examples are only used to understand the embodiments and do not limit the inventive concept. Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B The charge sharing operation and the sensing operation performed in relation to the voltage level supplied to the shielding bit line SBL are described, and reference to Fig. 8A The duplicate description provided.

[0087] Fig.9A and Fig. 9B is a timing diagram for describing the operation of a sense amplifier according to example embodiments.

[0088] Reference Figure 7 and Fig.9A , an offset compensation operation of the sense amplifier 28 is performed between time point T1 and time point T2, a charge sharing operation is performed between time point T2 and time point T3, a sensing operation is performed between time point T3 and time point T5, and a precharge operation is performed at time point T5.

[0089] During the charge sharing operation between time point T2 and time point T3, when data "1" is stored in the memory cell MC, the voltage level of the bit line BL increases by a specific level, and when data "0" is stored in the memory cell MC, the voltage level of the bit line BL decreases by a specific level. The charge sharing operation is dominated by the N-type sense amplifier circuit 720 connected to the bit line BL and the complementary bit line BLB. Due to the presence of the N-type sense amplifier circuit 720, a voltage difference may occur between the sense bit line SABL and the complementary sense bit line SABLB according to the voltage levels of the bit line BL and the complementary bit line BLB.

[0090] In some embodiments, due to problems in the semiconductor manufacturing process, the transistors of the sense amplifier 28 may have a slower operating characteristic. At this time, in order to enhance the operation of the N-type sense amplifier circuit 720, an internal power supply voltage VINTA may be provided to the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified, such as Fig.9A Therefore, the charge sharing operation can be performed quickly.

[0091] In some embodiments, due to problems in the semiconductor manufacturing process, the memory device 20 may have a slower operating speed for data "1". At this time, in order to enhance the operating speed of the N-type sense amplifier circuit 720 for data "1", the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with an internal power supply voltage VINTA, such as Fig.9A Therefore, the charge sharing for the operation of data "1" can be performed quickly.

[0092] In some embodiments, due to problems in the semiconductor manufacturing process, the memory device 20 may have a slower operating speed for data "0". At this time, in order to enhance the operating speed of the N-type sense amplifier circuit 720 for data "0", the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with a ground voltage VSS, such as Fig. 9B Therefore, the charge sharing for the operation of data "0" can be performed quickly.

[0093] In some embodiments, when the memory device 20 operates in a high temperature environment, it is necessary to reduce the operating speed of the memory device 20. In order to weaken the operation of the N-type sense amplifier circuit 720, a ground voltage VSS may be provided to the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified, such as Fig. 9B As shown, the charge sharing operation can be performed more slowly. On the contrary, when the memory device 20 operates in a low temperature environment, the internal power supply voltage VINTA can be provided to the shielding bit line SBL to speed up the charge sharing operation of the sense amplifier 28.

[0094] Fig. 10A and Fig. 10B is a timing diagram for describing the operation of a sense amplifier according to example embodiments.

[0095] Reference Figure 7 and Fig. 10A , an offset compensation operation of the sense amplifier 28 is performed between time point T1 and time point T2, a charge sharing operation is performed between time point T2 and time point T3, a sensing operation is performed between time point T3 and time point T5, and a precharge operation is performed at time point T5.

[0096] During the sensing operation between time point T3 and time point T5, based on the voltage difference between the sensing bit line SABL and the complementary sensing bit line SABLB, the sensing bit line SABL increases to the internal power supply voltage VINTA level, and the complementary sensing bit line SABLB may drop to the ground voltage VSS level. The sensing operation may be led by the P-type sensing amplifier circuit 710 connected to the sensing bit line SABL and the complementary sensing bit line SABLB and the N-type sensing amplifier circuit 720 connected to the bit line BL and the complementary bit line BLB. The same faster or slower ground operation of the P-type sensing amplifier circuit 710 and the N-type sensing amplifier circuit 720 is very important for balanced sensing operation.

[0097] In some embodiments, due to problems in semiconductor manufacturing processes, the P-type sense amplifier circuit 710 may have faster operating characteristics, and the N-type sense amplifier circuit 720 may have slower operating characteristics. At this time, in order to enhance the operation of the N-type sense amplifier circuit 720, the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with an internal power supply voltage VINTA, such as Fig. 10A Therefore, the sensing operations of the P-type sense amplifier circuit 710 and the N-type sense amplifier circuit 720 can be performed faster.

[0098] In some embodiments, due to problems in the semiconductor manufacturing process, the P-type sense amplifier circuit 710 may have a slower operating characteristic, and the N-type sense amplifier circuit 720 may have a faster operating characteristic. At this time, in order to weaken the operation of the N-type sense amplifier circuit 720, the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with a ground voltage VSS, such as Fig. 10B Therefore, the sensing operations of the P-type sense amplifier circuit 710 and the N-type sense amplifier circuit 720 may be performed more slowly.

[0099] In an embodiment, due to problems in the semiconductor manufacturing process, the memory device 20 may have a slower operating speed for data "1". At this time, in order to enhance the operating speed for data "1", the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with an internal power supply voltage VINTA, such as Fig. 10A Therefore, the sensing operation for data "1" can be performed quickly.

[0100] In some embodiments, due to problems in the semiconductor manufacturing process, the memory device 20 may have a slower operating speed for data "0". At this time, in order to enhance the operating speed for data "0", the shielding bit line SBL adjacent to the bit line BL to be sensed and amplified may be provided with a ground voltage VSS, such as Fig. 10B Therefore, the sensing operation for data "0" can be performed quickly.

[0101] Fig.11 and Fig.12 is a diagram for describing a shielded bit line according to example embodiments. Fig.11 and Fig.12 A method of detecting a bit line bridging by using a voltage level supplied to a shielded bit line SBL and a shielded bit line structure for a repair operation is shown.

[0102] Reference Figure 1 , Figure 2 and Fig.11 , the bit line BL of the memory cell array 22 may be connected to the sense amplifier 28, and the shielding bit line SBL may be connected to the voltage generating circuit 26 via the control circuit 24. Fig.11 In the embodiment, the shielded bit line SBL is integrally configured in the memory cell array 22 .

[0103] The control circuit 24 includes a plurality of first to fourth switches SW1, SW2, SW3, and SW4 connected to the shielding bit line SBL, and can provide the shielding bit line SBL with a bit line precharge voltage VBL or an internal power supply voltage VINTA generated by the voltage generating circuit 26. The control circuit 24 can be configured such that: when the first switch SW1 is turned on, the shielding bit line SBL floats; when the second switch SW2 is turned on, the precharge voltage VBL is provided to the shielding bit line SBL; when the third switch SW3 is turned on, the internal power supply voltage VINTA is provided to the shielding bit line SBL; and when the fourth switch SW4 is turned on, the ground voltage VSS is provided to the shielding bit line SBL.

[0104] In some embodiments, when specific data (e.g., data "1") is stored in the selected memory cell MC and then the memory cell data is read, the test host 32 may allow the control circuit 24 to turn on the fourth switch SW4 and receive the data read from the selected memory cell MC. The bit line BL of the selected memory cell MC is sensed as a logic high level by the sense amplifier 28 and has an internal power supply voltage VINTA level, and the shielded bit line SBL has a ground voltage VSS level due to the fourth switch SW4. This is a test method that intentionally generates defects when reading data. When there is a bridge between the bit line BL of the selected memory cell MC and the shielded bit line SBL, since the entire shielded bit line SBL has a large capacitance, the bit line BL becomes the ground voltage VSS level with the shielded bit line SBL, and the memory device 20 may output data "0". The test host 32 may determine "failure" for the read data "0" from the selected memory cell MC instead of the expected data "1".

[0105] In some embodiments, when specific data (e.g., data "0") is stored in the selected memory cell MC and then the memory cell data is read, the test host 32 may allow the control circuit 24 to turn on the third switch SW3 and receive the data read from the selected memory cell MC. The bit line BL of the selected memory cell MC is sensed as a logic low level by the sense amplifier 28 and may have a ground voltage VSS level, and the shielding bit line SBL may have an internal power supply voltage VINTA level due to the third switch SW3. When there is a bridge between the bit line BL of the selected memory cell MC and the shielding bit line SBL, since the entire shielding bit line SBL has a large capacitance, the bit line BL becomes to have the internal power supply voltage VINTA level of the shielding bit line SBL, and the memory device 20 may output data "1". The test host 32 may determine "failure" for the read data "1" from the selected memory cell MC instead of the expected data "0".

[0106] When the bit line bridge test performed by the test host 32 is determined to be "passed", the control circuit 24 can provide the shielding bit line SBL with the bit line precharge voltage VBL, the internal power supply voltage VINTA or the ground voltage VSS by selectively using the second to fourth switches SW2, SW3 and SW4 in the normal operation (e.g., read operation) of the memory device 20. Figure 7 , reference Fig. 8A , reference Figure 8B , reference Fig.9A , reference Fig. 9B , reference Fig. 10A and reference Fig. 10B As described above, the sense amplifier 28 may perform an offset compensation operation, a charge sharing operation, and / or a sensing operation by being affected by the bit line precharge voltage VBL, the internal power supply voltage VINTA, or the ground voltage VSS supplied to the shielding bit line SBL.

[0107] In some embodiments, in order not to change the voltage level of the shielded bit line SBL during the operation of the sense amplifier 28, the shielded bit line SBL may be set to be maintained at the bit line precharge voltage VBL level or in a floating state. The control circuit 24 may allow the shielded bit line SBL to be in a floating state by using the first switch SW1, and provide the bit line precharge voltage VBL to the shielded bit line SBL by using the second switch SW2 to control the sense amplifier 28 to operate.

[0108] Reference Fig.12The memory cell array 22 may include: a normal region 22a, in which a plurality of bit lines BL are arranged; and a redundant region 22b, in which a redundant bit line RBL is arranged. In the normal region 22a of the memory cell array 22, shielding bit lines SBL1 and SBL2 are arranged between the bit lines BL and across the lower portion of the bit lines BL; in the redundant region 22b, a shielding bit line SBL3 is arranged between the redundant bit lines RBL and across the lower portion of the redundant bit lines RBL.

[0109] The defective bit line BL in the normal area 22a of the memory cell can be replaced by the redundant bit line RBL of the redundant area 22b. For example, eight bit lines BL including defective memory cells can be replaced by eight redundant bit lines RBL of the redundant area 22b. The eight bit lines BL and the eight redundant bit lines RBL become a repair unit for performing a repair operation. In the normal area 22a, a plurality of shielded bit lines SBL1 and SBL2 are arranged corresponding to the eight bit lines BL as the repair unit, and each of the plurality of shielded bit lines SBL1 and SBL2 can be formed by an integrated body. In the redundant area 22b, an integrated shielded bit line SBL3 corresponding to the eight redundant bit lines RBL (i.e., the repair unit) can be arranged. For the sake of simplicity of the drawing, eight redundant bit lines RBL as a repair unit are shown in the redundant area 22b, but redundant bit lines RBL providing multiple repair units may be included.

[0110] The control unit 24 can perform a repair operation on the memory cell array 22. The control circuit 24 includes a plurality of repair switches RSW1, RSW2, RSW3 respectively connected to the plurality of shielded bit lines SBL1, SBL2, SBL3, and can selectively provide the bit line precharge voltage VBL generated by the voltage generating circuit 26 or the internal power supply voltage VINTA to the shielded bit lines SBL1, SBL2, SBL3.

[0111] In an embodiment, when performing a repair operation of replacing eight bit lines BL in a normal region 22a including defective memory cells with eight redundant bit lines RBL in a redundant region 22b, the control circuit 24 may control the second repair switch RSW2 to be turned off and the third repair switch RSW3 to be turned on. This means that since the eight bit lines BL in the normal region 22a including defective memory cells are shielded, the second shielding bit lines SBL2 corresponding to the eight bit lines BL are also shielded by the second repair switch RSW2. In addition, according to the use of eight redundant bit lines RBL instead of the eight bit lines BL including defective memory cells, this also means that the bit line precharge voltage VBL or the internal power supply voltage VINTA generated by the voltage generation circuit 26 is provided to the eight redundant bit lines RBL through the third repair switch RSW3. In another embodiment, the control circuit 24 may control the eight redundant bit lines RBL to be in a floating state or at a ground voltage VSS level by using the third repair switch RSW3.

[0112] Fig.13 is a block diagram for describing a system 1000 of an electronic device including a memory device according to example embodiments.

[0113] Reference Fig.13 , the system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, storage devices 1600a and 1600b, input / output (I / O) devices 1700a and 1700b, and an application processor (AP) 1800. The system 1000 may be implemented as a laptop computer, a mobile phone, a smart phone, a personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. In addition, the system 1000 may be implemented as a server or a tablet computer.

[0114] The camera 1100 can capture a still image or a moving image according to the control of the user, and can store the captured image / image or send the captured image / image data to the display 1200. The audio processor 1300 can process the audio data included in the storage devices 1600a and 1600b or in the content of the network. The modem 1400 can modulate and send a signal for transmitting and receiving wired / wireless data, and demodulate the modulated signal on the receiving side to restore the original signal. The I / O devices 1700a and 1700b may include devices that provide digital input and / or output functions, such as universal serial bus (USB) storage devices, digital cameras, secure digital (SD) cards, digital versatile discs (DVDs), network adapters, touch screens, etc.

[0115] The AP 1800 may control the overall operation of the system 1000. The AP 1800 may include a controller block 1810, an accelerator block or an accelerator chip 1820, and an interface block 1830. The AP 1800 may control the display 1200 so that part of the content stored in the storage devices 1600a and 1600b is displayed on the display 1200. When a user input is received via the I / O devices 1700a and 1700b, the AP 1800 may perform a control operation corresponding to the user input. The AP 1800 may include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data calculation, or may include an accelerator chip 1820 separated from the AP 1800. The DRAM 1500b may be additionally mounted on the accelerator block or the accelerator chip 1820. The accelerator may be a functional block dedicated to performing a specific function of the AP 1800, and may include a graphics processing unit (GPU) as a functional block dedicated to processing graphic data, a neural processing unit (NPU) as a block dedicated to AI calculation and inference, or a data processing unit (DPU) as a block dedicated to data transmission.

[0116] The system 1000 may include a plurality of DRAMs 1500a and 1500b. The AP 1800 may control the DRAMs 1500a and 1500b by setting a command and mode register (MRS) in accordance with the Joint Electron Device Engineering Council (JEDEC) standard, or may set a DRAM interface protocol and communicate to use enterprise-specific functions (such as low voltage, high speed, reliability, etc.), and a cyclic redundancy check (CRC) / error correction code (ECC) function. For example, the AP 1800 may communicate with the DRAM 1500a via an interface conforming to JEDEC standards such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 1820 may communicate by setting a new DRAM interface protocol to control the DRAM 1500b to be used as an accelerator having a higher bandwidth than the DRAM 1500a.

[0117] Fig.13Only DRAM 1500a and 1500b are shown, but the inventive concept is not limited thereto. As long as the bandwidth, response speed, and voltage conditions of AP 1800 or accelerator chip 1820 are met, memories such as PRAM, SRAM, MRAM, RRAM, FRAM, and hybrid RAM can be used. DRAM 1500a and 1500b may have a relatively smaller delay and bandwidth than I / O devices 1700a and 1700b or storage devices 1600a and 1600b. DRAM 1500a and 1500b may be initialized at the power-on time point of system 1000, and when the operating system and application data are loaded, they may be used as temporary storage devices for the operating system and application data, or as execution spaces for various software codes.

[0118] In DRAM 1500a and 1500b, four rules of addition / subtraction / multiplication / division, vector calculation, address calculation or fast Fourier transform (FFT) operation can be performed. In addition, in DRAM 1500a and 1500b, the function of performing inference can be realized. Here, it can be inferred by using a deep learning algorithm via an artificial neural network. The deep learning algorithm may include a training operation using various data training models and an inference operation by using a trained model to identify data. In an embodiment, the image captured by the user using the camera 1100 may be signal processed and stored in DRAM 1500b, and the accelerator block or accelerator chip 1820 may perform AI data calculations for identifying data by using the data stored in DRAM 1500b and the function for inference.

[0119] System 1000 may include multiple memories or multiple storage devices 1600a and 1600b, whose capacity is greater than that of DRAM 1500a and 1500b. The accelerator block or accelerator chip 1820 may perform training operations and AI data operations by using storage devices 1600a and 1600b. In an embodiment, each of storage devices 1600a and 1600b may include a memory controller 1610 and a flash memory 1620, and the training operations and AI data operations performed by AP 1800 and / or accelerator chip 1820 may be efficiently performed by utilizing the computing device provided in the memory controller 1610. Storage devices 1600a and 1600b may store photos captured using camera 1100, or may store data sent via a data network. For example, storage devices 1600a and 1600b may store augmented reality (AR) / virtual reality (VR), high definition (HD) or ultra high definition (UHD) content.

[0120] In system 1000, DRAM 1500a and 1500b may be the same as those described above. Figures 1 to 7 , Fig.11 and Fig.12 A memory device described herein. The memory device may include a sense amplifier that senses and amplifies data stored in a memory cell selected from among a plurality of memory cells in a memory cell array. The memory cell array may include: a plurality of bit lines connected to the plurality of memory cells; and a shielding bit line arranged between the plurality of bit lines and below the plurality of bit lines. According to a repair unit for replacing some bit lines including defective memory cells with redundant bit lines, the shielding bit line may be formed by an integrated body or a plurality of bodies. The control circuit includes a plurality of switches adaptively connected to the shielding bit line, and a bit line precharge voltage, an internal power supply voltage, or a ground voltage is selectively provided to the shielding bit line by controlling the plurality of switches during operation of the sense amplifier, and the shielding bit line may be allowed to be in a floating state. Therefore, the reliability and accuracy of the sense amplifier may be improved, and the performance of the memory device may be improved.

[0121] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A storage device, comprising: A memory cell array, comprising a plurality of bit lines connected to a plurality of memory cells and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines; a sense amplifier connected between the first sense drive signal line and the second sense drive signal line and configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells; a voltage generating circuit configured to generate a bit line precharge voltage and an internal power supply voltage based on a power supply voltage of the memory device; as well as a control circuit configured to selectively provide the bit line precharge voltage or the internal power supply voltage to the shielded bit line, Wherein, the level of the internal power supply voltage is greater than the level of the bit line precharge voltage.

2. The memory device according to claim 1, wherein: The sense amplifier is configured to perform an offset compensation operation in which a difference between threshold voltages of transistors included in the sense amplifier appears between a bit line to which a selected memory cell is connected and a complementary bit line, and The control circuit is configured to: during the offset compensation operation, provide the internal power supply voltage to the first sensing drive signal line, and provide a ground voltage to the second sensing drive signal line.

3. The memory device according to claim 2, wherein: The control circuit is configured to: providing the bit line precharge voltage to the shielded bit line before sensing and amplifying data stored in the selected memory cell; and During the offset compensation operation of the sense amplifier, the internal supply voltage is provided to the shielded bit line.

4. The memory device according to claim 2, wherein: The control circuit is configured to: providing the bit line precharge voltage to the shielded bit line before sensing and amplifying data stored in the selected memory cell; and During the offset compensation operation of the sense amplifier, the ground voltage is provided to the shielded bit line.

5. The memory device according to claim 2, wherein: The sense amplifier is configured to: after performing the offset compensation operation, perform a charge sharing operation based on the charge stored in the selected memory cell, and The control circuit is configured to provide the bit line precharge voltage to the first sensing drive signal line and the second sensing drive signal line during the charge sharing operation.

6. The memory device according to claim 5, wherein: The control circuit is configured to provide the internal supply voltage to the shielded bit line during the charge sharing operation of the sense amplifier.

7. The memory device according to claim 5, wherein: The control circuit is configured to provide the ground voltage to the shielded bit line during the charge sharing operation of the sense amplifier.

8. The memory device according to claim 5, wherein: The sense amplifier is configured to: after performing the charge sharing operation, perform a sensing operation based on voltage levels of the bit line and the complementary bit line, and The control circuit is configured to: during the sensing operation, provide the internal power supply voltage to the first sensing drive signal line, and provide the ground voltage to the second sensing drive signal line.

9. The memory device according to claim 8, wherein: The control circuit is configured to provide the internal supply voltage to the shielded bit line during the sensing operation of the sense amplifier.

10. The memory device according to claim 8, wherein: The control circuit is configured to provide the ground voltage to the shielded bit line during the sensing operation of the sense amplifier.

11. The memory device according to claim 1, wherein: The control circuit is configured to control the shielding bit line to be in a floating state.

12. A storage device comprising: A memory cell array comprises a normal area and a redundant area, wherein a plurality of bit lines connected to a plurality of memory cells are arranged in the normal area, and a redundant bit line is arranged in the redundant area, wherein: Some of the plurality of bit lines include defective memory cells, which are set as repair cells to be replaced by the redundant bit lines, and The memory cell array comprises: a first shielding bit line, arranged between first bit lines corresponding to the first repair unit among the plurality of bit lines, and arranged on a lower portion of the first bit line; a second shielding bit line disposed between second bit lines corresponding to the second repair unit among the plurality of bit lines and disposed on a lower portion of the second bit line; and a third shielding bit line disposed between the redundant bit lines and disposed on a lower portion of the redundant bit line; a voltage generating circuit configured to generate a bit line precharge voltage and an internal power supply voltage based on a power supply voltage of the memory device; and A control circuit configured to perform the following operations based on the connection of a memory cell selected from among the plurality of memory cells to one of the first bit lines: electrically connecting the voltage generating circuit to the first shielded bit line; and selectively providing a bit line precharge voltage or an internal power supply voltage to the first shielded bit line, Wherein, the level of the internal power supply voltage is greater than the level of the bit line precharge voltage.

13. The memory device according to claim 12, wherein: The control circuit is configured to perform the following operations based on the defective memory cell being connected to the second bit line: electrically disconnecting the voltage generating circuit from the second shielding bit line; electrically connecting the voltage generating circuit to the third shielded bit line; as well as The bit line precharge voltage or the internal power supply voltage is selectively provided to the third shielded bit line.

14. The memory device according to claim 12, further comprising: A sense amplifier is connected between the first sense drive signal line and the second sense drive signal line, and the sense amplifier is configured as follows: sensing and amplifying the data stored in the selected memory cell, and performing an offset compensation operation in which a difference between threshold voltages of transistors included in the sense amplifier appears between a bit line to which a selected memory cell is connected and a complementary bit line, The control circuit is configured to: during the offset compensation operation, provide the internal power supply voltage to the first sensing drive signal line, and provide a ground voltage to the second sensing drive signal line.

15. The memory device according to claim 14, wherein: The control circuit is configured to selectively provide the internal power supply voltage or the ground voltage to the first shielded bit line during the offset compensation operation of the sense amplifier.

16. The memory device according to claim 14, wherein: The sense amplifier is configured to: after performing the offset compensation operation, perform a charge sharing operation based on the charge stored in the selected memory cell, and The control circuit is configured to provide the bit line precharge voltage to the first sensing drive signal line and the second sensing drive signal line during the charge sharing operation.

17. The memory device according to claim 16, wherein: The control circuit is configured to selectively provide the internal power supply voltage or the ground voltage to the first shielded bit line during the charge sharing operation of the sense amplifier.

18. The memory device according to claim 16, wherein: The sense amplifier is configured to: after performing the charge sharing operation, perform a sensing operation based on voltage levels of the bit line and the complementary bit line, and The control circuit is configured to: during the sensing operation, provide the internal power supply voltage to the first sensing drive signal line, and provide the ground voltage to the second sensing drive signal line.

19. The memory device according to claim 18, wherein: The control circuit is configured to selectively provide the internal power supply voltage or the ground voltage to the first shielded bit line during the sensing operation of the sense amplifier.

20. A memory device comprising: A memory cell array, comprising a plurality of bit lines and a shielding bit line, the plurality of bit lines being connected to a plurality of memory cells, the shielding bit line being arranged between the plurality of bit lines and on lower portions of the plurality of bit lines, the shielding bit line being provided with a plurality of bodies; a voltage generating circuit configured to generate a bit line precharge voltage and an internal power supply voltage based on a power supply voltage of the memory device; as well as a control circuit comprising a plurality of switches respectively and adaptively electrically connected to the bodies of the plurality of shielded bit lines, Wherein, the control circuit is configured as follows: In response to the plurality of switches being turned on or off, selectively providing the bit line precharge voltage, the internal power supply voltage, or a ground voltage to each of the bodies of the plurality of shielded bit lines; and allowing each of the plurality of bodies of the shielded bit line to be in a floating state, and Wherein, the level of the internal power supply voltage is greater than the level of the bit line precharge voltage.

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