Memory and manufacturing method thereof, memory system and electronic equipment

Abstract

The embodiment of the invention discloses a memory and a manufacturing method thereof, a memory system and electronic equipment. The memory comprises a first semiconductor structure and a second semiconductor structure which are bonded, the first semiconductor structure includes: a global data processing circuit; the second semiconductor structure includes: a plurality of stacked dies, each die including a plurality of memory banks; wherein the at least two memory banks are coupled with the global data processing circuit and share the global data processing circuit.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to but are not limited to a memory and a manufacturing method thereof, a memory system, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) includes multiple banks, each of which is usually provided with a corresponding data processing circuit (e.g., a write driver, an input / output sense amplifier, etc.), which is used to process data to be written to the bank or data read from the bank.

[0003] However, each DRAM reads and writes only one target memory bank, and only the data processing circuit corresponding to the target memory bank is running, while the data circuits corresponding to other memory banks are idle, which may cause current leakage and additional overhead. Summary of the invention

[0004] The present disclosure provides a memory and a manufacturing method thereof, a memory system, and an electronic device.

[0005] According to a first aspect of an embodiment of the present disclosure, a memory is provided, including:

[0006] a bonded first semiconductor structure and a second semiconductor structure;

[0007] The first semiconductor structure includes: a global data processing circuit;

[0008] The second semiconductor structure includes: a plurality of stacked dies, each of which includes a plurality of memory banks; wherein at least two of the memory banks are coupled to the global data processing circuit and share the global data processing circuit.

[0009] In some embodiments, the global data processing circuit includes:

[0010] A write driver; wherein at least two of the storage bodies are coupled to the write driver and share the write driver.

[0011] In some embodiments, the global data processing circuit includes:

[0012] An input / output sense amplifier; wherein at least two of the memory banks are coupled to the input / output sense amplifier and share the input / output sense amplifier.

[0013] In some embodiments, the memory bank includes a plurality of memory array chips; the die further includes a plurality of local data processing circuits, the local data processing circuits being coupled to the global data processing circuit via local data lines;

[0014] The plurality of local data processing circuits correspond one-to-one to the plurality of storage array chips; wherein the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

[0015] In some embodiments, the local data processing circuit includes:

[0016] A word line driver, the word line driver is coupled to the memory array chip through a plurality of word lines; wherein the local data line includes the word line;

[0017] and / or;

[0018] A bit line sensing amplifier is coupled to the memory array slice through a plurality of bit lines; wherein the local data line includes the bit line.

[0019] In some embodiments, the memory bank includes a plurality of memory array chips; the first semiconductor structure further includes a plurality of local data processing circuits, the local data processing circuits being coupled to the global data processing circuit via local data lines;

[0020] The plurality of local data processing circuits correspond one-to-one to the plurality of storage array chips; wherein the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

[0021] In some embodiments, the local data processing circuit includes: a word line driver, a bit line sense amplifier, a row decoder, and a column decoder.

[0022] In some embodiments, the first semiconductor structure further comprises:

[0023] a multiplexer, coupled to at least two of the memory banks and the global data processing circuit, respectively;

[0024] The data cache circuit is coupled to the global data processing circuit via a global data line.

[0025] In some embodiments, the tube core includes a connection structure; wherein two adjacent tube cores are coupled via the connection structure.

[0026] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a memory is provided, the method comprising:

[0027] forming a first semiconductor structure comprising a global data processing circuit;

[0028] forming a second semiconductor structure, the second semiconductor structure comprising a plurality of stacked dies, the die comprising a plurality of memory banks;

[0029] The first semiconductor structure and the second semiconductor structure are bonded, and at least two of the memory banks are coupled to the global data processing circuit and share the global data processing circuit.

[0030] In some embodiments, forming the first semiconductor structure includes:

[0031] A write driver is formed; wherein the global data processing circuit includes the write driver; and at least two of the memory banks are coupled to the write driver and share the write driver.

[0032] In some embodiments, forming the first semiconductor structure includes:

[0033] An input / output sense amplifier is formed; wherein the global data processing circuit includes the input / output sense amplifier, and at least two of the memory banks are coupled to the input / output sense amplifier and share the input / output sense amplifier.

[0034] In some embodiments, the forming the second semiconductor structure includes: forming the die;

[0035] The forming of the tube core comprises:

[0036] forming a plurality of local data processing circuits; wherein the local data processing circuits are coupled to the global data processing circuit via local data lines;

[0037] A plurality of the storage bodies are formed; wherein the storage bodies include a plurality of storage array chips, and the plurality of storage array chips correspond one-to-one to the plurality of local data processing circuits; and the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

[0038] In some embodiments, forming a plurality of local data processing circuits comprises:

[0039] forming a word line driver; wherein the local data processing circuit includes the word line driver, the word line driver is coupled to the memory array slice through a plurality of word lines; the local data line includes the word line;

[0040] and / or,

[0041] A bit line sense amplifier is formed; wherein the local data processing circuit includes the bit line sense amplifier, and the bit line sense amplifier is coupled to the memory array slice through a plurality of bit lines; and the local data line includes the bit line.

[0042] In some embodiments, forming the first semiconductor structure includes:

[0043] forming a plurality of local data processing circuits; wherein the local data processing circuits are coupled to the global data processing circuit via local data lines;

[0044] The forming of the second semiconductor structure includes: forming the tube core;

[0045] The forming of the tube core comprises:

[0046] A plurality of the storage bodies are formed; wherein the storage bodies include a plurality of storage array chips, and the plurality of storage array chips correspond one-to-one to the plurality of local data processing circuits; and the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

[0047] In some embodiments, forming the first semiconductor structure includes:

[0048] forming a multiplexer, the multiplexer being coupled to at least two of the memory banks and the global data processing circuit, respectively;

[0049] A data cache circuit is formed, and the data cache circuit is coupled to the global data processing circuit through a global data line.

[0050] In some embodiments, forming the second semiconductor structure includes:

[0051] forming a plurality of the tube cores; wherein the tube cores include a connection structure;

[0052] Bonding a plurality of the tube cores; wherein two adjacent tube cores are coupled via the connection structure.

[0053] According to a third aspect of an embodiment of the present disclosure, a memory system is provided, including:

[0054] One or more memories as described in the first aspect of the embodiment of the present disclosure;

[0055] A memory controller is coupled to the memory and is configured to control the memory.

[0056] According to a fourth aspect of an embodiment of the present disclosure, an electronic device is provided, wherein the electronic device includes the memory system as described in the third aspect of the embodiment of the present disclosure.

[0057] In the embodiments of the present disclosure, a bonded first semiconductor structure and a second semiconductor structure are provided, and at least two storage bodies in the second semiconductor structure are coupled to the global data processing circuit in the first semiconductor structure and share the global data processing circuit. Thus, on the one hand, the number of global data processing circuits can be reduced, thereby reducing current leakage and additional overhead; on the other hand, the size of the memory can be reduced due to the reduction in the number of global data processing circuits and the stacking of multiple dies; on the third hand, the memory with a three-dimensional architecture provided by the present disclosure is compatible with existing 3D packaging without a significant increase in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0059] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0060] Figure 2 is a schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure;

[0061] Figure 3 is a schematic diagram showing the connection of word lines, bit lines and storage units of a dynamic random access memory according to an embodiment of the present disclosure;

[0062] Figure 4 It is a schematic diagram of the distribution of a memory bank, a memory array chip and a peripheral circuit in a dynamic random access memory according to an embodiment of the present disclosure;

[0063] Figure 5 is a schematic diagram showing the connection between a memory bank and a peripheral circuit in a dynamic random access memory according to an embodiment of the present disclosure;

[0064] Figure 6a is a cross-sectional diagram of a memory according to an embodiment of the present disclosure Figure 1 ;

[0065] Figure 6b is a schematic diagram of a first semiconductor structure and a second semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0066] Figure 7a is a cross-sectional diagram of a memory according to an embodiment of the present disclosure Figure 2 ;

[0067] Figure 7bis a schematic diagram of a first semiconductor structure and a second semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0068] Figure 8a is a cross-sectional diagram of a memory according to an embodiment of the present disclosure Figure 3 ;

[0069] Figure 8b is a schematic diagram of a first semiconductor structure and a second semiconductor structure according to an embodiment of the present disclosure Figure 3 ;

[0070] Fig. 9 is a schematic diagram of the structure of a memory according to an embodiment of the present disclosure;

[0071] Fig.10 It is a flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0073] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0074] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0075] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0077] Figure 1 1 is a schematic diagram of the composition structure of an electronic device 1 according to an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. Figure 1 As shown, the electronic device 1 may include a host HOST and a memory system 30, the memory system 30 including a memory controller 10 and one or more memories 20. The host HOST may be a processor of an electronic device (e.g., a central processing unit (CPU) or a graphic processing unit (GPU)). The host HOST may be configured to send data to the memory 20 or receive data from the memory 20. The memory controller 10 is coupled to the memory 20 and the host HOST, and is configured to control the memory 20. The memory controller 10 may manage data stored in the memory 20 and communicate with the host HOST.

[0078] The memory controller 10 may be configured to control operations of the memory 20, such as read, write, and refresh operations. In some embodiments, the memory controller 10 is also configured to process error correction codes (ECC) on data read from or written to the memory 20. The memory controller 10 may also perform any other suitable functions, such as formatting the memory 20.

[0079] In a specific embodiment, the memory controller 10 and one or more memories 20 can be integrated into various types of electronic devices. For example, the memory controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into a computer CPU, and multiple memories 20 can be integrated into a memory stick. In other words, the memory system 30 can be implemented and packaged into different types of terminal electronic products.

[0080] The memory controller 10 may send data to or receive data from the host HOST, and may send a command CMD and an address ADDR to the memory 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 may receive a command CMD and an address ADDR from the host HOST, and the command generator 110 may generate an access command, a refresh command, etc. by decoding the command CMD received from the host HOST, and may provide the access command and the refresh command to the memory 20 through the device interface 130. The access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. The refresh command may be a signal instructing the memory 20 to read out and rewrite data by accessing a row of the memory cell array 220 corresponding to the refresh address ADDR.

[0081] The address generator 120 in the memory controller 10 may generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. In addition, the memory 20 may generate an address of a bank to be accessed when the memory cell array 220 includes a plurality of banks.

[0082] In addition, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 130. For example, the memory controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20.

[0083] The memory 20 includes a memory cell array 220 and a peripheral circuit 210. The peripheral circuit 210 can write data to or read data from the memory cell array 220 based on a command CMD and an address ADDR received from the memory controller 10, or can send data to the memory cell array 220. Figure 2 The row decoder 212 and the column decoder 213 shown in FIG. 2 provide a control signal CTRL for refreshing memory cells included in the memory cell array 220. In other words, the peripheral circuit 210 may perform all operations to process data in the memory cell array 220.

[0084] The memory 20 may be a random access memory (RAM), DRAM, synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description only takes DRAM as an example.

[0085] Figure 2 FIG. 2 is a schematic diagram of a dynamic random access memory 20 according to an embodiment of the present disclosure. Figure 2 As shown, the dynamic random access memory 20 includes at least one die, each die includes a memory cell array, the memory cell array includes a plurality of memory bodies 221, each memory body includes a plurality of memory array tiles MAT (Memory Array Tile) 222, each memory array tile 222 includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. It should be noted that the number of memory bodies in the memory can be 2, 4, 8 or even more, and each memory body can independently perform operations such as activation, precharging, writing, and reading.

[0086] Figure 3 1 is a schematic diagram showing the connection of word lines, bit lines and storage units of a dynamic random access memory according to an embodiment of the present disclosure. Figure 3 As shown, the memory cell array 220 includes a plurality of memory cells 201 arranged in an array, each memory cell 201 includes a transistor T (Transistor) and a capacitor C (Capacitor), and the main working principle of the memory cell 201 is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells 201 are arranged in an array, which can be regarded as a typical mesh structure. The memory cell array uses rows (Row) and columns (Column) to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform operations such as reading, writing or refreshing on it.

[0087] Figure 4 1 is a schematic diagram showing the distribution of a memory bank, a memory array chip, and a peripheral circuit in a dynamic random access memory according to an embodiment of the present disclosure. Figure 4As shown, the peripheral circuit may include: a local data processing circuit corresponding to each memory array chip, for example, a bit line sensing amplifier BLSA (Bit Line Sensing Amplifier), a word line driver WLD (Word Line Driver), etc.; a global data processing circuit corresponding to each memory body, for example, a write driver WD (WriteDriver), an input / output sensing amplifier IOSA (Input / Output Sensing Amplifier), etc.; and other circuits corresponding to all memory bodies, for example, a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0088] Exemplarily, the memory includes 8 dies, each of which includes 2 memory banks. Therefore, there are 16 memory banks in the memory, which are respectively recorded as bank0, bank1, ..., bank15. Figure 4 As shown, each storage body includes multiple storage array slices MAT (such as Figure 4 As shown on the right side of the diagram, each memory array chip MAT is surrounded by bit line sense amplifiers BLSA and word line drivers WLD corresponding to the memory array chip MAT, and each memory bank is provided with input / output sense amplifiers IOSA and write drivers WD corresponding to the memory bank on both sides. Every 4 memory banks form a memory bank row, and 16 memory banks form 4 memory bank rows. Other circuits corresponding to all memory banks are provided between the two middle memory bank rows. It should be noted that Figure 4 The number of storage bodies in the figure is only used as an example and is not used to limit the number of storage bodies in this application.

[0089] Figure 5 1 is a schematic diagram showing the connection between a memory bank and a peripheral circuit in a dynamic random access memory according to an embodiment of the present disclosure. Figure 5 As shown, the memory includes N storage banks, which are respectively recorded as bank1, ..., bankN, where N is an integer greater than 1. The peripheral circuit includes a global data processing circuit and a multiplexer (MUX). Figure 5 Not shown in the figure, the peripheral circuit may also include other circuits known in the art.

[0090] The global data processing circuit includes at least one of a write driver and an input / output sense amplifier; wherein the write driver is used to process data to be written into the storage body, for example, writing data received from the transmitting end TX via the data bus Data bus into the storage body; the input / output sense amplifier is used to process data read from the storage body, for example, sending the data read from the storage body to the transmitting end TX via the data bus Data bus. Here, the transmitting end TX can be the above-mentioned Figure 1 The host HOST or memory controller 10. Of course, the transmitting end TX can also be any device capable of sending data, such as a computer, a mobile phone, a server, etc.

[0091] The global data processing circuit is coupled to the corresponding storage body through the local data line DL (Data Line). For example, the input / output sense amplifier IOSA_1 and the write driver WD_1 are coupled to the storage body bank1 through the local data line DL_BK1, and the input / output sense amplifier IOSA_N and the write driver WD_N are coupled to the storage body bankN through the local data line DL_BKN.

[0092] The multiplexer is configured to select one of the plurality of memory banks based on the received memory bank selection signal. For example, the multiplexer may select one of the plurality of memory bank addresses based on the received memory bank selection signal to select the memory bank corresponding to the memory bank address. Here, different memory banks correspond to different memory bank addresses.

[0093] The multiplexer is coupled to multiple global data processing circuits through multiple local data lines LBDL (Local Bank Data Line), for example, the multiplexer is coupled to the input / output sense amplifier IOSA_1 and the write driver WD_1 through the local data line LBDL_BK1, and the multiplexer is coupled to the input / output sense amplifier IOSA_N and the write driver WD_N through the local data line LBDL_BKN. The data bus is coupled to the multiplexer through the global data line GDAL (Global Data Access Line).

[0094] Each DRAM read and write operation targets only one target storage body. Taking bank1 as an example, the transmission path of the data read from bank1 is bank1→DL_BK1→LBDL_BK1→GDAL→Data bus→TX. Only the global data processing circuit corresponding to bank1 is running, and the global data circuits corresponding to other storage bodies are idle, which may cause current leakage and additional overhead.

[0095] Furthermore, in a conventional planar memory architecture, it is difficult to share global data circuits among multiple memory banks due to data line limitations and performance degradation.

[0096] Based on one or more of the above technical problems, the present disclosure provides a memory and a manufacturing method thereof, a memory system, and an electronic device.

[0097] Figure 6ais a cross-sectional view of a memory 300 according to an embodiment of the present disclosure. Figure 1 , Figure 6b is a schematic diagram of a first semiconductor structure 310 and a second semiconductor structure 320 according to an embodiment of the present disclosure. Figure 1 The following will combine Figure 6a and Figure 6b The memory 300 provided in the embodiment of the present disclosure is described.

[0098] Reference Figure 6a As shown, the memory 300 includes a bonded first semiconductor structure 310 and a second semiconductor structure 320. At least part of the peripheral circuit may be formed in the first semiconductor structure 310, and a memory cell array may be formed in the second semiconductor structure 320. The peripheral circuit is coupled to the memory cell array, and the peripheral circuit is configured to control the logical operation of the memory cell array (for example, writing, reading or refreshing, etc.). Here, the specific structure and composition of the peripheral circuit and the memory cell array can refer to the detailed description of the peripheral circuit and the memory cell array in the aforementioned embodiment. For the sake of brevity, it will not be repeated here. The memory 300 includes but is not limited to DRAM. In the embodiment of the present disclosure, the memory 300 is described as DRAM as an example.

[0099] The bonding method of the first semiconductor structure 310 and the second semiconductor structure 320 includes but is not limited to hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc. When the first semiconductor structure 310 and the second semiconductor structure 320 are stacked in a bonding manner, the global data processing circuit 330 and / or the local data processing circuit and other related circuits in the present disclosure can be placed under the memory cell array, thereby forming a DRAM with a three-dimensional architecture.

[0100] The first semiconductor structure 310 includes a global data processing circuit 330, which includes at least one of a write driver and an input / output sense amplifier. The write driver and the input / output sense amplifier will be described in detail in the embodiments below. The first semiconductor structure 310 can be a die or a wafer formed with at least part of the peripheral circuit.

[0101] The second semiconductor structure 320 includes a plurality of stacked dies, for example, Figure 6a It is shown that the tube core 320-1 to the tube core 320-M are stacked sequentially from bottom to top, and M is an integer greater than 1. The tube core includes multiple memory banks, and at least two memory banks are coupled to the global data processing circuit 330 and share the global data processing circuit 330. The number of memory banks in each tube core can be 2 or more, and the present disclosure has no special restrictions on this. The following will be described by taking each tube core including 2 memory banks and the second semiconductor structure 320 including 2M memory banks as an example.

[0102] In some embodiments, 2M memory bodies share a global data processing circuit 330, that is, only one global data processing circuit 330 may be set in the memory 300. In this way, current leakage and additional overhead caused by the global data circuit being in an idle state can be avoided; and since the number of global data processing circuits 330 is reduced, the size of the memory can be reduced.

[0103] In some embodiments, some of the 2M memory bodies share a global data processing circuit 330, and memory bodies other than some of the 2M memory bodies are provided with a global data processing circuit 330 corresponding to the memory body, that is, the number of global data processing circuits 330 in the memory 300 is less than 2M. In this way, the number of global data circuits in the memory 300 can be reduced, thereby reducing current leakage and additional overhead; and since the number of global data processing circuits 330 is reduced, the size of the memory can be reduced.

[0104] In the embodiments of the present disclosure, a bonded first semiconductor structure and a second semiconductor structure are provided, and at least two storage bodies in the second semiconductor structure are coupled to the global data processing circuit in the first semiconductor structure and share the global data processing circuit. Thus, on the one hand, the number of global data processing circuits can be reduced, thereby reducing current leakage and additional overhead; on the other hand, the size of the memory can be reduced due to the reduction in the number of global data processing circuits and the stacking of multiple dies; on the third hand, the memory with a three-dimensional architecture provided by the present disclosure is compatible with existing 3D packaging without a significant increase in cost.

[0105] In some embodiments, the first semiconductor structure further includes: a multiplexer 340, coupled to at least two memory banks and the global data processing circuit, respectively. Figure 6a and Figure 6b It is shown that a plurality of memory banks are coupled to the multiplexer 340 through a plurality of local data lines DL, and the multiplexer 340 is coupled to the global data processing circuit through a memory bank group data line BGDL (Bank Group Data Line).

[0106] In some embodiments, the multiplexer 340 is configured to select a memory bank address from among the multiple memory bank addresses based on the received memory bank selection signal to perform a corresponding logic operation on the memory bank corresponding to the memory bank address. The logic operation includes activation, precharging, writing, reading and other operations. In this way, each memory bank sharing the global data processing circuit can independently perform a corresponding logic operation, thereby avoiding data errors between each memory bank sharing the global data processing circuit and ensuring the reliability of the memory.

[0107] In some embodiments, the global data processing circuit includes: a write driver; wherein at least two storage bodies are coupled to the write driver and share the write driver. In this embodiment, the write driver is used to process data to be written into the storage body, for example, writing data received by the data bus Data bus from the transmitting end TX into the storage body.

[0108] Exemplarily, the write driver can write the data of the global data line GDAL to the storage bank1 via the storage group data line BGDL and the local data line DL_BK1 based on the received first write drive signal; the write driver can write the data of the global data line GDAL to the storage bankN via the storage group data line BGDL and the local data line DL_BKN based on the received second write drive signal; wherein the first write drive signal and the second write drive signal are received at different times. In this example, the storage bank1 and the storage bankN share a write driver, so that the number of write drivers in the memory can be reduced, thereby reducing current leakage and additional overhead during write operations. Here, the number of storage bodies that share a write driver is not limited to 2 in this example, but can be more.

[0109] In some embodiments, the global data processing circuit includes: an input / output sense amplifier; wherein at least two memory banks are coupled to the input / output sense amplifier and share the input / output sense amplifier. In this embodiment, the input / output sense amplifier is used to process data read from the memory bank, for example, to send the data read from the memory bank to the transmitting end TX through the data bus Data bus.

[0110] Exemplarily, the input / output sense amplifier can amplify the data read from the memory bank1 and transmitted via the local data line DL_BK1 and the memory group data line BGDL based on the received first read drive signal, and transmit the amplified data to the data bus Data bus via the global data line GDAL; the input / output sense amplifier can amplify the data read from the memory bankN and transmitted via the local data line DL_BKN and the memory group data line BGDL based on the received second read drive signal, and transmit the amplified data to the data bus Data bus via the global data line GDAL; wherein the first read drive signal and the second read drive signal are received at different times. In this example, bank1 and bankN share the input / output sense amplifier, so that the number of input / output sense amplifiers in the memory can be reduced, thereby reducing the current leakage and additional overhead during the read operation. Here, the number of memory banks that share the input / output sense amplifier is not limited to 2 in this example, but can also be more.

[0111] It should be noted that the global data processing circuit may include a write driver and an input / output sense amplifier and be arranged in a first semiconductor structure; or, the global data processing circuit may include a write driver (or an input / output sense amplifier) ​​and be arranged in a first semiconductor structure, and the input / output sense amplifier may be arranged as a separate circuit (or write driver) in a second semiconductor structure. In this way, the circuits related to the memory cell array can be flexibly arranged according to the storage characteristics.

[0112] In some embodiments, the storage body includes multiple storage array chips; the tube core also includes multiple local data processing circuits, and the local data processing circuits are coupled to the global data processing circuit through local data lines; the multiple local data processing circuits correspond one-to-one to the multiple storage array chips; wherein the local data processing circuits are coupled to the storage array chips through multiple local data lines.

[0113] The memory array chip can be coupled to the local data processing circuit via a plurality of local data lines. Here, the local data lines include word lines and bit lines. The local data processing circuit includes: a word line driver, a bit line sense amplifier, a row decoder, a column decoder, etc. The arrangement of the word line driver, the bit line sense amplifier, the row decoder, the column decoder and the memory array chip can refer to the relevant description in the above embodiments.

[0114] Exemplarily, the row decoder is used to decode and generate a row selection signal based on the received row address signal; the word line driver is used to select the corresponding word line based on the row selection signal; the column decoder is used to decode and generate a column selection signal based on the received column address signal; the bit line sense amplifier is used to select the corresponding bit line based on the column selection signal. By selecting the corresponding word line and bit line, each storage unit can be independently accessed and read, written or refreshed.

[0115] In a specific embodiment, local data processing circuits corresponding to each memory array chip may be arranged around the memory array chip. Thus, the local data processing circuits corresponding to each memory array chip may be arranged in the second semiconductor structure.

[0116] In the disclosed embodiment, by setting the local data processing circuit corresponding to each memory array chip in the second semiconductor structure, part of the peripheral circuit of the memory can be set in the second semiconductor structure, thereby increasing the flexibility of the circuit arrangement related to the memory cell array. In practical applications, those skilled in the art can make reasonable settings according to design requirements.

[0117] In one example, a local data processing circuit includes: a word line driver, the word line driver is coupled to a memory array slice via a plurality of word lines; wherein the local data line includes a word line.

[0118] In another example, a local data processing circuit includes: a bit line sense amplifier, the bit line sense amplifier is coupled to a memory array slice through a plurality of bit lines; wherein the local data lines include the bit lines.

[0119] In another example, a local data processing circuit includes: a word line driver and a bit line sense amplifier, the word line driver is coupled to a storage array chip through multiple word lines, and the bit line sense amplifier is coupled to a storage array chip through multiple bit lines; wherein the local data line includes a word line and a bit line.

[0120] It can be understood that the local data processing circuit may include a word line driver and a bit line sense amplifier and be arranged in the second semiconductor structure; alternatively, the local data processing circuit may include a word line driver (or a bit line sense amplifier) ​​and be arranged in the second semiconductor structure, and the bit line sense amplifier may be arranged as a separate circuit (or word line driver) in the first semiconductor structure. In this way, the circuits related to the memory cell array can be flexibly arranged according to the storage characteristics.

[0121] In other embodiments, the first semiconductor structure also includes multiple local data processing circuits, which are coupled to the global data processing circuits through local data lines; the multiple local data processing circuits correspond one-to-one to the multiple storage array chips; wherein the local data processing circuits are coupled to the storage array chips through multiple local data lines.

[0122] It can be understood that in this embodiment, the circuits related to the memory cell array can be set in the first semiconductor structure. In this way, the second semiconductor structure is a pure array, that is, it only includes a memory cell array composed of multiple memory cells, and the peripheral circuits for controlling the memory cell array are all set in the first semiconductor structure.

[0123] In some embodiments, the first semiconductor structure further includes: a data cache circuit coupled to the global data processing circuit via a global data line. Figure 2 .

[0124] The data cache circuit is coupled to the global data processing circuit via a global data line. When a write operation is performed on a selected storage unit in the storage bank, the data cache circuit can transmit the data to be written to the global data processing circuit via a data bus. When a read operation is performed on a selected storage unit in the storage bank, the global data processing circuit can transmit the read and amplified data to the data cache circuit via the data bus.

[0125] The data cache circuit can also receive data from the memory controller (refer to Figure 1 ) to transfer data to be written, or to transfer data read from a storage unit to a memory controller.

[0126] In some embodiments, the tube core includes a connection structure, wherein two adjacent tube cores are coupled through the connection structure. The connection structure can be a vertical interconnection that penetrates the wafer or tube core, for example, a through silicon via (TSV) structure, which is beneficial to multi-chip package (MCP) by utilizing TSV technology.

[0127] Figure 7a is a cross-sectional view of a memory 300 according to an embodiment of the present disclosure. Figure 2 , Figure 7b is a schematic diagram of a first semiconductor structure 310 and a second semiconductor structure 320 according to an embodiment of the present disclosure. Figure 2 The following will combine Figure 7a and Figure 7b An example in which the local data processing circuit is disposed in the second semiconductor structure 320 and the global data processing circuit is disposed in the first semiconductor structure 310 is described in detail.

[0128] Reference Figure 7a and Figure 7b As shown, the second semiconductor structure 320 includes a memory cell array Array and a local circuit Local circuit, and the memory cell array Array can be coupled to the local circuit Local circuit through a local data line DL. Here, the memory cell array Array can refer to the relevant description in the aforementioned embodiment, and the local circuit Local circuit can refer to the relevant description of the local data processing circuit in the aforementioned embodiment.

[0129] It should be noted that the local circuit Local circuit may include at least one of a word line driver and a bit line sense amplifier. When the local circuit Local circuit only includes a word line driver (or a bit line sense amplifier), the bit line sense amplifier (or word line driver) may be disposed in the first semiconductor structure. For example, the local circuit Local circuit only includes a bit line sense amplifier, and the first semiconductor structure may further include circuits such as a word line pre-driver or a column pre-decoder.

[0130] The first semiconductor structure 310 includes a functional circuit, a multiplexer MUX, a write driver WD / input / output sense amplifier IOSA, a data buffer circuit Buffers and other circuits. The local circuit Localcircuit can be coupled to the multiplexer MUX through a conductive structure Conjunction (e.g., a bonding structure). The functional circuit includes but is not limited to a charge pump, a voltage regulator, etc. The memory can transmit data to be written or read through a data interface DQblocks.

[0131] It should be noted that a signal line signal connection for transmitting a control signal is also provided in the second semiconductor structure 320, and the control signal is used to control the storage cell array to perform corresponding operations, for example, the first write drive signal, the second write drive signal, the first read drive signal, the second read drive signal and other control signals mentioned in the aforementioned embodiments.

[0132] Figure 8a is a cross-sectional view of a memory 300 according to an embodiment of the present disclosure. Figure 2 , Figure 8b is a schematic diagram of a first semiconductor structure 310 and a second semiconductor structure 320 according to an embodiment of the present disclosure. Figure 2 The following will combine Figure 8a and Figure 8b An example in which both the local data processing circuit and the global data processing circuit are disposed in the first semiconductor structure 310 is described in detail.

[0133] Reference Figure 8a and Figure 8b As shown, the second semiconductor structure 320 includes a memory cell array Array, that is, the second semiconductor structure is a pure array. The first semiconductor structure 310 includes a functional circuit functional circuit, a local circuit Localcircuit, a multiplexer MUX, a write driver WD / input / output sense amplifier IOSA, a data buffer circuit Buffers and other circuits. Here, the memory cell array Array can be coupled to the local circuit Local circuit through a conductive structure Connection (for example, a bonding structure).

[0134] Fig. 9 4 is a schematic diagram showing a structure of a memory 400 according to an embodiment of the present disclosure. Fig. 9As shown, the memory 400 includes a bonded first semiconductor structure 410 and a second semiconductor structure 420, the first semiconductor structure 410 includes a first bonding structure 411, the second semiconductor structure 420 includes a second bonding structure 421, the first semiconductor structure 410 and the second semiconductor structure 420 can be bonded through the first bonding structure 411 and the second bonding structure 421, and the contact interface between the first semiconductor structure 410 and the second semiconductor structure 420 can be a bonding interface between the first bonding structure 411 and the second bonding structure 421.

[0135] In some embodiments, the peripheral circuit is coupled to the first bonding structure 411 through a first interconnect structure. The first interconnect structure includes one or more first interconnect layers. Fig. 9 As shown, the first interconnect structure includes a plurality of first interconnect layers 412 , and two adjacent first interconnect layers 412 are coupled via first interconnect pillars 413 .

[0136] In some embodiments, the memory cell array is coupled to the second bonding structure 421 via a second interconnect structure. The second interconnect structure includes one or more second interconnect layers. Fig. 9 As shown, the second interconnect structure includes a plurality of second interconnect layers 422 , and two adjacent second interconnect layers 422 are coupled via second interconnect pillars 423 .

[0137] Here, the specific structure and composition of the memory 400 can refer to the detailed description of the memory 300 in the aforementioned embodiment, and other details of the memory 400 are similar to those described above, and will not be repeated here for the sake of brevity.

[0138] Based on the same inventive concept as the above-mentioned memory, an embodiment of the present disclosure also provides a method for manufacturing a memory. Fig.10 is a flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure. Fig.10 As shown, the manufacturing method at least comprises the following steps:

[0139] S510: forming a first semiconductor structure, wherein the first semiconductor structure includes a global data processing circuit;

[0140] S520: forming a second semiconductor structure, the second semiconductor structure comprising a plurality of stacked dies, the dies comprising a plurality of memory cells;

[0141] S530: Bonding the first semiconductor structure and the second semiconductor structure, at least two memory cells are coupled to the global data processing circuit and share the global data processing circuit.

[0142] In some embodiments, the above step S510 includes: forming a write driver; wherein the global data processing circuit includes the write driver; and at least two storage bodies are coupled to the write driver and share the write driver.

[0143] In some embodiments, the step S510 includes: forming an input / output sense amplifier; wherein the global data processing circuit includes the input / output sense amplifier, and at least two memory banks are coupled to the input / output sense amplifier and share the input / output sense amplifier.

[0144] In some embodiments, the above step S520 includes: forming a tube core. The specific steps of forming the tube core include: forming a plurality of local data processing circuits, the local data processing circuits are coupled to the global data processing circuit through local data lines; forming a plurality of storage bodies, the storage bodies include a plurality of storage array chips, the plurality of storage array chips correspond to the plurality of local data processing circuits one by one, and the local data processing circuits are coupled to the storage array chips through a plurality of local data lines.

[0145] In some embodiments, the above-mentioned forming of a plurality of local data processing circuits includes:

[0146] forming a word line driver; wherein the local data processing circuit includes a word line driver, the word line driver is coupled to the memory array slice through a plurality of word lines; the local data line includes a word line;

[0147] and / or,

[0148] A bit line sense amplifier is formed; wherein the local data processing circuit includes a bit line sense amplifier, the bit line sense amplifier is coupled to the storage array slice through a plurality of bit lines; and the local data line includes a bit line.

[0149] In some embodiments, the above step S510 includes: forming a plurality of local data processing circuits; wherein the local data processing circuits are coupled to the global data processing circuit via local data lines;

[0150] The above-mentioned step S520 includes: forming a tube core; the specific steps of forming the tube core include: forming multiple storage bodies; wherein the storage body includes multiple storage array chips, and the multiple storage array chips correspond one-to-one to multiple local data processing circuits; the local data processing circuit is coupled to the storage array chip through multiple local data lines.

[0151] In some embodiments, the above step S510 includes:

[0152] forming a multiplexer, the multiplexer being coupled to at least two memory banks and the global data processing circuit respectively;

[0153] A data cache circuit is formed, and the data cache circuit is coupled to the global data processing circuit through a global data line.

[0154] In some embodiments, the above step S520 includes:

[0155] forming a plurality of tube cores; wherein the tube cores include a connection structure;

[0156] A plurality of tube cores are bonded, wherein two adjacent tube cores are coupled via a connection structure.

[0157] Based on the above memory, an embodiment of the present disclosure further provides a memory system, including:

[0158] one or more memories;

[0159] A memory controller is coupled to the memory and is configured to control the memory.

[0160] Here, the specific structure and composition of the memory system can refer to the detailed description of the memory system in the aforementioned embodiment, and other details of the memory system are similar to the aforementioned ones, and will not be repeated here for the sake of brevity.

[0161] Based on the above memory, an embodiment of the present disclosure further provides an electronic device, and the electronic device includes the above memory system.

[0162] Here, the specific structure and composition of the electronic device can refer to the detailed description of the electronic device in the aforementioned embodiment, and other details of the electronic device are similar to the aforementioned ones, and will not be repeated here for the sake of brevity.

[0163] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0164] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0165] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0166] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0167] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: a bonded first semiconductor structure and a second semiconductor structure; The first semiconductor structure includes: a global data processing circuit; The second semiconductor structure includes: a plurality of stacked dies, each of which includes a plurality of memory banks; wherein at least two of the memory banks are coupled to the global data processing circuit and share the global data processing circuit.

2. The memory according to claim 1, characterized in that: The global data processing circuit comprises: A write driver; wherein at least two of the storage bodies are coupled to the write driver and share the write driver.

3. The memory according to claim 1 or 2, characterized in that: The global data processing circuit comprises: An input / output sense amplifier; wherein at least two of the memory banks are coupled to the input / output sense amplifier and share the input / output sense amplifier.

4. The memory according to claim 1, characterized in that: The memory body includes a plurality of memory array chips; the die also includes a plurality of local data processing circuits, and the local data processing circuits are coupled to the global data processing circuit via local data lines; The plurality of local data processing circuits correspond one-to-one to the plurality of storage array chips; wherein the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

5. The memory according to claim 4, characterized in that: The local data processing circuit comprises: A word line driver, the word line driver is coupled to the memory array chip through a plurality of word lines; wherein the local data line includes the word line; and / or; A bit line sensing amplifier is coupled to the memory array slice through a plurality of bit lines; wherein the local data line includes the bit line.

6. The memory according to claim 1, characterized in that: The memory body includes a plurality of memory array chips; the first semiconductor structure also includes a plurality of local data processing circuits, and the local data processing circuits are coupled to the global data processing circuit via local data lines; The plurality of local data processing circuits correspond one-to-one to the plurality of storage array chips; wherein the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

7. The memory according to claim 6, characterized in that: The local data processing circuit includes a word line driver, a bit line sense amplifier, a row decoder and a column decoder.

8. The memory according to claim 1, characterized in that: The first semiconductor structure further comprises: a multiplexer, coupled to at least two of the memory banks and the global data processing circuit, respectively; The data cache circuit is coupled to the global data processing circuit via a global data line.

9. The memory according to claim 1, characterized in that: The tube core includes a connection structure; wherein two adjacent tube cores are coupled via the connection structure.

10. The memory according to claim 1, characterized in that: The memory includes dynamic random access memory.

11. A method for manufacturing a memory, characterized in that: The production method comprises: forming a first semiconductor structure comprising a global data processing circuit; forming a second semiconductor structure, the second semiconductor structure comprising a plurality of stacked dies, the die comprising a plurality of memory banks; The first semiconductor structure and the second semiconductor structure are bonded, and at least two of the memory banks are coupled to the global data processing circuit and share the global data processing circuit.

12. The manufacturing method according to claim 11, characterized in that: The forming of the first semiconductor structure comprises: A write driver is formed; wherein the global data processing circuit includes the write driver; and at least two of the memory banks are coupled to the write driver and share the write driver.

13. The production method according to claim 11 or 12, characterized in that: The forming of the first semiconductor structure comprises: An input / output sense amplifier is formed; wherein the global data processing circuit includes the input / output sense amplifier, and at least two of the memory banks are coupled to the input / output sense amplifier and share the input / output sense amplifier.

14. The manufacturing method according to claim 11, characterized in that: The forming of the second semiconductor structure includes: forming the tube core; The forming of the tube core comprises: forming a plurality of local data processing circuits; wherein the local data processing circuits are coupled to the global data processing circuit via local data lines; A plurality of the storage bodies are formed; wherein the storage bodies include a plurality of storage array chips, and the plurality of storage array chips correspond one-to-one to the plurality of local data processing circuits; and the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

15. The manufacturing method according to claim 14, characterized in that: The forming of a plurality of local data processing circuits comprises: forming a word line driver; wherein the local data processing circuit includes the word line driver, the word line driver is coupled to the memory array slice through a plurality of word lines; the local data line includes the word line; and / or, A bit line sense amplifier is formed; wherein the local data processing circuit includes the bit line sense amplifier, and the bit line sense amplifier is coupled to the memory array slice through a plurality of bit lines; and the local data line includes the bit line.

16. The manufacturing method according to claim 11, characterized in that: The forming of the first semiconductor structure comprises: forming a plurality of local data processing circuits; wherein the local data processing circuits are coupled to the global data processing circuit via local data lines; The forming of the second semiconductor structure includes: forming the tube core; The forming of the tube core comprises: A plurality of the storage bodies are formed; wherein the storage bodies include a plurality of storage array chips, and the plurality of storage array chips correspond one-to-one to the plurality of local data processing circuits; and the local data processing circuits are coupled to the storage array chips via a plurality of local data lines.

17. The manufacturing method according to claim 11, characterized in that: The forming of the first semiconductor structure comprises: forming a multiplexer, the multiplexer being coupled to at least two of the memory banks and the global data processing circuit, respectively; A data cache circuit is formed, and the data cache circuit is coupled to the global data processing circuit through a global data line.

18. The manufacturing method according to claim 11, characterized in that: The forming of the second semiconductor structure comprises: forming a plurality of the tube cores; wherein the tube cores include a connection structure; Bonding a plurality of the tube cores; wherein two adjacent tube cores are coupled via the connection structure.

19. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 10; A memory controller is coupled to the memory and is configured to control the memory.

20. An electronic device, characterized in that: include: The memory system of claim 19.

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