Reconfigurable 10T SRAM cell circuit for energy-saving CAM operation and memory computation

Abstract

The invention relates to the field of integrated circuits, and discloses a reconfigurable 10T SRAM (Static Random Access Memory) unit circuit for energy-saving CAM (Content Addressable Memory) operation and memory calculation. The 10T SRAM circuit comprises reading ports which are decoupled in the horizontal direction and the vertical direction, supports cross-row and cross-column reading operation, and realizes matrix transposition, logic operation and parallel search functions. The invention provides a self-suppression discharge mechanism, the discharge swing of the matching line is obviously reduced, the sneak current problem caused by multi-row activation is effectively solved, and the anti-interference capability of the circuit is improved. Aiming at storage and calculation requirements, the invention provides three working modes, namely a conventional SRAM (Static Random Access Memory) mode, an in-memory logic operation mode and a content addressable memory mode. Especially in a content addressable memory mode, line-by-line search is adopted, additional data movement caused by vertical data storage is avoided, and compatibility among different working modes is enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit circuits, and in particular relates to a reconfigurable 10T SRAM unit circuit for energy-saving CAM operations and memory calculations. Background Art

[0002] For a long time, the von Neumann architecture has been considered a mainstream computing paradigm. However, with the rapid development of data-intensive applications such as machine learning and artificial intelligence, the frequent data transmission between computing units and storage units has led to increased power consumption and reduced throughput, resulting in bottlenecks of storage wall and bandwidth wall. In order to solve this bottleneck, the in-memory computing architecture was proposed. The in-memory computing structure is favored by academia and industry because it is expected to break through the bottleneck of the von Neumann architecture.

[0003] In-memory computing, as a key technology to break through the bottleneck of the von Neumann architecture, has received widespread attention in recent years. Its core lies in directly performing logical operations and data processing inside the memory, thereby reducing the energy consumption and delay of data transmission.

[0004] In-memory logic operations are an important part of in-memory computing. Existing studies have proposed circuit structures based on 8T SRAM and 10TSRAM, which implement Boolean logic operations (such as NAND, NOR, AND, OR, XOR, etc.) by adding additional circuits. At the same time, content-addressable memory (BCAM), as a typical application of in-memory computing, implements efficient search operations by comparing input data with stored data bit by bit, significantly improving search efficiency and reducing power consumption. However, existing BCAM designs have limitations, such as the mismatch between column-by-column search and conventional row writing methods, which increases the difficulty of data writing. In addition, existing SRAM faces problems of computational access interference and sneak current during multi-row activation. Summary of the invention

[0005] In order to overcome the problems faced by the above-mentioned existing SRAM, the present invention proposes a reconfigurable 10T SRAM cell circuit for energy-saving CAM operation and memory calculation. The 10T SRAM cell is configured with decoupled read ports in the horizontal and vertical directions, and can be configured to implement row-by-row logic operations and row-by-row CAM search operations, avoiding vertical data storage and improving compatibility between different modes. A self-suppressed discharge operation is proposed to achieve small swing discharge of the match line, thereby saving power consumption during CAM search.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A reconfigurable 10T SRAM cell circuit for energy-saving CAM operation and memory calculation includes a latch module composed of 4TSRAM, a write part composed of 2 NMOS transistors and a calculation part composed of 4 NMOS transistors;

[0008] The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are electrically connected to a power supply;

[0009] The drain of the PMOS transistor P1, the gate of the PMOS transistor P2, the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, the gate of the NMOS transistor N4 and the gate of the NMOS transistor N5 are electrically connected, and the connection node is denoted as Q;

[0010] The drain of the PMOS transistor P2, the gate of the PMOS transistor P1, the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, the gate of the NMOS transistor N3 and the gate of the NMOS transistor N6 are electrically connected, and the connected node is denoted as QB;

[0011] The source of the NMOS transistor N3, the source of the NMOS transistor N4, and the drain of the NMOS transistor N7 are electrically connected to the ground;

[0012] The drain of the NMOS transistor N5, the drain of the NMOS transistor N6, the gate of the NMOS transistor N7 and the source of the NMOS transistor N8 are electrically connected;

[0013] The gate of the NMOS transistor N1 and the gate of the NMOS transistor N2 are both connected to the write word line WWL;

[0014] The source of the NMOS transistor N1 is connected to the bit line BL, and the source of the NMOS transistor N2 is connected to the word line BLB;

[0015] The source of the NMOS transistor N5 is connected to the read bit line RBL;

[0016] The source of the NMOS transistor N6 is connected to the read word line RBLB;

[0017] The gate of the NMOS transistor N7 is connected to the read word line RWL;

[0018] A gate of the NMOS transistor N8 and a drain of the NMOS transistor N8 are connected to the HBL;

[0019] NMOS transistors N1 to N7, PMOS transistor P1 and PMOS transistor P2 all use conventional threshold transistors;

[0020] The NMOS transistor N8 uses a high threshold transistor;

[0021] When calculating by row logic, HBL of all rows in the array is connected to a level to turn off NMOS transistor N8; WBL and WBLB of all columns in the array are connected to a low level; RBL and RBLB of all columns in the array are precharged to a high level; RWL of unselected rows in the array is connected to a low level; RWL of selected rows in the array is connected to a positive pulse to turn on NMOS transistor N7; read bit lines RBL and RBLB are discharged according to the stored data or remain unchanged, and the bottom sense amplifier SA reads the result of the logic operation;

[0022] When performing a row CAM search operation, the read word lines RWL of all rows are connected to a low level; the write word lines WBL and WBLB of all columns are connected to a low level; the read bit lines RBL and RBLB are configured as search lines SL and SLB; and the horizontal bit line HBL is configured as a match line ML.

[0023] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0024] The present invention adopts a decoupled read port to perform in-memory calculation and reading, ensures the independence of stored data, and improves the anti-interference ability of the unit. A row-based CAM search operation scheme is proposed to avoid vertical data storage and improve the compatibility between different operation modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a 10T SRAM unit circuit provided by an embodiment of the present invention;

[0026] Figure 2 It is a structural schematic diagram and an operation timing diagram of reading data by row and by column according to an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of a row-by-row logic operation structure and an operation timing diagram provided by an embodiment of the present invention;

[0028] Figure 4 A schematic diagram of a simplified storage array (2*2) for implementing a row-by-row search operation of BCAM data provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Example 1

[0031] Reference Figure 1 As shown, the present invention discloses a reconfigurable 10TSRAM unit circuit for energy-saving CAM operation and memory calculation, including a latch module composed of a 4T SRAM, a writing part composed of 2 NMOS transistors and a calculation part composed of 4 NMOS transistors;

[0032] The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are electrically connected to a power supply;

[0033] The drain of the PMOS transistor P1, the gate of the PMOS transistor P2, the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, the gate of the NMOS transistor N4 and the gate of the NMOS transistor N5 are electrically connected, and the connection node is denoted as Q;

[0034] The drain of the PMOS transistor P2, the gate of the PMOS transistor P1, the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, the gate of the NMOS transistor N3 and the gate of the NMOS transistor N6 are electrically connected, and the connected node is denoted as QB;

[0035] The source of the NMOS transistor N3, the source of the NMOS transistor N4, and the drain of the NMOS transistor N7 are electrically connected to the ground;

[0036] The drain of the NMOS transistor N5, the drain of the NMOS transistor N6, the gate of the NMOS transistor N7 and the source of the NMOS transistor N8 are electrically connected;

[0037] The gate of the NMOS transistor N1 and the gate of the NMOS transistor N2 are both connected to the write word line WWL;

[0038] The source of the NMOS transistor N1 is connected to the bit line BL, the source of the NMOS transistor N2 is connected to the word line BLB; the source of the NMOS transistor N5 is connected to the read bit line RBL;

[0039] The source of the NMOS transistor N6 is connected to the read word line RBLB;

[0040] The gate of the NMOS transistor N7 is connected to the read word line RWL;

[0041] A gate of the NMOS transistor N8 and a drain of the NMOS transistor N8 are connected to the HBL;

[0042] NMOS transistors N1 to N7, PMOS transistor P1 and PMOS transistor P2 all use conventional threshold transistors;

[0043] The NMOS transistor N8 is a high threshold transistor.

[0044] Example 2

[0045] Reference Figure 2 As shown in parts (a) and (b), all read word lines RWL of all cells in the same row are connected together, all horizontal bit lines HBL of all cells in the same row are connected together, and all read bit lines RBL and RBLB of the same column are connected together;

[0046] Reference Figure 2 As shown in part (a) of FIG. 1 , when a row is read, the lines RBL and RBLB are disconnected from the drive circuit (not shown) and connected to the sense amplifier SA below. The lines HBL of all rows in the array are driven to a low level. The lines RWL are connected to a drive circuit (not shown), and the lines RWL of the selected row are driven to a high level. The lines RBL and RBLB are charged or remain unchanged according to the data stored in the SRAM. The sense amplifier compares the voltage values ​​of the lines RBL and RBLB to output the stored data.

[0047] Reference Figure 2 As shown in part (b) of the figure, when the column is read, the line HBL is disconnected from the driving circuit (not shown in the figure) and connected to the sense amplifier SA on the right. The line RBL and the line RBLB are connected to the driving circuit (not shown in the figure), the RBL of all columns are driven to a high level, and the line RBLB of the selected column is driven to a low level. The line HBL is discharged or remains unchanged according to the data stored in the SRAM, and the sense amplifier compares the line HBL with the reference voltage V REF The stored data can be output by changing the voltage value.

[0048] Example 3

[0049] Reference Figure 3 As shown in part (a) of FIG. 1 , when operating in row logic, lines RBL and RBLB are disconnected from the drive circuit (not shown) and connected to the sense amplifier SA below. Line HBL of all rows is connected to ground. Line RWL is connected to the drive circuit (not shown), and the lines RWL of the two selected rows are driven to a high level, while the lines RWL of the unselected rows remain at a low level. Lines RBL and RBLB are discharged or remain unchanged according to the data stored in the SRAM, and the sense amplifiers compare the voltage values ​​of lines RBL and RBLLB ​​with the reference voltage value V REF The size of can be used to implement row-by-row logical operations.

[0050] Reference Figure 3As shown in part (c) of the figure, there are four combinations between the two units of the logic operation: 00, 01, 10, and 11. When performing row logic operations, the lines RBL and RBLB will discharge or remain unchanged according to different operands. When 00, the line RBL remains unchanged and the line RBLB is discharged; when 01 and 10, the lines RBL and RBLB are both discharged; when 11, RBL is discharged and RBLB is not discharged.

[0051] Example 4

[0052] The circuit mentioned in the embodiment of the present invention makes full use of the decoupled read path mentioned above, and forms a row-by-row comparison module through vertical and horizontal bidirectional read bit lines, thereby realizing the BCAM search operation in the horizontal direction: the read bit lines RBL and RBLB are used as search lines SL and SLB, the horizontal bit line HBL is used as the match line ML, and the matching result is read out through the sensitive amplifier at the end of the horizontal bit line HBL;

[0053] For the search operation, the data to be searched is pre-written and stored in the cell by row. During the search, the RWL of all rows in the array is electrically connected to the low level, the match line ML (HBL) is pre-charged to the high level and then floats, and the search data lines SL (RBL) and SLB (RBLB) are set to the high level or low level according to the search data. If the search data is 1, the line SL is high level and the line SLB is low level; if the search data is 0, the line SL is the first level and the line SLB is high level.

[0054] Reference Figure 4 As shown, a simplified 2*2 array is used as an example to introduce the row search search method. The first row of SRAM cells are denoted as CELL00 and CELL01; the second row of SRAM cells are denoted as CELL10 and CELL11. The search data is 01, and the data search line SL1 and line SLB1 are connected to a low level and a high level respectively; the data search line SL2 and line SLB2 are connected to a high level and a low level respectively. For the first column, CELL00 and CELL01 store data 01, and the read port on the right side of CELL00 is turned on, but ML0 and SLB0 are high levels, which are not enough to form a conductive channel, so ML0 does not discharge; the left side of CELL00 is not turned on, so no conductive path is formed. The left port of CELL01 is turned on, but the lines SL0 and ML0 at both ends of the cell are at high voltages, which are not enough to form a conductive channel, so no discharge is formed. The right side of CELL01 is the same as the left side of CELL00, which is not turned on and does not discharge; therefore, the matching line ML0 does not discharge, and the sensitive amplifier on the right side matches the voltage of the matching line ML0 and the reference voltage V REFFor comparison, the result of the sense amplifier is 1, indicating a match; for the second row of data, CELL10 and CELL11 store data 00, where CELL10 and CELL00 are the same and no conductive path is formed; the left side of CELL11 is not conductive, so there is no conductive path, the read port on the right side of CELL11 is conductive, and SLB1 is at a low level, so ML1 will generate a conductive path, thereby discharging, and the sense amplifier on the right side compares the voltage of the match line ML1 with the reference voltage VREF, and the result of the sense amplifier is 0, indicating a mismatch.

[0055] In order to solve the problem of excessive discharge of the matching line during the search operation, the gate and drain of N8 are connected together in this design. Figure 1 When the matching line ML (HBL) discharges, the voltage of ML will gradually decrease, and the V GS The discharge rate of N8 is reduced until the voltage of the matching line ML drops to a level that makes N8's V GS <V TH , the transistor N8 is turned off, and the match line ML stops discharging, thereby reducing the excessive discharge of the match line when multiple bits are mismatched and reducing the power consumption of the circuit.

[0056] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reconfigurable 10T SRAM cell circuit for energy-efficient CAM operations and memory computing, characterized in that: It includes a latch module composed of 4T SRAM, a writing part composed of 2 NMOS transistors and a computing part composed of 4 NMOS transistors.

2. A reconfigurable 10T SRAM cell circuit for energy-saving CAM operations and memory computing as claimed in claim 1, characterized in that: A latch module includes NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2; the writing part composed of two NMOS includes NMOS transistor N1 and NMOS transistor N2; the calculation part composed of four NMOS includes NMOS transistor N5, NMOS transistor N6, NMOS transistor N7 and high threshold NMOS transistor N8.

3. A reconfigurable 10T SRAM cell circuit for energy-saving CAM operations and memory computing as claimed in claim 2, characterized in that: The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are electrically connected to a power supply; The drain of the PMOS transistor P1, the gate of the PMOS transistor P2, the drain of the NMOS transistor N1, the drain of the NMOS transistor N3, the gate of the NMOS transistor N4 and the gate of the NMOS transistor N5 are electrically connected, and the connection node is denoted as Q; The drain of the PMOS transistor P2, the gate of the PMOS transistor P1, the drain of the NMOS transistor N2, the drain of the NMOS transistor N4, the gate of the NMOS transistor N3 and the gate of the NMOS transistor N6 are electrically connected, and the connected node is denoted as QB; The source of the NMOS transistor N3, the source of the NMOS transistor N4, and the drain of the NMOS transistor N7 are electrically connected to the ground; The drain of the NMOS transistor N5, the drain of the NMOS transistor N6, the gate of the NMOS transistor N7 and the drain of the NMOS transistor N8 are electrically connected; The gate of the NMOS transistor N1 and the gate of the NMOS transistor N2 are both connected to the write word line WWL; The source of the NMOS transistor N1 is connected to the bit line BL, and the source of the NMOS transistor N2 is connected to the word line BLB; The source of the NMOS transistor N5 is connected to the read bit line RBL; The source of the NMOS transistor N6 is connected to the read word line RBLB; The gate of the NMOS transistor N7 is connected to the read word line RWL; A gate of the NMOS transistor N8 and a source of the NMOS transistor N8 are connected to the HBL; NMOS transistors N1 to N7, PMOS transistor P1 and PMOS transistor P2 all use conventional threshold transistors; The NMOS transistor N8 is a high threshold transistor.

4. A reconfigurable 10T SRAM cell circuit for energy-saving CAM operations and memory computing as claimed in claim 3, characterized in that: The row-based in-memory logical operations include: The HBL of all rows in the array is connected to a level to turn off the NMOS transistor N8; the WBL and WBLB of all columns in the array are connected to a low level; The RBL and RBLB of all columns in the array are precharged to high level; the RWL of unselected rows in the array is connected to low level; The RWL of the selected row in the array receives a positive pulse, turning on the NMOS transistor N7; the read bit lines RBL and RBLB are discharged or remain unchanged according to the stored data, and the bottom sense amplifier SA reads out the logic operation result.

5. A reconfigurable 10T SRAM cell circuit for energy-saving CAM operations and memory computing as claimed in claim 4, characterized in that: The row-wise CAM search operations include: The read word lines RWL of all rows are connected to a low level; the write word lines WBL and WBLB of all columns are connected to a low level; Read bit lines RBL and RBLB are configured as search lines SL and SLB; horizontal bit line HBL is configured as match line ML.

Images